The DBGDIDR characteristics are:
Specifies which version of the Debug architecture is implemented, and some features of the debug implementation.
This register is present only when AArch32 is supported. Otherwise, direct accesses to DBGDIDR are UNDEFINED.
If EL1 cannot use AArch32 then the implementation of this register is OPTIONAL and deprecated.
DBGDIDR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WRPs | BRPs | CTX_CMPs | Version | RES1 | nSUHD_imp | RES0 | SE_imp | RES0 |
The number of watchpoints implemented, minus 1.
Permitted values of this field are from 0b0001 for 2 implemented watchpoints, to 0b1111 for 16 implemented watchpoints.
The value of 0b0000 is reserved.
If AArch64 is implemented, this field has the same value as ID_AA64DFR0_EL1.WRPs.
The number of breakpoints implemented, minus 1.
Permitted values of this field are from 0b0001 for 2 implemented breakpoint, to 0b1111 for 16 implemented breakpoints.
The value of 0b0000 is reserved.
If AArch64 is implemented, this field has the same value as ID_AA64DFR0_EL1.BRPs.
The number of breakpoints that can be used for Context matching, minus 1.
Permitted values of this field are from 0b0000 for 1 Context matching breakpoint, to 0b1111 for 16 Context matching breakpoints.
The Context matching breakpoints must be the highest addressed breakpoints. For example, if six breakpoints are implemented and two are Context matching breakpoints, they must be breakpoints 4 and 5.
If AArch64 is implemented, this field has the same value as ID_AA64DFR0_EL1.CTX_CMPs.
Debug architecture version. Indicates presence of Armv8 debug architecture. Defined values are:
Version | Meaning |
---|---|
0b0000 |
Not supported. |
0b0001 |
Armv6, v6 Debug architecture, with System registers access. |
0b0010 |
Armv6, v6.1 Debug architecture, with System registers access. |
0b0011 |
Armv7, v7 Debug architecture, with only baseline System registers. |
0b0100 |
Armv7, v7 Debug architecture, with all System registers implemented. |
0b0101 |
Armv7, v7.1 Debug architecture, with System registers access. |
0b0110 |
Armv8 debug architecture. |
0b0111 |
Armv8 debug architecture with Virtualization Host Extensions. |
0b1000 |
Armv8.2 debug architecture, FEAT_Debugv8p2. |
0b1001 |
Armv8.4 debug architecture, FEAT_Debugv8p4. |
0b1010 |
Armv8.8 debug architecture, FEAT_Debugv8p8. |
All other values are reserved.
The values 0b0000, 0b0001, 0b0010, 0b0011, 0b0100, and 0b0101 are not permitted in Armv8.
FEAT_VHE adds the functionality identified by the value 0b0111.
FEAT_Debugv8p2 adds the functionality identified by the value 0b1000.
FEAT_Debugv8p4 adds the functionality identified by the value 0b1001.
FEAT_Debugv8p8 adds the functionality identified by the value 0b1010.
From Armv8.1, when FEAT_VHE is implemented the value 0b0110 is not permitted.
From Armv8.2, the values 0b0110 and 0b0111 are not permitted.
From Armv8.4, the value 0b1000 is not permitted.
From Armv8.8, the value 0b1001 is not permitted.
Reserved, RES1.
In Armv7-A, was Secure User Halting Debug not implemented.
The value of this bit must match the value of the SE_imp bit.
Reserved, RES0.
EL3 implemented. The meanings of the values of this bit are:
SE_imp | Meaning |
---|---|
0b0 |
EL3 not implemented. |
0b1 |
EL3 implemented. |
The value of this bit must match the value of the nSUHD_imp bit.
Reserved, RES0.
Arm deprecates any access to this register from EL0.
Accesses to this register use the following encodings in the System register encoding space:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1110 | 0b000 | 0b0000 | 0b0000 | 0b000 |
if Halted() && ConstrainUnpredictableBool(Unpredictable_IGNORETRAPINDEBUG) then return DBGDIDR; elsif PSTATE.EL == EL0 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then UNDEFINED; elsif !ELUsingAArch32(EL1) && MDSCR_EL1.TDCC == '1' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); else AArch64.AArch32SystemAccessTrap(EL1, 0x05); elsif ELUsingAArch32(EL1) && DBGDSCRext.UDCCdis == '1' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then AArch32.TakeHypTrapException(0x00); else UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && (HCR_EL2.TGE == '1' || MDCR_EL2.<TDE,TDA> != '00') then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && (HCR.TGE == '1' || HDCR.<TDE,TDA> != '00') then AArch32.TakeHypTrapException(0x05); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x05); else return DBGDIDR; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDA> != '00' then AArch32.TakeHypTrapException(0x05); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x05); else return DBGDIDR; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x05); else return DBGDIDR; elsif PSTATE.EL == EL3 then return DBGDIDR;
30/09/2021 15:34; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f
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