The PMCR_EL0 characteristics are:
Provides details of the Performance Monitors implementation, including the number of counters implemented, and configures and controls the counters.
External register PMCR_EL0 bits [7:0] are architecturally mapped to AArch32 System register PMCR[7:0].
External register PMCR_EL0 bits [7:0] are architecturally mapped to AArch64 System register PMCR_EL0[7:0].
PMCR_EL0 is in the Core power domain.
This register is only partially mapped to the internal PMCR System register. An external agent must use other means to discover the information held in PMCR[31:11], such as accessing PMCFGR and the ID registers.
PMCR_EL0 is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAZ/WI | RES0 | FZO | RES0 | LP | LC | DP | X | D | C | P | E |
Reserved, RAZ/WI.
Hardware must implement this field as RAZ/WI. Software must not rely on the register reading as zero, and must use a read-modify-write sequence to write to the register.
Reserved, RES0.
Freeze-on-overflow. Stop event counters on overflow.
In the description of this field:
If EL2 is implemented and is using AArch32, PMN is HDCR.HPMN.
If EL2 is implemented and is using AArch64, PMN is MDCR_EL2.HPMN.
If EL2 is not implemented, PMN is PMCR_EL0.N.
FZO | Meaning |
---|---|
0b0 |
Do not freeze on overflow. |
0b1 |
Event counter PMEVCNTR<n>_EL0 does not count when PMOVSCLR_EL0[(PMN-1):0] is nonzero and n is in the range of affected event counters. |
If PMN is not 0, this field affects the operation of event counters in the range [0 .. (PMN-1)].
This field does not affect the operation of other event counters and PMCCNTR_EL0.
The operation of this field applies even when EL2 is disabled in the current Security state.
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Long event counter enable. Determines when unsigned overflow is recorded by an event counter overflow bit.
In the description of this field:
If EL2 is implemented and is using AArch32, PMN is HDCR.HPMN.
If EL2 is implemented and is using AArch64, PMN is MDCR_EL2.HPMN.
If EL2 is not implemented, PMN is PMCR_EL0.N.
LP | Meaning |
---|---|
0b0 |
Event counter overflow on increment that causes unsigned overflow of PMEVCNTR<n>_EL0[31:0]. |
0b1 |
Event counter overflow on increment that causes unsigned overflow of PMEVCNTR<n>_EL0[63:0]. |
If PMN is not 0, this bit affects the operation of event counters in the range [0 .. (PMN-1)].
The field does not affect the operation of other event counters and PMCCNTR_EL0.
The operation of this field applies even when EL2 is disabled in the current Security state.
Reserved, RES0.
Long cycle counter enable. Determines when unsigned overflow is recorded by the cycle counter overflow bit.
LC | Meaning |
---|---|
0b0 |
Cycle counter overflow on increment that causes unsigned overflow of PMCCNTR_EL0[31:0]. |
0b1 |
Cycle counter overflow on increment that causes unsigned overflow of PMCCNTR_EL0[63:0]. |
Arm deprecates use of PMCR_EL0.LC = 0.
The reset behavior of this field is:
Reserved, RES1.
Disable cycle counter when event counting is prohibited. The possible values of this bit are:
DP | Meaning |
---|---|
0b0 |
Cycle counting by PMCCNTR_EL0 is not affected by this mechanism. |
0b1 | Cycle counting by PMCCNTR_EL0 is disabled in prohibited regions:
If MDCR_EL2.HPMN is not 0, this is when event counting by event counters in the range [0..(MDCR_EL2.HPMN-1)] is prohibited. |
For more information, see 'Prohibiting event counting'.
The reset behavior of this field is:
Reserved, RES0.
Enable export of events in an IMPLEMENTATION DEFINED PMU event export bus.
X | Meaning |
---|---|
0b0 |
Do not export events. |
0b1 |
Export events where not prohibited. |
This field enables the exporting of events over an IMPLEMENTATION DEFINED PMU event export bus to another device, for example to an OPTIONAL PE trace unit.
No events are exported when counting is prohibited.
This field does not affect the generation of Performance Monitors overflow interrupt requests or signaling to a cross-trigger interface (CTI) that can be implemented as signals exported from the PE.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field it resets to:
Reserved, RAZ/WI.
Clock divider.
D | Meaning |
---|---|
0b0 |
When enabled, PMCCNTR_EL0 counts every clock cycle. |
0b1 |
When enabled, PMCCNTR_EL0 counts once every 64 clock cycles. |
If PMCR_EL0.LC == 1, this bit is ignored and the cycle counter counts every clock cycle.
Arm deprecates use of PMCR_EL0.D = 1.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field it resets to:
Reserved, RES0.
Cycle counter reset. The effects of writing to this bit are:
C | Meaning |
---|---|
0b0 |
No action. |
0b1 |
Reset PMCCNTR_EL0 to zero. |
Resetting PMCCNTR_EL0 does not change the cycle counter overflow bit. If FEAT_PMUv3p5 is implemented, the value of PMCR_EL0.LC is ignored, and bits [63:0] of the cycle counter are reset.
Access to this field is WO/RAZ.
Event counter reset. The effects of writing to this bit are:
P | Meaning |
---|---|
0b0 |
No action. |
0b1 |
Reset all event counters, not including PMCCNTR_EL0, to zero. |
Resetting the event counters does not change the event counter overflow bits. If FEAT_PMUv3p5 is implemented, the value of MDCR_EL2.HLP, or PMCR_EL0.LP is ignored and bits [63:0] of all affected event counters are reset.
Access to this field is WO/RAZ.
Enable.
In the description of this field:
If EL2 is implemented and is using AArch32, PMN is HDCR.HPMN.
If EL2 is implemented and is using AArch64, PMN is MDCR_EL2.HPMN.
If EL2 is not implemented, PMN is PMCR_EL0.N.
E | Meaning |
---|---|
0b0 |
PMCCNTR_EL0 is disabled and event counters PMEVCNTR<n>_EL0, where n is in the range of affected event counters, are disabled. |
0b1 |
PMCCNTR_EL0 and event counters PMEVCNTR<n>_EL0, where n is in the range of affected event counters, are enabled by PMCNTENSET_EL0. |
If PMN is not 0, this field affects the operation of event counters in the range [0 .. (PMN-1)].
This field does not affect the operation of other event counters.
The operation of this field applies even when EL2 is disabled in the current Security state.
The reset behavior of this field is:
SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.
Component | Offset | Instance |
---|---|---|
PMU | 0xE04 | PMCR_EL0 |
This interface is accessible as follows:
30/09/2021 15:34; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.