The AMPIDR1 characteristics are:
Provides information to identify an activity monitors component.
For more information, see 'About the Peripheral identification scheme'.
The power domain of AMPIDR1 is IMPLEMENTATION DEFINED.
Implementation of this register is OPTIONAL.
This register is present only when FEAT_AMUv1 is implemented.
AMPIDR1 is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | DES_0 | PART_1 |
Reserved, RES0.
Designer, least significant nibble of JEP106 ID code.
For Arm Limited, this field is 0b1011.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Part number, most significant nibble.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Component | Offset | Instance |
---|---|---|
AMU | 0xFE4 | AMPIDR1 |
Accesses on this interface are RO.
30/09/2021 15:34; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f
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