EDCIDR1, External Debug Component Identification Register 1

The EDCIDR1 characteristics are:

Purpose

Provides information to identify an external debug component.

For more information, see 'About the Component Identification scheme'.

Configuration

Implementation of this register is OPTIONAL.

If FEAT_DoPD is implemented, this register is in the Core power domain. If FEAT_DoPD is not implemented, this register is in the Debug power domain.

This register is required for CoreSight compliance.

Attributes

EDCIDR1 is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
RES0CLASSPRMBL_1

Bits [31:8]

Reserved, RES0.

CLASS, bits [7:4]

Component class.

CLASSMeaning
0b1001

CoreSight component.

Other values are defined by the CoreSight Architecture.

This field reads as 0x9.

PRMBL_1, bits [3:0]

Preamble.

Reads as 0b0000.

Access to this field is RO.

Accessing EDCIDR1

EDCIDR1 can be accessed through the external debug interface:

ComponentOffsetInstance
Debug0xFF4EDCIDR1

This interface is accessible as follows:


20/09/2021 11:02; d4a233ffbdfb36e47856c443a7ce9a85f5e501ca

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