The MSMON_OFLOW_MSI_ATTR characteristics are:
MSMON_OFLOW_MSI_ATTR is a 32-bit read/write register that controls MPAM monitor overflow MSI write attributes for MPAM monitor overflows in this MSC.
MSMON_OFLOW_MSI_ATTR_s controls Secure MPAM monitor overflow MSI writes. MSMON_OFLOW_MSI_ATTR_ns controls Non-secure MPAM monitor overflow MSI writes.
The power domain of MSMON_OFLOW_MSI_ATTR is IMPLEMENTATION DEFINED.
This register is present only when FEAT_MPAMv1p1 is implemented and MPAMF_MSMON_IDR.HAS_OFLW_MSI == 1. Otherwise, direct accesses to MSMON_OFLOW_MSI_ATTR are RES0.
MSMON_OFLOW_MSI_ADDR_L, MSMON_OFLOW_MSI_ADDR_H, MSMON_OFLOW_MSI_ATTR, MSMON_OFLOW_MSI_DATA, and MSMON_OFLOW_MSI_MPAM must all be implemented to support MSI writes for monitor overflow interrupts.
The power and reset domain of each MSC component is specific to that component.
MSMON_OFLOW_MSI_ATTR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | MSI_SH | MSI_MEMATTR | RES0 | MSIEN |
Reserved, RES0.
Sharability attribute of MSI writes.
MSI_SH | Meaning |
---|---|
0b00 |
Non-shareable. |
0b01 |
Reserved, CONSTRAINED UNPREDICTABLE. |
0b10 |
Outer Shareable. |
0b11 |
Inner Shareable. |
When MSMON_OFLOW_MSI_ATTR.MSI_MEMATTR specifies a Device memory type, the contents of this field are IGNORED and Shareability is effectively Outer Shareable.
Memory attributes of MSI writes.
Note: This encoding matches the VMSAv8-64 stage 2 MemAttr[3:0] field as described in the Arm ARM, except that the following encodings are Reserved (not UNPREDICTABLE) and behave as DEvice-nGnRnE: 0b0100, 0b1000, and 0b1100.
MSI_MEMATTR | Meaning |
---|---|
0b0000 |
Device-nGnRnE. |
0b0001 |
Device-nGnRE. |
0b0010 |
Device-nGRE. |
0b0011 |
Device-GRE. |
0b0100 |
Reserved. Behave as Device-nGnRnE, 0b0000. |
0b0101 |
Normal Inner Non-cacheable, Outer Non-cacheable. |
0b0110 |
Normal Inner Write-Through Cacheable, Outer Non-cacheable. |
0b0111 |
Normal Inner Write-Back Cacheable, Outer Non-cacheable. |
0b1000 |
Reserved. Behave as Device-nGnRnE, 0b0000. |
0b1001 |
Normal Inner Non-Cachable, Outer Write-Through Cacheable. |
0b1010 |
Normal Inner Write-Through Cacheable, Outer Write-Through Cachable. |
0b1011 |
Normal Inner Write-Back Cacheable, Outer Write-Through Cachable. |
0b1100 |
Reserved. Behave as Device-nGnRnE, 0b0000. |
0b1101 |
Normal Inner Non-cacheable, Outer Write-Back Cacheable. |
0b1110 |
Normal Inner Write-Through Cacheable, Outer Write-Back Cacheable. |
0b1111 |
Normal Inner Write-Back Cacheable, Outer Write-Back Cacheable. |
When this field specifies a Device memory type, the contents of MSMON_OFLOW_MSI_ATTR.MSI_SH are IGNORED and Shareability is effectively Outer Shareable.
Device types may be implemented as any Device type with more n characters. For example, if this field is set to 0b0010, an implementation may treat the MSI write as the specified type, Device-nGRE, or as Device-nGnRE or as Device-nGnRnE.
Reserved encodings 0b0100, 0b1000, and 0b1100 must be implemented to behave the same as the 0b0000 encoding.
Reserved, RES0.
Monitor overflow MSI write enable.
MSIEN | Meaning |
---|---|
0b0 |
MPAM monitor overflow MSI writes are not generated to signal enabled MPAM monitor overflow interrupts. When monitor overflow MSI writes are disabled, hardwired monitor overflow interrupt could be generated if hardwired monitor overflow interrupt is implemented. |
0b1 |
MPAM monitor overflow MSI writes are generated to signal enabled MPAM monitor overflow interrupts. When monitor overflow MSI writes are enabled, hardwired monitor overflow interrupts are not generated. |
This enable affects whether a hardwired overlow interrupt is generated.
The reset behavior of this field is:
This register is within the MPAM feature page memory frames. In a system that supports Secure and Non-secure memory maps, there must be both Secure and Non-secure MPAM feature pages.
MSMON_OFLOW_MSI_ATTR_s must be accessible from the Secure MPAM feature page. MSMON_OFLOW_MSI_ATTR_ns must be accessible from the Non-secure MPAM feature page.
MSMON_OFLOW_MSI_ATTR_s and MSMON_OFLOW_MSI_ATTR_ns must be separate registers. The Secure instance (MSMON_OFLOW_MSI_ATTR_s) accesses the monitor overflow MSI write attributes of Secure monitors, and the Non-secure instance (MSMON_OFLOW_MSI_ATTR_ns) accesses the monitor overflow MSI write attributes of Non-secure monitors.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_s | 0x08EC | MSMON_OFLOW_MSI_ATTR_s |
Accesses on this interface are RW.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_ns | 0x08EC | MSMON_OFLOW_MSI_ATTR_ns |
Accesses on this interface are RW.
20/09/2021 11:02; d4a233ffbdfb36e47856c443a7ce9a85f5e501ca
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