The DC CVAU characteristics are:
Clean data cache by address to Point of Unification.
AArch64 System instruction DC CVAU performs the same function as AArch32 System instruction DCCMVAU.
DC CVAU is a 64-bit System instruction.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Virtual address to use | |||||||||||||||||||||||||||||||
Virtual address to use |
Virtual address to use. No alignment restrictions apply to this VA.
If EL0 access is enabled, when executed at EL0, this instruction requires read access permission to the VA, otherwise it generates a Permission fault, subject to the constraints described in 'Permission fault'.
Execution of this instruction might require an address translation from VA to PA, and that translation might fault. For more information, see 'The data cache maintenance instruction (DC)'.
Accesses to this instruction use the following encodings in the System instruction encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b01 | 0b011 | 0b0111 | 0b1011 | 0b001 |
if PSTATE.EL == EL0 then if !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && SCTLR_EL1.UCI == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && HCR_EL2.TPU == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && HCR_EL2.TOCU == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.DCCVAU == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && SCTLR_EL2.UCI == '0' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.DC(X[t], CacheType_Data, CacheOp_Clean, CacheOpScope_PoU); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TPU == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.TOCU == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.DCCVAU == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.DC(X[t], CacheType_Data, CacheOp_Clean, CacheOpScope_PoU); elsif PSTATE.EL == EL2 then AArch64.DC(X[t], CacheType_Data, CacheOp_Clean, CacheOpScope_PoU); elsif PSTATE.EL == EL3 then AArch64.DC(X[t], CacheType_Data, CacheOp_Clean, CacheOpScope_PoU);
30/09/2021 15:34; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f
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