The PMMIR characteristics are:
Describes Performance Monitors parameters specific to the implementation.
PMMIR is in the Core power domain.
This register is present only when FEAT_PMUv3p4 is implemented. Otherwise, direct accesses to PMMIR are RES0.
PMMIR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | BUS_WIDTH | BUS_SLOTS | SLOTS |
Reserved, RES0.
Bus width. Indicates the number of bytes each BUS_ACCESS event relates to. Encoded as Log2(number of bytes), plus one. Defined values are:
BUS_WIDTH | Meaning |
---|---|
0b0000 |
The information is not available. |
0b0011 |
Four bytes. |
0b0100 |
8 bytes. |
0b0101 |
16 bytes. |
0b0110 |
32 bytes. |
0b0111 |
64 bytes. |
0b1000 |
128 bytes. |
0b1001 |
256 bytes. |
0b1010 |
512 bytes. |
0b1011 |
1024 bytes. |
0b1100 |
2048 bytes. |
All other values are reserved.
Each transfer is up to this number of bytes. An access might be smaller than the bus width.
When this field is nonzero, each access counted by BUS_ACCESS is at most BUS_WIDTH bytes. An implementation might treat a wide bus as multiple narrower buses, such that a wide access on the bus increments the BUS_ACCESS counter by more than one.
Bus count. The largest value by which the BUS_ACCESS event might increment in a single BUS_CYCLES cycle.
When this field is nonzero, the largest value by which the BUS_ACCESS event might increment in a single BUS_CYCLES cycle is BUS_SLOTS.
Operation width. The largest value by which the STALL_SLOT event might increment by in a single cycle. If the STALL_SLOT event is implemented, this field must not be zero.
If the Core power domain is off or in a low-power state, access on this interface returns an Error.
Component | Offset | Instance |
---|---|---|
PMU | 0xE40 | PMMIR |
This interface is accessible as follows:
20/09/2021 11:02; d4a233ffbdfb36e47856c443a7ce9a85f5e501ca
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