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The CNTPS_TVAL_EL1 characteristics are:
Holds the timer value for the secure physical timer, usually accessible at EL3 but configurably accessible at EL1 in Secure state.
There are no configuration notes.
CNTPS_TVAL_EL1 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
TimerValue |
Reserved, RES0.
The TimerValue view of the secure physical timer.
On a read of this register:
On a write of this register, CNTPS_CVAL_EL1 is set to (CNTPCT_EL0 + TimerValue), where TimerValue is treated as a signed 32-bit integer.
When CNTPS_CTL_EL1.ENABLE is 1, the timer condition is met when (CNTPCT_EL0 - CNTPS_CVAL_EL1) is greater than or equal to zero. This means that TimerValue acts like a 32-bit downcounter timer. When the timer condition is met:
When CNTPS_CTL_EL1.ENABLE is 0, the timer condition is not met, but CNTPCT_EL0 continues to count, so the TimerValue view appears to continue to count down.
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b111 | 0b1110 | 0b0010 | 0b000 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && SCR_EL3.NS == '0' then
if SCR_EL3.EEL2 == '1' then
UNDEFINED;
elsif SCR_EL3.ST == '0' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif IsFeatureImplemented(FEAT_ECV) && EL2Enabled() && SCR_EL3.ECVEn == '1' && CNTHCTL_EL2.ECV == '1' then
if CNTPS_CTL_EL1.ENABLE == '0' then
return bits(64) UNKNOWN;
else
return CNTPS_CVAL_EL1 - (PhysicalCountInt() - CNTPOFF_EL2);
else
if CNTPS_CTL_EL1.ENABLE == '0' then
return bits(64) UNKNOWNCNTPS_TVAL_EL1;
else
return CNTPS_CVAL_EL1 - PhysicalCountInt();
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
UNDEFINED;
elsif PSTATE.EL == EL3 then
if CNTPS_CTL_EL1.ENABLE == '0' then
return bits(64) UNKNOWNCNTPS_TVAL_EL1;
else
return CNTPS_CVAL_EL1 - PhysicalCountInt();
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b111 | 0b1110 | 0b0010 | 0b000 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && SCR_EL3.NS == '0' then
if SCR_EL3.EEL2 == '1' then
UNDEFINED;
elsif SCR_EL3.ST == '0' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif IsFeatureImplemented(FEAT_ECV) && EL2Enabled() && SCR_EL3.ECVEn == '1' && CNTHCTL_EL2.ECV == '1' then
CNTPS_CVAL_EL1 = SignExtend((X[t]<31:0>),64) + PhysicalCountInt() - CNTPOFF_EL2;
else
CNTPS_CVAL_EL1CNTPS_TVAL_EL1 = SignExtend((X[t]<31:0>),64) + PhysicalCountInt();];
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
UNDEFINED;
elsif PSTATE.EL == EL3 then
CNTPS_CVAL_EL1CNTPS_TVAL_EL1 = SignExtend((X[t]<31:0>),64) + PhysicalCountInt();];
3020/09/2021 1511:3402; 092b4e1bbfbb45a293b198f9330c5f529ead2b0fd4a233ffbdfb36e47856c443a7ce9a85f5e501ca
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