The HCPTR characteristics are:
Controls:
Accesses to this functionality:
Exceptions generated by the CPACR and NSACR controls are higher priority than those generated by the HCPTR controls.
AArch32 System register HCPTR bits [31:0] are architecturally mapped to AArch64 System register CPTR_EL2[31:0].
This register is present only when AArch32 is supported. Otherwise, direct accesses to HCPTR are UNDEFINED.
If EL2 is not implemented, this register is RES0 from EL3.
HCPTR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TCPAC | TAM | RES0 | TTA | RES0 | TASE | RES0 | RES1 | TCP11 | TCP10 | RES1 |
Traps Non-secure EL1 accesses to the CPACR to Hyp mode.
TCPAC | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 |
Non-secure EL1 accesses to the CPACR are trapped to Hyp mode. |
The CPACR is not accessible at EL0.
The reset behavior of this field is:
Trap Activity Monitor access. Traps Non-secure EL1 and EL0 accesses to all Activity Monitor registers to EL2.
TAM | Meaning |
---|---|
0b0 |
Accesses from Non-secure EL1 and EL0 to Activity Monitor registers are not trapped. |
0b1 |
Accesses from Non-secure EL1 and EL0 to Activity Monitor registers are trapped to Hyp mode. |
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Traps Non-secure System register accesses to all implemented trace registers to Hyp mode.
TTA | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 | Any Non-secure System register access to an implemented trace register is trapped to Hyp mode, unless the access is trapped to EL1 by a CPACR or NSACR control, or the access is from Non-secure EL0 and the definition of the register in the appropriate trace architecture specification indicates that the register is not accessible from EL0. A trapped instruction generates:
|
If the implementation does not include a PE trace unit, or does not include a System register interface to the PE trace unit registers, it is IMPLEMENTATION DEFINED whether this bit:
If EL3 is implemented and is using AArch32, and the value of NSACR.NSTRCDIS is 1, in Non-secure state this field behaves as RAO/WI, regardless of its actual value.
System register accesses to the trace registers can have side-effects. When a System register access is trapped, any side-effects that are normally associated with the access do not occur before the exception is taken.
The reset behavior of this field is:
Reserved, RES0.
Traps Non-secure execution of Advanced SIMD instructions to Hyp mode when the value of HCPTR.TCP10 is 0.
TASE | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 | When the value of HCPTR.TCP10 is 0, any attempt to execute an Advanced SIMD instruction in Non-secure state is trapped to Hyp mode, unless it is trapped to EL1 by a CPACR or NSACR control. A trapped instruction generates:
|
When the value of HCPTR.TCP10 is 1, the value of this field is ignored.
If the implementation does not include Advanced SIMD and floating-point functionality, this field is RES1. Otherwise, it is IMPLEMENTATION DEFINED whether this field is implemented as a RW field. If it is not implemented as a RW field, then it is RAZ/WI.
If EL3 is implemented and is using AArch32, and the value of NSACR.NSASEDIS is 1, in Non-secure state this field behaves as RAO/WI, regardless of its actual value. This applies even if the field is implemented as RAZ/WI.
For the list of instructions affected by this field, see 'Controls of Advanced SIMD operation that do not apply to floating-point operation'.
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES1.
The value of this field is ignored. If this field is programmed with a different value to the TCP10 bit then this field is UNKNOWN on a direct read of the HCPTR.
If the implementation does not include Advanced SIMD and floating-point functionality, this field is RES1.
If EL3 is implemented and is using AArch32, and the value of NSACR.cp10 is 0, in Non-secure state this field behaves as RAO/WI, regardless of its actual value.
The reset behavior of this field is:
Trap Non-secure accesses to Advanced SIMD and floating-point functionality to Hyp mode:
TCP10 | Meaning |
---|---|
0b0 |
This control does not cause any instructions to be trapped. |
0b1 | Any attempted access to Advanced SIMD and floating-point functionality from Non-secure state is trapped to Hyp mode, unless it is trapped to EL1 by a CPACR or NSACR control. A trapped instruction generates:
|
The Advanced SIMD and floating-point features controlled by these fields are:
If the implementation does not include Advanced SIMD and floating-point functionality, this field is RES1.
If EL3 is implemented and is using AArch32, and the value of NSACR.cp10 is 0, in Non-secure state this field behaves as RAO/WI, regardless of its actual value.
The reset behavior of this field is:
Reserved, RES1.
Accesses to this register use the following encodings in the System register encoding space:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b100 | 0b0001 | 0b0001 | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T1 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T1 == '1' then AArch32.TakeHypTrapException(0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && CPTR_EL3.TCPAC == '1' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TCPAC == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); else return HCPTR; elsif PSTATE.EL == EL3 then if SCR.NS == '0' then UNDEFINED; else return HCPTR;
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b100 | 0b0001 | 0b0001 | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T1 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T1 == '1' then AArch32.TakeHypTrapException(0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && CPTR_EL3.TCPAC == '1' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TCPAC == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); else HCPTR = R[t]; elsif PSTATE.EL == EL3 then if SCR.NS == '0' then UNDEFINED; else HCPTR = R[t];
30/09/2021 15:33; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f
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