AMEVCNTVOFF1<n>_EL2, Activity Monitors Event Counter Virtual Offset Registers 1, n = 0 - 15

The AMEVCNTVOFF1<n>_EL2 characteristics are:

Purpose

Holds the 64-bit virtual offset for auxiliary activity monitor events.

Configuration

This register is present only when FEAT_AMUv1p1 is implemented. Otherwise, direct accesses to AMEVCNTVOFF1<n>_EL2 are UNDEFINED.

Attributes

AMEVCNTVOFF1<n>_EL2 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
Virtual offset
Virtual offset

Bits [63:0]

Virtual offset.

The reset behavior of this field is:

Accessing AMEVCNTVOFF1<n>_EL2

Note

AMCG1IDR_EL0 identifies which auxiliary activity monitor event counters have a corresponding virtual offset implemented.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, AMEVCNTVOFF1<n>_EL2

op0op1CRnCRmop2
0b110b1000b11010b101:n[3]n[2:0]

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then return NVMem[0xA80+8*UInt(CRm<0>:op2<2:0>)]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TAM == '1' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.AMVOFFEN == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.AMVOFFEN == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TAM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return AMEVCNTVOFF1_EL2[UInt(CRm<0>:op2<2:0>)]; elsif PSTATE.EL == EL3 then return AMEVCNTVOFF1_EL2[UInt(CRm<0>:op2<2:0>)];

MSR AMEVCNTVOFF1<n>_EL2, <Xt>

op0op1CRnCRmop2
0b110b1000b11010b101:n[3]n[2:0]

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then NVMem[0xA80+8*UInt(CRm<0>:op2<2:0>)] = X[t]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TAM == '1' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.AMVOFFEN == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.AMVOFFEN == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TAM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else AMEVCNTVOFF1_EL2[UInt(CRm<0>:op2<2:0>)] = X[t]; elsif PSTATE.EL == EL3 then AMEVCNTVOFF1_EL2[UInt(CRm<0>:op2<2:0>)] = X[t];


20/09/2021 11:02; d4a233ffbdfb36e47856c443a7ce9a85f5e501ca

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