(old) htmldiff from-(new)

GICM_SETSPI_NSR, Set Non-secure SPI Pending Register

The GICM_SETSPI_NSR characteristics are:

Purpose

Adds the pending state to a valid SPI if permitted by the Security state of the access and the GICD_NSACR<n> value for that SPI.

A write to this register changes the state of an inactive SPI to pending, and the state of an active SPI to active and pending.

Configuration

When GICD_CTLR.DS==1, this register provides functionality for all SPIs.

Attributes

GICM_SETSPI_NSR is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
RES0INTID

Bits [31:13]

Reserved, RES0.

INTID, bits [12:0]

This field is an alias of GICD_SETSPI_NSR.

Accessing GICM_SETSPI_NSR

Writes to this register have no effect if:

16-bit accesses to bits [15:0] of this register must be supported.

Note

A Secure access to this register can set the pending state of any valid SPI.

GICM_SETSPI_NSR can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
GIC DistributorMSI_base0x0040GICM_SETSPI_NSR

AccessesThis oninterface thisis interfaceaccessible areas follows: WO.


3020/09/2021 1511:3301; 092b4e1bbfbb45a293b198f9330c5f529ead2b0fd4a233ffbdfb36e47856c443a7ce9a85f5e501ca

Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

(old) htmldiff from-(new)