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The ATS1CPW characteristics are:
Performs stage 1 address translation as defined for PL1 and the current Security state, with permissions as if writing to the given virtual address.
This instruction is present only when AArch32 is supported. Otherwise, direct accesses to ATS1CPW are UNDEFINED.
ATS1CPW is a 32-bit System instruction.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Input address for translation |
Input address for translation. The resulting address can be read from the PAR.
This System instruction takes a VA as input. If EL2 is implemented and enabled in the current Security state, the resulting address is the IPA that is the output address of the stage 1 translation. Otherwise, the resulting address is a PA.
Accesses to this instruction use the following encodings in the System instruction encoding space:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0111 | 0b1000 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T7 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T7 == '1' then
AArch32.TakeHypTrapException(0x03);
else
AArch32.ATATS1CPW(R[t], TranslationStage_1, EL1, ATAccess_Write);]);
elsif PSTATE.EL == EL2 then
AArch32.ATATS1CPW(R[t], TranslationStage_1, EL1, ATAccess_Write);]);
elsif PSTATE.EL == EL3 then
if SCR.NS == '0' then
AArch32.ATATS1CPW(R[t], TranslationStage_1, EL3, ATAccess_Write);
else
AArch32.AT(R[t], TranslationStage_1, EL1, ATAccess_Write);]);
3020/09/2021 1511:3402; 092b4e1bbfbb45a293b198f9330c5f529ead2b0fd4a233ffbdfb36e47856c443a7ce9a85f5e501ca
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