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The GICD_INMIR<n>E characteristics are:
Holds whether the corresponding SPI in the extended SPI range has the non-maskable property.
This register is present only when FEAT_GICv3p1 is implemented and FEAT_GICv3_NMI is implemented. Otherwise, direct accesses to GICD_INMIR<n>E are RES0.
When GICD_TYPER.ESPI is 0 or GICD_TYPER.NMI is 0, these registers are RES0.
When GICD_TYPER.ESPI is 1: the number of implemented GICD_INMIR<n>E registers is (GICD_TYPER.ESPI_range+1). Registers are numbered from 0.
GICD_INMIR<n>E is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NMI31 | NMI30 | NMI29 | NMI28 | NMI27 | NMI26 | NMI25 | NMI24 | NMI23 | NMI22 | NMI21 | NMI20 | NMI19 | NMI18 | NMI17 | NMI16 | NMI15 | NMI14 | NMI13 | NMI12 | NMI11 | NMI10 | NMI9 | NMI8 | NMI7 | NMI6 | NMI5 | NMI4 | NMI3 | NMI2 | NMI1 | NMI0 |
Non-maskable property.
NMI<x> | Meaning |
---|---|
0b0 | Interrupt does not have the non-maskable property. |
0b1 | Interrupt has the the non-maskable property. |
If affinity routing is disabled for the Security state of an interrupt, the bit is RES0.
The reset behavior of this field is:
For INTID m, when DIV and MOD are the integer division and modulo operations:
When affinity routing is not enabled for the Security state of an interrupt in GICD_IGROUPR<n>E, the corresponding bit is RES0.
Bits corresponding to unimplemented interrupts are RAZ/WI.
Component | Frame | Offset | Instance |
---|---|---|---|
GIC Distributor | Dist_base | 0x3B00 + (4 * n) | GICD_INMIR<n>E |
Accesses on this interface are RW.
30/09/2021 15:34; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f
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