GICD_INMIR<n>, Non-maskable Interrupt Registers, x = 0 to 31, n = 0 - 31

The GICD_INMIR<n> characteristics are:

Purpose

Holds whether the corresponding SPI has the non-maskable property.

Configuration

This register is present only when FEAT_GICv3_NMI is implemented. Otherwise, direct accesses to GICD_INMIR<n> are RES0.

When GICR_TYPER.NMI is 0, this register is RES0.

The number of implemented GICD_INMIR<n> registers is (GICD_TYPER.ITLinesNumber+1). Registers are numbered from 0.

Attributes

GICD_INMIR<n> is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
NMI31NMI30NMI29NMI28NMI27NMI26NMI25NMI24NMI23NMI22NMI21NMI20NMI19NMI18NMI17NMI16NMI15NMI14NMI13NMI12NMI11NMI10NMI9NMI8NMI7NMI6NMI5NMI4NMI3NMI2NMI1NMI0

NMI<x>, bit [x], for x = 31 to 0

Non-maskable property.

NMI<x>Meaning
0b0

Interrupt does not have the non-maskable property.

0b1

Interrupt has the the non-maskable property.

The reset behavior of this field is:

For INTID m, when DIV and MOD are the integer division and modulo operations:

Accessing GICD_INMIR<n>

For SGIs and PPIs:

When affinity routing is not enabled for the Security state of an interrupt in GICD_IGROUPR<n>E, the corresponding bit is RES0.

Bits corresponding to unimplemented interrupts are RAZ/WI.

GICD_INMIR<n> can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
GIC DistributorDist_base0x0F80 + (4 * n)GICD_INMIR<n>

Accesses on this interface are RW.


30/09/2021 15:34; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f

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