The ID_AA64ZFR0_EL1 characteristics are:
Provides additional information about the implemented features of the AArch64 Scalable Vector Extension, when the ID_AA64PFR0_EL1.SVE field is not zero.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'.
Prior to the introduction of the features described by this register, this register was unnamed and reserved, RES0 from EL1, EL2, and EL3.
ID_AA64ZFR0_EL1 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | F64MM | F32MM | RES0 | I8MM | RES0 | ||||||||||||||||||||||||||
RES0 | BF16 | RES0 | SVEver |
Reserved, RES0.
Indicates support for SVE FP64 double-precision floating-point matrix multiplication instructions. Defined values are:
F64MM | Meaning |
---|---|
0b0000 |
FP64 matrix multiplication and related instructions are not implemented. |
0b0001 |
FP64 variant of the FMMLA instruction, and LD1RO* instructions are implemented. The 128-bit element variations of TRN1, TRN2, UZP1, UZP2, ZIP1, and ZIP2 are also implemented. |
All other values are reserved.
FEAT_F64MM implements the functionality identified by 0b0001.
From Armv8.2, the permitted values are 0b0000 and 0b0001.
Indicates support for the SVE FP32 single-precision floating-point matrix multiplication instruction. Defined values are:
F32MM | Meaning |
---|---|
0b0000 |
FP32 matrix multiplication instruction is not implemented. |
0b0001 |
FP32 variant of the FMMLA instruction is implemented. |
All other values are reserved.
FEAT_F32MM implements the functionality identified by 0b0001.
From Arm v8.2, the permitted values are 0b0000 and 0b0001.
Reserved, RES0.
Indicates support for SVE Int8 matrix multiplication instructions. Defined values are:
I8MM | Meaning |
---|---|
0b0000 |
Int8 matrix multiplication instructions are not implemented. |
0b0001 |
SMMLA, SUDOT, UMMLA, USMMLA, and USDOT instructions are implemented. |
All other values are reserved.
FEAT_I8MM implements the functionality identified by 0b0001.
When Advanced SIMD and SVE are both implemented, this field must return the same value as ID_AA64ISAR1_EL1.I8MM.
From Armv8.6, the only permitted value is 0b0001.
Reserved, RES0.
Indicates support for SVE BFloat16 instructions. Defined values are:
BF16 | Meaning |
---|---|
0b0000 |
BFloat16 instructions are not implemented. |
0b0001 |
BFCVT, BFCVTNT, BFDOT, BFMLALB, BFMLALT, and BFMMLA instructions are implemented. |
All other values are reserved.
FEAT_BF16 implements the functionality identified by 0b0001.
When Advanced SIMD and SVE are both implemented, this field must return the same value as ID_AA64ISAR1_EL1.BF16.
From Armv8.6, the only permitted value is 0b0001.
Reserved, RES0.
Indicates support for SVE. Defined values are:
SVEver | Meaning |
---|---|
0b0000 |
SVE instructions are implemented. |
All other values are reserved.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0000 | 0b0100 | 0b100 |
if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && (!IsZero(ID_AA64ZFR0_EL1) || boolean IMPLEMENTATION_DEFINED "ID_AA64ZFR0_EL1 trapped by HCR_EL2.TID3") && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_AA64ZFR0_EL1; elsif PSTATE.EL == EL2 then return ID_AA64ZFR0_EL1; elsif PSTATE.EL == EL3 then return ID_AA64ZFR0_EL1;
20/09/2021 11:02; d4a233ffbdfb36e47856c443a7ce9a85f5e501ca
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