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The PMEVFILTR<n> characteristics are:
External access to PMEVTYPER<n>_EL0[63:32].
External register PMEVFILTR<n> bits [31:0] are architecturally mapped to AArch64 System register PMEVTYPER<n>_EL0[63:32] when AArch64 is supported.
PMEVFILTR<n> is in the Core power domain.
This register is present only when FEAT_PMUv3_TH is implemented. Otherwise, direct accesses to PMEVFILTR<n> are RES0.
If FEAT_Debugv8p4 is implemented, the OPTIONAL Software Lock is not implemented.
If FEAT_DoPD is implemented, FEAT_DoubleLock is not implemented.
PMEVFILTR<n> is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TC | RES0 | TH |
Threshold Control. Defines the threshold function. In the description of this field, the value V is the value the event specified by PMEVTYPER<n>_EL0 would increment the counter by on a processor cycle if the threshold function is disabled. Comparisons treat V and PMEVFILTR<n>.TH as unsigned integer values.
TC | Meaning |
---|---|
0b000 | Not-equal. The counter increments by V on each processor cycle when V is not equal to PMEVFILTR<n>.TH. If PMEVFILTR<n>.TH is zero, the threshold function is disabled. |
0b001 | Not-equal, count. The counter increments by 1 on each processor cycle when V is not equal to PMEVFILTR<n>.TH. |
0b010 | Equals. The counter increments by V on each processor cycle when V is equal to PMEVFILTR<n>.TH. |
0b011 | Equals, count. The counter increments by 1 on each processor cycle when V is equal to PMEVFILTR<n>.TH. |
0b100 | Greater-than-or-equal. The counter increments by V on each processor cycle when V is PMEVFILTR<n>.TH or more. |
0b101 | Greater-than-or-equal, count. The counter increments by 1 on each processor cycle when V is PMEVFILTR<n>.TH or more. |
0b110 | Less-than. The counter increments by V on each processor cycle when V is less than PMEVFILTR<n>.TH. |
0b111 | Less-than, count. The counter increments by 1 on each processor cycle when V is less than PMEVFILTR<n>.TH. |
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Threshold value. Provides the unsigned value for the threshold function defined by PMEVFILTR<n>.TC.
If PMEVFILTR<n>.TC is 0b000 and PMEVFILTR<n>.TH is zero, then the threshold function is disabled.
If PMMIR.THWIDTH is less than 12, then bits PMEVFILTR<n>.TH[11:PMMIR.THWIDTH] are RES0. This accounts for the behavior when writing a value greater-than-or-equal-to 2(PMMIR.THWIDTH).
The reset behavior of this field is:
Reserved, RES0.
Component | Offset | Instance |
---|---|---|
PMU | 0xA00 + (4 * n) | PMEVFILTR<n> |
This interface is accessible as follows:
30/09/2021 15:34; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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