ERRCRICR1, Critical Error Interrupt Configuration Register 1

The ERRCRICR1 characteristics are:

Purpose

Critical Error Interrupt configuration register.

Configuration

This register is present only when (the Critical Error Interrupt is implemented or the implementation does not use the recommended layout for the ERRIRQCR<n> registers) and interrupt configuration registers are implemented. Otherwise, direct accesses to ERRCRICR1 are RES0.

ERRCRICR1 is implemented only as part of a memory-mapped group of error records.

Attributes

ERRCRICR1 is a 32-bit register.

Field descriptions

When the Critical Error Interrupt is implemented and the implementation uses the recommended layout for the ERRIRQCR<n> registers:

313029282726252423222120191817161514131211109876543210
DATA

DATA, bits [31:0]

Payload for the message signaled interrupt.

The reset behavior of this field is:

When the implementation does not use the recommended layout for the ERRIRQCR<n> registers:

313029282726252423222120191817161514131211109876543210
IMPLEMENTATION DEFINED

IMPLEMENTATION DEFINED, bits [31:0]

IMPLEMENTATION DEFINED.

Accessing ERRCRICR1

ERRCRICR1 can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
RAS0xEA8ERRCRICR1

Accesses on this interface are RW.


30/09/2021 15:34; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f

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