System Register XML
for Armv8.8
(2021-09)
30 September 2021
1. Introduction
This is the 2021-09 release
of the System registers XML for Armv8.8 A-profile architecture, describing:
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The AArch64 and AArch32 views of the System registers, including Debug, PMU, AMU, MPAM, Generic Timer, and GIC.
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The AArch64 and AArch32 system control operations.
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The memory-mapped Debug, CTI, PMU, AMU, MPAM, GIC, and Generic Timer registers.
The Proprietary Notice
gives details of the terms and conditions under which this package
is provided.
If you have comments on the content of this package, please send
them by e-mail to
support-aarchv8@arm.com. Give:
- The title, "System Register XML for Armv8.8".
- The version, "2021-09".
- A concise explanation of your comments.
Please see the Documentation for
more information on the general structure of these descriptions.
2. Contents
3. Release notes
Change history
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This is the first release of the System register XML that includes all the features introduced
by the Armv8.8 2021 Extensions. See: Features-in-A-profile.
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The accessibility pseudocode is updated to represent the generic timer registers accesses more
accurately.
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Pseudocode functions for AArch32 and AArch64 AT System instructions are added and called from
the System instruction accessibility pseudocode.
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GICR_VPROPBASER.Indirect field description is corrected from RES0 to RAZ/WI when GIC
implementations that only support flat tables.
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The HPFAR.FIPA field description is clarified to indicate the bits of the address it represents.
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The accessibility pseudocode for the following System registers and System instructions is
updated:
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AArch64: CNTV_TVAL_EL0, CNTHVS_TVAL_EL2, CNTHV_TVAL_EL2, ID_AA64MMFR2_EL1, ID_DFR1_EL1.
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AArch32: ATS1HR, ATS1HW, ICC_MSRE, MVBAR, NSACR, SDCR, SDER.
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Generic timer TVAL register accessibility is updated to respect the related ENABLE field on
read access.
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The EL3 accessibility for CNTVOFF is corrected.
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The field widths in the upper 24 bits of CNTSR are updated to align mismatched FCACK and FCREQ
fields.
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MDRAR_EL1.ROMADDR incorrect reset is removed.
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ID_AA64ISAR2_EL1.WFxT value 0b0010 is defined to indicate that the register number is recorded
in bits [9:5] of the ISS of ESR_ELx for trapped WFxT instructions.
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ICC_CTLR_EL3.RM description is clarified to remove ambiguity.
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The PMEVTYPER<n>.evtCount description is updated to clarify the behavior for events that
are reserved or not supported.
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The following fields are updated to clarify that execution timing of instructions in the
speculative sequence is not a function of data loaded under speculation:
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AArch64: ID_AA64PFR0_EL1.CSV3.
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AArch32: ID_PFR2.CSV3.
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Conditions when EDPCSR and PMPSCR return 0xFFFFFFF or an UNKNOWN value are relaxed.
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CNTKCTL_EL1 and CNTHCTL_EL2 are clarified to indicate that CNTVCT_EL0 and CNTPCT_EL0, when
part of the event stream, are seen from EL1 and EL2 respectively.
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The conditions previously rendered 'AArch64 is supported at the highest implemented Exception
level' and 'AArch32 is supported at EL0' are replaced by 'AArch64 is supported' and AArch32 is
supported.
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The description in PMCID2SR is updated to clarify when CONTEXIDR_EL2 is sampled.
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MPAMF_IDR.{PMG_MAX, PARTID_MAX} is updated to indicate that the value of each field is
permitted to vary between Non-secure and Secure instances of MPAM_IDR, and that in
MPAMF_IDR_s these fields are permitted to give the values for either the Non-secure or
Secure PARTID space.
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Reserved values of HTCR.HWU62, HTCR.HWU61, HTCR.HWU60, HTCR.HWU59 are corrected to be
Reserved, RAZ/WI instead of RES0.
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The defintion of HCR_EL2.DCT is updated to indicate that it is permitted to be cached in a
TLB.
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The SCTLR_EL2.EPAN field condition is corrected by removing the condition on HCR_EL2.TGE==1.
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GICR_ICFGR0 and GICR_ICFGR1 descriptions are clarified to indicate when the value is RAZ/WI.
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Relaxation is added in the MDSCR_EL1.{RXO, TXU} and DBGDSCRext.{RXO, TXU} fields to clarify
behavior when restoring invalid values to EDSCR through the OS save/restore mechanism.
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The access permissions of the External registers GITS_STATUSR and GITS_UMSIR are corrected to
be RW and RO respectively.
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The CPP RCTX and CPPRCTX descriptions are clarified to indicate that they cannot influence
speculative execution rather than preventing exploitative control of speculative execution.
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The PAR_EL1.ATTR field is clarified to indicate the actual implemented memory attributes can
be returned instead of the value that appears in the translation table descriptor.
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A note is added to CNTP_TVAL_EL0 to clarify that the calculations use the value of CNTPCT_EL0
as seen from the EL being accessed.
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HAS_NFU is added to the MPAMF_IDR external register.
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Many simple clarifications and corrections are also present, but are too small to be listed
here.
Known issues
All issues identified in the below list would be fixed in a future release.
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Recommendations for ERR<n>STATUS will be clarified.
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The reserved type for the HWU* fields will be reverted back to RES0 from RAZ/WI in the
following System registers:
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AArch64: TCR_EL1, TCR_EL2, TCR_EL3, VTCR_EL2.
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AArch32: TTBCR2, TTBCR.T2E, VTCR.
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Descriptions of the ID_AAPFR0_EL1.MPAM and ID_AAPFR1_EL1.MPAM_frac fields will be clarified.
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The SCTLR_EL2.EPAN field condition will be corrected to remove HCR_EL2.TGE.
Potential upcoming changes
Arm is constantly exploring ways to make the architecture presentation precise and clear. Towards
this, the following changes are expected in future releases (2021-12, 2022-03, 2022-06):
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Make the bit width clear, rather than contextual. For example:
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X[n, 32] or X[n, 64] or X[n, datawidth] vs. bits(datawidth) operand1 = X[n]
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Zeros(32), Replicate(element, 64 DIV esize) vs. Zeros(), Replicate(element), etc.
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In system register accessibility for register reads, for example, MRS, MRC, instructions: make
the register replace the return value today with register assignment to make this symmetric
with the writes. For example:
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X[t, 64] = SCTLR_EL1; instead of return SCTLR_EL1;
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Replace keywords IMPLEMENTATION_DEFINED, UNDEFINED, SEE, and UNPREDICTABLE with functions.
These are proposed to be removed as special language features and treated as ASL functions.
In addition, we are looking in improvements to the information that is provided in the XML. In some cases these changes may
impact users. Here is a list of areas where we may make change in a future release:
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When bits of two registers are architecturally mapped, it is captured in XML via (mapped_from_startbit,
mapped_from_endbit) and (mapped_to_startbit, mapped_to_endbit) tags. This does not allow for succinctly
describing a non-contiguous mapping. We are looking into refining the presentation in a future release.
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We are looking at separating accessors (instructions/external accesses) from registers. This is likely to impact
"Index by Encoding", "External registers by offset" and may introduce separate pages for instructions/accessors
vs. the registers. This may impact the schema and the presentation of the content.
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Some changes to register names may be introduced and there may be changes to the number of registers or names.
The instructions accessing registers would be unchanged preserving the architecture intent.
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Register accesses that always look like simple reads or writes might be extended to have some ASL expressions.
Where register accesses cause additional side effects, ASL functions that describe these effects would be added.
Currently these details are only expressed in text.
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We are considering the obsoletion of some DTD elements based on usage and analysis.
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The instruction encoding tables currently present values as binary values, with the prefix "0b". We are
considering whether these values are better represented in a syntax compatible with pseudocode.
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The reset information in the 'Configuration' section of some register descriptions have incorrect information,
and must not be relied upon. Please refer to the field descriptions for the correct reset information. The
information in the 'Configuration' section will be removed in a future release.
4. Documentation
General
A description within the XML contains the following sections:
- Purpose
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A short description of the purpose of the register in the
Armv8 Architecture.
- Configuration
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How the register is architecturally mapped onto another System
register or a memory-mapped register. If the configuration of
the PE affects the implementation of the register, then
information about this is also included here.
- Attributes
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The size of the register.
- Field descriptions
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The register diagram and a description of the behavior of each field within the register.
Memory-mapped registers
A memory-mapped register description also contains the following
sections:
- Accessing ...
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The address or offset of the register in the memory map, and
the accessibility.
System registers
A System register description also contains an "Accessing ..." section, that includes:
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The assembler syntax for the instructions used to access the
register, and how the instruction is encoded.
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Pseudocode that describes the execution of all instructions
used to access the register, including information about
traps and enables that apply upon that access.
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For some System registers, additional text is provided which
gives extra information regarding the access to the
register.
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The accessibility pseudocode for a register assumes that
that register is implemented and that all features which
affects its accesses are implemented. In most cases, the
behavior upon access to a register is determined in part or
in whole by the Exception level at which it is accessed.