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HCRX_EL2, Extended Hypervisor Configuration Register

The HCRX_EL2 characteristics are:

Purpose

Provides configuration controls for virtualization, including defining whether various operations are trapped to EL2.

Configuration

This register is present only when FEAT_HCX is implemented. Otherwise, direct accesses to HCRX_EL2 are UNDEFINED.

If EL2 is not implemented, this register is RES0 from EL3.

The bits in this register behave as if they are 0 for all purposes other than direct reads of the register if:

Attributes

HCRX_EL2 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0MSCEnFGTnXSMCE2FnXSCMOWEnASRVFNMIEnALSVINMIEnAS0TALLINTRES0FGTnXSFnXSEnASREnALSEnAS0

Bits [63:125]

Reserved, RES0.

MSCEn, bit [11]
When FEAT_MOPS is implemented:

Memory Set and Memory Copy instructions Enable. Enables execution of the CPY*, SETG*, SETP*, SETM*, and SETE* instructions at EL1 or EL0.

MSCEnMeaning
0b0

Execution of the Memory Copy and Memory Set instructions is UNDEFINED at EL1 or EL0.

0b1

This control does not cause any instructions to be UNDEFINED.

If EL2 is not implemented or enabled, this bit behaves as if it is 1.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

MCE2, bit [10]
When FEAT_MOPS is implemented:

Controls Memory Copy and Memory Set exceptions generated as part of attempting to execute the Memory Copy and Memory Set instructions from EL1.

MCE2Meaning
0b0

Memory Copy and Memory Set exceptions generated from EL1 are taken to EL1.

0b1

Memory Copy and Memory Set exceptions generated from EL1 are taken to EL2.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

CMOW, bit [9]
When FEAT_CMOW is implemented:

Controls cache maintenance instruction permission for the following instructions executed at EL1 or EL0.

CMOWMeaning
0b0

These instructions executed at EL1 or EL0 with stage 2 read permission, but without stage 2 write permission do not generate a stage 2 permission fault.

0b1

These instructions executed at EL1 or EL0, if enabled as a result of SCTLR_EL1.UCI==1, with stage 2 read permission, but without stage 2 write permission generate a stage 2 permission fault.

For this control, stage 2 has write permission if S2AP[1] is 1 or DBM is 1 in the stage 2 descriptor. The instructions do not cause an update to the dirty state.

This bit is permitted to be cached in a TLB.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

VFNMI, bit [8]
When FEAT_NMI is implemented:

Virtual FIQ Interrupt with Superpriority. Enables signaling of virtual FIQ interrupts with Superpriority.

VFNMIMeaning
0b0

When HCR_EL2.VF is 1, a signaled pending virtual FIQ interrupt does not have Superpriority.

0b1

When HCR_EL2.VF is 1, a signaled pending virtual FIQ interrupt has Superpriority.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

VINMI, bit [7]
When FEAT_NMI is implemented:

Virtual IRQ Interrupt with Superpriority. Enables signaling of virtual IRQ interrupts with Superpriority.

VINMIMeaning
0b0

When HCR_EL2.VI is 1, a signaled pending virtual IRQ interrupt does not have Superpriority.

0b1

When HCR_EL2.VI is 1, a signaled pending virtual IRQ interrupt has Superpriority.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

TALLINT, bit [6]
When FEAT_NMI is implemented:

Trap MSR writes of ALLINT at EL1 using AArch64 to EL2, when EL2 is implemented and enabled in the current Security state, reported using EC syndrome value 0x18.

TALLINTMeaning
0b0

MSR writes of ALLINT are not trapped by this mechanism.

0b1

MSR writes of ALLINT at EL1 using AArch64 are trapped to EL2.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Bit [5]

Reserved, RES0.

FGTnXS, bit [4]
When FEAT_XS is implemented:

Determines if the fine-grained traps in HFGITR_EL2 that apply to each of the TLBI maintenance instructions that are accessible at EL1 also apply to the corresponding TLBI maintenance instructions with the nXS qualifier.

FGTnXSMeaning
0b0

The fine-grained trap in the HFGITR_EL2 that applies to a TLBI maintenance instruction at EL1 also applies to the corresponding TLBI instruction with the nXS qualifier at EL1.

0b1

The fine-grained trap in the HFGITR_EL2 that applies to a TLBI maintenance instruction at EL1 does not apply to the corresponding TLBI instruction with the nXS qualifier at EL1.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

FnXS, bit [3]
When FEAT_XS is implemented:

Determines the behavior of TLBI instructions affected by the XS attribute.

This control bit also determines whether an AArch64 DSB instruction behaves as a DSB instruction with an nXS qualifier when executed at EL0 and EL1.

FnXSMeaning
0b0

This control does not have any effect on the behavior of the TLBI maintenance instructions.

0b1

A TLBI maintenance instruction without the nXS qualifier executed at EL1 behaves in the same way as the corresponding TLBI maintenance instruction with the nXS qualifier.

An AArch64 DSB instruction executed at EL1 or EL0 behaves in the same way as the corresponding DSB instruction with the nXS qualifier executed at EL1 or EL0.

This bit is permitted to be cached in a TLB.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

EnASR, bit [2]
When FEAT_LS64 is implemented:

When HCR_EL2.{E2H, TGE} != {1, 1}, traps execution of an ST64BV instruction at EL0 or EL1 to EL2.

EnASRMeaning
0b0

Execution of an ST64BV instruction at EL0 is trapped to EL2 if the execution is not trapped by SCTLR_EL1.EnASR.

Execution of an ST64BV instruction at EL1 is trapped to EL2.

0b1

This control does not cause any instructions to be trapped.

A trap of an ST64BV instruction is reported using an ESR_ELx.EC value of 0x0A, with an ISS code of 0x0000000.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

EnALS, bit [1]
When FEAT_LS64 is implemented:

When HCR_EL2.{E2H, TGE} != {1, 1}, traps execution of an LD64B or ST64B instruction at EL0 or EL1 to EL2.

EnALSMeaning
0b0

Execution of an LD64B or ST64B instruction at EL0 is trapped to EL2 if the execution is not trapped by SCTLR_EL1.EnALS.

Execution of an LD64B or ST64B instruction at EL1 is trapped to EL2.

0b1

This control does not cause any instructions to be trapped.

A trap of an LD64B or ST64B instruction is reported using an ESR_ELx.EC value of 0x0A, with an ISS code of 0x0000002.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

EnAS0, bit [0]
When FEAT_LS64 is implemented:

When HCR_EL2.{E2H, TGE} != {1, 1}, traps execution of an ST64BV0 instruction at EL0 or EL1 to EL2.

EnAS0Meaning
0b0

Execution of an ST64BV0 instruction at EL0 is trapped to EL2 if the execution is not trapped by SCTLR_EL1.EnAS0.

Execution of an ST64BV0 instruction at EL1 is trapped to EL2.

0b1

This control does not cause any instructions to be trapped.

A trap of an ST64BV0 instruction is reported using an ESR_ELx.EC value of 0x0A, with an ISS code of 0x0000001.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Accessing HCRX_EL2

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, HCRX_EL2

op0op1CRnCRmop2
0b110b1000b00010b00100b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then return NVMem[0xA0]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.HXEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.HXEn == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return HCRX_EL2; elsif PSTATE.EL == EL3 then return HCRX_EL2;

MSR HCRX_EL2, <Xt>

op0op1CRnCRmop2
0b110b1000b00010b00100b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then NVMem[0xA0] = X[t]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.HXEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.HXEn == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else HCRX_EL2 = X[t]; elsif PSTATE.EL == EL3 then HCRX_EL2 = X[t];


3020/09/2021 1511:3301; 092b4e1bbfbb45a293b198f9330c5f529ead2b0fd4a233ffbdfb36e47856c443a7ce9a85f5e501ca

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