The NMRR characteristics are:
Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in the PRRR.
Used in conjunction with the PRRR.
AArch32 System register NMRR bits [31:0] are architecturally mapped to AArch64 System register MAIR_EL1[63:32] when EL3 is not implemented or EL3 is using AArch64.
AArch32 System register NMRR bits [31:0] are architecturally mapped to AArch32 System register MAIR1[31:0] when EL3 is not implemented or EL3 is using AArch64.
AArch32 System register NMRR bits [31:0] (NMRR_S) are architecturally mapped to AArch32 System register MAIR1[31:0] (MAIR1_S) when EL3 is using AArch32.
AArch32 System register NMRR bits [31:0] (NMRR_NS) are architecturally mapped to AArch32 System register MAIR1[31:0] (MAIR1_NS) when EL3 is using AArch32.
This register is present only when AArch32 is supported. Otherwise, direct accesses to NMRR are UNDEFINED.
MAIR1 and NMRR are the same register, with a different view depending on the value of TTBCR.EAE:
NMRR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OR7 | OR6 | OR5 | OR4 | OR3 | OR2 | OR1 | OR0 | IR7 | IR6 | IR5 | IR4 | IR3 | IR2 | IR1 | IR0 |
Outer Cacheable property mapping for memory attributes n, if the region is mapped as Normal memory by the PRRR.TR<n> entry. n is the value of the TEX[0], C, and B bits concatenated.
OR<n> | Meaning |
---|---|
0b00 |
Region is Non-cacheable. |
0b01 |
Region is Write-Back, Write-Allocate. |
0b10 |
Region is Write-Through, no Write-Allocate. |
0b11 |
Region is Write-Back, no Write-Allocate. |
The meaning of the field with n = 6 is IMPLEMENTATION DEFINED and might differ from the meaning given here. This is because the meaning of the attribute combination {TEX[0] = 1, C = 1, B = 0} is IMPLEMENTATION DEFINED.
When FEAT_XS is implemented, stage 1 Outer Write-Back Cacheable memory types have the XS attribute set to 0.
The reset behavior of this field is:
Inner Cacheable property mapping for memory attributes n, if the region is mapped as Normal memory by the PRRR.TR<n> entry. n is the value of the TEX[0], C, and B bits concatenated.
IR<n> | Meaning |
---|---|
0b00 |
Region is Non-cacheable. |
0b01 |
Region is Write-Back, Write-Allocate. |
0b10 |
Region is Write-Through, no Write-Allocate. |
0b11 |
Region is Write-Back, no Write-Allocate. |
The meaning of the field with n = 6 is IMPLEMENTATION DEFINED and might differ from the meaning given here. This is because the meaning of the attribute combination {TEX[0] = 1, C = 1, B = 0} is IMPLEMENTATION DEFINED.
When FEAT_XS is implemented, stage 1 Inner Write-Back Cacheable memory types have the XS attribute set to 0.
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b1010 | 0b0010 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T10 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T10 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TRVM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TRVM == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) then if TTBCR.EAE == '1' then return MAIR1_NS; else return NMRR_NS; else if TTBCR.EAE == '1' then return MAIR1; else return NMRR; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && ELUsingAArch32(EL3) then if TTBCR.EAE == '1' then return MAIR1_NS; else return NMRR_NS; else if TTBCR.EAE == '1' then return MAIR1; else return NMRR; elsif PSTATE.EL == EL3 then if TTBCR.EAE == '1' then if SCR.NS == '0' then return MAIR1_S; else return MAIR1_NS; else if SCR.NS == '0' then return NMRR_S; else return NMRR_NS;
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b1010 | 0b0010 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T10 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T10 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TVM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TVM == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) then if TTBCR.EAE == '1' then MAIR1_NS = R[t]; else NMRR_NS = R[t]; else if TTBCR.EAE == '1' then MAIR1 = R[t]; else NMRR = R[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && ELUsingAArch32(EL3) then if TTBCR.EAE == '1' then MAIR1_NS = R[t]; else NMRR_NS = R[t]; else if TTBCR.EAE == '1' then MAIR1 = R[t]; else NMRR = R[t]; elsif PSTATE.EL == EL3 then if SCR.NS == '0' && CP15SDISABLE == HIGH then UNDEFINED; elsif SCR.NS == '0' && CP15SDISABLE2 == HIGH then UNDEFINED; else if TTBCR.EAE == '1' then if SCR.NS == '0' then MAIR1_S = R[t]; else MAIR1_NS = R[t]; else if SCR.NS == '0' then NMRR_S = R[t]; else NMRR_NS = R[t];
30/09/2021 15:33; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f
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