AMCNTENSET0, Activity Monitors Count Enable Set Register 0

The AMCNTENSET0 characteristics are:

Purpose

Enable control bits for the architected activity monitors event counters, AMEVCNTR0<n>.

Configuration

External register AMCNTENSET0 bits [31:0] are architecturally mapped to AArch64 System register AMCNTENSET0_EL0[31:0].

External register AMCNTENSET0 bits [31:0] are architecturally mapped to AArch32 System register AMCNTENSET0[31:0].

The power domain of AMCNTENSET0 is IMPLEMENTATION DEFINED.

This register is present only when FEAT_AMUv1 is implemented. Otherwise, direct accesses to AMCNTENSET0 are RES0.

Attributes

AMCNTENSET0 is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
RES0RAZ/WIP3P2P1P0

Bits [31:16]

Reserved, RES0.

Bits [15:4]

Reserved, RAZ/WI.

This field is reserved for additional architected activity monitor event counters, which Arm might define in a future version of the Activity Monitors architecture.

P<n>, bit [n], for n = 3 to 0

Activity monitor event counter enable bit for AMEVCNTR0<n>.

Note

AMCGCR.CG0NC identifies the number of architected activity monitor event counters. In an implementation that includes FEAT_AMUv1, the number of architected activity monitor event counters is 4.

Possible values of each bit are:

P<n>Meaning
0b0

When read, means that AMEVCNTR0<n> is disabled.

0b1

When read, means that AMEVCNTR0<n> is enabled.

The reset behavior of this field is:

Accessing AMCNTENSET0

AMCNTENSET0 can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
AMU0xC00AMCNTENSET0

Accesses on this interface are RO.


30/09/2021 15:34; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f

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