The MPAMF_ECR characteristics are:
MPAMF_ECR is a 32-bit read/write register that controls MPAM error interrupts for this MSC.
MPAMF_ECR_s controls Secure MPAM error handling. MPAMF_ECR_ns controls Non-secure MPAM error handling.
The power domain of MPAMF_ECR is IMPLEMENTATION DEFINED.
This register is present only when FEAT_MPAM is implemented. Otherwise, direct accesses to MPAMF_ECR are RES0.
If an MSC cannot encounter any of the error conditions listed in 'Errors in MSCs' in Arm® Architecture Reference Manual Supplement, Memory System Resource Partitioning and Monitoring (MPAM), for Armv8-A (ARM DDI 0598), both the MPAMF_ESR and MPAMF_ECR must be RAZ/WI.
The power and reset domain of each MSC component is specific to that component.
MPAMF_ECR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | INTEN |
Reserved, RES0.
Interrupt Enable.
INTEN | Meaning |
---|---|
0b0 |
MPAM error interrupts are not signaled. |
0b1 |
MPAM error interrupts are signaled. |
This register is within the MPAM feature page memory frames. In a system that supports Secure and Non-secure memory maps, there must be both Secure and Non-secure MPAM feature pages.
MPAMF_ECR_s must be accessible from the Secure MPAM feature page. MPAMF_ECR_ns must be accessible from the Non-secure MPAM feature page.
MPAMF_ECR_s and MPAMF_ECR_ns must be separate registers. The Secure instance (MPAMF_ECR_s) accesses the error interrupt controls used for Secure PARTIDs, and the Non-secure instance (MPAMF_ECR_ns) accesses the error interrupt controls used for Non-secure PARTIDs.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_s | 0x00F0 | MPAMF_ECR_s |
Accesses on this interface are RW.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_ns | 0x00F0 | MPAMF_ECR_ns |
Accesses on this interface are RW.
30/09/2021 15:34; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f
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