The MPIDR_EL1 characteristics are:
In a multiprocessor system, provides an additional PE identification mechanism for scheduling purposes.
AArch64 System register MPIDR_EL1 bits [31:0] are architecturally mapped to AArch32 System register MPIDR[31:0].
In a uniprocessor system, Arm recommends that each Aff<n> field of this register returns a value of 0.
MPIDR_EL1 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | Aff3 | ||||||||||||||||||||||||||||||
RES1 | U | RES0 | MT | Aff2 | Aff1 | Aff0 |
Reserved, RES0.
Affinity level 3. See the description of Aff0 for more information.
Aff3 is not supported in AArch32 state.
Reserved, RES1.
Indicates a Uniprocessor system, as distinct from PE 0 in a multiprocessor system.
U | Meaning |
---|---|
0b0 |
Processor is part of a multiprocessor system. |
0b1 |
Processor is part of a uniprocessor system. |
Reserved, RES0.
Indicates whether the lowest level of affinity consists of logical PEs that are implemented using a multithreading type approach. See the description of Aff0 for more information about affinity levels.
MT | Meaning |
---|---|
0b0 |
Performance of PEs with different affinity level 0 values, and the same values for affinity level 1 and higher, is largely independent. |
0b1 |
Performance of PEs with different affinity level 0 values, and the same values for affinity level 1 and higher, is very interdependent. |
Affinity level 2. See the description of Aff0 for more information.
Affinity level 1. See the description of Aff0 for more information.
Affinity level 0. This is the affinity level that is most significant for determining PE behavior. Higher affinity levels are increasingly less significant in determining PE behavior. The assigned value of the MPIDR.{Aff2, Aff1, Aff0} or MPIDR_EL1.{Aff3, Aff2, Aff1, Aff0} set of fields of each PE must be unique within the system as a whole.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0000 | 0b0000 | 0b101 |
if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.MPIDR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() then return VMPIDR_EL2; else return MPIDR_EL1; elsif PSTATE.EL == EL2 then return MPIDR_EL1; elsif PSTATE.EL == EL3 then return MPIDR_EL1;
20/09/2021 11:02; d4a233ffbdfb36e47856c443a7ce9a85f5e501ca
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