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PMMIR, Performance Monitors Machine Identification Register

The PMMIR characteristics are:

Purpose

Describes Performance Monitors parameters specific to the implementation.

Configuration

PMMIR is in the Core power domain.

This register is present only when FEAT_PMUv3p4 is implemented. Otherwise, direct accesses to PMMIR are RES0.

Attributes

PMMIR is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
RES0THWIDTHBUS_WIDTHBUS_WIDTHBUS_SLOTSBUS_SLOTSSLOTSSLOTS

Bits [31:2420]

Reserved, RES0.

THWIDTH, bits [23:20]

PMEVFILTR<n>.TH width. Indicates implementation of the FEAT_PMUv3_TH feature, and, if implemented, the size of the PMEVFILTR<n>.TH field.

THWIDTHMeaning
0b0000

FEAT_PMUv3_TH is not implemented.

0b0001

1 bit. PMEVFILTR<n>.TH[11:1] are RES0.

0b0010

2 bits. PMEVFILTR<n>.TH[11:2] are RES0.

0b0011

3 bits. PMEVFILTR<n>.TH[11:3] are RES0.

0b0100

4 bits. PMEVFILTR<n>.TH[11:4] are RES0.

0b0101

5 bits. PMEVFILTR<n>.TH[11:5] are RES0.

0b0110

6 bits. PMEVFILTR<n>.TH[11:6] are RES0.

0b0111

7 bits. PMEVFILTR<n>.TH[11:7] are RES0.

0b1000

8 bits. PMEVFILTR<n>.TH[11:8] are RES0.

0b1001

9 bits. PMEVFILTR<n>.TH[11:9] are RES0.

0b1010

10 bits. PMEVFILTR<n>.TH[11:10] are RES0.

0b1011

11 bits. PMEVFILTR<n>.TH[11] is RES0.

0b1100

12 bits.

All other values are reserved.

If FEAT_PMUv3_TH is not implemented, this field is zero.

Otherwise, the largest value that can be written to PMEVFILTR<n>.TH is 2(PMMIR.THWIDTH) minus one.

Access to this field is RO.

BUS_WIDTH, bits [19:16]

Bus width. Indicates the number of bytes each BUS_ACCESS event relates to. Encoded as Log2(number of bytes), plus one. Defined values are:

BUS_WIDTHMeaning
0b0000

The information is not available.

0b0011

Four bytes.

0b0100

8 bytes.

0b0101

16 bytes.

0b0110

32 bytes.

0b0111

64 bytes.

0b1000

128 bytes.

0b1001

256 bytes.

0b1010

512 bytes.

0b1011

1024 bytes.

0b1100

2048 bytes.

All other values are reserved.

Each transfer is up to this number of bytes. An access might be smaller than the bus width.

When this field is nonzero, each access counted by BUS_ACCESS is at most BUS_WIDTH bytes. An implementation might treat a wide bus as multiple narrower buses, such that a wide access on the bus increments the BUS_ACCESS counter by more than one.

Access to this field is RO.

BUS_SLOTS, bits [15:8]

Bus count. The largest value by which the BUS_ACCESS event might increment by in a single BUS_CYCLES cycle.

When this field is nonzero, the largest value by which the BUS_ACCESS event might increment in a single BUS_CYCLES cycle is BUS_SLOTS.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

SLOTS, bits [7:0]

Operation width. The largest value by which the STALL_SLOT event might increment by in a single cycle. If the STALL_SLOT event is not implemented, this field mightmust readnot asbe zero.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Accessing PMMIR

If the Core power domain is off or in a low-power state, access on this interface returns an Error.

PMMIR can be accessed through the external debug interface:

ComponentOffsetInstance
PMU0xE40PMMIR

This interface is accessible as follows:


3020/09/2021 1511:3402; 092b4e1bbfbb45a293b198f9330c5f529ead2b0fd4a233ffbdfb36e47856c443a7ce9a85f5e501ca

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