The HPFAR_EL2 characteristics are:
Holds the faulting IPA for some aborts on a stage 2 translation taken to EL2.
AArch64 System register HPFAR_EL2 bits [31:0] are architecturally mapped to AArch32 System register HPFAR[31:0].
If EL2 is not implemented, this register is RES0 from EL3.
This register has no effect if EL2 is not enabled in the current Security state.
The HPFAR_EL2 is written for:
For all other exceptions taken to EL2, this register is UNKNOWN.
The address held in this register is an address accessed by the instruction fetch or data access that caused the exception that gave rise to the Instruction Abort or Data Abort. It is the lowest address that gave rise to the fault. Where different faults from different addresses arise from the same instruction, such as for an instruction that loads or stores an unaligned address that crosses a page boundary, the architecture does not prioritize between those different faults.
HPFAR_EL2 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NS | RES0 | FIPA | |||||||||||||||||||||||||||||
FIPA | RES0 |
Execution at EL1 or EL0 makes HPFAR_EL2 become UNKNOWN.
Faulting IPA address space.
NS | Meaning |
---|---|
0b0 |
Faulting IPA is from the Secure IPA space. |
0b1 |
Faulting IPA is from the Non-secure IPA space. |
For Data Aborts or Instruction Aborts taken to Non-secure EL2:
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
38 | 37 | 36 | 35 | 34 | 33 | 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIPA |
Bits [51:12] of the Faulting Intermediate Physical Address.
For implementations with fewer than 52 physical address bits, the corresponding upper bits in this field are RES0.
The reset behavior of this field is:
38 | 37 | 36 | 35 | 34 | 33 | 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | FIPA |
Reserved, RES0.
Bits[47:12] Faulting Intermediate Physical Address.
For implementations with fewer than 48 physical address bits, the corresponding upper bits in this field are RES0.
The reset behavior of this field is:
Reserved, RES0.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0110 | 0b0000 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then return HPFAR_EL2; elsif PSTATE.EL == EL3 then return HPFAR_EL2;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0110 | 0b0000 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then HPFAR_EL2 = X[t]; elsif PSTATE.EL == EL3 then HPFAR_EL2 = X[t];
30/09/2021 15:33; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f
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