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The GICR_ICFGR0 characteristics are:
Determines whether the corresponding SGI is edge-triggered or level-sensitive.
A copy of this register is provided for each Redistributor.
GICR_ICFGR0 is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Int_config15 | Int_config14 | Int_config13 | Int_config12 | Int_config11 | Int_config10 | Int_config9 | Int_config8 | Int_config7 | Int_config6 | Int_config5 | Int_config4 | Int_config3 | Int_config2 | Int_config1 | Int_config0 |
Indicates whether the is level-sensitive or edge-triggered.
Int_config<x> | Meaning |
---|---|
0b00 | Corresponding interrupt is level-sensitive. |
0b10 | Corresponding interrupt is edge-triggered. |
For SGIs, arethis field always indidicates edge-triggered.
When the interrupt is visible to the current Security state, aA read of this bit always returns the correct value to indicate the interrupt triggering method.
The reset behavior of this field is:
This register is used when affinity routing is enabled.
When affinity routing is disabled for the Security state of an interrupt, the field for that interrupt is RES0 and an implementation is permitted to make the field RAZ/WI in this case. Equivalent functionality is provided by GICD_ICFGR<n> with n=0.
When GICD_CTLR.DS==0, a register bit that corresponds to a Group 0 or Secure Group 1 interrupt is RAZ/WI to Non-secure accesses.
Component | Frame | Offset | Instance |
---|---|---|---|
GIC Redistributor | SGI_base | 0x0C00 | GICR_ICFGR0 |
AccessesThis oninterface thisis interfaceaccessible areas follows: RW.
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