The AMCGCR characteristics are:
Provides information on the number of activity monitor event counters implemented within each counter group.
External register AMCGCR bits [31:0] are architecturally mapped to AArch64 System register AMCGCR_EL0[31:0].
External register AMCGCR bits [31:0] are architecturally mapped to AArch32 System register AMCGCR[31:0].
The power domain of AMCGCR is IMPLEMENTATION DEFINED.
This register is present only when FEAT_AMUv1 is implemented. Otherwise, direct accesses to AMCGCR are RES0.
AMCGCR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | CG1NC | CG0NC |
Reserved, RES0.
Counter Group 1 Number of Counters. The number of counters in the auxiliary counter group.
In an implementation that includes FEAT_AMUv1, the permitted range of values is 0 to 16.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Counter Group 0 Number of Counters. The number of counters in the architected counter group.
Reads as 0x04.
Access to this field is RO.
Component | Offset | Instance |
---|---|---|
AMU | 0xCE0 | AMCGCR |
Accesses on this interface are RO.
20/09/2021 11:02; d4a233ffbdfb36e47856c443a7ce9a85f5e501ca
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