CNTTIDR, Counter-timer Timer ID Register

The CNTTIDR characteristics are:

Purpose

Indicates the implemented timers in the memory map, and their features. For each value of N from 0 to 7 it indicates whether:

Configuration

The power domain of CNTTIDR is IMPLEMENTATION DEFINED.

For more information, see 'Power and reset domains for the system level implementation of the Generic Timer'.

Attributes

CNTTIDR is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
Frame7Frame6Frame5Frame4Frame3Frame2Frame1Frame0

Frame<n>, bits [4n+3:4n], for n = 7 to 0

A 4-bit field indicating the features of frame CNTBase<n>.

Bit[3] of the field is RES0.

Bit[2], the FEL0 subfield, indicates whether frame CNTBase<n> has a second view, CNTEL0Base<n>. The possible values of this bit are:

Bit[2]Meaning
0b0Frame<n> does not have a second view. The CNTEL0ACR register in the first view of the frame isRES0
0b1Frame<n> has a second view, CNTEL0Base<n>.

If bit[0] is 0, bit[2] is RES0.

Bit[1], the FVI subfield, indicates whether both:

The possible values of bit[1] are:

Bit[1]Meaning
0b0Frame<n> does not have virtual capability. The virtual time and offset registers areRES0.
0b1Frame<n> has virtual capability. The virtual time and offset registers are implemented

If bit[0] is 0, bit[1] is RES0.

Bit[0], the FI subfield, indicates whether frame CNTBase<n> is implemented. The possible values of this bit are:

Bit[0]Meaning
0b0Frame<n> is not implemented. All registers associated with the frame areRES0.
0b1Frame<n> is implemented

Accessing CNTTIDR

In a system that recognizes two Security states this register is accessible by both Secure and Non-secure accesses.

CNTTIDR can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
TimerCNTCTLBase0x008CNTTIDR

Accesses on this interface are RO.


20/09/2021 11:02; d4a233ffbdfb36e47856c443a7ce9a85f5e501ca

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