The PMCNTENCLR_EL0 characteristics are:
Disables the Cycle Count Register, PMCCNTR_EL0, and any implemented event counters PMEVCNTR<n>. Reading this register shows which counters are enabled.
External register PMCNTENCLR_EL0 bits [31:0] are architecturally mapped to AArch64 System register PMCNTENCLR_EL0[31:0].
External register PMCNTENCLR_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMCNTENCLR[31:0].
PMCNTENCLR_EL0 is in the Core power domain.
PMCNTENCLR_EL0 is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
C | P30 | P29 | P28 | P27 | P26 | P25 | P24 | P23 | P22 | P21 | P20 | P19 | P18 | P17 | P16 | P15 | P14 | P13 | P12 | P11 | P10 | P9 | P8 | P7 | P6 | P5 | P4 | P3 | P2 | P1 | P0 |
PMCCNTR_EL0 disable bit. Disables the cycle counter register. Possible values are:
C | Meaning |
---|---|
0b0 |
When read, means the cycle counter is disabled. When written, has no effect. |
0b1 |
When read, means the cycle counter is enabled. When written, disables the cycle counter. |
The reset behavior of this field is:
Event counter disable bit for PMEVCNTR<n>_EL0.
If PMCFGR.N is less than 31, bits [30:PMCFGR.N] are RAZ/WI.
P<n> | Meaning |
---|---|
0b0 |
When read, means that PMEVCNTR<n>_EL0 is disabled. When written, has no effect. |
0b1 |
When read, means that PMEVCNTR<n>_EL0 is enabled. When written, disables PMEVCNTR<n>_EL0. |
The reset behavior of this field is:
SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.
Component | Offset | Instance |
---|---|---|
PMU | 0xC20 | PMCNTENCLR_EL0 |
This interface is accessible as follows:
30/09/2021 15:33; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f
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