LDLAR

Load LOAcquire Register loads a 32-bit word or 64-bit doubleword from memory, and writes it to a register. The instruction also has memory ordering semantics as described in Load LOAcquire, Store LORelease. For information about memory accesses, see Load/Store addressing modes.

No offset
(ARMv8.1)

313029282726252423222120191817161514131211109876543210
1x001000110(1)(1)(1)(1)(1)0(1)(1)(1)(1)(1)RnRt
sizeLRso0Rt2

32-bit (size == 10)

LDLAR <Wt>, [<Xn|SP>{,#0}]

64-bit (size == 11)

LDLAR <Xt>, [<Xn|SP>{,#0}]

integer n = UInt(Rn); integer t = UInt(Rt); integer elsize = 8 << UInt(size); integer regsize = if elsize == 64 then 64 else 32;

Assembler Symbols

<Wt>

Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xt>

Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

Operation

bits(64) address; bits(elsize) data; constant integer dbytes = elsize DIV 8; if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n]; data = Mem[address, dbytes, AccType_LIMITEDORDERED]; X[t] = ZeroExtend(data, regsize);


Internal version only: isa v25.07, AdvSIMD v23.0, pseudocode v31.3

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