ISA_v82A_A64_xml_00bet3.1 (old) | htmldiff from-ISA_v82A_A64_xml_00bet3.1 | (new) ISA_v82A_A64_xml_00bet3.1_OPT |
Load Exclusive Register derives an address from a base register value, loads a 32-bit word or a 64-bit doubleword from memory, and writes it to a register. The memory access is atomic. The PE marks the physical address being accessed as an exclusive access. This exclusive access mark is checked by Store Exclusive instructions. See Synchronization and semaphores. For information about memory accesses see Load/Store addressing modes.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | x | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | (1) | (1) | (1) | (1) | (1) | 0 | (1) | (1) | (1) | (1) | (1) | Rn | Rt | ||||||||
size | L | Rs | o0 | Rt2 |
integer n = UInt(Rn);
integer t = UInt(Rt);
integer elsize = 8 <<integer t2 = UInt(size);
integer regsize = if elsize == 64 then 64 else 32;(Rt2); // ignored by load/store single register
integer s =UInt(Rs); // ignored by all loads and store-release
AccType acctype = if o0 == '1' then AccType_ORDERED else AccType_ATOMIC;
boolean pair = FALSE;
MemOp memop = if L == '1' then MemOp_LOAD else MemOp_STORE;
integer elsize = 8 << UInt(size);
integer regsize = if elsize == 64 then 64 else 32;
integer datasize = if pair then elsize * 2 else elsize;
<Wt> | Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field. |
<Xt> | Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field. |
<Xn|SP> | Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
bits(64) address;
bits(elsize) data;
constant integer dbytes = elsize DIV 8;
bits(datasize) data;
constant integer dbytes = datasize DIV 8;
boolean rt_unknown = FALSE;
boolean rn_unknown = FALSE;
if n == 31 thenif memop ==
MemOp_LOAD && pair && t == t2 then
Constraint c = ConstrainUnpredictable(Unpredictable_LDPOVERLAP);
assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP};
case c of
when Constraint_UNKNOWN rt_unknown = TRUE; // result is UNKNOWN
when Constraint_UNDEF UnallocatedEncoding();
when Constraint_NOP EndOfInstruction();
if memop == MemOp_STORE then
if s == t || (pair && s == t2) then
Constraint c = ConstrainUnpredictable(Unpredictable_DATAOVERLAP);
assert c IN {Constraint_UNKNOWN, Constraint_NONE, Constraint_UNDEF, Constraint_NOP};
case c of
when Constraint_UNKNOWN rt_unknown = TRUE; // store UNKNOWN value
when Constraint_NONE rt_unknown = FALSE; // store original value
when Constraint_UNDEF UnallocatedEncoding();
when Constraint_NOP EndOfInstruction();
if s == n && n != 31 then
Constraint c = ConstrainUnpredictable(Unpredictable_BASEOVERLAP);
assert c IN {Constraint_UNKNOWN, Constraint_NONE, Constraint_UNDEF, Constraint_NOP};
case c of
when Constraint_UNKNOWN rn_unknown = TRUE; // address is UNKNOWN
when Constraint_NONE rn_unknown = FALSE; // address is original base
when Constraint_UNDEF UnallocatedEncoding();
when Constraint_NOP EndOfInstruction();
if n == 31 then
CheckSPAlignment();
address = SP[];
elsif rn_unknown then
address = bits(64) UNKNOWN;
else
address = X[n];
// Tell the Exclusive Monitors to record a sequence of one or more atomic
// memory reads from virtual address range [address, address+dbytes-1].
// The Exclusive Monitor will only be set if all the reads are from the
// same dbytes-aligned physical address, to allow for the possibility of
// an atomicity break if the translation is changed between reads.case memop of
when
MemOp_STORE
if rt_unknown then
data = bits(datasize) UNKNOWN;
elsif pair then
bits(datasize DIV 2) el1 = X[t];
bits(datasize DIV 2) el2 = X[t2];
data = if BigEndian() then el1 : el2 else el2 : el1;
else
data = X[t];
bit status = '1';
// Check whether the Exclusive Monitors are set to include the
// physical memory locations corresponding to virtual address
// range [address, address+dbytes-1].
if AArch64.ExclusiveMonitorsPass(address, dbytes) then
// This atomic write will be rejected if it does not refer
// to the same physical locations after address translation.
Mem[address, dbytes, acctype] = data;
status = ExclusiveMonitorsStatus();
X[s] = ZeroExtend(status, 32);
when MemOp_LOAD
// Tell the Exclusive Monitors to record a sequence of one or more atomic
// memory reads from virtual address range [address, address+dbytes-1].
// The Exclusive Monitor will only be set if all the reads are from the
// same dbytes-aligned physical address, to allow for the possibility of
// an atomicity break if the translation is changed between reads.
AArch64.SetExclusiveMonitors(address, dbytes);
data = if pair then
if rt_unknown then
// ConstrainedUNPREDICTABLE case X[t] = bits(datasize) UNKNOWN;
elsif elsize == 32 then
// 32-bit load exclusive pair (atomic)
data = Mem[address, dbytes,[address, dbytes, acctype];
if () then
X[t] = data<datasize-1:elsize>;
X[t2] = data<elsize-1:0>;
else
X[t] = data<elsize-1:0>;
X[t2] = data<datasize-1:elsize>;
else // elsize == 64
// 64-bit load exclusive pair (not atomic),
// but must be 128-bit aligned
if address != Align(address, dbytes) then
iswrite = FALSE;
secondstage = FALSE;
AArch64.Abort(address, AArch64.AlignmentFault(acctype, iswrite, secondstage));
X[t] = Mem[address + 0, 8, acctype];
X[t2] = Mem[address + 8, 8, acctype];
else
data = MemAccType_ATOMICBigEndian];[address, dbytes, acctype];
X[t] = ZeroExtend(data, regsize);
Internal version only: isa v25.07, AdvSIMD v23.0, pseudocode v31.3
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Confidential.
ISA_v82A_A64_xml_00bet3.1 (old) | htmldiff from-ISA_v82A_A64_xml_00bet3.1 | (new) ISA_v82A_A64_xml_00bet3.1_OPT |