LDCLR, LDCLRA, LDCLRAL, LDCLRL

Atomic bit clear on word or doubleword in memory atomically loads a 32-bit word or 64-bit doubleword from memory, performs a bitwise AND with the complement of the value held in a register on it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register.

For more information about memory ordering semantics see Load-Acquire, Store-Release.

For information about memory accesses see Load/Store addressing modes.

Integer
(ARMv8.1)

313029282726252423222120191817161514131211109876543210
1x111000AR1Rs000100RnRt
sizeVo3opc

32-bit, acquire (size == 10 && A == 1 && R == 0)

LDCLRA <Ws>, <Wt>, [<Xn|SP>]

32-bit, acquire and release (size == 10 && A == 1 && R == 1)

LDCLRAL <Ws>, <Wt>, [<Xn|SP>]

32-bit, no memory ordering (size == 10 && A == 0 && R == 0 && Rt != 11111)

LDCLR <Ws>, <Wt>, [<Xn|SP>]

32-bit, release (size == 10 && A == 0 && R == 1 && Rt != 11111)

LDCLRL <Ws>, <Wt>, [<Xn|SP>]

64-bit, acquire (size == 11 && A == 1 && R == 0)

LDCLRA <Xs>, <Xt>, [<Xn|SP>]

64-bit, acquire and release (size == 11 && A == 1 && R == 1)

LDCLRAL <Xs>, <Xt>, [<Xn|SP>]

64-bit, no memory ordering (size == 11 && A == 0 && R == 0 && Rt != 11111)

LDCLR <Xs>, <Xt>, [<Xn|SP>]

64-bit, release (size == 11 && A == 0 && R == 1 && Rt != 11111)

LDCLRL <Xs>, <Xt>, [<Xn|SP>]

if !HaveAtomicExt() then UnallocatedEncoding(); integer t = UInt(Rt); integer n = UInt(Rn); integer s = UInt(Rs); integer datasize = 8 << UInt(size); integer regsize = if datasize == 64 then 64 else 32; AccType ldacctype = if A == '1' && Rt != '11111' then AccType_ORDEREDRW else AccType_ATOMICRW; AccType stacctype = if R == '1' then AccType_ORDEREDRW else AccType_ATOMICRW;

Assembler Symbols

<Ws>

Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

<Wt>

Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

<Xs>

Is the 64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

<Xt>

Is the 64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

Operation

bits(64) address; bits(datasize) value; bits(datasize) data; bits(datasize) result; value = X[s]; if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n]; data = Mem[address, datasize DIV 8, ldacctype]; result = data AND NOT(value); // All observers in the shareability domain observe the // following load and store atomically. Mem[address, datasize DIV 8, stacctype] = result; X[t] = ZeroExtend(data, regsize);


Internal version only: isa v25.07, AdvSIMD v23.0, pseudocode v31.3

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