SWPB, SWPAB, SWPALB, SWPLB

Swap byte in memory atomically loads an 8-bit byte from a memory location, and stores the value held in a register back to the same memory location. The value initially loaded from memory is returned in the destination register.

For more information about memory ordering semantics see Load-Acquire, Store-Release.

For information about memory accesses see Load/Store addressing modes.

Integer
(ARMv8.1)

313029282726252423222120191817161514131211109876543210
00111000AR1Rs100000RnRt
sizeVo3opc

Acquire (A == 1 && R == 0)

SWPAB <Ws>, <Wt>, [<Xn|SP>]

Acquire and release (A == 1 && R == 1)

SWPALB <Ws>, <Wt>, [<Xn|SP>]

No memory ordering (A == 0 && R == 0)

SWPB <Ws>, <Wt>, [<Xn|SP>]

Release (A == 0 && R == 1)

SWPLB <Ws>, <Wt>, [<Xn|SP>]

if !HaveAtomicExt() then UnallocatedEncoding(); integer t = UInt(Rt); integer n = UInt(Rn); integer s = UInt(Rs); AccType ldacctype = if A == '1' && Rt != '11111' then AccType_ORDEREDRW else AccType_ATOMICRW; AccType stacctype = if R == '1' then AccType_ORDEREDRW else AccType_ATOMICRW;

Assembler Symbols

<Ws>

Is the 32-bit name of the general-purpose register to be stored, encoded in the "Rs" field.

<Wt>

Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

Operation

bits(64) address; bits(8) value; bits(8) data; value = X[s]; if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n]; data = Mem[address, 1, ldacctype]; // All observers in the shareability domain observe the // following load and store atomically. Mem[address, 1, stacctype] = value; X[t] = ZeroExtend(data, 32);


Internal version only: isa v25.07, AdvSIMD v23.0, pseudocode v31.3

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