BFM

Bitfield Move copies any number of low-order bits from a source register into the same number of adjacent bits at any position in the destination register, leaving other bits unchanged.

This instruction is used by the aliases BFC, BFI, and BFXIL.

313029282726252423222120191817161514131211109876543210
sf01100110NimmrimmsRnRd
opc

32-bit (sf == 0 && N == 0)

BFM <Wd>, <Wn>, #<immr>, #<imms>

64-bit (sf == 1 && N == 1)

BFM <Xd>, <Xn>, #<immr>, #<imms>

integer d = UInt(Rd); integer n = UInt(Rn); integer datasize = if sf == '1' then 64 else 32; integer R; bits(datasize) wmask; bits(datasize) tmask; if sf == '1' && N != '1' then ReservedValue(); if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue(); R = UInt(immr); (wmask, tmask) = DecodeBitMasks(N, imms, immr, FALSE);

Assembler Symbols

<Wd>

Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Wn>

Is the 32-bit name of the general-purpose source register, encoded in the "Rn" field.

<Xd>

Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Xn>

Is the 64-bit name of the general-purpose source register, encoded in the "Rn" field.

<immr>

For the 32-bit variant: is the right rotate amount, in the range 0 to 31, encoded in the "immr" field.

For the 64-bit variant: is the right rotate amount, in the range 0 to 63, encoded in the "immr" field.

<imms>

For the 32-bit variant: is the leftmost bit number to be moved from the source, in the range 0 to 31, encoded in the "imms" field.

For the 64-bit variant: is the leftmost bit number to be moved from the source, in the range 0 to 63, encoded in the "imms" field.

Alias Conditions

AliasIs preferred when
BFCRn == '11111' && UInt(imms) < UInt(immr)
BFIRn != '11111' && UInt(imms) < UInt(immr)
BFXILUInt(imms) >= UInt(immr)

Operation

bits(datasize) dst = X[d]; bits(datasize) src = X[n]; // perform bitfield move on low bits bits(datasize) bot = (dst AND NOT(wmask)) OR (ROR(src, R) AND wmask); // combine extension bits and result bits X[d] = (dst AND NOT(tmask)) OR (bot AND tmask);


Internal version only: isa v25.07, AdvSIMD v23.0, pseudocode v31.3

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