STCLR, STCLRL

Atomic bit clear on word or doubleword in memory, without return, atomically loads a 32-bit word or 64-bit doubleword from memory, performs a bitwise AND with the complement of the value held in a register on it, and stores the result back to memory.

For information about memory accesses see Load/Store addressing modes.

Integer
(ARMv8.1)

313029282726252423222120191817161514131211109876543210
1x1110000R1Rs000100Rn11111
sizeVAo3opc

32-bit, no memory ordering (size == 10 && R == 0)

STCLR <Ws>, [<Xn|SP>]

32-bit, release (size == 10 && R == 1)

STCLRL <Ws>, [<Xn|SP>]

64-bit, no memory ordering (size == 11 && R == 0)

STCLR <Xs>, [<Xn|SP>]

64-bit, release (size == 11 && R == 1)

STCLRL <Xs>, [<Xn|SP>]

if !HaveAtomicExt() then UnallocatedEncoding(); integer n = UInt(Rn); integer s = UInt(Rs); integer datasize = 8 << UInt(size); AccType stacctype = if R == '1' then AccType_ORDEREDRW else AccType_ATOMICRW;

Assembler Symbols

<Ws>

Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

<Xs>

Is the 64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

Operation

bits(64) address; bits(datasize) value; bits(datasize) data; bits(datasize) result; value = X[s]; if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n]; data = Mem[address, datasize DIV 8, AccType_ATOMICRW]; result = data AND NOT(value); // All observers in the shareability domain observe the // following load and store atomically. Mem[address, datasize DIV 8, stacctype] = result;


Internal version only: isa v25.07, AdvSIMD v23.0, pseudocode v31.3

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