SWPH, SWPAH, SWPALH, SWPLH

Swap halfword in memory atomically loads a 16-bit halfword from a memory location, and stores the value held in a register back to the same memory location. The value initially loaded from memory is returned in the destination register.

For more information about memory ordering semantics see Load-Acquire, Store-Release.

For information about memory accesses see Load/Store addressing modes.

Integer
(ARMv8.1)

313029282726252423222120191817161514131211109876543210
01111000AR1Rs100000RnRt
sizeVo3opc

Acquire (A == 1 && R == 0)

SWPAH <Ws>, <Wt>, [<Xn|SP>]

Acquire and release (A == 1 && R == 1)

SWPALH <Ws>, <Wt>, [<Xn|SP>]

No memory ordering (A == 0 && R == 0)

SWPH <Ws>, <Wt>, [<Xn|SP>]

Release (A == 0 && R == 1)

SWPLH <Ws>, <Wt>, [<Xn|SP>]

if !HaveAtomicExt() then UnallocatedEncoding(); integer t = UInt(Rt); integer n = UInt(Rn); integer s = UInt(Rs); integer datasize = 8 << UInt(size); integer regsize = if datasize == 64 then 64 else 32; AccType ldacctype = if A == '1' && Rt != '11111' then AccType_ORDEREDRW else AccType_ATOMICRW; AccType stacctype = if R == '1' then AccType_ORDEREDRW else AccType_ATOMICRW; MemAtomicOp op; case o3:opc of when '0000' op = MemAtomicOp_ADD; when '0001' op = MemAtomicOp_BIC; when '0010' op = MemAtomicOp_EOR; when '0011' op = MemAtomicOp_ORR; when '0100' op = MemAtomicOp_SMAX; when '0101' op = MemAtomicOp_SMIN; when '0110' op = MemAtomicOp_UMAX; when '0111' op = MemAtomicOp_UMIN; when '1000' op = MemAtomicOp_SWP; otherwise UnallocatedEncoding();

Assembler Symbols

<Ws>

Is the 32-bit name of the general-purpose register to be stored, encoded in the "Rs" field.

<Wt>

Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

Operation

bits(64) address; bits(datasize) value; bits(datasize) data; bits(datasize) result; value = X[s]; if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n]; data = Mem[address, datasize DIV 8, ldacctype]; case op of when MemAtomicOp_ADD result = data + value; when MemAtomicOp_BIC result = data AND NOT(value); when MemAtomicOp_EOR result = data EOR value; when MemAtomicOp_ORR result = data OR value; when MemAtomicOp_SMAX result = if SInt(data) > SInt(value) then data else value; when MemAtomicOp_SMIN result = if SInt(data) > SInt(value) then value else data; when MemAtomicOp_UMAX result = if UInt(data) > UInt(value) then data else value; when MemAtomicOp_UMIN result = if UInt(data) > UInt(value) then value else data; when MemAtomicOp_SWP result = value; // All observers in the shareability domain observe the // following load and store atomically. Mem[address, datasize DIV 8, stacctype] = result; X[t] = ZeroExtend(data, regsize);


Internal version only: isa v25.07, AdvSIMD v23.0, pseudocode v31.3

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