Unsigned Bitfield Move copies any number of low-order bits from a source register into the same number of adjacent bits at any position in the destination register, with zeros in the upper and lower bits.
This instruction is used by the aliases LSL (immediate), LSR (immediate), UBFIZ, UBFX, UXTB, and UXTH.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
sf | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | N | immr | imms | Rn | Rd | ||||||||||||||||||
opc |
integer d = UInt(Rd); integer n = UInt(Rn); integer datasize = if sf == '1' then 64 else 32; integer R; bits(datasize) wmask; bits(datasize) tmask; if sf == '1' && N != '1' then ReservedValue(); if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue(); R = UInt(immr); (wmask, tmask) = DecodeBitMasks(N, imms, immr, FALSE);
<Wd> |
Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. |
<Wn> |
Is the 32-bit name of the general-purpose source register, encoded in the "Rn" field. |
<Xd> |
Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field. |
<Xn> |
Is the 64-bit name of the general-purpose source register, encoded in the "Rn" field. |
Alias | Of variant | Is preferred when |
---|---|---|
LSL (immediate) | 32-bit | imms != '011111' && imms + 1 == immr |
LSL (immediate) | 64-bit | imms != '111111' && imms + 1 == immr |
LSR (immediate) | 32-bit | imms == '011111' |
LSR (immediate) | 64-bit | imms == '111111' |
UBFIZ | UInt(imms) < UInt(immr) | |
UBFX | BFXPreferred(sf, opc<1>, imms, immr) | |
UXTB | immr == '000000' && imms == '000111' | |
UXTH | immr == '000000' && imms == '001111' |
bits(datasize) src = X[n]; // perform bitfield move on low bits bits(datasize) bot = ROR(src, R) AND wmask; // combine extension bits and result bits X[d] = bot AND tmask;
Internal version only: isa v25.07, AdvSIMD v23.0, pseudocode v31.3
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