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SBFM

Signed Bitfield Move copies any number of low-order bits from a source register into the same number of adjacent bits at any position in the destination register, shifting in copies of the sign bit in the upper bits and zeros in the lower bits.

This instruction is used by the aliases ASR (immediate), SBFIZ, SBFX, SXTB, SXTH, and SXTW.

313029282726252423222120191817161514131211109876543210
sf00100110NimmrimmsRnRd
opc

32-bit (sf == 0 && N == 0)

SBFM <Wd>, <Wn>, #<immr>, #<imms>

64-bit (sf == 1 && N == 1)

SBFM <Xd>, <Xn>, #<immr>, #<imms>

integer d = UInt(Rd); integer n = UInt(Rn); integer datasize = if sf == '1' then 64 else 32; boolean inzero; boolean extend; integer R; integer S; bits(datasize) wmask; bits(datasize) tmask; if sf == '1' && N != '1' thencase opc of when '00' inzero = TRUE; extend = TRUE; // SBFM when '01' inzero = FALSE; extend = FALSE; // BFM when '10' inzero = TRUE; extend = FALSE; // UBFM when '11' UnallocatedEncoding(); if sf == '1' && N != '1' then ReservedValue(); if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue(); R = UInt(immr); S = UInt(imms); (wmask, tmask) = DecodeBitMasks(N, imms, immr, FALSE);

Assembler Symbols

<Wd>

Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Wn>

Is the 32-bit name of the general-purpose source register, encoded in the "Rn" field.

<Xd>

Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Xn>

Is the 64-bit name of the general-purpose source register, encoded in the "Rn" field.

<immr>

For the 32-bit variant: is the right rotate amount, in the range 0 to 31, encoded in the "immr" field.

For the 64-bit variant: is the right rotate amount, in the range 0 to 63, encoded in the "immr" field.

<imms>

For the 32-bit variant: is the leftmost bit number to be moved from the source, in the range 0 to 31, encoded in the "imms" field.

For the 64-bit variant: is the leftmost bit number to be moved from the source, in the range 0 to 63, encoded in the "imms" field.

Alias Conditions

AliasOf variantIs preferred when
ASR (immediate)32-bitimms == '011111'
ASR (immediate)64-bitimms == '111111'
SBFIZUInt(imms) < UInt(immr)
SBFXBFXPreferred(sf, opc<1>, imms, immr)
SXTBimmr == '000000' && imms == '000111'
SXTHimmr == '000000' && imms == '001111'
SXTWimmr == '000000' && imms == '011111'

Operation

bits(datasize) src =bits(datasize) dst = if inzero then Zeros() else X[d]; bits(datasize) src = X[n]; // perform bitfield move on low bits bits(datasize) bot = (dst AND NOT[n]; // perform bitfield move on low bits bits(datasize) bot =(wmask)) OR ( ROR(src, R) AND wmask; (src, R) AND wmask); // determine extension bits (sign, zero or dest register) bits(datasize) top =bits(datasize) top = if extend then Replicate(src<S>); (src<S>) else dst; // combine extension bits and result bits X[d] = (top AND NOT(tmask)) OR (bot AND tmask);


Internal version only: isa v25.07, AdvSIMD v23.0, pseudocode v31.3

Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Confidential.

ISA_v82A_A64_xml_00bet3.1 (old)htmldiff from-ISA_v82A_A64_xml_00bet3.1(new) ISA_v82A_A64_xml_00bet3.1_OPT