HINT

Hint instruction is for the instruction set space that is reserved for architectural hint instructions.

Some encodings described here are unallocated in this revision of the architecture, and behave as NOPs. These encodings might be allocated to other hint functionality in future revisions of the architecture.

313029282726252423222120191817161514131211109876543210
11010101000000110010CRmop211111

Hints 6 and 7 (CRm == 0000 && op2 == 11x)

HINT #<imm>

Hints 8 to 15, and 24 to 127 (CRm != 00x0)

HINT #<imm>

Hints 17 to 23 (CRm == 0010 && op2 != 00x)

HINT #<imm>

SystemHintOp op; case CRm:op2 of when '0000 000' op = SystemHintOp_NOP; when '0000 001' op = SystemHintOp_YIELD; when '0000 010' op = SystemHintOp_WFE; when '0000 011' op = SystemHintOp_WFI; when '0000 100' op = SystemHintOp_SEV; when '0000 101' op = SystemHintOp_SEVL; when '0010 000' op = if HaveRASExt() then SystemHintOp_ESB else SystemHintOp_NOP; when '0010 001' op = if HaveStatisticalProfiling() then SystemHintOp_PSB else SystemHintOp_NOP; otherwise op = SystemHintOp_NOP;

Assembler Symbols

<imm>

Is a 7-bit unsigned immediate, in the range 0 to 127, excluding the allocated encodings described below, encoded in "CRm:op2".

The following encodings of "CRm:op2" are allocated:

0000000
NOP
0000001
YIELD
0000010
WFE
0000011
WFI
0000100
SEV
0000101
SEVL

For allocated encodings of "CRm:op2":

  • A disassembler will disassemble the allocated instruction, rather than the HINT instruction.
  • An assembler may support assembly of allocated encodings using HINT with the corresponding <imm> value, but it is not required to do so.

Operation

case op of when SystemHintOp_YIELD Hint_Yield(); when SystemHintOp_WFE if IsEventRegisterSet() then ClearEventRegister(); else if PSTATE.EL == EL0 then // Check for traps described by the OS which may be EL1 or EL2. AArch64.CheckForWFxTrap(EL1, TRUE); if HaveEL(EL2) && !IsSecure() && PSTATE.EL IN {EL0,EL1} && !IsInHost() then // Check for traps described by the Hypervisor. AArch64.CheckForWFxTrap(EL2, TRUE); if HaveEL(EL3) && PSTATE.EL != EL3 then // Check for traps described by the Secure Monitor. AArch64.CheckForWFxTrap(EL3, TRUE); WaitForEvent(); when SystemHintOp_WFI if !InterruptPending() then if PSTATE.EL == EL0 then // Check for traps described by the OS which may be EL1 or EL2. AArch64.CheckForWFxTrap(EL1, FALSE); if HaveEL(EL2) && !IsSecure() && PSTATE.EL IN {EL0,EL1} && !IsInHost() then // Check for traps described by the Hypervisor. AArch64.CheckForWFxTrap(EL2, FALSE); if HaveEL(EL3) && PSTATE.EL != EL3 then // Check for traps described by the Secure Monitor. AArch64.CheckForWFxTrap(EL3, FALSE); WaitForInterrupt(); when SystemHintOp_SEV SendEvent(); when SystemHintOp_SEVL SendEventLocal(); when SystemHintOp_ESB ErrorSynchronizationBarrier(MBReqDomain_FullSystem, MBReqTypes_All); AArch64.ESBOperation(); if HaveEL(EL2) && !IsSecure() && PSTATE.EL IN {EL0,EL1} then AArch64.vESBOperation(); TakeUnmaskedSErrorInterrupts(); when SystemHintOp_PSB ProfilingSynchronizationBarrier(); otherwise // do nothing


Internal version only: isa v25.07, AdvSIMD v23.0, pseudocode v31.3

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