ISA_v82A_A64_xml_00bet3.2 (old) | htmldiff from-ISA_v82A_A64_xml_00bet3.2 | (new) ISA_v82A_A64_xml_00bet3.2_OPT |
Atomic add on word or doubleword in memory atomically loads a 32-bit word or 64-bit doubleword from memory, adds the value held in a register to it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register.
For more information about memory ordering semantics see Load-Acquire, Store-Release.
For information about memory accesses see Load/Store addressing modes.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | x | 1 | 1 | 1 | 0 | 0 | 0 | A | R | 1 | Rs | 0 | 0 | 0 | 0 | 0 | 0 | Rn | Rt | ||||||||||||
size | V | o3 | opc |
if !HaveAtomicExt() then UnallocatedEncoding();
integer t = UInt(Rt);
integer n = UInt(Rn);
integer s = UInt(Rs);
integer datasize = 8 << UInt(size);
integer regsize = if datasize == 64 then 64 else 32;
AccType ldacctype = if A == '1' && Rt != '11111' then AccType_ORDEREDRW else AccType_ATOMICRW;
AccType stacctype = if R == '1' then AccType_ORDEREDRW else AccType_ATOMICRW;MemAtomicOp op;
case o3:opc of
when '0000' op = MemAtomicOp_ADD;
when '0001' op = MemAtomicOp_BIC;
when '0010' op = MemAtomicOp_EOR;
when '0011' op = MemAtomicOp_ORR;
when '0100' op = MemAtomicOp_SMAX;
when '0101' op = MemAtomicOp_SMIN;
when '0110' op = MemAtomicOp_UMAX;
when '0111' op = MemAtomicOp_UMIN;
when '1000' op = MemAtomicOp_SWP;
otherwise UnallocatedEncoding();
<Ws> | Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field. |
<Wt> | Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field. |
<Xs> | Is the 64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field. |
<Xt> | Is the 64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field. |
<Xn|SP> | Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
bits(64) address;
bits(datasize) value;
bits(datasize) data;
bits(datasize) result;
value = X[s];
if n == 31 then
CheckSPAlignment();
address = SP[];
else
address = X[n];
data = Mem[address, datasize DIV 8, ldacctype];
result = data + value;
// All observers in the shareability domain observe the
// following load and store atomically.case op of
when
MemAtomicOp_ADD result = data + value;
when MemAtomicOp_BIC result = data AND NOT(value);
when MemAtomicOp_EOR result = data EOR value;
when MemAtomicOp_ORR result = data OR value;
when MemAtomicOp_SMAX result = if SInt(data) > SInt(value) then data else value;
when MemAtomicOp_SMIN result = if SInt(data) > SInt(value) then value else data;
when MemAtomicOp_UMAX result = if UInt(data) > UInt(value) then data else value;
when MemAtomicOp_UMIN result = if UInt(data) > UInt(value) then value else data;
when MemAtomicOp_SWP result = value;
// All observers in the shareability domain observe the
// following load and store atomically.
Mem[address, datasize DIV 8, stacctype] = result;
X[t] = ZeroExtend(data, regsize);
Internal version only: isa v25.07, AdvSIMD v23.0, pseudocode v31.3
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.
ISA_v82A_A64_xml_00bet3.2 (old) | htmldiff from-ISA_v82A_A64_xml_00bet3.2 | (new) ISA_v82A_A64_xml_00bet3.2_OPT |