Atomic unsigned minimum on word or doubleword in memory, without return, atomically loads a 32-bit word or 64-bit doubleword from memory, compares it against the value held in a register, and stores the smaller value back to memory, treating the values as unsigned numbers.
For information about memory accesses see Load/Store addressing modes.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | x | 1 | 1 | 1 | 0 | 0 | 0 | 0 | R | 1 | Rs | 0 | 1 | 1 | 1 | 0 | 0 | Rn | 1 | 1 | 1 | 1 | 1 | ||||||||
size | V | A | o3 | opc |
if !HaveAtomicExt() then UnallocatedEncoding(); integer n = UInt(Rn); integer s = UInt(Rs); integer datasize = 8 << UInt(size); AccType stacctype = if R == '1' then AccType_ORDEREDRW else AccType_ATOMICRW;
<Ws> |
Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field. |
<Xs> |
Is the 64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field. |
<Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
bits(64) address; bits(datasize) value; bits(datasize) data; bits(datasize) result; value = X[s]; if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n]; data = Mem[address, datasize DIV 8, AccType_ATOMICRW]; result = if UInt(data) > UInt(value) then value else data; // All observers in the shareability domain observe the // following load and store atomically. Mem[address, datasize DIV 8, stacctype] = result;
Internal version only: isa v25.07, AdvSIMD v23.0, pseudocode v31.3
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