Atomic exclusive OR on byte in memory, without return, atomically loads an 8-bit byte from memory, performs an exclusive OR with the value held in a register on it, and stores the result back to memory.
For information about memory accesses see Load/Store addressing modes.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | R | 1 | Rs | 0 | 0 | 1 | 0 | 0 | 0 | Rn | 1 | 1 | 1 | 1 | 1 | ||||||||
size | V | A | o3 | opc |
if !HaveAtomicExt() then UnallocatedEncoding(); integer n = UInt(Rn); integer s = UInt(Rs); AccType stacctype = if R == '1' then AccType_ORDEREDRW else AccType_ATOMICRW;
<Ws> |
Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field. |
<Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
bits(64) address; bits(8) value; bits(8) data; bits(8) result; value = X[s]; if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n]; data = Mem[address, 1, AccType_ATOMICRW]; result = data EOR value; // All observers in the shareability domain observe the // following load and store atomically. Mem[address, 1, stacctype] = result;
Internal version only: isa v25.07, AdvSIMD v23.0, pseudocode v31.3
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