SHA256SU0

SHA256 schedule update 0.

313029282726252423222120191817161514131211109876543210
0101111000101000001010RnRd

Advanced SIMD

SHA256SU0 <Vd>.4S, <Vn>.4S

integer d = UInt(Rd); integer n = UInt(Rn); if !HaveCryptoExt() then UnallocatedEncoding();

Assembler Symbols

<Vd>

Is the name of the SIMD&FP source and destination register, encoded in the "Rd" field.

<Vn>

Is the name of the second SIMD&FP source register, encoded in the "Rn" field.

Operation

CheckCryptoEnabled64(); bits(128) operand1 = V[d]; bits(128) operand2 = V[n]; bits(128) result; bits(128) T = operand2<31:0>:operand1<127:32>; bits(32) elt; for e = 0 to 3 elt = Elem[T, e, 32]; elt = ROR(elt, 7) EOR ROR(elt, 18) EOR LSR(elt, 3); Elem[result, e, 32] = elt + Elem[operand1, e, 32]; V[d] = result;


Internal version only: isa v25.07, AdvSIMD v23.0, pseudocode v31.3

Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.