Top-level encodings for A64

313029282726252423222120191817161514131211109876543210
op0
Decode fields Instruction details
op0
00xx UNALLOCATED
100x Data Processing -- Immediate
101x Branches, Exception Generating and System instructions
x1x0 Loads and Stores
x101 Data Processing -- Register
x111 Data Processing -- Scalar Floating-Point and Advanced SIMD

Data Processing -- Immediate

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
100op0
Decode fields Instruction details
op0
00x PC-rel. addressing
01x Add/subtract (immediate)
100 Logical (immediate)
101 Move wide (immediate)
110 Bitfield
111 Extract

PC-rel. addressing

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
opimmlo10000immhiRd
Decode fields Instruction Details
op
0 ADR
1 ADRP

Add/subtract (immediate)

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopS10001shiftimm12RnRd
Decode fields Instruction Details
sf op S shift
1x UNALLOCATED
0 0 0 ADD (immediate)32-bit
0 0 1 ADDS (immediate)32-bit
0 1 0 SUB (immediate)32-bit
0 1 1 SUBS (immediate)32-bit
1 0 0 ADD (immediate)64-bit
1 0 1 ADDS (immediate)64-bit
1 1 0 SUB (immediate)64-bit
1 1 1 SUBS (immediate)64-bit

Logical (immediate)

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopc100100NimmrimmsRnRd
Decode fields Instruction Details
sf opc N
0 1 UNALLOCATED
0 00 0 AND (immediate)32-bit
0 01 0 ORR (immediate)32-bit
0 10 0 EOR (immediate)32-bit
0 11 0 ANDS (immediate)32-bit
1 00 AND (immediate)64-bit
1 01 ORR (immediate)64-bit
1 10 EOR (immediate)64-bit
1 11 ANDS (immediate)64-bit

Move wide (immediate)

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopc100101hwimm16Rd
Decode fields Instruction Details
sf opc hw
01 UNALLOCATED
0 1x UNALLOCATED
0 00 MOVN32-bit
0 10 MOVZ32-bit
0 11 MOVK32-bit
1 00 MOVN64-bit
1 10 MOVZ64-bit
1 11 MOVK64-bit

Bitfield

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopc100110NimmrimmsRnRd
Decode fields Instruction Details
sf opc N
11 UNALLOCATED
0 1 UNALLOCATED
0 00 0 SBFM32-bit
0 01 0 BFM32-bit
0 10 0 UBFM32-bit
1 0 UNALLOCATED
1 00 1 SBFM64-bit
1 01 1 BFM64-bit
1 10 1 UBFM64-bit

Extract

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfop21100111No0RmimmsRnRd
Decode fields Instruction Details
sf op21 N o0 imms
x1 UNALLOCATED
00 1 UNALLOCATED
1x UNALLOCATED
0 1xxxxx UNALLOCATED
0 1 UNALLOCATED
0 00 0 0 0xxxxx EXTR32-bit
1 0 UNALLOCATED
1 00 1 0 EXTR64-bit

Branches, Exception Generating and System instructions

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
op0101op1
Decode fields Instruction details
op0op1
010 0xxx Conditional branch (immediate)
010 1xxx UNALLOCATED
110 00xx Exception generation
110 0100 System
110 0101 UNALLOCATED
110 011x UNALLOCATED
110 1xxx Unconditional branch (register)
x00 Unconditional branch (immediate)
x01 0xxx Compare and branch (immediate)
x01 1xxx Test and branch (immediate)
x11 UNALLOCATED

Conditional branch (immediate)

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
0101010o1imm19o0cond
Decode fields Instruction Details
o1 o0
0 0 B.cond
0 1 UNALLOCATED
1 UNALLOCATED

Exception generation

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
11010100opcimm16op2LL
Decode fields Instruction Details
opc op2 LL
xx1 UNALLOCATED
x1x UNALLOCATED
1xx UNALLOCATED
000 000 00 UNALLOCATED
000 000 01 SVC
000 000 10 HVC
000 000 11 SMC
001 000 x1 UNALLOCATED
001 000 00 BRK
001 000 1x UNALLOCATED
010 000 x1 UNALLOCATED
010 000 00 HLT
010 000 1x UNALLOCATED
011 000 UNALLOCATED
100 000 UNALLOCATED
101 000 00 UNALLOCATED
101 000 01 DCPS1
101 000 10 DCPS2
101 000 11 DCPS3
11x 000 UNALLOCATED

System

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101010100Lop0op1CRnCRmop2Rt
Decode fields Instruction Details Architecture Version
L op0 op1 CRn CRm op2 Rt
0 00 000x UNALLOCATED-
0 00 0100 != 11111 UNALLOCATED-
0 00 0100 11111 MSR (immediate)-
0 00 0101 UNALLOCATED-
0 00 011x UNALLOCATED-
0 00 1xxx UNALLOCATED-
0 00 xx0 001x UNALLOCATED-
0 00 x0x 001x UNALLOCATED-
0 00 011 001x != 11111 UNALLOCATED-
0 00 011 0010 != 00x0 11111 HINThints 8 to 15, and 24 to 127-
0 00 011 0010 0000 000 11111 NOP-
0 00 011 0010 0000 001 11111 YIELD-
0 00 011 0010 0000 010 11111 WFE-
0 00 011 0010 0000 011 11111 WFI-
0 00 011 0010 0000 100 11111 SEV-
0 00 011 0010 0000 101 11111 SEVL-
0 00 011 0010 0000 11x 11111 HINThints 6 and 7-
0 00 011 0010 0010 != 00x 11111 HINThints 17 to 23-
0 00 011 0010 0010 000 11111 ESBARMv8.2
0 00 011 0010 0010 001 11111 PSB CSYNCARMv8.2
0 00 011 0011 000 UNALLOCATED-
0 00 011 0011 001 UNALLOCATED-
0 00 011 0011 010 11111 CLREX-
0 00 011 0011 011 UNALLOCATED-
0 00 011 0011 100 11111 DSB-
0 00 011 0011 101 11111 DMB-
0 00 011 0011 110 11111 ISB-
0 00 011 0011 111 UNALLOCATED-
0 00 1xx 001x UNALLOCATED-
0 01 SYS-
0 1x MSR (register)-
1 00 UNALLOCATED-
1 01 SYSL-
1 1x MRS-

Unconditional branch (register)

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101011opcop2op3Rnop4
Decode fields Instruction Details
opc op2 op3 Rn op4
!= 00000 UNALLOCATED
!= 000000 UNALLOCATED
!= 11111 UNALLOCATED
0000 11111 000000 00000 BR
0001 11111 000000 00000 BLR
0010 11111 000000 00000 RET
0011 UNALLOCATED
010x != 11111 UNALLOCATED
0100 11111 000000 11111 00000 ERET
0101 11111 000000 11111 00000 DRPS
011x UNALLOCATED
1xxx UNALLOCATED

Unconditional branch (immediate)

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
op00101imm26
Decode fields Instruction Details
op
0 B
1 BL

Compare and branch (immediate)

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
sf011010opimm19Rt
Decode fields Instruction Details
sf op
0 0 CBZ32-bit
0 1 CBNZ32-bit
1 0 CBZ64-bit
1 1 CBNZ64-bit

Test and branch (immediate)

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
b5011011opb40imm14Rt
Decode fields Instruction Details
op
0 TBZ
1 TBNZ

Loads and Stores

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
op0op11op20op3op4op5
Decode fields Instruction details
op0op1op2op3op4op5
0 00 1 00 000000 Advanced SIMD load/store multiple structures
0 00 1 01 0xxxxx Advanced SIMD load/store multiple structures (post-indexed)
0 00 1 0x 1xxxxx UNALLOCATED
0 00 1 10 x00000 Advanced SIMD load/store single structure
0 00 1 11 Advanced SIMD load/store single structure (post-indexed)
0 00 1 x0 x1xxxx UNALLOCATED
0 00 1 x0 xx1xxx UNALLOCATED
0 00 1 x0 xxx1xx UNALLOCATED
0 00 1 x0 xxxx1x UNALLOCATED
0 00 1 x0 xxxxx1 UNALLOCATED
1 00 1 UNALLOCATED
00 0 0x Load/store exclusive
00 0 1x UNALLOCATED
01 0x Load register (literal)
01 1x UNALLOCATED
10 00 Load/store no-allocate pair (offset)
10 01 Load/store register pair (post-indexed)
10 10 Load/store register pair (offset)
10 11 Load/store register pair (pre-indexed)
11 0x 0xxxxx 00 Load/store register (unscaled immediate)
11 0x 0xxxxx 01 Load/store register (immediate post-indexed)
11 0x 0xxxxx 10 Load/store register (unprivileged)
11 0x 0xxxxx 11 Load/store register (immediate pre-indexed)
11 0x 1xxxxx 00 Atomic memory operations
11 0x 1xxxxx 10 Load/store register (register offset)
11 1x Load/store register (unsigned immediate)

Advanced SIMD load/store multiple structures

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
0Q0011000L000000opcodesizeRnRt
Decode fields Instruction Details
L opcode
0 0000 ST4 (multiple structures)
0 0001 UNALLOCATED
0 0010 ST1 (multiple structures)four registers
0 0011 UNALLOCATED
0 0100 ST3 (multiple structures)
0 0101 UNALLOCATED
0 0110 ST1 (multiple structures)three registers
0 0111 ST1 (multiple structures)one register
0 1000 ST2 (multiple structures)
0 1001 UNALLOCATED
0 1010 ST1 (multiple structures)two registers
0 1011 UNALLOCATED
0 11xx UNALLOCATED
1 0000 LD4 (multiple structures)
1 0001 UNALLOCATED
1 0010 LD1 (multiple structures)four registers
1 0011 UNALLOCATED
1 0100 LD3 (multiple structures)
1 0101 UNALLOCATED
1 0110 LD1 (multiple structures)three registers
1 0111 LD1 (multiple structures)one register
1 1000 LD2 (multiple structures)
1 1001 UNALLOCATED
1 1010 LD1 (multiple structures)two registers
1 1011 UNALLOCATED
1 11xx UNALLOCATED

Advanced SIMD load/store multiple structures (post-indexed)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
0Q0011001L0RmopcodesizeRnRt
Decode fields Instruction Details
L Rm opcode
0 0001 UNALLOCATED
0 0011 UNALLOCATED
0 0101 UNALLOCATED
0 1001 UNALLOCATED
0 1011 UNALLOCATED
0 11xx UNALLOCATED
0 != 11111 0000 ST4 (multiple structures)register offset
0 != 11111 0010 ST1 (multiple structures)four registers, register offset
0 != 11111 0100 ST3 (multiple structures)register offset
0 != 11111 0110 ST1 (multiple structures)three registers, register offset
0 != 11111 0111 ST1 (multiple structures)one register, register offset
0 != 11111 1000 ST2 (multiple structures)register offset
0 != 11111 1010 ST1 (multiple structures)two registers, register offset
0 11111 0000 ST4 (multiple structures)immediate offset
0 11111 0010 ST1 (multiple structures)four registers, immediate offset
0 11111 0100 ST3 (multiple structures)immediate offset
0 11111 0110 ST1 (multiple structures)three registers, immediate offset
0 11111 0111 ST1 (multiple structures)one register, immediate offset
0 11111 1000 ST2 (multiple structures)immediate offset
0 11111 1010 ST1 (multiple structures)two registers, immediate offset
1 0001 UNALLOCATED
1 0011 UNALLOCATED
1 0101 UNALLOCATED
1 1001 UNALLOCATED
1 1011 UNALLOCATED
1 11xx UNALLOCATED
1 != 11111 0000 LD4 (multiple structures)register offset
1 != 11111 0010 LD1 (multiple structures)four registers, register offset
1 != 11111 0100 LD3 (multiple structures)register offset
1 != 11111 0110 LD1 (multiple structures)three registers, register offset
1 != 11111 0111 LD1 (multiple structures)one register, register offset
1 != 11111 1000 LD2 (multiple structures)register offset
1 != 11111 1010 LD1 (multiple structures)two registers, register offset
1 11111 0000 LD4 (multiple structures)immediate offset
1 11111 0010 LD1 (multiple structures)four registers, immediate offset
1 11111 0100 LD3 (multiple structures)immediate offset
1 11111 0110 LD1 (multiple structures)three registers, immediate offset
1 11111 0111 LD1 (multiple structures)one register, immediate offset
1 11111 1000 LD2 (multiple structures)immediate offset
1 11111 1010 LD1 (multiple structures)two registers, immediate offset

Advanced SIMD load/store single structure

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
0Q0011010LR00000opcodeSsizeRnRt
Decode fields Instruction Details
L R opcode S size
0 11x UNALLOCATED
0 0 000 ST1 (single structure)8-bit
0 0 001 ST3 (single structure)8-bit
0 0 010 x0 ST1 (single structure)16-bit
0 0 010 x1 UNALLOCATED
0 0 011 x0 ST3 (single structure)16-bit
0 0 011 x1 UNALLOCATED
0 0 100 00 ST1 (single structure)32-bit
0 0 100 1x UNALLOCATED
0 0 100 0 01 ST1 (single structure)64-bit
0 0 100 1 01 UNALLOCATED
0 0 101 00 ST3 (single structure)32-bit
0 0 101 10 UNALLOCATED
0 0 101 0 01 ST3 (single structure)64-bit
0 0 101 0 11 UNALLOCATED
0 0 101 1 x1 UNALLOCATED
0 1 000 ST2 (single structure)8-bit
0 1 001 ST4 (single structure)8-bit
0 1 010 x0 ST2 (single structure)16-bit
0 1 010 x1 UNALLOCATED
0 1 011 x0 ST4 (single structure)16-bit
0 1 011 x1 UNALLOCATED
0 1 100 00 ST2 (single structure)32-bit
0 1 100 10 UNALLOCATED
0 1 100 0 01 ST2 (single structure)64-bit
0 1 100 0 11 UNALLOCATED
0 1 100 1 x1 UNALLOCATED
0 1 101 00 ST4 (single structure)32-bit
0 1 101 10 UNALLOCATED
0 1 101 0 01 ST4 (single structure)64-bit
0 1 101 0 11 UNALLOCATED
0 1 101 1 x1 UNALLOCATED
1 0 000 LD1 (single structure)8-bit
1 0 001 LD3 (single structure)8-bit
1 0 010 x0 LD1 (single structure)16-bit
1 0 010 x1 UNALLOCATED
1 0 011 x0 LD3 (single structure)16-bit
1 0 011 x1 UNALLOCATED
1 0 100 00 LD1 (single structure)32-bit
1 0 100 1x UNALLOCATED
1 0 100 0 01 LD1 (single structure)64-bit
1 0 100 1 01 UNALLOCATED
1 0 101 00 LD3 (single structure)32-bit
1 0 101 10 UNALLOCATED
1 0 101 0 01 LD3 (single structure)64-bit
1 0 101 0 11 UNALLOCATED
1 0 101 1 x1 UNALLOCATED
1 0 110 0 LD1R
1 0 110 1 UNALLOCATED
1 0 111 0 LD3R
1 0 111 1 UNALLOCATED
1 1 000 LD2 (single structure)8-bit
1 1 001 LD4 (single structure)8-bit
1 1 010 x0 LD2 (single structure)16-bit
1 1 010 x1 UNALLOCATED
1 1 011 x0 LD4 (single structure)16-bit
1 1 011 x1 UNALLOCATED
1 1 100 00 LD2 (single structure)32-bit
1 1 100 10 UNALLOCATED
1 1 100 0 01 LD2 (single structure)64-bit
1 1 100 0 11 UNALLOCATED
1 1 100 1 x1 UNALLOCATED
1 1 101 00 LD4 (single structure)32-bit
1 1 101 10 UNALLOCATED
1 1 101 0 01 LD4 (single structure)64-bit
1 1 101 0 11 UNALLOCATED
1 1 101 1 x1 UNALLOCATED
1 1 110 0 LD2R
1 1 110 1 UNALLOCATED
1 1 111 0 LD4R
1 1 111 1 UNALLOCATED

Advanced SIMD load/store single structure (post-indexed)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
0Q0011011LRRmopcodeSsizeRnRt
Decode fields Instruction Details
L R Rm opcode S size
0 11x UNALLOCATED
0 0 010 x1 UNALLOCATED
0 0 011 x1 UNALLOCATED
0 0 100 1x UNALLOCATED
0 0 100 1 01 UNALLOCATED
0 0 101 10 UNALLOCATED
0 0 101 0 11 UNALLOCATED
0 0 101 1 x1 UNALLOCATED
0 0 != 11111 000 ST1 (single structure)8-bit, register offset
0 0 != 11111 001 ST3 (single structure)8-bit, register offset
0 0 != 11111 010 x0 ST1 (single structure)16-bit, register offset
0 0 != 11111 011 x0 ST3 (single structure)16-bit, register offset
0 0 != 11111 100 00 ST1 (single structure)32-bit, register offset
0 0 != 11111 100 0 01 ST1 (single structure)64-bit, register offset
0 0 != 11111 101 00 ST3 (single structure)32-bit, register offset
0 0 != 11111 101 0 01 ST3 (single structure)64-bit, register offset
0 0 11111 000 ST1 (single structure)8-bit, immediate offset
0 0 11111 001 ST3 (single structure)8-bit, immediate offset
0 0 11111 010 x0 ST1 (single structure)16-bit, immediate offset
0 0 11111 011 x0 ST3 (single structure)16-bit, immediate offset
0 0 11111 100 00 ST1 (single structure)32-bit, immediate offset
0 0 11111 100 0 01 ST1 (single structure)64-bit, immediate offset
0 0 11111 101 00 ST3 (single structure)32-bit, immediate offset
0 0 11111 101 0 01 ST3 (single structure)64-bit, immediate offset
0 1 010 x1 UNALLOCATED
0 1 011 x1 UNALLOCATED
0 1 100 10 UNALLOCATED
0 1 100 0 11 UNALLOCATED
0 1 100 1 x1 UNALLOCATED
0 1 101 10 UNALLOCATED
0 1 101 0 11 UNALLOCATED
0 1 101 1 x1 UNALLOCATED
0 1 != 11111 000 ST2 (single structure)8-bit, register offset
0 1 != 11111 001 ST4 (single structure)8-bit, register offset
0 1 != 11111 010 x0 ST2 (single structure)16-bit, register offset
0 1 != 11111 011 x0 ST4 (single structure)16-bit, register offset
0 1 != 11111 100 00 ST2 (single structure)32-bit, register offset
0 1 != 11111 100 0 01 ST2 (single structure)64-bit, register offset
0 1 != 11111 101 00 ST4 (single structure)32-bit, register offset
0 1 != 11111 101 0 01 ST4 (single structure)64-bit, register offset
0 1 11111 000 ST2 (single structure)8-bit, immediate offset
0 1 11111 001 ST4 (single structure)8-bit, immediate offset
0 1 11111 010 x0 ST2 (single structure)16-bit, immediate offset
0 1 11111 011 x0 ST4 (single structure)16-bit, immediate offset
0 1 11111 100 00 ST2 (single structure)32-bit, immediate offset
0 1 11111 100 0 01 ST2 (single structure)64-bit, immediate offset
0 1 11111 101 00 ST4 (single structure)32-bit, immediate offset
0 1 11111 101 0 01 ST4 (single structure)64-bit, immediate offset
1 0 010 x1 UNALLOCATED
1 0 011 x1 UNALLOCATED
1 0 100 1x UNALLOCATED
1 0 100 1 01 UNALLOCATED
1 0 101 10 UNALLOCATED
1 0 101 0 11 UNALLOCATED
1 0 101 1 x1 UNALLOCATED
1 0 110 1 UNALLOCATED
1 0 111 1 UNALLOCATED
1 0 != 11111 000 LD1 (single structure)8-bit, register offset
1 0 != 11111 001 LD3 (single structure)8-bit, register offset
1 0 != 11111 010 x0 LD1 (single structure)16-bit, register offset
1 0 != 11111 011 x0 LD3 (single structure)16-bit, register offset
1 0 != 11111 100 00 LD1 (single structure)32-bit, register offset
1 0 != 11111 100 0 01 LD1 (single structure)64-bit, register offset
1 0 != 11111 101 00 LD3 (single structure)32-bit, register offset
1 0 != 11111 101 0 01 LD3 (single structure)64-bit, register offset
1 0 != 11111 110 0 LD1Rregister offset
1 0 != 11111 111 0 LD3Rregister offset
1 0 11111 000 LD1 (single structure)8-bit, immediate offset
1 0 11111 001 LD3 (single structure)8-bit, immediate offset
1 0 11111 010 x0 LD1 (single structure)16-bit, immediate offset
1 0 11111 011 x0 LD3 (single structure)16-bit, immediate offset
1 0 11111 100 00 LD1 (single structure)32-bit, immediate offset
1 0 11111 100 0 01 LD1 (single structure)64-bit, immediate offset
1 0 11111 101 00 LD3 (single structure)32-bit, immediate offset
1 0 11111 101 0 01 LD3 (single structure)64-bit, immediate offset
1 0 11111 110 0 LD1Rimmediate offset
1 0 11111 111 0 LD3Rimmediate offset
1 1 010 x1 UNALLOCATED
1 1 011 x1 UNALLOCATED
1 1 100 10 UNALLOCATED
1 1 100 0 11 UNALLOCATED
1 1 100 1 x1 UNALLOCATED
1 1 101 10 UNALLOCATED
1 1 101 0 11 UNALLOCATED
1 1 101 1 x1 UNALLOCATED
1 1 110 1 UNALLOCATED
1 1 111 1 UNALLOCATED
1 1 != 11111 000 LD2 (single structure)8-bit, register offset
1 1 != 11111 001 LD4 (single structure)8-bit, register offset
1 1 != 11111 010 x0 LD2 (single structure)16-bit, register offset
1 1 != 11111 011 x0 LD4 (single structure)16-bit, register offset
1 1 != 11111 100 00 LD2 (single structure)32-bit, register offset
1 1 != 11111 100 0 01 LD2 (single structure)64-bit, register offset
1 1 != 11111 101 00 LD4 (single structure)32-bit, register offset
1 1 != 11111 101 0 01 LD4 (single structure)64-bit, register offset
1 1 != 11111 110 0 LD2Rregister offset
1 1 != 11111 111 0 LD4Rregister offset
1 1 11111 000 LD2 (single structure)8-bit, immediate offset
1 1 11111 001 LD4 (single structure)8-bit, immediate offset
1 1 11111 010 x0 LD2 (single structure)16-bit, immediate offset
1 1 11111 011 x0 LD4 (single structure)16-bit, immediate offset
1 1 11111 100 00 LD2 (single structure)32-bit, immediate offset
1 1 11111 100 0 01 LD2 (single structure)64-bit, immediate offset
1 1 11111 101 00 LD4 (single structure)32-bit, immediate offset
1 1 11111 101 0 01 LD4 (single structure)64-bit, immediate offset
1 1 11111 110 0 LD2Rimmediate offset
1 1 11111 111 0 LD4Rimmediate offset

Load/store exclusive

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size001000o2Lo1Rso0Rt2RnRt
Decode fields Instruction Details Architecture Version
size o2 L o1 o0 Rt2
1 1 != 11111 UNALLOCATED-
0x 0 1 != 11111 UNALLOCATED-
00 0 0 0 0 STXRB-
00 0 0 0 1 STLXRB-
00 0 0 1 0 11111 CASP, CASPA, CASPAL, CASPL32-bit, no memory orderingARMv8.1
00 0 0 1 1 11111 CASP, CASPA, CASPAL, CASPL32-bit, releaseARMv8.1
00 0 1 0 0 LDXRB-
00 0 1 0 1 LDAXRB-
00 0 1 1 0 11111 CASP, CASPA, CASPAL, CASPL32-bit, acquireARMv8.1
00 0 1 1 1 11111 CASP, CASPA, CASPAL, CASPL32-bit, acquire and releaseARMv8.1
00 1 0 0 0 STLLRBARMv8.1
00 1 0 0 1 STLRB-
00 1 0 1 0 11111 CASB, CASAB, CASALB, CASLBno memory orderingARMv8.1
00 1 0 1 1 11111 CASB, CASAB, CASALB, CASLBreleaseARMv8.1
00 1 1 0 0 LDLARBARMv8.1
00 1 1 0 1 LDARB-
00 1 1 1 0 11111 CASB, CASAB, CASALB, CASLBacquireARMv8.1
00 1 1 1 1 11111 CASB, CASAB, CASALB, CASLBacquire and releaseARMv8.1
01 0 0 0 0 STXRH-
01 0 0 0 1 STLXRH-
01 0 0 1 0 11111 CASP, CASPA, CASPAL, CASPL64-bit, no memory orderingARMv8.1
01 0 0 1 1 11111 CASP, CASPA, CASPAL, CASPL64-bit, releaseARMv8.1
01 0 1 0 0 LDXRH-
01 0 1 0 1 LDAXRH-
01 0 1 1 0 11111 CASP, CASPA, CASPAL, CASPL64-bit, acquireARMv8.1
01 0 1 1 1 11111 CASP, CASPA, CASPAL, CASPL64-bit, acquire and releaseARMv8.1
01 1 0 0 0 STLLRHARMv8.1
01 1 0 0 1 STLRH-
01 1 0 1 0 11111 CASH, CASAH, CASALH, CASLHno memory orderingARMv8.1
01 1 0 1 1 11111 CASH, CASAH, CASALH, CASLHreleaseARMv8.1
01 1 1 0 0 LDLARHARMv8.1
01 1 1 0 1 LDARH-
01 1 1 1 0 11111 CASH, CASAH, CASALH, CASLHacquireARMv8.1
01 1 1 1 1 11111 CASH, CASAH, CASALH, CASLHacquire and releaseARMv8.1
10 0 0 0 0 STXR32-bit-
10 0 0 0 1 STLXR32-bit-
10 0 0 1 0 STXP32-bit-
10 0 0 1 1 STLXP32-bit-
10 0 1 0 0 LDXR32-bit-
10 0 1 0 1 LDAXR32-bit-
10 0 1 1 0 LDXP32-bit-
10 0 1 1 1 LDAXP32-bit-
10 1 0 0 0 STLLR32-bitARMv8.1
10 1 0 0 1 STLR32-bit-
10 1 0 1 0 11111 CAS, CASA, CASAL, CASL32-bit, no memory orderingARMv8.1
10 1 0 1 1 11111 CAS, CASA, CASAL, CASL32-bit, releaseARMv8.1
10 1 1 0 0 LDLAR32-bitARMv8.1
10 1 1 0 1 LDAR32-bit-
10 1 1 1 0 11111 CAS, CASA, CASAL, CASL32-bit, acquireARMv8.1
10 1 1 1 1 11111 CAS, CASA, CASAL, CASL32-bit, acquire and releaseARMv8.1
11 0 0 0 0 STXR64-bit-
11 0 0 0 1 STLXR64-bit-
11 0 0 1 0 STXP64-bit-
11 0 0 1 1 STLXP64-bit-
11 0 1 0 0 LDXR64-bit-
11 0 1 0 1 LDAXR64-bit-
11 0 1 1 0 LDXP64-bit-
11 0 1 1 1 LDAXP64-bit-
11 1 0 0 0 STLLR64-bitARMv8.1
11 1 0 0 1 STLR64-bit-
11 1 0 1 0 11111 CAS, CASA, CASAL, CASL64-bit, no memory orderingARMv8.1
11 1 0 1 1 11111 CAS, CASA, CASAL, CASL64-bit, releaseARMv8.1
11 1 1 0 0 LDLAR64-bitARMv8.1
11 1 1 0 1 LDAR64-bit-
11 1 1 1 0 11111 CAS, CASA, CASAL, CASL64-bit, acquireARMv8.1
11 1 1 1 1 11111 CAS, CASA, CASAL, CASL64-bit, acquire and releaseARMv8.1

Load register (literal)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
opc011V00imm19Rt
Decode fields Instruction Details
opc V
00 0 LDR (literal)32-bit
00 1 LDR (literal, SIMD&FP)32-bit
01 0 LDR (literal)64-bit
01 1 LDR (literal, SIMD&FP)64-bit
10 0 LDRSW (literal)
10 1 LDR (literal, SIMD&FP)128-bit
11 0 PRFM (literal)
11 1 UNALLOCATED

Load/store no-allocate pair (offset)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
opc101V000Limm7Rt2RnRt
Decode fields Instruction Details
opc V L
00 0 0 STNP32-bit
00 0 1 LDNP32-bit
00 1 0 STNP (SIMD&FP)32-bit
00 1 1 LDNP (SIMD&FP)32-bit
01 0 UNALLOCATED
01 1 0 STNP (SIMD&FP)64-bit
01 1 1 LDNP (SIMD&FP)64-bit
10 0 0 STNP64-bit
10 0 1 LDNP64-bit
10 1 0 STNP (SIMD&FP)128-bit
10 1 1 LDNP (SIMD&FP)128-bit
11 UNALLOCATED

Load/store register pair (post-indexed)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
opc101V001Limm7Rt2RnRt
Decode fields Instruction Details
opc V L
00 0 0 STP32-bit
00 0 1 LDP32-bit
00 1 0 STP (SIMD&FP)32-bit
00 1 1 LDP (SIMD&FP)32-bit
01 0 0 UNALLOCATED
01 0 1 LDPSW
01 1 0 STP (SIMD&FP)64-bit
01 1 1 LDP (SIMD&FP)64-bit
10 0 0 STP64-bit
10 0 1 LDP64-bit
10 1 0 STP (SIMD&FP)128-bit
10 1 1 LDP (SIMD&FP)128-bit
11 UNALLOCATED

Load/store register pair (offset)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
opc101V010Limm7Rt2RnRt
Decode fields Instruction Details
opc V L
00 0 0 STP32-bit
00 0 1 LDP32-bit
00 1 0 STP (SIMD&FP)32-bit
00 1 1 LDP (SIMD&FP)32-bit
01 0 0 UNALLOCATED
01 0 1 LDPSW
01 1 0 STP (SIMD&FP)64-bit
01 1 1 LDP (SIMD&FP)64-bit
10 0 0 STP64-bit
10 0 1 LDP64-bit
10 1 0 STP (SIMD&FP)128-bit
10 1 1 LDP (SIMD&FP)128-bit
11 UNALLOCATED

Load/store register pair (pre-indexed)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
opc101V011Limm7Rt2RnRt
Decode fields Instruction Details
opc V L
00 0 0 STP32-bit
00 0 1 LDP32-bit
00 1 0 STP (SIMD&FP)32-bit
00 1 1 LDP (SIMD&FP)32-bit
01 0 0 UNALLOCATED
01 0 1 LDPSW
01 1 0 STP (SIMD&FP)64-bit
01 1 1 LDP (SIMD&FP)64-bit
10 0 0 STP64-bit
10 0 1 LDP64-bit
10 1 0 STP (SIMD&FP)128-bit
10 1 1 LDP (SIMD&FP)128-bit
11 UNALLOCATED

Load/store register (unscaled immediate)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111V00opc0imm900RnRt
Decode fields Instruction Details
size V opc
x1 1 1x UNALLOCATED
00 0 00 STURB
00 0 01 LDURB
00 0 10 LDURSB64-bit
00 0 11 LDURSB32-bit
00 1 00 STUR (SIMD&FP)8-bit
00 1 01 LDUR (SIMD&FP)8-bit
00 1 10 STUR (SIMD&FP)128-bit
00 1 11 LDUR (SIMD&FP)128-bit
01 0 00 STURH
01 0 01 LDURH
01 0 10 LDURSH64-bit
01 0 11 LDURSH32-bit
01 1 00 STUR (SIMD&FP)16-bit
01 1 01 LDUR (SIMD&FP)16-bit
1x 0 11 UNALLOCATED
1x 1 1x UNALLOCATED
10 0 00 STUR32-bit
10 0 01 LDUR32-bit
10 0 10 LDURSW
10 1 00 STUR (SIMD&FP)32-bit
10 1 01 LDUR (SIMD&FP)32-bit
11 0 00 STUR64-bit
11 0 01 LDUR64-bit
11 0 10 PRFM (unscaled offset)
11 1 00 STUR (SIMD&FP)64-bit
11 1 01 LDUR (SIMD&FP)64-bit

Load/store register (immediate post-indexed)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111V00opc0imm901RnRt
Decode fields Instruction Details
size V opc
x1 1 1x UNALLOCATED
00 0 00 STRB (immediate)
00 0 01 LDRB (immediate)
00 0 10 LDRSB (immediate)64-bit
00 0 11 LDRSB (immediate)32-bit
00 1 00 STR (immediate, SIMD&FP)8-bit
00 1 01 LDR (immediate, SIMD&FP)8-bit
00 1 10 STR (immediate, SIMD&FP)128-bit
00 1 11 LDR (immediate, SIMD&FP)128-bit
01 0 00 STRH (immediate)
01 0 01 LDRH (immediate)
01 0 10 LDRSH (immediate)64-bit
01 0 11 LDRSH (immediate)32-bit
01 1 00 STR (immediate, SIMD&FP)16-bit
01 1 01 LDR (immediate, SIMD&FP)16-bit
1x 0 11 UNALLOCATED
1x 1 1x UNALLOCATED
10 0 00 STR (immediate)32-bit
10 0 01 LDR (immediate)32-bit
10 0 10 LDRSW (immediate)
10 1 00 STR (immediate, SIMD&FP)32-bit
10 1 01 LDR (immediate, SIMD&FP)32-bit
11 0 00 STR (immediate)64-bit
11 0 01 LDR (immediate)64-bit
11 0 10 UNALLOCATED
11 1 00 STR (immediate, SIMD&FP)64-bit
11 1 01 LDR (immediate, SIMD&FP)64-bit

Load/store register (unprivileged)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111V00opc0imm910RnRt
Decode fields Instruction Details
size V opc
1 UNALLOCATED
00 0 00 STTRB
00 0 01 LDTRB
00 0 10 LDTRSB64-bit
00 0 11 LDTRSB32-bit
01 0 00 STTRH
01 0 01 LDTRH
01 0 10 LDTRSH64-bit
01 0 11 LDTRSH32-bit
1x 0 11 UNALLOCATED
10 0 00 STTR32-bit
10 0 01 LDTR32-bit
10 0 10 LDTRSW
11 0 00 STTR64-bit
11 0 01 LDTR64-bit
11 0 10 UNALLOCATED

Load/store register (immediate pre-indexed)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111V00opc0imm911RnRt
Decode fields Instruction Details
size V opc
x1 1 1x UNALLOCATED
00 0 00 STRB (immediate)
00 0 01 LDRB (immediate)
00 0 10 LDRSB (immediate)64-bit
00 0 11 LDRSB (immediate)32-bit
00 1 00 STR (immediate, SIMD&FP)8-bit
00 1 01 LDR (immediate, SIMD&FP)8-bit
00 1 10 STR (immediate, SIMD&FP)128-bit
00 1 11 LDR (immediate, SIMD&FP)128-bit
01 0 00 STRH (immediate)
01 0 01 LDRH (immediate)
01 0 10 LDRSH (immediate)64-bit
01 0 11 LDRSH (immediate)32-bit
01 1 00 STR (immediate, SIMD&FP)16-bit
01 1 01 LDR (immediate, SIMD&FP)16-bit
1x 0 11 UNALLOCATED
1x 1 1x UNALLOCATED
10 0 00 STR (immediate)32-bit
10 0 01 LDR (immediate)32-bit
10 0 10 LDRSW (immediate)
10 1 00 STR (immediate, SIMD&FP)32-bit
10 1 01 LDR (immediate, SIMD&FP)32-bit
11 0 00 STR (immediate)64-bit
11 0 01 LDR (immediate)64-bit
11 0 10 UNALLOCATED
11 1 00 STR (immediate, SIMD&FP)64-bit
11 1 01 LDR (immediate, SIMD&FP)64-bit

Atomic memory operations

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111V00AR1Rso3opc00RnRt
Decode fields Instruction Details Architecture Version
size V A R o3 opc Rt
0 1 001 UNALLOCATED-
0 1 01x UNALLOCATED-
0 1 101 UNALLOCATED-
0 1 11x UNALLOCATED-
0 0 1 100 UNALLOCATED-
0 1 1 1 100 UNALLOCATED-
1 UNALLOCATED-
00 0 0 0 0 000 != 11111 LDADDB, LDADDAB, LDADDALB, LDADDLBno memory orderingARMv8.1
00 0 0 0 0 000 11111 STADDB, STADDLBno memory orderingARMv8.1
00 0 0 0 0 001 != 11111 LDCLRB, LDCLRAB, LDCLRALB, LDCLRLBno memory orderingARMv8.1
00 0 0 0 0 001 11111 STCLRB, STCLRLBno memory orderingARMv8.1
00 0 0 0 0 010 != 11111 LDEORB, LDEORAB, LDEORALB, LDEORLBno memory orderingARMv8.1
00 0 0 0 0 010 11111 STEORB, STEORLBno memory orderingARMv8.1
00 0 0 0 0 011 != 11111 LDSETB, LDSETAB, LDSETALB, LDSETLBno memory orderingARMv8.1
00 0 0 0 0 011 11111 STSETB, STSETLBno memory orderingARMv8.1
00 0 0 0 0 100 != 11111 LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLBno memory orderingARMv8.1
00 0 0 0 0 100 11111 STSMAXB, STSMAXLBno memory orderingARMv8.1
00 0 0 0 0 101 != 11111 LDSMINB, LDSMINAB, LDSMINALB, LDSMINLBno memory orderingARMv8.1
00 0 0 0 0 101 11111 STSMINB, STSMINLBno memory orderingARMv8.1
00 0 0 0 0 110 != 11111 LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLBno memory orderingARMv8.1
00 0 0 0 0 110 11111 STUMAXB, STUMAXLBno memory orderingARMv8.1
00 0 0 0 0 111 != 11111 LDUMINB, LDUMINAB, LDUMINALB, LDUMINLBno memory orderingARMv8.1
00 0 0 0 0 111 11111 STUMINB, STUMINLBno memory orderingARMv8.1
00 0 0 0 1 000 SWPB, SWPAB, SWPALB, SWPLBno memory orderingARMv8.1
00 0 0 1 0 000 != 11111 LDADDB, LDADDAB, LDADDALB, LDADDLBreleaseARMv8.1
00 0 0 1 0 000 11111 STADDB, STADDLBreleaseARMv8.1
00 0 0 1 0 001 != 11111 LDCLRB, LDCLRAB, LDCLRALB, LDCLRLBreleaseARMv8.1
00 0 0 1 0 001 11111 STCLRB, STCLRLBreleaseARMv8.1
00 0 0 1 0 010 != 11111 LDEORB, LDEORAB, LDEORALB, LDEORLBreleaseARMv8.1
00 0 0 1 0 010 11111 STEORB, STEORLBreleaseARMv8.1
00 0 0 1 0 011 != 11111 LDSETB, LDSETAB, LDSETALB, LDSETLBreleaseARMv8.1
00 0 0 1 0 011 11111 STSETB, STSETLBreleaseARMv8.1
00 0 0 1 0 100 != 11111 LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLBreleaseARMv8.1
00 0 0 1 0 100 11111 STSMAXB, STSMAXLBreleaseARMv8.1
00 0 0 1 0 101 != 11111 LDSMINB, LDSMINAB, LDSMINALB, LDSMINLBreleaseARMv8.1
00 0 0 1 0 101 11111 STSMINB, STSMINLBreleaseARMv8.1
00 0 0 1 0 110 != 11111 LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLBreleaseARMv8.1
00 0 0 1 0 110 11111 STUMAXB, STUMAXLBreleaseARMv8.1
00 0 0 1 0 111 != 11111 LDUMINB, LDUMINAB, LDUMINALB, LDUMINLBreleaseARMv8.1
00 0 0 1 0 111 11111 STUMINB, STUMINLBreleaseARMv8.1
00 0 0 1 1 000 SWPB, SWPAB, SWPALB, SWPLBreleaseARMv8.1
00 0 1 0 0 000 LDADDB, LDADDAB, LDADDALB, LDADDLBacquireARMv8.1
00 0 1 0 0 001 LDCLRB, LDCLRAB, LDCLRALB, LDCLRLBacquireARMv8.1
00 0 1 0 0 010 LDEORB, LDEORAB, LDEORALB, LDEORLBacquireARMv8.1
00 0 1 0 0 011 LDSETB, LDSETAB, LDSETALB, LDSETLBacquireARMv8.1
00 0 1 0 0 100 LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLBacquireARMv8.1
00 0 1 0 0 101 LDSMINB, LDSMINAB, LDSMINALB, LDSMINLBacquireARMv8.1
00 0 1 0 0 110 LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLBacquireARMv8.1
00 0 1 0 0 111 LDUMINB, LDUMINAB, LDUMINALB, LDUMINLBacquireARMv8.1
00 0 1 0 1 000 SWPB, SWPAB, SWPALB, SWPLBacquireARMv8.1
00 0 1 1 0 000 LDADDB, LDADDAB, LDADDALB, LDADDLBacquire and releaseARMv8.1
00 0 1 1 0 001 LDCLRB, LDCLRAB, LDCLRALB, LDCLRLBacquire and releaseARMv8.1
00 0 1 1 0 010 LDEORB, LDEORAB, LDEORALB, LDEORLBacquire and releaseARMv8.1
00 0 1 1 0 011 LDSETB, LDSETAB, LDSETALB, LDSETLBacquire and releaseARMv8.1
00 0 1 1 0 100 LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLBacquire and releaseARMv8.1
00 0 1 1 0 101 LDSMINB, LDSMINAB, LDSMINALB, LDSMINLBacquire and releaseARMv8.1
00 0 1 1 0 110 LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLBacquire and releaseARMv8.1
00 0 1 1 0 111 LDUMINB, LDUMINAB, LDUMINALB, LDUMINLBacquire and releaseARMv8.1
00 0 1 1 1 000 SWPB, SWPAB, SWPALB, SWPLBacquire and releaseARMv8.1
01 0 0 0 0 000 != 11111 LDADDH, LDADDAH, LDADDALH, LDADDLHno memory orderingARMv8.1
01 0 0 0 0 000 11111 STADDH, STADDLHno memory orderingARMv8.1
01 0 0 0 0 001 != 11111 LDCLRH, LDCLRAH, LDCLRALH, LDCLRLHno memory orderingARMv8.1
01 0 0 0 0 001 11111 STCLRH, STCLRLHno memory orderingARMv8.1
01 0 0 0 0 010 != 11111 LDEORH, LDEORAH, LDEORALH, LDEORLHno memory orderingARMv8.1
01 0 0 0 0 010 11111 STEORH, STEORLHno memory orderingARMv8.1
01 0 0 0 0 011 != 11111 LDSETH, LDSETAH, LDSETALH, LDSETLHno memory orderingARMv8.1
01 0 0 0 0 011 11111 STSETH, STSETLHno memory orderingARMv8.1
01 0 0 0 0 100 != 11111 LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLHno memory orderingARMv8.1
01 0 0 0 0 100 11111 STSMAXH, STSMAXLHno memory orderingARMv8.1
01 0 0 0 0 101 != 11111 LDSMINH, LDSMINAH, LDSMINALH, LDSMINLHno memory orderingARMv8.1
01 0 0 0 0 101 11111 STSMINH, STSMINLHno memory orderingARMv8.1
01 0 0 0 0 110 != 11111 LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLHno memory orderingARMv8.1
01 0 0 0 0 110 11111 STUMAXH, STUMAXLHno memory orderingARMv8.1
01 0 0 0 0 111 != 11111 LDUMINH, LDUMINAH, LDUMINALH, LDUMINLHno memory orderingARMv8.1
01 0 0 0 0 111 11111 STUMINH, STUMINLHno memory orderingARMv8.1
01 0 0 0 1 000 SWPH, SWPAH, SWPALH, SWPLHno memory orderingARMv8.1
01 0 0 1 0 000 != 11111 LDADDH, LDADDAH, LDADDALH, LDADDLHreleaseARMv8.1
01 0 0 1 0 000 11111 STADDH, STADDLHreleaseARMv8.1
01 0 0 1 0 001 != 11111 LDCLRH, LDCLRAH, LDCLRALH, LDCLRLHreleaseARMv8.1
01 0 0 1 0 001 11111 STCLRH, STCLRLHreleaseARMv8.1
01 0 0 1 0 010 != 11111 LDEORH, LDEORAH, LDEORALH, LDEORLHreleaseARMv8.1
01 0 0 1 0 010 11111 STEORH, STEORLHreleaseARMv8.1
01 0 0 1 0 011 != 11111 LDSETH, LDSETAH, LDSETALH, LDSETLHreleaseARMv8.1
01 0 0 1 0 011 11111 STSETH, STSETLHreleaseARMv8.1
01 0 0 1 0 100 != 11111 LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLHreleaseARMv8.1
01 0 0 1 0 100 11111 STSMAXH, STSMAXLHreleaseARMv8.1
01 0 0 1 0 101 != 11111 LDSMINH, LDSMINAH, LDSMINALH, LDSMINLHreleaseARMv8.1
01 0 0 1 0 101 11111 STSMINH, STSMINLHreleaseARMv8.1
01 0 0 1 0 110 != 11111 LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLHreleaseARMv8.1
01 0 0 1 0 110 11111 STUMAXH, STUMAXLHreleaseARMv8.1
01 0 0 1 0 111 != 11111 LDUMINH, LDUMINAH, LDUMINALH, LDUMINLHreleaseARMv8.1
01 0 0 1 0 111 11111 STUMINH, STUMINLHreleaseARMv8.1
01 0 0 1 1 000 SWPH, SWPAH, SWPALH, SWPLHreleaseARMv8.1
01 0 1 0 0 000 LDADDH, LDADDAH, LDADDALH, LDADDLHacquireARMv8.1
01 0 1 0 0 001 LDCLRH, LDCLRAH, LDCLRALH, LDCLRLHacquireARMv8.1
01 0 1 0 0 010 LDEORH, LDEORAH, LDEORALH, LDEORLHacquireARMv8.1
01 0 1 0 0 011 LDSETH, LDSETAH, LDSETALH, LDSETLHacquireARMv8.1
01 0 1 0 0 100 LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLHacquireARMv8.1
01 0 1 0 0 101 LDSMINH, LDSMINAH, LDSMINALH, LDSMINLHacquireARMv8.1
01 0 1 0 0 110 LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLHacquireARMv8.1
01 0 1 0 0 111 LDUMINH, LDUMINAH, LDUMINALH, LDUMINLHacquireARMv8.1
01 0 1 0 1 000 SWPH, SWPAH, SWPALH, SWPLHacquireARMv8.1
01 0 1 1 0 000 LDADDH, LDADDAH, LDADDALH, LDADDLHacquire and releaseARMv8.1
01 0 1 1 0 001 LDCLRH, LDCLRAH, LDCLRALH, LDCLRLHacquire and releaseARMv8.1
01 0 1 1 0 010 LDEORH, LDEORAH, LDEORALH, LDEORLHacquire and releaseARMv8.1
01 0 1 1 0 011 LDSETH, LDSETAH, LDSETALH, LDSETLHacquire and releaseARMv8.1
01 0 1 1 0 100 LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLHacquire and releaseARMv8.1
01 0 1 1 0 101 LDSMINH, LDSMINAH, LDSMINALH, LDSMINLHacquire and releaseARMv8.1
01 0 1 1 0 110 LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLHacquire and releaseARMv8.1
01 0 1 1 0 111 LDUMINH, LDUMINAH, LDUMINALH, LDUMINLHacquire and releaseARMv8.1
01 0 1 1 1 000 SWPH, SWPAH, SWPALH, SWPLHacquire and releaseARMv8.1
10 0 0 0 0 000 != 11111 LDADD, LDADDA, LDADDAL, LDADDL32-bit, no memory orderingARMv8.1
10 0 0 0 0 000 11111 STADD, STADDL32-bit, no memory orderingARMv8.1
10 0 0 0 0 001 != 11111 LDCLR, LDCLRA, LDCLRAL, LDCLRL32-bit, no memory orderingARMv8.1
10 0 0 0 0 001 11111 STCLR, STCLRL32-bit, no memory orderingARMv8.1
10 0 0 0 0 010 != 11111 LDEOR, LDEORA, LDEORAL, LDEORL32-bit, no memory orderingARMv8.1
10 0 0 0 0 010 11111 STEOR, STEORL32-bit, no memory orderingARMv8.1
10 0 0 0 0 011 != 11111 LDSET, LDSETA, LDSETAL, LDSETL32-bit, no memory orderingARMv8.1
10 0 0 0 0 011 11111 STSET, STSETL32-bit, no memory orderingARMv8.1
10 0 0 0 0 100 != 11111 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL32-bit, no memory orderingARMv8.1
10 0 0 0 0 100 11111 STSMAX, STSMAXL32-bit, no memory orderingARMv8.1
10 0 0 0 0 101 != 11111 LDSMIN, LDSMINA, LDSMINAL, LDSMINL32-bit, no memory orderingARMv8.1
10 0 0 0 0 101 11111 STSMIN, STSMINL32-bit, no memory orderingARMv8.1
10 0 0 0 0 110 != 11111 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL32-bit, no memory orderingARMv8.1
10 0 0 0 0 110 11111 STUMAX, STUMAXL32-bit, no memory orderingARMv8.1
10 0 0 0 0 111 != 11111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL32-bit, no memory orderingARMv8.1
10 0 0 0 0 111 11111 STUMIN, STUMINL32-bit, no memory orderingARMv8.1
10 0 0 0 1 000 SWP, SWPA, SWPAL, SWPL32-bit, no memory orderingARMv8.1
10 0 0 1 0 000 != 11111 LDADD, LDADDA, LDADDAL, LDADDL32-bit, releaseARMv8.1
10 0 0 1 0 000 11111 STADD, STADDL32-bit, releaseARMv8.1
10 0 0 1 0 001 != 11111 LDCLR, LDCLRA, LDCLRAL, LDCLRL32-bit, releaseARMv8.1
10 0 0 1 0 001 11111 STCLR, STCLRL32-bit, releaseARMv8.1
10 0 0 1 0 010 != 11111 LDEOR, LDEORA, LDEORAL, LDEORL32-bit, releaseARMv8.1
10 0 0 1 0 010 11111 STEOR, STEORL32-bit, releaseARMv8.1
10 0 0 1 0 011 != 11111 LDSET, LDSETA, LDSETAL, LDSETL32-bit, releaseARMv8.1
10 0 0 1 0 011 11111 STSET, STSETL32-bit, releaseARMv8.1
10 0 0 1 0 100 != 11111 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL32-bit, releaseARMv8.1
10 0 0 1 0 100 11111 STSMAX, STSMAXL32-bit, releaseARMv8.1
10 0 0 1 0 101 != 11111 LDSMIN, LDSMINA, LDSMINAL, LDSMINL32-bit, releaseARMv8.1
10 0 0 1 0 101 11111 STSMIN, STSMINL32-bit, releaseARMv8.1
10 0 0 1 0 110 != 11111 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL32-bit, releaseARMv8.1
10 0 0 1 0 110 11111 STUMAX, STUMAXL32-bit, releaseARMv8.1
10 0 0 1 0 111 != 11111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL32-bit, releaseARMv8.1
10 0 0 1 0 111 11111 STUMIN, STUMINL32-bit, releaseARMv8.1
10 0 0 1 1 000 SWP, SWPA, SWPAL, SWPL32-bit, releaseARMv8.1
10 0 1 0 0 000 LDADD, LDADDA, LDADDAL, LDADDL32-bit, acquireARMv8.1
10 0 1 0 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL32-bit, acquireARMv8.1
10 0 1 0 0 010 LDEOR, LDEORA, LDEORAL, LDEORL32-bit, acquireARMv8.1
10 0 1 0 0 011 LDSET, LDSETA, LDSETAL, LDSETL32-bit, acquireARMv8.1
10 0 1 0 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL32-bit, acquireARMv8.1
10 0 1 0 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL32-bit, acquireARMv8.1
10 0 1 0 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL32-bit, acquireARMv8.1
10 0 1 0 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL32-bit, acquireARMv8.1
10 0 1 0 1 000 SWP, SWPA, SWPAL, SWPL32-bit, acquireARMv8.1
10 0 1 1 0 000 LDADD, LDADDA, LDADDAL, LDADDL32-bit, acquire and releaseARMv8.1
10 0 1 1 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL32-bit, acquire and releaseARMv8.1
10 0 1 1 0 010 LDEOR, LDEORA, LDEORAL, LDEORL32-bit, acquire and releaseARMv8.1
10 0 1 1 0 011 LDSET, LDSETA, LDSETAL, LDSETL32-bit, acquire and releaseARMv8.1
10 0 1 1 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL32-bit, acquire and releaseARMv8.1
10 0 1 1 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL32-bit, acquire and releaseARMv8.1
10 0 1 1 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL32-bit, acquire and releaseARMv8.1
10 0 1 1 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL32-bit, acquire and releaseARMv8.1
10 0 1 1 1 000 SWP, SWPA, SWPAL, SWPL32-bit, acquire and releaseARMv8.1
11 0 0 0 0 000 != 11111 LDADD, LDADDA, LDADDAL, LDADDL64-bit, no memory orderingARMv8.1
11 0 0 0 0 000 11111 STADD, STADDL64-bit, no memory orderingARMv8.1
11 0 0 0 0 001 != 11111 LDCLR, LDCLRA, LDCLRAL, LDCLRL64-bit, no memory orderingARMv8.1
11 0 0 0 0 001 11111 STCLR, STCLRL64-bit, no memory orderingARMv8.1
11 0 0 0 0 010 != 11111 LDEOR, LDEORA, LDEORAL, LDEORL64-bit, no memory orderingARMv8.1
11 0 0 0 0 010 11111 STEOR, STEORL64-bit, no memory orderingARMv8.1
11 0 0 0 0 011 != 11111 LDSET, LDSETA, LDSETAL, LDSETL64-bit, no memory orderingARMv8.1
11 0 0 0 0 011 11111 STSET, STSETL64-bit, no memory orderingARMv8.1
11 0 0 0 0 100 != 11111 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL64-bit, no memory orderingARMv8.1
11 0 0 0 0 100 11111 STSMAX, STSMAXL64-bit, no memory orderingARMv8.1
11 0 0 0 0 101 != 11111 LDSMIN, LDSMINA, LDSMINAL, LDSMINL64-bit, no memory orderingARMv8.1
11 0 0 0 0 101 11111 STSMIN, STSMINL64-bit, no memory orderingARMv8.1
11 0 0 0 0 110 != 11111 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL64-bit, no memory orderingARMv8.1
11 0 0 0 0 110 11111 STUMAX, STUMAXL64-bit, no memory orderingARMv8.1
11 0 0 0 0 111 != 11111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL64-bit, no memory orderingARMv8.1
11 0 0 0 0 111 11111 STUMIN, STUMINL64-bit, no memory orderingARMv8.1
11 0 0 0 1 000 SWP, SWPA, SWPAL, SWPL64-bit, no memory orderingARMv8.1
11 0 0 1 0 000 != 11111 LDADD, LDADDA, LDADDAL, LDADDL64-bit, releaseARMv8.1
11 0 0 1 0 000 11111 STADD, STADDL64-bit, releaseARMv8.1
11 0 0 1 0 001 != 11111 LDCLR, LDCLRA, LDCLRAL, LDCLRL64-bit, releaseARMv8.1
11 0 0 1 0 001 11111 STCLR, STCLRL64-bit, releaseARMv8.1
11 0 0 1 0 010 != 11111 LDEOR, LDEORA, LDEORAL, LDEORL64-bit, releaseARMv8.1
11 0 0 1 0 010 11111 STEOR, STEORL64-bit, releaseARMv8.1
11 0 0 1 0 011 != 11111 LDSET, LDSETA, LDSETAL, LDSETL64-bit, releaseARMv8.1
11 0 0 1 0 011 11111 STSET, STSETL64-bit, releaseARMv8.1
11 0 0 1 0 100 != 11111 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL64-bit, releaseARMv8.1
11 0 0 1 0 100 11111 STSMAX, STSMAXL64-bit, releaseARMv8.1
11 0 0 1 0 101 != 11111 LDSMIN, LDSMINA, LDSMINAL, LDSMINL64-bit, releaseARMv8.1
11 0 0 1 0 101 11111 STSMIN, STSMINL64-bit, releaseARMv8.1
11 0 0 1 0 110 != 11111 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL64-bit, releaseARMv8.1
11 0 0 1 0 110 11111 STUMAX, STUMAXL64-bit, releaseARMv8.1
11 0 0 1 0 111 != 11111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL64-bit, releaseARMv8.1
11 0 0 1 0 111 11111 STUMIN, STUMINL64-bit, releaseARMv8.1
11 0 0 1 1 000 SWP, SWPA, SWPAL, SWPL64-bit, releaseARMv8.1
11 0 1 0 0 000 LDADD, LDADDA, LDADDAL, LDADDL64-bit, acquireARMv8.1
11 0 1 0 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL64-bit, acquireARMv8.1
11 0 1 0 0 010 LDEOR, LDEORA, LDEORAL, LDEORL64-bit, acquireARMv8.1
11 0 1 0 0 011 LDSET, LDSETA, LDSETAL, LDSETL64-bit, acquireARMv8.1
11 0 1 0 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL64-bit, acquireARMv8.1
11 0 1 0 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL64-bit, acquireARMv8.1
11 0 1 0 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL64-bit, acquireARMv8.1
11 0 1 0 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL64-bit, acquireARMv8.1
11 0 1 0 1 000 SWP, SWPA, SWPAL, SWPL64-bit, acquireARMv8.1
11 0 1 1 0 000 LDADD, LDADDA, LDADDAL, LDADDL64-bit, acquire and releaseARMv8.1
11 0 1 1 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL64-bit, acquire and releaseARMv8.1
11 0 1 1 0 010 LDEOR, LDEORA, LDEORAL, LDEORL64-bit, acquire and releaseARMv8.1
11 0 1 1 0 011 LDSET, LDSETA, LDSETAL, LDSETL64-bit, acquire and releaseARMv8.1
11 0 1 1 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL64-bit, acquire and releaseARMv8.1
11 0 1 1 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL64-bit, acquire and releaseARMv8.1
11 0 1 1 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL64-bit, acquire and releaseARMv8.1
11 0 1 1 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL64-bit, acquire and releaseARMv8.1
11 0 1 1 1 000 SWP, SWPA, SWPAL, SWPL64-bit, acquire and releaseARMv8.1

Load/store register (register offset)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111V00opc1RmoptionS10RnRt
Decode fields Instruction Details
size V opc option
x0x UNALLOCATED
x1 1 1x UNALLOCATED
00 0 00 != 011 STRB (register)extended register
00 0 00 011 STRB (register)shifted register
00 0 01 != 011 LDRB (register)extended register
00 0 01 011 LDRB (register)shifted register
00 0 10 != 011 LDRSB (register)64-bit with extended register offset
00 0 10 011 LDRSB (register)64-bit with shifted register offset
00 0 11 != 011 LDRSB (register)32-bit with extended register offset
00 0 11 011 LDRSB (register)32-bit with shifted register offset
00 1 00 != 011 STR (register, SIMD&FP)
00 1 00 011 STR (register, SIMD&FP)
00 1 01 != 011 LDR (register, SIMD&FP)
00 1 01 011 LDR (register, SIMD&FP)
00 1 10 STR (register, SIMD&FP)
00 1 11 LDR (register, SIMD&FP)
01 0 00 STRH (register)
01 0 01 LDRH (register)
01 0 10 LDRSH (register)64-bit
01 0 11 LDRSH (register)32-bit
01 1 00 STR (register, SIMD&FP)
01 1 01 LDR (register, SIMD&FP)
1x 0 11 UNALLOCATED
1x 1 1x UNALLOCATED
10 0 00 STR (register)32-bit
10 0 01 LDR (register)32-bit
10 0 10 LDRSW (register)
10 1 00 STR (register, SIMD&FP)
10 1 01 LDR (register, SIMD&FP)
11 0 00 STR (register)64-bit
11 0 01 LDR (register)64-bit
11 0 10 PRFM (register)
11 1 00 STR (register, SIMD&FP)
11 1 01 LDR (register, SIMD&FP)

Load/store register (unsigned immediate)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111V01opcimm12RnRt
Decode fields Instruction Details
size V opc
x1 1 1x UNALLOCATED
00 0 00 STRB (immediate)
00 0 01 LDRB (immediate)
00 0 10 LDRSB (immediate)64-bit
00 0 11 LDRSB (immediate)32-bit
00 1 00 STR (immediate, SIMD&FP)8-bit
00 1 01 LDR (immediate, SIMD&FP)8-bit
00 1 10 STR (immediate, SIMD&FP)128-bit
00 1 11 LDR (immediate, SIMD&FP)128-bit
01 0 00 STRH (immediate)
01 0 01 LDRH (immediate)
01 0 10 LDRSH (immediate)64-bit
01 0 11 LDRSH (immediate)32-bit
01 1 00 STR (immediate, SIMD&FP)16-bit
01 1 01 LDR (immediate, SIMD&FP)16-bit
1x 0 11 UNALLOCATED
1x 1 1x UNALLOCATED
10 0 00 STR (immediate)32-bit
10 0 01 LDR (immediate)32-bit
10 0 10 LDRSW (immediate)
10 1 00 STR (immediate, SIMD&FP)32-bit
10 1 01 LDR (immediate, SIMD&FP)32-bit
11 0 00 STR (immediate)64-bit
11 0 01 LDR (immediate)64-bit
11 0 10 PRFM (immediate)
11 1 00 STR (immediate, SIMD&FP)64-bit
11 1 01 LDR (immediate, SIMD&FP)64-bit

Data Processing -- Register

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
op0op1101op2op3
Decode fields Instruction details
op0op1op2op3
0 1 0110 Data-processing (2 source)
1 1 0110 Data-processing (1 source)
0 0xxx Logical (shifted register)
0 1xx0 Add/subtract (shifted register)
0 1xx1 Add/subtract (extended register)
1 0000 Add/subtract (with carry)
1 0010 0 Conditional compare (register)
1 0010 1 Conditional compare (immediate)
1 0100 Conditional select
1 0xx1 UNALLOCATED
1 1xxx Data-processing (3 source)

Data-processing (2 source)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sf0S11010110RmopcodeRnRd
Decode fields Instruction Details
sf S opcode
00000x UNALLOCATED
011xxx UNALLOCATED
1xxxxx UNALLOCATED
0 0001xx UNALLOCATED
0 0011xx UNALLOCATED
1 UNALLOCATED
0 0 000010 UDIV32-bit
0 0 000011 SDIV32-bit
0 0 001000 LSLV32-bit
0 0 001001 LSRV32-bit
0 0 001010 ASRV32-bit
0 0 001011 RORV32-bit
0 0 010x11 UNALLOCATED
0 0 010000 CRC32B, CRC32H, CRC32W, CRC32XCRC32B
0 0 010001 CRC32B, CRC32H, CRC32W, CRC32XCRC32H
0 0 010010 CRC32B, CRC32H, CRC32W, CRC32XCRC32W
0 0 010100 CRC32CB, CRC32CH, CRC32CW, CRC32CXCRC32CB
0 0 010101 CRC32CB, CRC32CH, CRC32CW, CRC32CXCRC32CH
0 0 010110 CRC32CB, CRC32CH, CRC32CW, CRC32CXCRC32CW
1 0 000010 UDIV64-bit
1 0 000011 SDIV64-bit
1 0 001000 LSLV64-bit
1 0 001001 LSRV64-bit
1 0 001010 ASRV64-bit
1 0 001011 RORV64-bit
1 0 010xx0 UNALLOCATED
1 0 010x0x UNALLOCATED
1 0 010011 CRC32B, CRC32H, CRC32W, CRC32XCRC32X
1 0 010111 CRC32CB, CRC32CH, CRC32CW, CRC32CXCRC32CX

Data-processing (1 source)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sf1S11010110opcode2opcodeRnRd
Decode fields Instruction Details
sf S opcode2 opcode
xx1xxx UNALLOCATED
x1xxxx UNALLOCATED
1xxxxx UNALLOCATED
xxxx1 UNALLOCATED
xxx1x UNALLOCATED
xx1xx UNALLOCATED
x1xxx UNALLOCATED
1xxxx UNALLOCATED
0 00000 00011x UNALLOCATED
1 UNALLOCATED
0 0 00000 000000 RBIT32-bit
0 0 00000 000001 REV1632-bit
0 0 00000 000010 REV32-bit
0 0 00000 000011 UNALLOCATED
0 0 00000 000100 CLZ32-bit
0 0 00000 000101 CLS32-bit
1 0 00000 000000 RBIT64-bit
1 0 00000 000001 REV1664-bit
1 0 00000 000010 REV32
1 0 00000 000011 REV64-bit
1 0 00000 000100 CLZ64-bit
1 0 00000 000101 CLS64-bit

Logical (shifted register)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopc01010shiftNRmimm6RnRd
Decode fields Instruction Details
sf opc N imm6
0 1xxxxx UNALLOCATED
0 00 0 AND (shifted register)32-bit
0 00 1 BIC (shifted register)32-bit
0 01 0 ORR (shifted register)32-bit
0 01 1 ORN (shifted register)32-bit
0 10 0 EOR (shifted register)32-bit
0 10 1 EON (shifted register)32-bit
0 11 0 ANDS (shifted register)32-bit
0 11 1 BICS (shifted register)32-bit
1 00 0 AND (shifted register)64-bit
1 00 1 BIC (shifted register)64-bit
1 01 0 ORR (shifted register)64-bit
1 01 1 ORN (shifted register)64-bit
1 10 0 EOR (shifted register)64-bit
1 10 1 EON (shifted register)64-bit
1 11 0 ANDS (shifted register)64-bit
1 11 1 BICS (shifted register)64-bit

Add/subtract (shifted register)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS01011shift0Rmimm6RnRd
Decode fields Instruction Details
sf op S shift imm6
11 UNALLOCATED
0 1xxxxx UNALLOCATED
0 0 0 ADD (shifted register)32-bit
0 0 1 ADDS (shifted register)32-bit
0 1 0 SUB (shifted register)32-bit
0 1 1 SUBS (shifted register)32-bit
1 0 0 ADD (shifted register)64-bit
1 0 1 ADDS (shifted register)64-bit
1 1 0 SUB (shifted register)64-bit
1 1 1 SUBS (shifted register)64-bit

Add/subtract (extended register)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS01011opt1Rmoptionimm3RnRd
Decode fields Instruction Details
sf op S opt imm3
1x1 UNALLOCATED
11x UNALLOCATED
x1 UNALLOCATED
1x UNALLOCATED
0 0 0 00 ADD (extended register)32-bit
0 0 1 00 ADDS (extended register)32-bit
0 1 0 00 SUB (extended register)32-bit
0 1 1 00 SUBS (extended register)32-bit
1 0 0 00 ADD (extended register)64-bit
1 0 1 00 ADDS (extended register)64-bit
1 1 0 00 SUB (extended register)64-bit
1 1 1 00 SUBS (extended register)64-bit

Add/subtract (with carry)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010000Rmopcode2RnRd
Decode fields Instruction Details
sf op S opcode2
xxxxx1 UNALLOCATED
xxxx1x UNALLOCATED
xxx1xx UNALLOCATED
xx1xxx UNALLOCATED
x1xxxx UNALLOCATED
1xxxxx UNALLOCATED
0 0 0 000000 ADC32-bit
0 0 1 000000 ADCS32-bit
0 1 0 000000 SBC32-bit
0 1 1 000000 SBCS32-bit
1 0 0 000000 ADC64-bit
1 0 1 000000 ADCS64-bit
1 1 0 000000 SBC64-bit
1 1 1 000000 SBCS64-bit

Conditional compare (register)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010010Rmcond0o2Rno3nzcv
Decode fields Instruction Details
sf op S o2 o3
1 UNALLOCATED
1 UNALLOCATED
0 UNALLOCATED
0 0 1 0 0 CCMN (register)32-bit
0 1 1 0 0 CCMP (register)32-bit
1 0 1 0 0 CCMN (register)64-bit
1 1 1 0 0 CCMP (register)64-bit

Conditional compare (immediate)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010010imm5cond1o2Rno3nzcv
Decode fields Instruction Details
sf op S o2 o3
1 UNALLOCATED
1 UNALLOCATED
0 UNALLOCATED
0 0 1 0 0 CCMN (immediate)32-bit
0 1 1 0 0 CCMP (immediate)32-bit
1 0 1 0 0 CCMN (immediate)64-bit
1 1 1 0 0 CCMP (immediate)64-bit

Conditional select

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010100Rmcondop2RnRd
Decode fields Instruction Details
sf op S op2
1x UNALLOCATED
1 UNALLOCATED
0 0 0 00 CSEL32-bit
0 0 0 01 CSINC32-bit
0 1 0 00 CSINV32-bit
0 1 0 01 CSNEG32-bit
1 0 0 00 CSEL64-bit
1 0 0 01 CSINC64-bit
1 1 0 00 CSINV64-bit
1 1 0 01 CSNEG64-bit

Data-processing (3 source)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfop5411011op31Rmo0RaRnRd
Decode fields Instruction Details
sf op54 op31 o0
00 010 1 UNALLOCATED
00 011 UNALLOCATED
00 100 UNALLOCATED
00 110 1 UNALLOCATED
00 111 UNALLOCATED
01 UNALLOCATED
1x UNALLOCATED
0 00 000 0 MADD32-bit
0 00 000 1 MSUB32-bit
0 00 001 0 UNALLOCATED
0 00 001 1 UNALLOCATED
0 00 010 0 UNALLOCATED
0 00 101 0 UNALLOCATED
0 00 101 1 UNALLOCATED
0 00 110 0 UNALLOCATED
1 00 000 0 MADD64-bit
1 00 000 1 MSUB64-bit
1 00 001 0 SMADDL
1 00 001 1 SMSUBL
1 00 010 0 SMULH
1 00 101 0 UMADDL
1 00 101 1 UMSUBL
1 00 110 0 UMULH

Data Processing -- Scalar Floating-Point and Advanced SIMD

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
op0111op1op2op3op4
Decode fields Instruction details
op0op1op2op3op4
0000 0x x101 00 xxxx10 UNALLOCATED
0010 0x x101 00 xxxx10 UNALLOCATED
0100 0x x101 00 xxxx10 Cryptographic AES
0101 0x x0xx 0xxx00 Cryptographic three-register SHA
0101 0x x0xx 0xxx10 UNALLOCATED
0101 0x x101 00 xxxx10 Cryptographic two-register SHA
0110 0x x101 00 xxxx10 UNALLOCATED
0111 0x x0xx 0xxxx0 UNALLOCATED
0111 0x x101 00 xxxx10 UNALLOCATED
01x1 00 00xx 0xxxx1 Advanced SIMD scalar copy
01x1 01 00xx 0xxxx1 UNALLOCATED
01x1 0x 0111 00 xxxx10 UNALLOCATED
01x1 0x 10xx 00xxx1 Advanced SIMD scalar three same FP16
01x1 0x 10xx 01xxx1 UNALLOCATED
01x1 0x 1111 00 xxxx10 Advanced SIMD scalar two-register miscellaneous FP16
01x1 0x x0xx 1xxxx0 UNALLOCATED
01x1 0x x0xx 1xxxx1 Advanced SIMD scalar three same extra
01x1 0x x100 00 xxxx10 Advanced SIMD scalar two-register miscellaneous
01x1 0x x110 00 xxxx10 Advanced SIMD scalar pairwise
01x1 0x x1xx 1x xxxx10 UNALLOCATED
01x1 0x x1xx x1 xxxx10 UNALLOCATED
01x1 0x x1xx xxxx00 Advanced SIMD scalar three different
01x1 0x x1xx xxxxx1 Advanced SIMD scalar three same
01x1 10 xxxxx1 Advanced SIMD scalar shift by immediate
01x1 11 xxxxx1 UNALLOCATED
01x1 1x xxxxx0 Advanced SIMD scalar x indexed element
0x00 0x x0xx 0xxx00 Advanced SIMD table lookup
0x00 0x x0xx 0xxx10 Advanced SIMD permute
0x10 0x x0xx 0xxxx0 Advanced SIMD extract
0xx0 00 00xx 0xxxx1 Advanced SIMD copy
0xx0 01 00xx 0xxxx1 UNALLOCATED
0xx0 0x 0111 00 xxxx10 UNALLOCATED
0xx0 0x 10xx 00xxx1 Advanced SIMD three same (FP16)
0xx0 0x 10xx 01xxx1 UNALLOCATED
0xx0 0x 1111 00 xxxx10 Advanced SIMD two-register miscellaneous (FP16)
0xx0 0x x0xx 1xxxx0 UNALLOCATED
0xx0 0x x0xx 1xxxx1 Advanced SIMD three same extra
0xx0 0x x100 00 xxxx10 Advanced SIMD two-register miscellaneous
0xx0 0x x110 00 xxxx10 Advanced SIMD across lanes
0xx0 0x x1xx 1x xxxx10 UNALLOCATED
0xx0 0x x1xx x1 xxxx10 UNALLOCATED
0xx0 0x x1xx xxxx00 Advanced SIMD three different
0xx0 0x x1xx xxxxx1 Advanced SIMD three same
0xx0 10 0000 xxxxx1 Advanced SIMD modified immediate
0xx0 10 != 0000 xxxxx1 Advanced SIMD shift by immediate
0xx0 11 xxxxx1 UNALLOCATED
0xx0 1x xxxxx0 Advanced SIMD vector x indexed element
11x1 UNALLOCATED
1xx0 UNALLOCATED
x0x1 0x x0xx Conversion between floating-point and fixed-point
x0x1 0x x1xx 000000 Conversion between floating-point and integer
x0x1 0x x1xx 100000 UNALLOCATED
x0x1 0x x1xx x10000 Floating-point data-processing (1 source)
x0x1 0x x1xx xx1000 Floating-point compare
x0x1 0x x1xx xxx100 Floating-point immediate
x0x1 0x x1xx xxxx01 Floating-point conditional compare
x0x1 0x x1xx xxxx10 Floating-point data-processing (2 source)
x0x1 0x x1xx xxxx11 Floating-point conditional select
x0x1 1x Floating-point data-processing (3 source)

Cryptographic AES

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01001110size10100opcode10RnRd
Decode fields Instruction Details
size opcode
x1xxx UNALLOCATED
000xx UNALLOCATED
1xxxx UNALLOCATED
x1 UNALLOCATED
00 00100 AESE
00 00101 AESD
00 00110 AESMC
00 00111 AESIMC
1x UNALLOCATED

Cryptographic three-register SHA

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01011110size0Rm0opcode00RnRd
Decode fields Instruction Details
size opcode
111 UNALLOCATED
x1 UNALLOCATED
00 000 SHA1C
00 001 SHA1P
00 010 SHA1M
00 011 SHA1SU0
00 100 SHA256H
00 101 SHA256H2
00 110 SHA256SU1
1x UNALLOCATED

Cryptographic two-register SHA

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01011110size10100opcode10RnRd
Decode fields Instruction Details
size opcode
xx1xx UNALLOCATED
x1xxx UNALLOCATED
1xxxx UNALLOCATED
x1 UNALLOCATED
00 00000 SHA1H
00 00001 SHA1SU1
00 00010 SHA256SU0
00 00011 UNALLOCATED
1x UNALLOCATED

Advanced SIMD scalar copy

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01op11110000imm50imm41RnRd
Decode fields Instruction Details
op imm5 imm4
0 xxx1 UNALLOCATED
0 xx1x UNALLOCATED
0 x1xx UNALLOCATED
0 0000 DUP (element)
0 1xxx UNALLOCATED
0 x0000 0000 UNALLOCATED
1 UNALLOCATED

Advanced SIMD scalar three same FP16

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110a10Rm00opcode1RnRd
Decode fields Instruction Details Architecture Version
U a opcode
110 UNALLOCATED-
1 011 UNALLOCATED-
0 0 011 FMULXARMv8.2
0 0 100 FCMEQ (register)ARMv8.2
0 0 101 UNALLOCATED-
0 0 111 FRECPSARMv8.2
0 1 100 UNALLOCATED-
0 1 101 UNALLOCATED-
0 1 111 FRSQRTSARMv8.2
1 0 011 UNALLOCATED-
1 0 100 FCMGE (register)ARMv8.2
1 0 101 FACGEARMv8.2
1 0 111 UNALLOCATED-
1 1 010 FABDARMv8.2
1 1 100 FCMGT (register)ARMv8.2
1 1 101 FACGTARMv8.2
1 1 111 UNALLOCATED-

Advanced SIMD scalar two-register miscellaneous FP16

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110a111100opcode10RnRd
Decode fields Instruction Details Architecture Version
U a opcode
00xxx UNALLOCATED-
010xx UNALLOCATED-
10xxx UNALLOCATED-
1100x UNALLOCATED-
11110 UNALLOCATED-
0 011xx UNALLOCATED-
0 11111 UNALLOCATED-
1 01111 UNALLOCATED-
1 11100 UNALLOCATED-
0 0 11010 FCVTNS (vector)ARMv8.2
0 0 11011 FCVTMS (vector)ARMv8.2
0 0 11100 FCVTAS (vector)ARMv8.2
0 0 11101 SCVTF (vector, integer)ARMv8.2
0 1 01100 FCMGT (zero)ARMv8.2
0 1 01101 FCMEQ (zero)ARMv8.2
0 1 01110 FCMLT (zero)ARMv8.2
0 1 11010 FCVTPS (vector)ARMv8.2
0 1 11011 FCVTZS (vector, integer)ARMv8.2
0 1 11101 FRECPEARMv8.2
0 1 11111 FRECPXARMv8.2
1 0 11010 FCVTNU (vector)ARMv8.2
1 0 11011 FCVTMU (vector)ARMv8.2
1 0 11100 FCVTAU (vector)ARMv8.2
1 0 11101 UCVTF (vector, integer)ARMv8.2
1 1 01100 FCMGE (zero)ARMv8.2
1 1 01101 FCMLE (zero)ARMv8.2
1 1 01110 UNALLOCATED-
1 1 11010 FCVTPU (vector)ARMv8.2
1 1 11011 FCVTZU (vector, integer)ARMv8.2
1 1 11101 FRSQRTEARMv8.2
1 1 11111 UNALLOCATED-

Advanced SIMD scalar three same extra

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110size0Rm1opcode1RnRd
Decode fields Instruction Details Architecture Version
U opcode
001x UNALLOCATED-
01xx UNALLOCATED-
1xxx UNALLOCATED-
0 0000 UNALLOCATED-
0 0001 UNALLOCATED-
1 0000 SQRDMLAH (vector)ARMv8.1
1 0001 SQRDMLSH (vector)ARMv8.1

Advanced SIMD scalar two-register miscellaneous

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110size10000opcode10RnRd
Decode fields Instruction Details
U size opcode
0000x UNALLOCATED
00010 UNALLOCATED
0010x UNALLOCATED
00110 UNALLOCATED
01111 UNALLOCATED
1000x UNALLOCATED
10011 UNALLOCATED
10101 UNALLOCATED
10111 UNALLOCATED
1100x UNALLOCATED
11110 UNALLOCATED
0x 011xx UNALLOCATED
0x 11111 UNALLOCATED
1x 10110 UNALLOCATED
1x 11100 UNALLOCATED
0 00011 SUQADD
0 00111 SQABS
0 01000 CMGT (zero)
0 01001 CMEQ (zero)
0 01010 CMLT (zero)
0 01011 ABS
0 10010 UNALLOCATED
0 10100 SQXTN, SQXTN2
0 0x 10110 UNALLOCATED
0 0x 11010 FCVTNS (vector)
0 0x 11011 FCVTMS (vector)
0 0x 11100 FCVTAS (vector)
0 0x 11101 SCVTF (vector, integer)
0 1x 01100 FCMGT (zero)
0 1x 01101 FCMEQ (zero)
0 1x 01110 FCMLT (zero)
0 1x 11010 FCVTPS (vector)
0 1x 11011 FCVTZS (vector, integer)
0 1x 11101 FRECPE
0 1x 11111 FRECPX
1 00011 USQADD
1 00111 SQNEG
1 01000 CMGE (zero)
1 01001 CMLE (zero)
1 01010 UNALLOCATED
1 01011 NEG (vector)
1 10010 SQXTUN, SQXTUN2
1 10100 UQXTN, UQXTN2
1 0x 10110 FCVTXN, FCVTXN2
1 0x 11010 FCVTNU (vector)
1 0x 11011 FCVTMU (vector)
1 0x 11100 FCVTAU (vector)
1 0x 11101 UCVTF (vector, integer)
1 1x 01100 FCMGE (zero)
1 1x 01101 FCMLE (zero)
1 1x 01110 UNALLOCATED
1 1x 11010 FCVTPU (vector)
1 1x 11011 FCVTZU (vector, integer)
1 1x 11101 FRSQRTE
1 1x 11111 UNALLOCATED

Advanced SIMD scalar pairwise

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110size11000opcode10RnRd
Decode fields Instruction Details Architecture Version
U size opcode
00xxx UNALLOCATED-
010xx UNALLOCATED-
01110 UNALLOCATED-
10xxx UNALLOCATED-
1100x UNALLOCATED-
11010 UNALLOCATED-
111xx UNALLOCATED-
1x 01101 UNALLOCATED-
0 11011 ADDP (scalar)-
0 00 01100 FMAXNMP (scalar)half-precisionARMv8.2
0 00 01101 FADDP (scalar)half-precisionARMv8.2
0 00 01111 FMAXP (scalar)half-precisionARMv8.2
0 01 01100 UNALLOCATED-
0 01 01101 UNALLOCATED-
0 01 01111 UNALLOCATED-
0 10 01100 FMINNMP (scalar)half-precisionARMv8.2
0 10 01111 FMINP (scalar)half-precisionARMv8.2
0 11 01100 UNALLOCATED-
0 11 01111 UNALLOCATED-
1 11011 UNALLOCATED-
1 0x 01100 FMAXNMP (scalar)single-precision and double-precision-
1 0x 01101 FADDP (scalar)single-precision and double-precision-
1 0x 01111 FMAXP (scalar)single-precision and double-precision-
1 1x 01100 FMINNMP (scalar)single-precision and double-precision-
1 1x 01111 FMINP (scalar)single-precision and double-precision-

Advanced SIMD scalar three different

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110size1Rmopcode00RnRd
Decode fields Instruction Details
U opcode
00xx UNALLOCATED
01xx UNALLOCATED
1000 UNALLOCATED
1010 UNALLOCATED
1100 UNALLOCATED
111x UNALLOCATED
0 1001 SQDMLAL, SQDMLAL2 (vector)
0 1011 SQDMLSL, SQDMLSL2 (vector)
0 1101 SQDMULL, SQDMULL2 (vector)
1 1001 UNALLOCATED
1 1011 UNALLOCATED
1 1101 UNALLOCATED

Advanced SIMD scalar three same

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110size1Rmopcode1RnRd
Decode fields Instruction Details
U size opcode
00000 UNALLOCATED
0001x UNALLOCATED
00100 UNALLOCATED
011xx UNALLOCATED
1001x UNALLOCATED
1x 11011 UNALLOCATED
0 00001 SQADD
0 00101 SQSUB
0 00110 CMGT (register)
0 00111 CMGE (register)
0 01000 SSHL
0 01001 SQSHL (register)
0 01010 SRSHL
0 01011 SQRSHL
0 10000 ADD (vector)
0 10001 CMTST
0 10100 UNALLOCATED
0 10101 UNALLOCATED
0 10110 SQDMULH (vector)
0 10111 UNALLOCATED
0 0x 11000 UNALLOCATED
0 0x 11001 UNALLOCATED
0 0x 11010 UNALLOCATED
0 0x 11011 FMULX
0 0x 11100 FCMEQ (register)
0 0x 11101 UNALLOCATED
0 0x 11110 UNALLOCATED
0 0x 11111 FRECPS
0 1x 11000 UNALLOCATED
0 1x 11001 UNALLOCATED
0 1x 11010 UNALLOCATED
0 1x 11100 UNALLOCATED
0 1x 11101 UNALLOCATED
0 1x 11110 UNALLOCATED
0 1x 11111 FRSQRTS
1 00001 UQADD
1 00101 UQSUB
1 00110 CMHI (register)
1 00111 CMHS (register)
1 01000 USHL
1 01001 UQSHL (register)
1 01010 URSHL
1 01011 UQRSHL
1 10000 SUB (vector)
1 10001 CMEQ (register)
1 10100 UNALLOCATED
1 10101 UNALLOCATED
1 10110 SQRDMULH (vector)
1 10111 UNALLOCATED
1 0x 11000 UNALLOCATED
1 0x 11001 UNALLOCATED
1 0x 11010 UNALLOCATED
1 0x 11011 UNALLOCATED
1 0x 11100 FCMGE (register)
1 0x 11101 FACGE
1 0x 11110 UNALLOCATED
1 0x 11111 UNALLOCATED
1 1x 11000 UNALLOCATED
1 1x 11001 UNALLOCATED
1 1x 11010 FABD
1 1x 11100 FCMGT (register)
1 1x 11101 FACGT
1 1x 11110 UNALLOCATED
1 1x 11111 UNALLOCATED

Advanced SIMD scalar shift by immediate

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U111110immhimmbopcode1RnRd
Decode fields Instruction Details
U immh opcode
!= 0000 00001 UNALLOCATED
!= 0000 00011 UNALLOCATED
!= 0000 00101 UNALLOCATED
!= 0000 00111 UNALLOCATED
!= 0000 01001 UNALLOCATED
!= 0000 01011 UNALLOCATED
!= 0000 01101 UNALLOCATED
!= 0000 01111 UNALLOCATED
!= 0000 101xx UNALLOCATED
!= 0000 110xx UNALLOCATED
!= 0000 11101 UNALLOCATED
!= 0000 11110 UNALLOCATED
0000 UNALLOCATED
0 != 0000 00000 SSHR
0 != 0000 00010 SSRA
0 != 0000 00100 SRSHR
0 != 0000 00110 SRSRA
0 != 0000 01000 UNALLOCATED
0 != 0000 01010 SHL
0 != 0000 01100 UNALLOCATED
0 != 0000 01110 SQSHL (immediate)
0 != 0000 10000 UNALLOCATED
0 != 0000 10001 UNALLOCATED
0 != 0000 10010 SQSHRN, SQSHRN2
0 != 0000 10011 SQRSHRN, SQRSHRN2
0 != 0000 11100 SCVTF (vector, fixed-point)
0 != 0000 11111 FCVTZS (vector, fixed-point)
1 != 0000 00000 USHR
1 != 0000 00010 USRA
1 != 0000 00100 URSHR
1 != 0000 00110 URSRA
1 != 0000 01000 SRI
1 != 0000 01010 SLI
1 != 0000 01100 SQSHLU
1 != 0000 01110 UQSHL (immediate)
1 != 0000 10000 SQSHRUN, SQSHRUN2
1 != 0000 10001 SQRSHRUN, SQRSHRUN2
1 != 0000 10010 UQSHRN, UQSHRN2
1 != 0000 10011 UQRSHRN, UQRSHRN2
1 != 0000 11100 UCVTF (vector, fixed-point)
1 != 0000 11111 FCVTZU (vector, fixed-point)

Advanced SIMD scalar x indexed element

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11111sizeLMRmopcodeH0RnRd
Decode fields Instruction Details Architecture Version
U size opcode
0000 UNALLOCATED-
0010 UNALLOCATED-
0100 UNALLOCATED-
0110 UNALLOCATED-
1000 UNALLOCATED-
1010 UNALLOCATED-
1110 UNALLOCATED-
01 0001 UNALLOCATED-
01 0101 UNALLOCATED-
01 1001 UNALLOCATED-
0 0011 SQDMLAL, SQDMLAL2 (by element)-
0 0111 SQDMLSL, SQDMLSL2 (by element)-
0 1011 SQDMULL, SQDMULL2 (by element)-
0 1100 SQDMULH (by element)-
0 1101 SQRDMULH (by element)-
0 1111 UNALLOCATED-
0 00 0001 FMLA (by element)half-precisionARMv8.2
0 00 0101 FMLS (by element)half-precisionARMv8.2
0 00 1001 FMUL (by element)half-precisionARMv8.2
0 1x 0001 FMLA (by element)single-precision and double-precision-
0 1x 0101 FMLS (by element)single-precision and double-precision-
0 1x 1001 FMUL (by element)single-precision and double-precision-
1 0011 UNALLOCATED-
1 0111 UNALLOCATED-
1 1011 UNALLOCATED-
1 1100 UNALLOCATED-
1 1101 SQRDMLAH (by element)ARMv8.1
1 1111 SQRDMLSH (by element)ARMv8.1
1 00 0001 UNALLOCATED-
1 00 0101 UNALLOCATED-
1 00 1001 FMULX (by element)half-precisionARMv8.2
1 1x 0001 UNALLOCATED-
1 1x 0101 UNALLOCATED-
1 1x 1001 FMULX (by element)single-precision and double-precision-

Advanced SIMD table lookup

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0Q001110op20Rm0lenop00RnRd
Decode fields Instruction Details
op2 len op
x1 UNALLOCATED
00 00 0 TBLsingle register table
00 00 1 TBXsingle register table
00 01 0 TBLtwo register table
00 01 1 TBXtwo register table
00 10 0 TBLthree register table
00 10 1 TBXthree register table
00 11 0 TBLfour register table
00 11 1 TBXfour register table
1x UNALLOCATED

Advanced SIMD permute

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0Q001110size0Rm0opcode10RnRd
Decode fields Instruction Details
opcode
000 UNALLOCATED
001 UZP1
010 TRN1
011 ZIP1
100 UNALLOCATED
101 UZP2
110 TRN2
111 ZIP2

Advanced SIMD extract

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0Q101110op20Rm0imm40RnRd
Decode fields Instruction Details
op2
x1 UNALLOCATED
00 EXT
1x UNALLOCATED

Advanced SIMD copy

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0Qop01110000imm50imm41RnRd
Decode fields Instruction Details
Q op imm5 imm4
x0000 UNALLOCATED
0 0000 DUP (element)
0 0001 DUP (general)
0 0010 UNALLOCATED
0 0100 UNALLOCATED
0 0110 UNALLOCATED
0 1xxx UNALLOCATED
0 0 0011 UNALLOCATED
0 0 0101 SMOV
0 0 0111 UMOV
0 1 UNALLOCATED
1 0 0011 INS (general)
1 0 0101 SMOV
1 0 x1000 0111 UMOV
1 1 INS (element)

Advanced SIMD three same (FP16)

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110a10Rm00opcode1RnRd
Decode fields Instruction Details Architecture Version
U a opcode
0 0 000 FMAXNM (vector)ARMv8.2
0 0 001 FMLA (vector)ARMv8.2
0 0 010 FADD (vector)ARMv8.2
0 0 011 FMULXARMv8.2
0 0 100 FCMEQ (register)ARMv8.2
0 0 101 UNALLOCATED-
0 0 110 FMAX (vector)ARMv8.2
0 0 111 FRECPSARMv8.2
0 1 000 FMINNM (vector)ARMv8.2
0 1 001 FMLS (vector)ARMv8.2
0 1 010 FSUB (vector)ARMv8.2
0 1 011 UNALLOCATED-
0 1 100 UNALLOCATED-
0 1 101 UNALLOCATED-
0 1 110 FMIN (vector)ARMv8.2
0 1 111 FRSQRTSARMv8.2
1 0 000 FMAXNMP (vector)ARMv8.2
1 0 001 UNALLOCATED-
1 0 010 FADDP (vector)ARMv8.2
1 0 011 FMUL (vector)ARMv8.2
1 0 100 FCMGE (register)ARMv8.2
1 0 101 FACGEARMv8.2
1 0 110 FMAXP (vector)ARMv8.2
1 0 111 FDIV (vector)ARMv8.2
1 1 000 FMINNMP (vector)ARMv8.2
1 1 001 UNALLOCATED-
1 1 010 FABDARMv8.2
1 1 011 UNALLOCATED-
1 1 100 FCMGT (register)ARMv8.2
1 1 101 FACGTARMv8.2
1 1 110 FMINP (vector)ARMv8.2
1 1 111 UNALLOCATED-

Advanced SIMD two-register miscellaneous (FP16)

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110a111100opcode10RnRd
Decode fields Instruction Details Architecture Version
U a opcode
00xxx UNALLOCATED-
010xx UNALLOCATED-
10xxx UNALLOCATED-
11110 UNALLOCATED-
0 011xx UNALLOCATED-
0 11111 UNALLOCATED-
1 11100 UNALLOCATED-
0 0 11000 FRINTN (vector)ARMv8.2
0 0 11001 FRINTM (vector)ARMv8.2
0 0 11010 FCVTNS (vector)ARMv8.2
0 0 11011 FCVTMS (vector)ARMv8.2
0 0 11100 FCVTAS (vector)ARMv8.2
0 0 11101 SCVTF (vector, integer)ARMv8.2
0 1 01100 FCMGT (zero)ARMv8.2
0 1 01101 FCMEQ (zero)ARMv8.2
0 1 01110 FCMLT (zero)ARMv8.2
0 1 01111 FABS (vector)ARMv8.2
0 1 11000 FRINTP (vector)ARMv8.2
0 1 11001 FRINTZ (vector)ARMv8.2
0 1 11010 FCVTPS (vector)ARMv8.2
0 1 11011 FCVTZS (vector, integer)ARMv8.2
0 1 11101 FRECPEARMv8.2
0 1 11111 UNALLOCATED-
1 0 11000 FRINTA (vector)ARMv8.2
1 0 11001 FRINTX (vector)ARMv8.2
1 0 11010 FCVTNU (vector)ARMv8.2
1 0 11011 FCVTMU (vector)ARMv8.2
1 0 11100 FCVTAU (vector)ARMv8.2
1 0 11101 UCVTF (vector, integer)ARMv8.2
1 1 01100 FCMGE (zero)ARMv8.2
1 1 01101 FCMLE (zero)ARMv8.2
1 1 01110 UNALLOCATED-
1 1 01111 FNEG (vector)ARMv8.2
1 1 11000 UNALLOCATED-
1 1 11001 FRINTI (vector)ARMv8.2
1 1 11010 FCVTPU (vector)ARMv8.2
1 1 11011 FCVTZU (vector, integer)ARMv8.2
1 1 11101 FRSQRTEARMv8.2
1 1 11111 FSQRT (vector)ARMv8.2

Advanced SIMD three same extra

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110size0Rm1opcode1RnRd
Decode fields Instruction Details Architecture Version
U opcode
001x UNALLOCATED-
01xx UNALLOCATED-
0 0000 UNALLOCATED-
0 0001 UNALLOCATED-
0 1xxx UNALLOCATED-
1 0000 SQRDMLAH (vector)ARMv8.1
1 0001 SQRDMLSH (vector)ARMv8.1
1 11x1 UNALLOCATED-

Advanced SIMD two-register miscellaneous

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110size10000opcode10RnRd
Decode fields Instruction Details
U size opcode
1000x UNALLOCATED
10101 UNALLOCATED
11110 UNALLOCATED
0x 011xx UNALLOCATED
0x 11111 UNALLOCATED
1x 10110 UNALLOCATED
1x 10111 UNALLOCATED
0 00000 REV64
0 00001 REV16 (vector)
0 00010 SADDLP
0 00011 SUQADD
0 00100 CLS (vector)
0 00101 CNT
0 00110 SADALP
0 00111 SQABS
0 01000 CMGT (zero)
0 01001 CMEQ (zero)
0 01010 CMLT (zero)
0 01011 ABS
0 10010 XTN, XTN2
0 10011 UNALLOCATED
0 10100 SQXTN, SQXTN2
0 0x 10110 FCVTN, FCVTN2
0 0x 10111 FCVTL, FCVTL2
0 0x 11000 FRINTN (vector)
0 0x 11001 FRINTM (vector)
0 0x 11010 FCVTNS (vector)
0 0x 11011 FCVTMS (vector)
0 0x 11100 FCVTAS (vector)
0 0x 11101 SCVTF (vector, integer)
0 1x 01100 FCMGT (zero)
0 1x 01101 FCMEQ (zero)
0 1x 01110 FCMLT (zero)
0 1x 01111 FABS (vector)
0 1x 11000 FRINTP (vector)
0 1x 11001 FRINTZ (vector)
0 1x 11010 FCVTPS (vector)
0 1x 11011 FCVTZS (vector, integer)
0 1x 11100 URECPE
0 1x 11101 FRECPE
0 1x 11111 UNALLOCATED
1 00000 REV32 (vector)
1 00001 UNALLOCATED
1 00010 UADDLP
1 00011 USQADD
1 00100 CLZ (vector)
1 00110 UADALP
1 00111 SQNEG
1 01000 CMGE (zero)
1 01001 CMLE (zero)
1 01010 UNALLOCATED
1 01011 NEG (vector)
1 10010 SQXTUN, SQXTUN2
1 10011 SHLL, SHLL2
1 10100 UQXTN, UQXTN2
1 0x 10110 FCVTXN, FCVTXN2
1 0x 10111 UNALLOCATED
1 0x 11000 FRINTA (vector)
1 0x 11001 FRINTX (vector)
1 0x 11010 FCVTNU (vector)
1 0x 11011 FCVTMU (vector)
1 0x 11100 FCVTAU (vector)
1 0x 11101 UCVTF (vector, integer)
1 00 00101 NOT
1 01 00101 RBIT (vector)
1 1x 00101 UNALLOCATED
1 1x 01100 FCMGE (zero)
1 1x 01101 FCMLE (zero)
1 1x 01110 UNALLOCATED
1 1x 01111 FNEG (vector)
1 1x 11000 UNALLOCATED
1 1x 11001 FRINTI (vector)
1 1x 11010 FCVTPU (vector)
1 1x 11011 FCVTZU (vector, integer)
1 1x 11100 URSQRTE
1 1x 11101 FRSQRTE
1 1x 11111 FSQRT (vector)

Advanced SIMD across lanes

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110size11000opcode10RnRd
Decode fields Instruction Details Architecture Version
U size opcode
0000x UNALLOCATED-
00010 UNALLOCATED-
001xx UNALLOCATED-
0100x UNALLOCATED-
01011 UNALLOCATED-
01101 UNALLOCATED-
01110 UNALLOCATED-
10xxx UNALLOCATED-
1100x UNALLOCATED-
111xx UNALLOCATED-
0 00011 SADDLV-
0 01010 SMAXV-
0 11010 SMINV-
0 11011 ADDV-
0 00 01100 FMAXNMVhalf-precisionARMv8.2
0 00 01111 FMAXVhalf-precisionARMv8.2
0 01 01100 UNALLOCATED-
0 01 01111 UNALLOCATED-
0 10 01100 FMINNMVhalf-precisionARMv8.2
0 10 01111 FMINVhalf-precisionARMv8.2
0 11 01100 UNALLOCATED-
0 11 01111 UNALLOCATED-
1 00011 UADDLV-
1 01010 UMAXV-
1 11010 UMINV-
1 11011 UNALLOCATED-
1 0x 01100 FMAXNMVsingle-precision and double-precision-
1 0x 01111 FMAXVsingle-precision and double-precision-
1 1x 01100 FMINNMVsingle-precision and double-precision-
1 1x 01111 FMINVsingle-precision and double-precision-

Advanced SIMD three different

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110size1Rmopcode00RnRd
Decode fields Instruction Details
U opcode
1111 UNALLOCATED
0 0000 SADDL, SADDL2
0 0001 SADDW, SADDW2
0 0010 SSUBL, SSUBL2
0 0011 SSUBW, SSUBW2
0 0100 ADDHN, ADDHN2
0 0101 SABAL, SABAL2
0 0110 SUBHN, SUBHN2
0 0111 SABDL, SABDL2
0 1000 SMLAL, SMLAL2 (vector)
0 1001 SQDMLAL, SQDMLAL2 (vector)
0 1010 SMLSL, SMLSL2 (vector)
0 1011 SQDMLSL, SQDMLSL2 (vector)
0 1100 SMULL, SMULL2 (vector)
0 1101 SQDMULL, SQDMULL2 (vector)
0 1110 PMULL, PMULL2
1 0000 UADDL, UADDL2
1 0001 UADDW, UADDW2
1 0010 USUBL, USUBL2
1 0011 USUBW, USUBW2
1 0100 RADDHN, RADDHN2
1 0101 UABAL, UABAL2
1 0110 RSUBHN, RSUBHN2
1 0111 UABDL, UABDL2
1 1000 UMLAL, UMLAL2 (vector)
1 1001 UNALLOCATED
1 1010 UMLSL, UMLSL2 (vector)
1 1011 UNALLOCATED
1 1100 UMULL, UMULL2 (vector)
1 1101 UNALLOCATED
1 1110 UNALLOCATED

Advanced SIMD three same

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110size1Rmopcode1RnRd
Decode fields Instruction Details
U size opcode
0 00000 SHADD
0 00001 SQADD
0 00010 SRHADD
0 00100 SHSUB
0 00101 SQSUB
0 00110 CMGT (register)
0 00111 CMGE (register)
0 01000 SSHL
0 01001 SQSHL (register)
0 01010 SRSHL
0 01011 SQRSHL
0 01100 SMAX
0 01101 SMIN
0 01110 SABD
0 01111 SABA
0 10000 ADD (vector)
0 10001 CMTST
0 10010 MLA (vector)
0 10011 MUL (vector)
0 10100 SMAXP
0 10101 SMINP
0 10110 SQDMULH (vector)
0 10111 ADDP (vector)
0 0x 11000 FMAXNM (vector)
0 0x 11001 FMLA (vector)
0 0x 11010 FADD (vector)
0 0x 11011 FMULX
0 0x 11100 FCMEQ (register)
0 0x 11101 UNALLOCATED
0 0x 11110 FMAX (vector)
0 0x 11111 FRECPS
0 00 00011 AND (vector)
0 01 00011 BIC (vector, register)
0 1x 11000 FMINNM (vector)
0 1x 11001 FMLS (vector)
0 1x 11010 FSUB (vector)
0 1x 11011 UNALLOCATED
0 1x 11100 UNALLOCATED
0 1x 11101 UNALLOCATED
0 1x 11110 FMIN (vector)
0 1x 11111 FRSQRTS
0 10 00011 ORR (vector, register)
0 11 00011 ORN (vector)
1 00000 UHADD
1 00001 UQADD
1 00010 URHADD
1 00100 UHSUB
1 00101 UQSUB
1 00110 CMHI (register)
1 00111 CMHS (register)
1 01000 USHL
1 01001 UQSHL (register)
1 01010 URSHL
1 01011 UQRSHL
1 01100 UMAX
1 01101 UMIN
1 01110 UABD
1 01111 UABA
1 10000 SUB (vector)
1 10001 CMEQ (register)
1 10010 MLS (vector)
1 10011 PMUL
1 10100 UMAXP
1 10101 UMINP
1 10110 SQRDMULH (vector)
1 10111 UNALLOCATED
1 0x 11000 FMAXNMP (vector)
1 0x 11001 UNALLOCATED
1 0x 11010 FADDP (vector)
1 0x 11011 FMUL (vector)
1 0x 11100 FCMGE (register)
1 0x 11101 FACGE
1 0x 11110 FMAXP (vector)
1 0x 11111 FDIV (vector)
1 00 00011 EOR (vector)
1 01 00011 BSL
1 1x 11000 FMINNMP (vector)
1 1x 11001 UNALLOCATED
1 1x 11010 FABD
1 1x 11011 UNALLOCATED
1 1x 11100 FCMGT (register)
1 1x 11101 FACGT
1 1x 11110 FMINP (vector)
1 1x 11111 UNALLOCATED
1 10 00011 BIT
1 11 00011 BIF

Advanced SIMD modified immediate

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0Qop0111100000abccmodeo21defghRd
Decode fields Instruction Details Architecture Version
Q op cmode o2
0 0xxx 1 UNALLOCATED-
0 0xx0 0 MOVI32-bit shifted immediate-
0 0xx1 0 ORR (vector, immediate)32-bit-
0 10xx 1 UNALLOCATED-
0 10x0 0 MOVI16-bit shifted immediate-
0 10x1 0 ORR (vector, immediate)16-bit-
0 110x 0 MOVI32-bit shifting ones-
0 110x 1 UNALLOCATED-
0 1110 0 MOVI8-bit-
0 1110 1 UNALLOCATED-
0 1111 0 FMOV (vector, immediate)single-precision-
0 1111 1 FMOV (vector, immediate)half-precisionARMv8.2
1 1 UNALLOCATED-
1 0xx0 0 MVNI32-bit shifted immediate-
1 0xx1 0 BIC (vector, immediate)32-bit-
1 10x0 0 MVNI16-bit shifted immediate-
1 10x1 0 BIC (vector, immediate)16-bit-
1 110x 0 MVNI32-bit shifting ones-
0 1 1110 0 MOVI64-bit scalar-
0 1 1111 0 UNALLOCATED-
1 1 1110 0 MOVI64-bit vector-
1 1 1111 0 FMOV (vector, immediate)double-precision-

Advanced SIMD shift by immediate

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU011110!= 0000immbopcode1RnRd
immh

The following constraints also apply to this encoding: immh != 0000 && immh != 0000

Decode fields Instruction Details
U opcode
00001 UNALLOCATED
00011 UNALLOCATED
00101 UNALLOCATED
00111 UNALLOCATED
01001 UNALLOCATED
01011 UNALLOCATED
01101 UNALLOCATED
01111 UNALLOCATED
10101 UNALLOCATED
1011x UNALLOCATED
110xx UNALLOCATED
11101 UNALLOCATED
11110 UNALLOCATED
0 00000 SSHR
0 00010 SSRA
0 00100 SRSHR
0 00110 SRSRA
0 01000 UNALLOCATED
0 01010 SHL
0 01100 UNALLOCATED
0 01110 SQSHL (immediate)
0 10000 SHRN, SHRN2
0 10001 RSHRN, RSHRN2
0 10010 SQSHRN, SQSHRN2
0 10011 SQRSHRN, SQRSHRN2
0 10100 SSHLL, SSHLL2
0 11100 SCVTF (vector, fixed-point)
0 11111 FCVTZS (vector, fixed-point)
1 00000 USHR
1 00010 USRA
1 00100 URSHR
1 00110 URSRA
1 01000 SRI
1 01010 SLI
1 01100 SQSHLU
1 01110 UQSHL (immediate)
1 10000 SQSHRUN, SQSHRUN2
1 10001 SQRSHRUN, SQRSHRUN2
1 10010 UQSHRN, UQSHRN2
1 10011 UQRSHRN, UQRSHRN2
1 10100 USHLL, USHLL2
1 11100 UCVTF (vector, fixed-point)
1 11111 FCVTZU (vector, fixed-point)

Advanced SIMD vector x indexed element

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01111sizeLMRmopcodeH0RnRd
Decode fields Instruction Details Architecture Version
U size opcode
1110 UNALLOCATED-
01 1001 UNALLOCATED-
0 0000 UNALLOCATED-
0 0010 SMLAL, SMLAL2 (by element)-
0 0011 SQDMLAL, SQDMLAL2 (by element)-
0 0100 UNALLOCATED-
0 0110 SMLSL, SMLSL2 (by element)-
0 0111 SQDMLSL, SQDMLSL2 (by element)-
0 1000 MUL (by element)-
0 1010 SMULL, SMULL2 (by element)-
0 1011 SQDMULL, SQDMULL2 (by element)-
0 1100 SQDMULH (by element)-
0 1101 SQRDMULH (by element)-
0 1111 UNALLOCATED-
0 00 0001 FMLA (by element)half-precisionARMv8.2
0 00 0101 FMLS (by element)half-precisionARMv8.2
0 00 1001 FMUL (by element)half-precisionARMv8.2
0 01 0001 UNALLOCATED-
0 01 0101 UNALLOCATED-
0 1x 0001 FMLA (by element)single-precision and double-precision-
0 1x 0101 FMLS (by element)single-precision and double-precision-
0 1x 1001 FMUL (by element)single-precision and double-precision-
1 0000 MLA (by element)-
1 0010 UMLAL, UMLAL2 (by element)-
1 0100 MLS (by element)-
1 0110 UMLSL, UMLSL2 (by element)-
1 1000 UNALLOCATED-
1 1010 UMULL, UMULL2 (by element)-
1 1011 UNALLOCATED-
1 1100 UNALLOCATED-
1 1101 SQRDMLAH (by element)ARMv8.1
1 1111 SQRDMLSH (by element)ARMv8.1
1 00 0001 UNALLOCATED-
1 00 0011 UNALLOCATED-
1 00 0101 UNALLOCATED-
1 00 0111 UNALLOCATED-
1 00 1001 FMULX (by element)half-precisionARMv8.2
1 1x 0101 UNALLOCATED-
1 1x 1001 FMULX (by element)single-precision and double-precision-
1 11 0001 UNALLOCATED-
1 11 0011 UNALLOCATED-
1 11 0111 UNALLOCATED-

Conversion between floating-point and fixed-point

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
sf0S11110type0rmodeopcodescaleRnRd
Decode fields Instruction Details Architecture Version
sf S type rmode opcode scale
1xx UNALLOCATED-
x0 00x UNALLOCATED-
x1 01x UNALLOCATED-
0x 00x UNALLOCATED-
1x 01x UNALLOCATED-
10 UNALLOCATED-
1 UNALLOCATED-
0 0xxxxx UNALLOCATED-
0 0 00 00 010 SCVTF (scalar, fixed-point)32-bit to single-precision-
0 0 00 00 011 UCVTF (scalar, fixed-point)32-bit to single-precision-
0 0 00 11 000 FCVTZS (scalar, fixed-point)single-precision to 32-bit-
0 0 00 11 001 FCVTZU (scalar, fixed-point)single-precision to 32-bit-
0 0 01 00 010 SCVTF (scalar, fixed-point)32-bit to double-precision-
0 0 01 00 011 UCVTF (scalar, fixed-point)32-bit to double-precision-
0 0 01 11 000 FCVTZS (scalar, fixed-point)double-precision to 32-bit-
0 0 01 11 001 FCVTZU (scalar, fixed-point)double-precision to 32-bit-
0 0 11 00 010 SCVTF (scalar, fixed-point)32-bit to half-precisionARMv8.2
0 0 11 00 011 UCVTF (scalar, fixed-point)32-bit to half-precisionARMv8.2
0 0 11 11 000 FCVTZS (scalar, fixed-point)half-precision to 32-bitARMv8.2
0 0 11 11 001 FCVTZU (scalar, fixed-point)half-precision to 32-bitARMv8.2
1 0 00 00 010 SCVTF (scalar, fixed-point)64-bit to single-precision-
1 0 00 00 011 UCVTF (scalar, fixed-point)64-bit to single-precision-
1 0 00 11 000 FCVTZS (scalar, fixed-point)single-precision to 64-bit-
1 0 00 11 001 FCVTZU (scalar, fixed-point)single-precision to 64-bit-
1 0 01 00 010 SCVTF (scalar, fixed-point)64-bit to double-precision-
1 0 01 00 011 UCVTF (scalar, fixed-point)64-bit to double-precision-
1 0 01 11 000 FCVTZS (scalar, fixed-point)double-precision to 64-bit-
1 0 01 11 001 FCVTZU (scalar, fixed-point)double-precision to 64-bit-
1 0 11 00 010 SCVTF (scalar, fixed-point)64-bit to half-precisionARMv8.2
1 0 11 00 011 UCVTF (scalar, fixed-point)64-bit to half-precisionARMv8.2
1 0 11 11 000 FCVTZS (scalar, fixed-point)half-precision to 64-bitARMv8.2
1 0 11 11 001 FCVTZU (scalar, fixed-point)half-precision to 64-bitARMv8.2

Conversion between floating-point and integer

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
sf0S11110type1rmodeopcode000000RnRd
Decode fields Instruction Details Architecture Version
sf S type rmode opcode
x1 01x UNALLOCATED-
x1 10x UNALLOCATED-
1x 01x UNALLOCATED-
1x 10x UNALLOCATED-
0 10 0xx UNALLOCATED-
0 10 10x UNALLOCATED-
1 UNALLOCATED-
0 0 00 x1 11x UNALLOCATED-
0 0 00 00 000 FCVTNS (scalar)single-precision to 32-bit-
0 0 00 00 001 FCVTNU (scalar)single-precision to 32-bit-
0 0 00 00 010 SCVTF (scalar, integer)32-bit to single-precision-
0 0 00 00 011 UCVTF (scalar, integer)32-bit to single-precision-
0 0 00 00 100 FCVTAS (scalar)single-precision to 32-bit-
0 0 00 00 101 FCVTAU (scalar)single-precision to 32-bit-
0 0 00 00 110 FMOV (general)single-precision to 32-bit-
0 0 00 00 111 FMOV (general)32-bit to single-precision-
0 0 00 01 000 FCVTPS (scalar)single-precision to 32-bit-
0 0 00 01 001 FCVTPU (scalar)single-precision to 32-bit-
0 0 00 1x 11x UNALLOCATED-
0 0 00 10 000 FCVTMS (scalar)single-precision to 32-bit-
0 0 00 10 001 FCVTMU (scalar)single-precision to 32-bit-
0 0 00 11 000 FCVTZS (scalar, integer)single-precision to 32-bit-
0 0 00 11 001 FCVTZU (scalar, integer)single-precision to 32-bit-
0 0 01 0x 11x UNALLOCATED-
0 0 01 00 000 FCVTNS (scalar)double-precision to 32-bit-
0 0 01 00 001 FCVTNU (scalar)double-precision to 32-bit-
0 0 01 00 010 SCVTF (scalar, integer)32-bit to double-precision-
0 0 01 00 011 UCVTF (scalar, integer)32-bit to double-precision-
0 0 01 00 100 FCVTAS (scalar)double-precision to 32-bit-
0 0 01 00 101 FCVTAU (scalar)double-precision to 32-bit-
0 0 01 01 000 FCVTPS (scalar)double-precision to 32-bit-
0 0 01 01 001 FCVTPU (scalar)double-precision to 32-bit-
0 0 01 10 000 FCVTMS (scalar)double-precision to 32-bit-
0 0 01 10 001 FCVTMU (scalar)double-precision to 32-bit-
0 0 01 10 11x UNALLOCATED-
0 0 01 11 000 FCVTZS (scalar, integer)double-precision to 32-bit-
0 0 01 11 001 FCVTZU (scalar, integer)double-precision to 32-bit-
0 0 01 11 111 UNALLOCATED-
0 0 10 11x UNALLOCATED-
0 0 11 00 000 FCVTNS (scalar)half-precision to 32-bitARMv8.2
0 0 11 00 001 FCVTNU (scalar)half-precision to 32-bitARMv8.2
0 0 11 00 010 SCVTF (scalar, integer)32-bit to half-precisionARMv8.2
0 0 11 00 011 UCVTF (scalar, integer)32-bit to half-precisionARMv8.2
0 0 11 00 100 FCVTAS (scalar)half-precision to 32-bitARMv8.2
0 0 11 00 101 FCVTAU (scalar)half-precision to 32-bitARMv8.2
0 0 11 00 110 FMOV (general)half-precision to 32-bitARMv8.2
0 0 11 00 111 FMOV (general)32-bit to half-precisionARMv8.2
0 0 11 01 000 FCVTPS (scalar)half-precision to 32-bitARMv8.2
0 0 11 01 001 FCVTPU (scalar)half-precision to 32-bitARMv8.2
0 0 11 10 000 FCVTMS (scalar)half-precision to 32-bitARMv8.2
0 0 11 10 001 FCVTMU (scalar)half-precision to 32-bitARMv8.2
0 0 11 11 000 FCVTZS (scalar, integer)half-precision to 32-bitARMv8.2
0 0 11 11 001 FCVTZU (scalar, integer)half-precision to 32-bitARMv8.2
1 0 00 11x UNALLOCATED-
1 0 00 00 000 FCVTNS (scalar)single-precision to 64-bit-
1 0 00 00 001 FCVTNU (scalar)single-precision to 64-bit-
1 0 00 00 010 SCVTF (scalar, integer)64-bit to single-precision-
1 0 00 00 011 UCVTF (scalar, integer)64-bit to single-precision-
1 0 00 00 100 FCVTAS (scalar)single-precision to 64-bit-
1 0 00 00 101 FCVTAU (scalar)single-precision to 64-bit-
1 0 00 01 000 FCVTPS (scalar)single-precision to 64-bit-
1 0 00 01 001 FCVTPU (scalar)single-precision to 64-bit-
1 0 00 10 000 FCVTMS (scalar)single-precision to 64-bit-
1 0 00 10 001 FCVTMU (scalar)single-precision to 64-bit-
1 0 00 11 000 FCVTZS (scalar, integer)single-precision to 64-bit-
1 0 00 11 001 FCVTZU (scalar, integer)single-precision to 64-bit-
1 0 01 x1 11x UNALLOCATED-
1 0 01 00 000 FCVTNS (scalar)double-precision to 64-bit-
1 0 01 00 001 FCVTNU (scalar)double-precision to 64-bit-
1 0 01 00 010 SCVTF (scalar, integer)64-bit to double-precision-
1 0 01 00 011 UCVTF (scalar, integer)64-bit to double-precision-
1 0 01 00 100 FCVTAS (scalar)double-precision to 64-bit-
1 0 01 00 101 FCVTAU (scalar)double-precision to 64-bit-
1 0 01 00 110 FMOV (general)double-precision to 64-bit-
1 0 01 00 111 FMOV (general)64-bit to double-precision-
1 0 01 01 000 FCVTPS (scalar)double-precision to 64-bit-
1 0 01 01 001 FCVTPU (scalar)double-precision to 64-bit-
1 0 01 1x 11x UNALLOCATED-
1 0 01 10 000 FCVTMS (scalar)double-precision to 64-bit-
1 0 01 10 001 FCVTMU (scalar)double-precision to 64-bit-
1 0 01 11 000 FCVTZS (scalar, integer)double-precision to 64-bit-
1 0 01 11 001 FCVTZU (scalar, integer)double-precision to 64-bit-
1 0 10 x0 11x UNALLOCATED-
1 0 10 01 110 FMOV (general)top half of 128-bit to 64-bit-
1 0 10 01 111 FMOV (general)64-bit to top half of 128-bit-
1 0 10 1x 11x UNALLOCATED-
1 0 11 00 000 FCVTNS (scalar)half-precision to 64-bitARMv8.2
1 0 11 00 001 FCVTNU (scalar)half-precision to 64-bitARMv8.2
1 0 11 00 010 SCVTF (scalar, integer)64-bit to half-precisionARMv8.2
1 0 11 00 011 UCVTF (scalar, integer)64-bit to half-precisionARMv8.2
1 0 11 00 100 FCVTAS (scalar)half-precision to 64-bitARMv8.2
1 0 11 00 101 FCVTAU (scalar)half-precision to 64-bitARMv8.2
1 0 11 00 110 FMOV (general)half-precision to 64-bitARMv8.2
1 0 11 00 111 FMOV (general)64-bit to half-precisionARMv8.2
1 0 11 01 000 FCVTPS (scalar)half-precision to 64-bitARMv8.2
1 0 11 01 001 FCVTPU (scalar)half-precision to 64-bitARMv8.2
1 0 11 10 000 FCVTMS (scalar)half-precision to 64-bitARMv8.2
1 0 11 10 001 FCVTMU (scalar)half-precision to 64-bitARMv8.2
1 0 11 11 000 FCVTZS (scalar, integer)half-precision to 64-bitARMv8.2
1 0 11 11 001 FCVTZU (scalar, integer)half-precision to 64-bitARMv8.2

Floating-point data-processing (1 source)

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110type1opcode10000RnRd
Decode fields Instruction Details Architecture Version
M S type opcode
x1xxxx UNALLOCATED-
1xxxxx UNALLOCATED-
1 UNALLOCATED-
0 0 00 000000 FMOV (register)single-precision-
0 0 00 000001 FABS (scalar)single-precision-
0 0 00 000010 FNEG (scalar)single-precision-
0 0 00 000011 FSQRT (scalar)single-precision-
0 0 00 000100 UNALLOCATED-
0 0 00 000101 FCVTsingle-precision to double-precision-
0 0 00 000110 UNALLOCATED-
0 0 00 000111 FCVTsingle-precision to half-precision-
0 0 00 001000 FRINTN (scalar)single-precision-
0 0 00 001001 FRINTP (scalar)single-precision-
0 0 00 001010 FRINTM (scalar)single-precision-
0 0 00 001011 FRINTZ (scalar)single-precision-
0 0 00 001100 FRINTA (scalar)single-precision-
0 0 00 001101 UNALLOCATED-
0 0 00 001110 FRINTX (scalar)single-precision-
0 0 00 001111 FRINTI (scalar)single-precision-
0 0 01 000000 FMOV (register)double-precision-
0 0 01 000001 FABS (scalar)double-precision-
0 0 01 000010 FNEG (scalar)double-precision-
0 0 01 000011 FSQRT (scalar)double-precision-
0 0 01 000100 FCVTdouble-precision to single-precision-
0 0 01 000101 UNALLOCATED-
0 0 01 000110 UNALLOCATED-
0 0 01 000111 FCVTdouble-precision to half-precision-
0 0 01 001000 FRINTN (scalar)double-precision-
0 0 01 001001 FRINTP (scalar)double-precision-
0 0 01 001010 FRINTM (scalar)double-precision-
0 0 01 001011 FRINTZ (scalar)double-precision-
0 0 01 001100 FRINTA (scalar)double-precision-
0 0 01 001101 UNALLOCATED-
0 0 01 001110 FRINTX (scalar)double-precision-
0 0 01 001111 FRINTI (scalar)double-precision-
0 0 10 00xxxx UNALLOCATED-
0 0 11 000000 FMOV (register)half-precisionARMv8.2
0 0 11 000001 FABS (scalar)half-precisionARMv8.2
0 0 11 000010 FNEG (scalar)half-precisionARMv8.2
0 0 11 000011 FSQRT (scalar)half-precisionARMv8.2
0 0 11 000100 FCVThalf-precision to single-precision-
0 0 11 000101 FCVThalf-precision to double-precision-
0 0 11 00011x UNALLOCATED-
0 0 11 001000 FRINTN (scalar)half-precisionARMv8.2
0 0 11 001001 FRINTP (scalar)half-precisionARMv8.2
0 0 11 001010 FRINTM (scalar)half-precisionARMv8.2
0 0 11 001011 FRINTZ (scalar)half-precisionARMv8.2
0 0 11 001100 FRINTA (scalar)half-precisionARMv8.2
0 0 11 001101 UNALLOCATED-
0 0 11 001110 FRINTX (scalar)half-precisionARMv8.2
0 0 11 001111 FRINTI (scalar)half-precisionARMv8.2
1 UNALLOCATED-

Floating-point compare

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110type1Rmop1000Rnopcode2
Decode fields Instruction Details Architecture Version
M S type op opcode2
xxxx1 UNALLOCATED-
xxx1x UNALLOCATED-
xx1xx UNALLOCATED-
x1 UNALLOCATED-
1x UNALLOCATED-
10 UNALLOCATED-
1 UNALLOCATED-
0 0 00 00 00000 FCMP-
0 0 00 00 01000 FCMP-
0 0 00 00 10000 FCMPE-
0 0 00 00 11000 FCMPE-
0 0 01 00 00000 FCMP-
0 0 01 00 01000 FCMP-
0 0 01 00 10000 FCMPE-
0 0 01 00 11000 FCMPE-
0 0 11 00 00000 FCMPARMv8.2
0 0 11 00 01000 FCMPARMv8.2
0 0 11 00 10000 FCMPEARMv8.2
0 0 11 00 11000 FCMPEARMv8.2
1 UNALLOCATED-

Floating-point immediate

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110type1imm8100imm5Rd
Decode fields Instruction Details Architecture Version
M S type imm5
xxxx1 UNALLOCATED-
xxx1x UNALLOCATED-
xx1xx UNALLOCATED-
x1xxx UNALLOCATED-
1xxxx UNALLOCATED-
10 UNALLOCATED-
1 UNALLOCATED-
0 0 00 00000 FMOV (scalar, immediate)single-precision-
0 0 01 00000 FMOV (scalar, immediate)double-precision-
0 0 11 00000 FMOV (scalar, immediate)half-precisionARMv8.2
1 UNALLOCATED-

Floating-point conditional compare

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110type1Rmcond01Rnopnzcv
Decode fields Instruction Details Architecture Version
M S type op
10 UNALLOCATED-
1 UNALLOCATED-
0 0 00 0 FCCMPsingle-precision-
0 0 00 1 FCCMPEsingle-precision-
0 0 01 0 FCCMPdouble-precision-
0 0 01 1 FCCMPEdouble-precision-
0 0 11 0 FCCMPhalf-precisionARMv8.2
0 0 11 1 FCCMPEhalf-precisionARMv8.2
1 UNALLOCATED-

Floating-point data-processing (2 source)

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110type1Rmopcode10RnRd
Decode fields Instruction Details Architecture Version
M S type opcode
1xx1 UNALLOCATED-
1x1x UNALLOCATED-
11xx UNALLOCATED-
10 UNALLOCATED-
1 UNALLOCATED-
0 0 00 0000 FMUL (scalar)single-precision-
0 0 00 0001 FDIV (scalar)single-precision-
0 0 00 0010 FADD (scalar)single-precision-
0 0 00 0011 FSUB (scalar)single-precision-
0 0 00 0100 FMAX (scalar)single-precision-
0 0 00 0101 FMIN (scalar)single-precision-
0 0 00 0110 FMAXNM (scalar)single-precision-
0 0 00 0111 FMINNM (scalar)single-precision-
0 0 00 1000 FNMUL (scalar)single-precision-
0 0 01 0000 FMUL (scalar)double-precision-
0 0 01 0001 FDIV (scalar)double-precision-
0 0 01 0010 FADD (scalar)double-precision-
0 0 01 0011 FSUB (scalar)double-precision-
0 0 01 0100 FMAX (scalar)double-precision-
0 0 01 0101 FMIN (scalar)double-precision-
0 0 01 0110 FMAXNM (scalar)double-precision-
0 0 01 0111 FMINNM (scalar)double-precision-
0 0 01 1000 FNMUL (scalar)double-precision-
0 0 11 0000 FMUL (scalar)half-precisionARMv8.2
0 0 11 0001 FDIV (scalar)half-precisionARMv8.2
0 0 11 0010 FADD (scalar)half-precisionARMv8.2
0 0 11 0011 FSUB (scalar)half-precisionARMv8.2
0 0 11 0100 FMAX (scalar)half-precisionARMv8.2
0 0 11 0101 FMIN (scalar)half-precisionARMv8.2
0 0 11 0110 FMAXNM (scalar)half-precisionARMv8.2
0 0 11 0111 FMINNM (scalar)half-precisionARMv8.2
0 0 11 1000 FNMUL (scalar)half-precisionARMv8.2
1 UNALLOCATED-

Floating-point conditional select

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110type1Rmcond11RnRd
Decode fields Instruction Details Architecture Version
M S type
10 UNALLOCATED-
1 UNALLOCATED-
0 0 00 FCSELsingle-precision-
0 0 01 FCSELdouble-precision-
0 0 11 FCSELhalf-precisionARMv8.2
1 UNALLOCATED-

Floating-point data-processing (3 source)

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11111typeo1Rmo0RaRnRd
Decode fields Instruction Details Architecture Version
M S type o1 o0
10 UNALLOCATED-
1 UNALLOCATED-
0 0 00 0 0 FMADDsingle-precision-
0 0 00 0 1 FMSUBsingle-precision-
0 0 00 1 0 FNMADDsingle-precision-
0 0 00 1 1 FNMSUBsingle-precision-
0 0 01 0 0 FMADDdouble-precision-
0 0 01 0 1 FMSUBdouble-precision-
0 0 01 1 0 FNMADDdouble-precision-
0 0 01 1 1 FNMSUBdouble-precision-
0 0 11 0 0 FMADDhalf-precisionARMv8.2
0 0 11 0 1 FMSUBhalf-precisionARMv8.2
0 0 11 1 0 FNMADDhalf-precisionARMv8.2
0 0 11 1 1 FNMSUBhalf-precisionARMv8.2
1 UNALLOCATED-

Internal version only: isa v25.07, AdvSIMD v23.0, pseudocode v31.3

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