LDTR

Load Register (unprivileged) loads a word or doubleword from memory, and writes it to a register. The address that is used for the load is calculated from a base register and an immediate offset.

The memory is restricted as if execution is at EL0 when:

Otherwise, the access permission is for the Exception level at which the instruction is executed. For information about memory accesses, see Load/Store addressing modes.

313029282726252423222120191817161514131211109876543210
1x111000010imm910RnRt
sizeopc

32-bit (size == 10)

LDTR <Wt>, [<Xn|SP>{, #<simm>}]

64-bit (size == 11)

LDTR <Xt>, [<Xn|SP>{, #<simm>}]

integer scale = UInt(size); bits(64) offset = SignExtend(imm9, 64);

Assembler Symbols

<Wt>

Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xt>

Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<simm>

Is the optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.

Shared Decode

integer n = UInt(Rn); integer t = UInt(Rt); integer regsize; regsize = if size == '11' then 64 else 32; integer datasize = 8 << scale;

Operation

bits(64) address; bits(datasize) data; if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n]; address = address + offset; data = Mem[address, datasize DIV 8, AccType_UNPRIV]; X[t] = ZeroExtend(data, regsize);


Internal version only: isa v25.07, AdvSIMD v23.0, pseudocode v31.3

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