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ESB

Error Synchronization Barrier is a synchronization barrier instruction to barrier between errors. This instruction can be used at all Exception levels and in Debug state. This instruction might update DISR_EL1 and VDISR_EL2.

In Debug state, this instruction behaves as if SError interrupts are masked at all Exception levels. See Error Synchronization Barrier in the ARM(R) Reliability, Availability, and Serviceability (RAS) Specification, ARMv8, for ARMv8-A architecture profile.

System
(ARMv8.2)

313029282726252423222120191817161514131211109876543210
11010101000000110010001000011111
CRmop2

System

ESB

SystemHintOp op; op = ifcase CRm:op2 of when '0000 000' op = SystemHintOp_NOP; when '0000 001' op = SystemHintOp_YIELD; when '0000 010' op = SystemHintOp_WFE; when '0000 011' op = SystemHintOp_WFI; when '0000 100' op = SystemHintOp_SEV; when '0000 101' op = SystemHintOp_SEVL; when '0010 000' op = if HaveRASExt() then SystemHintOp_ESB else SystemHintOp_NOP;() then SystemHintOp_ESB else SystemHintOp_NOP; when '0010 001' op = ifHaveStatisticalProfiling() then SystemHintOp_PSB else SystemHintOp_NOP; otherwise op = SystemHintOp_NOP;

Operation

case op of when SystemHintOp_YIELD Hint_Yield(); when SystemHintOp_WFE if IsEventRegisterSet() then ClearEventRegister(); else if PSTATE.EL == EL0 then // Check for traps described by the OS which may be EL1 or EL2. AArch64.CheckForWFxTrap(EL1, TRUE); if HaveEL(EL2) && !IsSecure() && PSTATE.EL IN {EL0, EL1} && !IsInHost() then // Check for traps described by the Hypervisor. AArch64.CheckForWFxTrap(EL2, TRUE); if HaveEL(EL3) && PSTATE.EL != EL3 then // Check for traps described by the Secure Monitor. AArch64.CheckForWFxTrap(EL3, TRUE); WaitForEvent(); when SystemHintOp_WFI if !InterruptPending() then if PSTATE.EL == EL0 then // Check for traps described by the OS which may be EL1 or EL2. AArch64.CheckForWFxTrap(EL1, FALSE); if HaveEL(EL2) && !IsSecure() && PSTATE.EL IN {EL0, EL1} && !IsInHost() then // Check for traps described by the Hypervisor. AArch64.CheckForWFxTrap(EL2, FALSE); if HaveEL(EL3) && PSTATE.EL != EL3 then // Check for traps described by the Secure Monitor. AArch64.CheckForWFxTrap(EL3, FALSE); WaitForInterrupt(); when SystemHintOp_SEV SendEvent(); when SystemHintOp_SEVL SendEventLocal(); when SystemHintOp_ESB ErrorSynchronizationBarrier(MBReqDomain_FullSystem, MBReqTypes_All); AArch64.ESBOperation(); if HaveEL(EL2) && !IsSecure() && PSTATE.EL IN {EL0, EL1} then AArch64.vESBOperation(); TakeUnmaskedSErrorInterrupts(); when SystemHintOp_PSB ProfilingSynchronizationBarrier(); otherwise // do nothing


Internal version only: isa v25.07, AdvSIMD v23.0, pseudocode v31.3

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ISA_v82A_A64_xml_00bet3.2 (old)htmldiff from-ISA_v82A_A64_xml_00bet3.2(new) ISA_v82A_A64_xml_00bet3.2_OPT