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BIC (vector, register)

Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&FP register and the complement of the second source SIMD&FP register, and writes the result to the destination SIMD&FP register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

313029282726252423222120191817161514131211109876543210
0Q001110011Rm000111RnRd
size

Three registers of the same type

BIC <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); integer datasize = if Q == '1' then 128 else 64;integer esize = 8; integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; boolean invert = (size<0> == '1');LogicalOp op = if size<1> == '1' then LogicalOp_ORR else LogicalOp_AND;

Assembler Symbols

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T> Is an arrangement specifier, encoded in Q:
Q<T>
08B
116B
<Vn>

Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm>

Is the name of the second SIMD&FP source register, encoded in the "Rm" field.

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; operand2 =if invert then operand2 = NOT(operand2); result = operand1 AND operand2;case op of when LogicalOp_AND result = operand1 AND operand2; when LogicalOp_ORR result = operand1 OR operand2; V[d] = result;


Internal version only: isa v25.07, AdvSIMD v23.0, pseudocode v31.3

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ISA_v82A_A64_xml_00bet3.2 (old)htmldiff from-ISA_v82A_A64_xml_00bet3.2(new) ISA_v82A_A64_xml_00bet3.2_OPT