Instruction Synchronization Barrier flushes the pipeline in the PE and is a context synchronization event. For more information, see Instruction Synchronization Barrier (ISB).
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1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | CRm | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | |||
opc |
MemBarrierOp op; MBReqDomain domain; MBReqTypes types; case opc of when '00' op = MemBarrierOp_DSB; when '01' op = MemBarrierOp_DMB; when '10' op = MemBarrierOp_ISB; otherwise UnallocatedEncoding(); case CRm<3:2> of when '00' domain = MBReqDomain_OuterShareable; when '01' domain = MBReqDomain_Nonshareable; when '10' domain = MBReqDomain_InnerShareable; when '11' domain = MBReqDomain_FullSystem; case CRm<1:0> of when '01' types = MBReqTypes_Reads; when '10' types = MBReqTypes_Writes; when '11' types = MBReqTypes_All; otherwise types = MBReqTypes_All; domain = MBReqDomain_FullSystem;
<imm> |
Is an optional 4-bit unsigned immediate, in the range 0 to 15, defaulting to 15 and encoded in the "CRm" field. |
case op of when MemBarrierOp_DSB DataSynchronizationBarrier(domain, types); when MemBarrierOp_DMB DataMemoryBarrier(domain, types); when MemBarrierOp_ISB InstructionSynchronizationBarrier();
Internal version only: isa v25.07, AdvSIMD v23.0, pseudocode v31.3
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