ISA_v82A_A64_xml_00bet3.2 (old)htmldiff from-ISA_v82A_A64_xml_00bet3.2(new) ISA_v82A_A64_xml_00bet3.2_OPT

Permuted index of instructions

12346ABCDEFGHIKLMNOPQRSTUVWXYZ

REV16 (vector): Reverse elements in

REV16: Reverse bytes in

16-bit halfwords.

LD2R: Load single

ST2 (single structure): Store single

2-element structure from one lane of two registers.

2-element structure to one lane of two registers.

ST2 (multiple structures): Store multiple

2-element structures from two registers.

2-element structures to two registers.

LD3R: Load single

ST3 (single structure): Store single

3-element structure from one lane of three registers.

3-element structure to one lane of three registers).

ST3 (multiple structures): Store multiple

3-element structures from three registers.

3-element structures to three registers.

REV32 (vector): Reverse elements in

32-bit words (vector).

REV32: Reverse bytes in

32-bit words.

LD4R: Load single

ST4 (single structure): Store single

4-element structure from one lane of four registers.

4-element structure to one lane of four registers.

ST4 (multiple structures): Store multiple

4-element structures from four registers.

4-element structures to four registers.

REV64: Reverse elements in

FACGT: Floating-point

Absolute Compare Greater than (vector).

FACGE: Floating-point

Absolute Compare Greater than or Equal (vector).

FABD: Floating-point

Absolute Difference (vector).

UABD: Unsigned

Absolute Difference (vector).

SABAL, SABAL2: Signed

Absolute difference and Accumulate Long.

UABAL, UABAL2: Unsigned

Absolute difference and Accumulate Long.

SABA: Signed

Absolute difference and Accumulate.

UABA: Unsigned

Absolute difference and Accumulate.

SABDL, SABDL2: Signed

Absolute Difference Long.

UABDL, UABDL2: Unsigned

Absolute Difference Long.

SABD: Signed

Absolute Difference.

FABS (scalar): Floating-point

Absolute value (scalar).

ABS:

Absolute value (vector).

FABS (vector): Floating-point

Absolute value (vector).

SQABS: Signed saturating

Absolute value.

SRSRA: Signed Rounding Shift Right and

Accumulate (immediate).

SSRA: Signed Shift Right and

Accumulate (immediate).

URSRA: Unsigned Rounding Shift Right and

Accumulate (immediate).

USRA: Unsigned Shift Right and

Accumulate (immediate).

SADALP: Signed Add and

Accumulate Long Pairwise.

UADALP: Unsigned Add and

Accumulate Long Pairwise.

SABAL, SABAL2: Signed Absolute difference and

Accumulate Long.

UABAL, UABAL2: Unsigned Absolute difference and

Accumulate Long.

USQADD: Unsigned saturating

Accumulate of Signed value.

SUQADD: Signed saturating

Accumulate of Unsigned value.

SQRDMLAH (by element): Signed Saturating Rounding Doubling Multiply

Accumulate returning High Half (by element).

SQRDMLAH (vector): Signed Saturating Rounding Doubling Multiply

Accumulate returning High Half (vector).

SABA: Signed Absolute difference and

Accumulate.

UABA: Unsigned Absolute difference and

Accumulate.

FMLA (by element): Floating-point fused Multiply-Add to

accumulator (by element).

FMLS (by element): Floating-point fused Multiply-Subtract from

accumulator (by element).

FMLA (vector): Floating-point fused Multiply-Add to

accumulator (vector).

FMLS (vector): Floating-point fused Multiply-Subtract from

accumulator (vector).

MLA (vector): Multiply-Add to

accumulator (vector).

MLS (vector): Multiply-Subtract from

accumulator (vector).

MLA (by element): Multiply-Add to

accumulator (vector, by element).

MLS (by element): Multiply-Subtract from

accumulator (vector, by element).

LDAXP: Load-

Acquire Exclusive Pair of Registers.

LDAXRB: Load-

Acquire Exclusive Register Byte.

LDAXRH: Load-

Acquire Exclusive Register Halfword.

LDAXR: Load-

Acquire Exclusive Register.

LDARB: Load-

Acquire Register Byte.

LDLARB: Load LO

Acquire Register Byte.

LDARH: Load-

Acquire Register Halfword.

LDLARH: Load LO

Acquire Register Halfword.

LDAR: Load-

Acquire Register.

LDLAR: Load LO

Acquire Register.

ADDV: Add

across Vector.

FMAXNMV: Floating-point Maximum Number

across Vector.

FMAXV: Floating-point Maximum

across Vector.

FMINNMV: Floating-point Minimum Number

across Vector.

FMINV: Floating-point Minimum

across Vector.

SADDLV: Signed Add Long

across Vector.

SMAXV: Signed Maximum

across Vector.

SMINV: Signed Minimum

across Vector.

UADDLV: Unsigned sum Long

across Vector.

UMAXV: Unsigned Maximum

across Vector.

UMINV: Unsigned Minimum

across Vector.

ADC: Add with Carry.

ADCS: Add with Carry, setting flags.

Add (extended register), setting flags.

Add (extended register).

ADD (extended register): Add (extended register).

Add (immediate), setting flags.

Add (immediate).

MOV (to/from SP): Move between register and stack pointer: an alias of

ADD (immediate).

ADD (immediate): Add (immediate).

FADD (scalar): Floating-point

Add (scalar).

FMADD: Floating-point fused Multiply-

Add (scalar).

FNMADD: Floating-point Negated fused Multiply-

Add (scalar).

Add (shifted register), setting flags.

Add (shifted register).

ADD (shifted register): Add (shifted register).

ADD (vector):

Add (vector).

FADD (vector): Floating-point

Add (vector).

ADD (vector): Add (vector).

ADDV:

Add across Vector.

SADALP: Signed

Add and Accumulate Long Pairwise.

UADALP: Unsigned

Add and Accumulate Long Pairwise.

SQDMLAL, SQDMLAL2 (by element): Signed saturating Doubling Multiply-

Add Long (by element).

SADDL, SADDL2: Signed

Add Long (vector).

SMLAL, SMLAL2 (vector): Signed Multiply-

Add Long (vector).

UADDL, UADDL2: Unsigned

Add Long (vector).

UMLAL, UMLAL2 (vector): Unsigned Multiply-

Add Long (vector).

SMLAL, SMLAL2 (by element): Signed Multiply-

Add Long (vector, by element).

UMLAL, UMLAL2 (by element): Unsigned Multiply-

Add Long (vector, by element).

SADDLV: Signed

Add Long across Vector.

SADDLP: Signed

Add Long Pairwise.

UADDLP: Unsigned

Add Long Pairwise.

SMADDL: Signed Multiply-

Add Long.

SQDMLAL, SQDMLAL2 (vector): Signed saturating Doubling Multiply-

Add Long.

UMADDL: Unsigned Multiply-

Add Long.

add on byte in memory, without return.

add on byte in memory.

add on halfword in memory, without return.

add on halfword in memory.

STADD, STADDL: Atomic

add on word or doubleword in memory, without return.

add on word or doubleword in memory.

ADDP (scalar):

Add Pair of elements (scalar).

FADDP (scalar): Floating-point

Add Pair of elements (scalar).

ADDP (vector):

Add Pairwise (vector).

FADDP (vector): Floating-point

Add Pairwise (vector).

ADDHN, ADDHN2:

Add returning High Narrow.

RADDHN, RADDHN2: Rounding

Add returning High Narrow.

FMLA (by element): Floating-point fused Multiply-

Add to accumulator (by element).

FMLA (vector): Floating-point fused Multiply-

Add to accumulator (vector).

MLA (vector): Multiply-

Add to accumulator (vector).

MLA (by element): Multiply-

Add to accumulator (vector, by element).

SADDW, SADDW2: Signed

Add Wide.

UADDW, UADDW2: Unsigned

Add Wide.

Add with Carry, setting flags.

ADC:

Add with Carry.

MADD: Multiply-

Add.

SHADD: Signed Halving

Add.

SQADD: Signed saturating

Add.

SRHADD: Signed Rounding Halving

Add.

UHADD: Unsigned Halving

Add.

UQADD: Unsigned saturating

Add.

URHADD: Unsigned Rounding Halving

Add.

ADDHN, ADDHN2: Add returning High Narrow.

ADDHN,

ADDHN2: Add returning High Narrow.

ADDP (scalar): Add Pair of elements (scalar).

ADDP (vector): Add Pairwise (vector).

ADRP: Form PC-relative

address to 4KB page.

AT:

Address Translate: an alias of SYS.

ADR: Form PC-relative

address.

CMN (extended register): Compare Negative (extended register): an alias of

ADDS (extended register).

ADDS (extended register): Add (extended register), setting flags.

CMN (immediate): Compare Negative (immediate): an alias of

ADDS (immediate).

ADDS (immediate): Add (immediate), setting flags.

CMN (shifted register): Compare Negative (shifted register): an alias of

ADDS (shifted register).

ADDS (shifted register): Add (shifted register), setting flags.

ADDV: Add across Vector.

ADR: Form PC-relative address.

ADRP: Form PC-relative address to 4KB page.

AES inverse mix columns.

AES mix columns.

AES single round decryption.

AES single round encryption.

AESD: AES single round decryption.

AESE: AES single round encryption.

AESIMC: AES inverse mix columns.

AESMC: AES mix columns.

MOV (to/from SP): Move between register and stack pointer: an

alias of ADD (immediate).

CMN (extended register): Compare Negative (extended register): an

alias of ADDS (extended register).

CMN (immediate): Compare Negative (immediate): an

alias of ADDS (immediate).

CMN (shifted register): Compare Negative (shifted register): an

alias of ADDS (shifted register).

TST (immediate): Test bits (immediate): an

alias of ANDS (immediate).

TST (shifted register): Test (shifted register): an

alias of ANDS (shifted register).

ASR (register): Arithmetic Shift Right (register): an

alias of ASRV.

BFC: Bitfield Clear, leaving other bits unchanged: an

alias of BFM.

BFI: Bitfield Insert: an

alias of BFM.

BFXIL: Bitfield extract and insert at low end: an

alias of BFM.

CINC: Conditional Increment: an

alias of CSINC.

CSET: Conditional Set: an

alias of CSINC.

CINV: Conditional Invert: an

alias of CSINV.

CSETM: Conditional Set Mask: an

alias of CSINV.

CNEG: Conditional Negate: an

alias of CSNEG.

MOV (scalar): Move vector element to scalar: an

alias of DUP (element).

ROR (immediate): Rotate right (immediate): an

alias of EXTR.

MOV (element): Move vector element to another vector element: an

alias of INS (element).

MOV (from general): Move general-purpose register to a vector element: an

alias of INS (general).

LSL (register): Logical Shift Left (register): an

alias of LSLV.

LSR (register): Logical Shift Right (register): an

alias of LSRV.

MUL: Multiply: an

alias of MADD.

MOV (inverted wide immediate): Move (inverted wide immediate): an

alias of MOVN.

MOV (wide immediate): Move (wide immediate): an

alias of MOVZ.

MNEG: Multiply-Negate: an

alias of MSUB.

MVN: Bitwise NOT (vector): an

alias of NOT.

MVN: Bitwise NOT: an

alias of ORN (shifted register).

MOV (bitmask immediate): Move (bitmask immediate): an

alias of ORR (immediate).

MOV (register): Move (register): an

alias of ORR (shifted register).

MOV (vector): Move vector: an

alias of ORR (vector, register).

REV64: Reverse Bytes: an

alias of REV.

ROR (register): Rotate Right (register): an

alias of RORV.

NGC: Negate with Carry: an

alias of SBC.

NGCS: Negate with Carry, setting flags: an

alias of SBCS.

ASR (immediate): Arithmetic Shift Right (immediate): an

alias of SBFM.

SBFIZ: Signed Bitfield Insert in Zero: an

alias of SBFM.

SBFX: Signed Bitfield Extract: an

alias of SBFM.

SXTB: Signed Extend Byte: an

alias of SBFM.

SXTH: Sign Extend Halfword: an

alias of SBFM.

SXTW: Sign Extend Word: an

alias of SBFM.

SMULL: Signed Multiply Long: an

alias of SMADDL.

SMNEGL: Signed Multiply-Negate Long: an

alias of SMSUBL.

SXTL, SXTL2: Signed extend Long: an

alias of SSHLL, SSHLL2.

NEG (shifted register): Negate (shifted register): an

alias of SUB (shifted register).

CMP (extended register): Compare (extended register): an

alias of SUBS (extended register).

CMP (immediate): Compare (immediate): an

alias of SUBS (immediate).

CMP (shifted register): Compare (shifted register): an

alias of SUBS (shifted register).

NEGS: Negate, setting flags: an

alias of SUBS (shifted register).

AT: Address Translate: an

alias of SYS.

DC: Data Cache operation: an

alias of SYS.

IC: Instruction Cache operation: an

alias of SYS.

TLBI: TLB Invalidate operation: an

alias of SYS.

LSL (immediate): Logical Shift Left (immediate): an

alias of UBFM.

LSR (immediate): Logical Shift Right (immediate): an

alias of UBFM.

UBFIZ: Unsigned Bitfield Insert in Zero: an

alias of UBFM.

UBFX: Unsigned Bitfield Extract: an

alias of UBFM.

UXTB: Unsigned Extend Byte: an

alias of UBFM.

UXTH: Unsigned Extend Halfword: an

alias of UBFM.

UMULL: Unsigned Multiply Long: an

alias of UMADDL.

MOV (to general): Move vector element to general-purpose register: an

alias of UMOV.

UMNEGL: Unsigned Multiply-Negate Long: an

alias of UMSUBL.

UXTL, UXTL2: Unsigned extend Long: an

alias of USHLL, USHLL2.

LD1R: Load one single-element structure and Replicate to

all lanes (of one register).

LD4R: Load single 4-element structure and Replicate to

all lanes of four registers.

LD3R: Load single 3-element structure and Replicate to

all lanes of three registers.

LD2R: Load single 2-element structure and Replicate to

all lanes of two registers.

MOV (to/from SP): Move between register and stack pointer:

an alias of ADD (immediate).

CMN (extended register): Compare Negative (extended register):

an alias of ADDS (extended register).

CMN (immediate): Compare Negative (immediate):

an alias of ADDS (immediate).

CMN (shifted register): Compare Negative (shifted register):

an alias of ADDS (shifted register).

TST (immediate): Test bits (immediate):

an alias of ANDS (immediate).

TST (shifted register): Test (shifted register):

an alias of ANDS (shifted register).

ASR (register): Arithmetic Shift Right (register):

an alias of ASRV.

BFC: Bitfield Clear, leaving other bits unchanged:

an alias of BFM.

BFI: Bitfield Insert:

an alias of BFM.

BFXIL: Bitfield extract and insert at low end:

an alias of BFM.

CINC: Conditional Increment:

an alias of CSINC.

CSET: Conditional Set:

an alias of CSINC.

CINV: Conditional Invert:

an alias of CSINV.

CSETM: Conditional Set Mask:

an alias of CSINV.

CNEG: Conditional Negate:

an alias of CSNEG.

MOV (scalar): Move vector element to scalar:

an alias of DUP (element).

ROR (immediate): Rotate right (immediate):

an alias of EXTR.

MOV (element): Move vector element to another vector element:

an alias of INS (element).

MOV (from general): Move general-purpose register to a vector element:

an alias of INS (general).

LSL (register): Logical Shift Left (register):

an alias of LSLV.

LSR (register): Logical Shift Right (register):

an alias of LSRV.

MUL: Multiply:

an alias of MADD.

MOV (inverted wide immediate): Move (inverted wide immediate):

an alias of MOVN.

MOV (wide immediate): Move (wide immediate):

an alias of MOVZ.

MNEG: Multiply-Negate:

an alias of MSUB.

MVN: Bitwise NOT (vector):

an alias of NOT.

MVN: Bitwise NOT:

an alias of ORN (shifted register).

MOV (bitmask immediate): Move (bitmask immediate):

an alias of ORR (immediate).

MOV (register): Move (register):

an alias of ORR (shifted register).

MOV (vector): Move vector:

an alias of ORR (vector, register).

REV64: Reverse Bytes:

an alias of REV.

ROR (register): Rotate Right (register):

an alias of RORV.

NGC: Negate with Carry:

an alias of SBC.

NGCS: Negate with Carry, setting flags:

an alias of SBCS.

ASR (immediate): Arithmetic Shift Right (immediate):

an alias of SBFM.

SBFIZ: Signed Bitfield Insert in Zero:

an alias of SBFM.

SBFX: Signed Bitfield Extract:

an alias of SBFM.

SXTB: Signed Extend Byte:

an alias of SBFM.

SXTH: Sign Extend Halfword:

an alias of SBFM.

SXTW: Sign Extend Word:

an alias of SBFM.

SMULL: Signed Multiply Long:

an alias of SMADDL.

SMNEGL: Signed Multiply-Negate Long:

an alias of SMSUBL.

SXTL, SXTL2: Signed extend Long:

an alias of SSHLL, SSHLL2.

NEG (shifted register): Negate (shifted register):

an alias of SUB (shifted register).

CMP (extended register): Compare (extended register):

an alias of SUBS (extended register).

CMP (immediate): Compare (immediate):

an alias of SUBS (immediate).

CMP (shifted register): Compare (shifted register):

an alias of SUBS (shifted register).

NEGS: Negate, setting flags:

an alias of SUBS (shifted register).

AT: Address Translate:

an alias of SYS.

DC: Data Cache operation:

an alias of SYS.

IC: Instruction Cache operation:

an alias of SYS.

TLBI: TLB Invalidate operation:

an alias of SYS.

LSL (immediate): Logical Shift Left (immediate):

an alias of UBFM.

LSR (immediate): Logical Shift Right (immediate):

an alias of UBFM.

UBFIZ: Unsigned Bitfield Insert in Zero:

an alias of UBFM.

UBFX: Unsigned Bitfield Extract:

an alias of UBFM.

UXTB: Unsigned Extend Byte:

an alias of UBFM.

UXTH: Unsigned Extend Halfword:

an alias of UBFM.

UMULL: Unsigned Multiply Long:

an alias of UMADDL.

MOV (to general): Move vector element to general-purpose register:

an alias of UMOV.

UMNEGL: Unsigned Multiply-Negate Long:

an alias of UMSUBL.

UXTL, UXTL2: Unsigned extend Long:

an alias of USHLL, USHLL2.

AND (immediate), setting flags.

AND (immediate): Bitwise

AND (immediate).

AND (immediate): Bitwise AND (immediate).

AND (shifted register), setting flags.

AND (shifted register).

AND (shifted register): Bitwise AND (shifted register).

AND (vector): Bitwise

AND (vector).

AND (vector): Bitwise AND (vector).

TST (immediate): Test bits (immediate): an alias of

ANDS (immediate).

ANDS (immediate): Bitwise AND (immediate), setting flags.

TST (shifted register): Test (shifted register): an alias of

ANDS (shifted register).

ANDS (shifted register): Bitwise AND (shifted register), setting flags.

INS (element): Insert vector element from

another vector element.

MOV (element): Move vector element to

another vector element: an alias of INS (element).

ASR (immediate):

Arithmetic Shift Right (immediate): an alias of SBFM.

ASR (register):

Arithmetic Shift Right (register): an alias of ASRV.

ASRV:

Arithmetic Shift Right Variable.

ASR (immediate): Arithmetic Shift Right (immediate): an alias of SBFM.

ASR (register): Arithmetic Shift Right (register): an alias of ASRV.

ASR (register): Arithmetic Shift Right (register): an alias of

ASRV.

ASRV: Arithmetic Shift Right Variable.

BFXIL: Bitfield extract and insert

at low end: an alias of BFM.

AT: Address Translate: an alias of SYS.

Atomic add on byte in memory, without return.

Atomic add on byte in memory.

Atomic add on halfword in memory, without return.

Atomic add on halfword in memory.

Atomic add on word or doubleword in memory, without return.

Atomic add on word or doubleword in memory.

Atomic bit clear on byte in memory, without return.

Atomic bit clear on byte in memory.

Atomic bit clear on halfword in memory, without return.

Atomic bit clear on halfword in memory.

Atomic bit clear on word or doubleword in memory, without return.

Atomic bit clear on word or doubleword in memory.

Atomic bit set on byte in memory, without return.

Atomic bit set on byte in memory.

Atomic bit set on halfword in memory, without return.

Atomic bit set on halfword in memory.

Atomic bit set on word or doubleword in memory, without return.

Atomic bit set on word or doubleword in memory.

Atomic exclusive OR on byte in memory, without return.

Atomic exclusive OR on byte in memory.

Atomic exclusive OR on halfword in memory, without return.

Atomic exclusive OR on halfword in memory.

Atomic exclusive OR on word or doubleword in memory, without return.

Atomic exclusive OR on word or doubleword in memory.

Atomic signed maximum on byte in memory, without return.

Atomic signed maximum on byte in memory.

Atomic signed maximum on halfword in memory, without return.

Atomic signed maximum on halfword in memory.

Atomic signed maximum on word or doubleword in memory, without return.

Atomic signed maximum on word or doubleword in memory.

Atomic signed minimum on byte in memory, without return.

Atomic signed minimum on byte in memory.

Atomic signed minimum on halfword in memory, without return.

Atomic signed minimum on halfword in memory.

Atomic signed minimum on word or doubleword in memory, without return.

Atomic signed minimum on word or doubleword in memory.

Atomic unsigned maximum on byte in memory, without return.

Atomic unsigned maximum on byte in memory.

Atomic unsigned maximum on halfword in memory, without return.

Atomic unsigned maximum on halfword in memory.

Atomic unsigned maximum on word or doubleword in memory, without return.

Atomic unsigned maximum on word or doubleword in memory.

Atomic unsigned minimum on byte in memory, without return.

Atomic unsigned minimum on byte in memory.

Atomic unsigned minimum on halfword in memory, without return.

Atomic unsigned minimum on halfword in memory.

Atomic unsigned minimum on word or doubleword in memory, without return.

Atomic unsigned minimum on word or doubleword in memory.

FCVTAS (scalar): Floating-point Convert to Signed integer, rounding to nearest with ties to

Away (scalar).

FCVTAU (scalar): Floating-point Convert to Unsigned integer, rounding to nearest with ties to

Away (scalar).

FRINTA (scalar): Floating-point Round to Integral, to nearest with ties to

Away (scalar).

FCVTAS (vector): Floating-point Convert to Signed integer, rounding to nearest with ties to

Away (vector).

FCVTAU (vector): Floating-point Convert to Unsigned integer, rounding to nearest with ties to

Away (vector).

FRINTA (vector): Floating-point Round to Integral, to nearest with ties to

Away (vector).

B: Branch.

DMB: Data Memory

Barrier.

DSB: Data Synchronization

Barrier.

ESB: Error Synchronization

Barrier.

ISB: Instruction Synchronization

Barrier.

PSB CSYNC: Profiling Synchronization

Barrier.

MOV (to/from SP): Move

between register and stack pointer: an alias of ADD (immediate).

BFC: Bitfield Clear, leaving other bits unchanged: an alias of BFM.

BFI: Bitfield Insert: an alias of BFM.

BFC: Bitfield Clear, leaving other bits unchanged: an alias of

BFM.

BFI: Bitfield Insert: an alias of

BFM.

BFXIL: Bitfield extract and insert at low end: an alias of

BFM.

BFM: Bitfield Move.

BFXIL: Bitfield extract and insert at low end: an alias of BFM.

BIC (shifted register): Bitwise Bit Clear (shifted register).

BIC (vector, immediate): Bitwise bit Clear (vector, immediate).

BIC (vector, register): Bitwise bit Clear (vector, register).

BICS (shifted register): Bitwise Bit Clear (shifted register), setting flags.

BIF: Bitwise Insert if False.

TBNZ: Test

bit and Branch if Nonzero.

TBZ: Test

bit and Branch if Zero.

Bit Clear (shifted register), setting flags.

Bit Clear (shifted register).

bit Clear (vector, immediate).

bit Clear (vector, register).

bit clear on byte in memory, without return.

bit clear on byte in memory.

bit clear on halfword in memory, without return.

bit clear on halfword in memory.

STCLR, STCLRL: Atomic

bit clear on word or doubleword in memory, without return.

bit clear on word or doubleword in memory.

RBIT (vector): Reverse

Bit order (vector).

bit set on byte in memory, without return.

bit set on byte in memory.

bit set on halfword in memory, without return.

bit set on halfword in memory.

STSET, STSETL: Atomic

bit set on word or doubleword in memory, without return.

bit set on word or doubleword in memory.

BIT: Bitwise Insert if True.

BFC:

Bitfield Clear, leaving other bits unchanged: an alias of BFM.

BFXIL:

Bitfield extract and insert at low end: an alias of BFM.

SBFX: Signed

Bitfield Extract: an alias of SBFM.

UBFX: Unsigned

Bitfield Extract: an alias of UBFM.

SBFIZ: Signed

Bitfield Insert in Zero: an alias of SBFM.

UBFIZ: Unsigned

Bitfield Insert in Zero: an alias of UBFM.

BFI:

Bitfield Insert: an alias of BFM.

BFM:

Bitfield Move.

SBFM: Signed

Bitfield Move.

UBFM: Unsigned

Bitfield Move.

MOV (bitmask immediate): Move (

bitmask immediate): an alias of ORR (immediate).

MOV (

bitmask immediate): Move (bitmask immediate): an alias of ORR (immediate).

TST (immediate): Test

bits (immediate): an alias of ANDS (immediate).

CLS (vector): Count Leading Sign

bits (vector).

CLZ (vector): Count Leading Zero

bits (vector).

CMTST: Compare bitwise Test

bits nonzero (vector).

BFC: Bitfield Clear, leaving other

bits unchanged: an alias of BFM.

CLS: Count leading sign

bits.

CLZ: Count leading zero

bits.

RBIT: Reverse

Bits.

Bitwise AND (immediate), setting flags.

Bitwise AND (immediate).

Bitwise AND (shifted register), setting flags.

Bitwise AND (shifted register).

Bitwise AND (vector).

Bitwise Bit Clear (shifted register), setting flags.

Bitwise Bit Clear (shifted register).

Bitwise bit Clear (vector, immediate).

Bitwise bit Clear (vector, register).

CMEQ (register): Compare

bitwise Equal (vector).

CMEQ (zero): Compare

bitwise Equal to zero (vector).

Bitwise Exclusive OR (immediate).

Bitwise Exclusive OR (shifted register).

Bitwise Exclusive OR (vector).

Bitwise Exclusive OR NOT (shifted register).

Bitwise inclusive OR (vector, immediate).

Bitwise inclusive OR (vector, register).

Bitwise inclusive OR NOT (vector).

BIF:

Bitwise Insert if False.

BIT:

Bitwise Insert if True.

NOT:

Bitwise NOT (vector).

MVN:

Bitwise NOT (vector): an alias of NOT.

MVN:

Bitwise NOT: an alias of ORN (shifted register).

Bitwise OR (immediate).

Bitwise OR (shifted register).

Bitwise OR NOT (shifted register).

BSL:

Bitwise Select.

CMTST: Compare

bitwise Test bits nonzero (vector).

BL: Branch with Link.

BLR: Branch with Link to Register.

BR: Branch to Register.

B.cond:

Branch conditionally.

TBNZ: Test bit and

Branch if Nonzero.

TBZ: Test bit and

Branch if Zero.

CBNZ: Compare and

Branch on Nonzero.

CBZ: Compare and

Branch on Zero.

BR:

Branch to Register.

BLR:

Branch with Link to Register.

BL:

Branch with Link.

B:

Branch.

BRK:

Breakpoint instruction.

BRK: Breakpoint instruction.

BSL: Bitwise Select.

LDRB (immediate): Load Register

Byte (immediate).

LDRSB (immediate): Load Register Signed

Byte (immediate).

STRB (immediate): Store Register

Byte (immediate).

LDRB (register): Load Register

Byte (register).

LDRSB (register): Load Register Signed

Byte (register).

STRB (register): Store Register

Byte (register).

LDTRB: Load Register

Byte (unprivileged).

LDTRSB: Load Register Signed

Byte (unprivileged).

STTRB: Store Register

Byte (unprivileged).

LDURB: Load Register

Byte (unscaled).

LDURSB: Load Register Signed

Byte (unscaled).

STURB: Store Register

Byte (unscaled).

STADDB, STADDLB: Atomic add on

byte in memory, without return.

STCLRB, STCLRLB: Atomic bit clear on

byte in memory, without return.

STEORB, STEORLB: Atomic exclusive OR on

byte in memory, without return.

STSETB, STSETLB: Atomic bit set on

byte in memory, without return.

STSMAXB, STSMAXLB: Atomic signed maximum on

byte in memory, without return.

STSMINB, STSMINLB: Atomic signed minimum on

byte in memory, without return.

STUMAXB, STUMAXLB: Atomic unsigned maximum on

byte in memory, without return.

STUMINB, STUMINLB: Atomic unsigned minimum on

byte in memory, without return.

CASB, CASAB, CASALB, CASLB: Compare and Swap

byte in memory.

byte in memory.

byte in memory.

LDEORB, LDEORAB, LDEORALB, LDEORLB: Atomic exclusive OR on

byte in memory.

byte in memory.

LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB: Atomic signed maximum on

byte in memory.

LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB: Atomic signed minimum on

byte in memory.

LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB: Atomic unsigned maximum on

byte in memory.

LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB: Atomic unsigned minimum on

byte in memory.

byte in memory.

CNT: Population Count per

byte.

LDARB: Load-Acquire Register

Byte.

LDAXRB: Load-Acquire Exclusive Register

Byte.

LDLARB: Load LOAcquire Register

Byte.

LDXRB: Load Exclusive Register

Byte.

STLLRB: Store LORelease Register

Byte.

STLRB: Store-Release Register

Byte.

STLXRB: Store-Release Exclusive Register

Byte.

STXRB: Store Exclusive Register

Byte.

SXTB: Signed Extend

Byte: an alias of SBFM.

UXTB: Unsigned Extend

Byte: an alias of UBFM.

REV16: Reverse

bytes in 16-bit halfwords.

REV32: Reverse

bytes in 32-bit words.

REV: Reverse

Bytes.

REV64: Reverse

Bytes: an alias of REV.

DC: Data

IC: Instruction

Cache operation: an alias of SYS.

HVC: Hypervisor

Call.

SMC: Secure Monitor

Call.

SVC: Supervisor

Call.

ADCS: Add with

Carry, setting flags.

SBCS: Subtract with

Carry, setting flags.

NGCS: Negate with

Carry, setting flags: an alias of SBCS.

ADC: Add with

Carry.

SBC: Subtract with

Carry.

NGC: Negate with

Carry: an alias of SBC.

CAS, CASA, CASAL, CASL: Compare and Swap word or doubleword in memory.

CAS,

CASA, CASAL, CASL: Compare and Swap word or doubleword in memory.

CASAB, CASALB, CASLB: Compare and Swap byte in memory.

CASAH, CASALH, CASLH: Compare and Swap halfword in memory.

CAS, CASA,

CASAL, CASL: Compare and Swap word or doubleword in memory.

CASALB, CASLB: Compare and Swap byte in memory.

CASALH, CASLH: Compare and Swap halfword in memory.

CASB, CASAB, CASALB, CASLB: Compare and Swap byte in memory.

CASH, CASAH, CASALH, CASLH: Compare and Swap halfword in memory.

CAS, CASA, CASAL,

CASL: Compare and Swap word or doubleword in memory.

CASLB: Compare and Swap byte in memory.

CASLH: Compare and Swap halfword in memory.

CASP, CASPA, CASPAL, CASPL: Compare and Swap Pair of words or doublewords in memory.

CASPA, CASPAL, CASPL: Compare and Swap Pair of words or doublewords in memory.

CASPAL, CASPL: Compare and Swap Pair of words or doublewords in memory.

CASPL: Compare and Swap Pair of words or doublewords in memory.

CBNZ: Compare and Branch on Nonzero.

CBZ: Compare and Branch on Zero.

CCMN (immediate): Conditional Compare Negative (immediate).

CCMN (register): Conditional Compare Negative (register).

CCMP (immediate): Conditional Compare (immediate).

CCMP (register): Conditional Compare (register).

DCPS1: Debug

Change PE State to EL1..

DCPS2: Debug

Change PE State to EL2..

DCPS3: Debug

Change PE State to EL3.

checksum.

checksum.

SHA1C: SHA1 hash update (

choose).

CINC: Conditional Increment: an alias of CSINC.

CINV: Conditional Invert: an alias of CSINV.

Clear (shifted register), setting flags.

Clear (shifted register).

Clear (vector, immediate).

Clear (vector, register).

CLREX:

Clear Exclusive.

STCLRB, STCLRLB: Atomic bit

clear on byte in memory, without return.

clear on byte in memory.

STCLRH, STCLRLH: Atomic bit

clear on halfword in memory, without return.

clear on halfword in memory.

STCLR, STCLRL: Atomic bit

clear on word or doubleword in memory, without return.

clear on word or doubleword in memory.

BFC: Bitfield

Clear, leaving other bits unchanged: an alias of BFM.

CLREX: Clear Exclusive.

CLS (vector): Count Leading Sign bits (vector).

CLS: Count leading sign bits.

CLZ (vector): Count Leading Zero bits (vector).

CLZ: Count leading zero bits.

CMEQ (register): Compare bitwise Equal (vector).

CMEQ (zero): Compare bitwise Equal to zero (vector).

CMGE (register): Compare signed Greater than or Equal (vector).

CMGE (zero): Compare signed Greater than or Equal to zero (vector).

CMGT (register): Compare signed Greater than (vector).

CMGT (zero): Compare signed Greater than zero (vector).

CMHI (register): Compare unsigned Higher (vector).

CMHS (register): Compare unsigned Higher or Same (vector).

CMLE (zero): Compare signed Less than or Equal to zero (vector).

CMLT (zero): Compare signed Less than zero (vector).

CMN (extended register): Compare Negative (extended register): an alias of ADDS (extended register).

CMN (immediate): Compare Negative (immediate): an alias of ADDS (immediate).

CMN (shifted register): Compare Negative (shifted register): an alias of ADDS (shifted register).

CMP (extended register): Compare (extended register): an alias of SUBS (extended register).

CMP (immediate): Compare (immediate): an alias of SUBS (immediate).

CMP (shifted register): Compare (shifted register): an alias of SUBS (shifted register).

CMTST: Compare bitwise Test bits nonzero (vector).

CNEG: Conditional Negate: an alias of CSNEG.

CNT: Population Count per byte.

AESIMC: AES inverse mix

columns.

AESMC: AES mix

columns.

CMP (extended register):

Compare (extended register): an alias of SUBS (extended register).

CCMP (immediate): Conditional

Compare (immediate).

CMP (immediate):

Compare (immediate): an alias of SUBS (immediate).

CCMP (register): Conditional

Compare (register).

FCCMP: Floating-point Conditional quiet

Compare (scalar).

FCCMPE: Floating-point Conditional signaling

Compare (scalar).

FCMP: Floating-point quiet

Compare (scalar).

FCMPE: Floating-point signaling

Compare (scalar).

CMP (shifted register):

Compare (shifted register): an alias of SUBS (shifted register).

Compare and Branch on Nonzero.

CBZ:

Compare and Branch on Zero.

Compare and Swap byte in memory.

Compare and Swap halfword in memory.

Compare and Swap Pair of words or doublewords in memory.

CAS, CASA, CASAL, CASL:

Compare and Swap word or doubleword in memory.

CMEQ (register):

Compare bitwise Equal (vector).

CMEQ (zero):

Compare bitwise Equal to zero (vector).

CMTST:

Compare bitwise Test bits nonzero (vector).

FCMEQ (register): Floating-point

Compare Equal (vector).

FCMEQ (zero): Floating-point

Compare Equal to zero (vector).

FACGT: Floating-point Absolute

Compare Greater than (vector).

FCMGT (register): Floating-point

Compare Greater than (vector).

FACGE: Floating-point Absolute

Compare Greater than or Equal (vector).

FCMGE (register): Floating-point

Compare Greater than or Equal (vector).

FCMGE (zero): Floating-point

Compare Greater than or Equal to zero (vector).

FCMGT (zero): Floating-point

Compare Greater than zero (vector).

FCMLE (zero): Floating-point

Compare Less than or Equal to zero (vector).

FCMLT (zero): Floating-point

Compare Less than zero (vector).

CMN (extended register):

Compare Negative (extended register): an alias of ADDS (extended register).

CCMN (immediate): Conditional

Compare Negative (immediate).

CMN (immediate):

Compare Negative (immediate): an alias of ADDS (immediate).

CCMN (register): Conditional

Compare Negative (register).

CMN (shifted register):

Compare Negative (shifted register): an alias of ADDS (shifted register).

CMGT (register):

Compare signed Greater than (vector).

CMGE (register):

Compare signed Greater than or Equal (vector).

CMGE (zero):

Compare signed Greater than or Equal to zero (vector).

CMGT (zero):

Compare signed Greater than zero (vector).

CMLE (zero):

Compare signed Less than or Equal to zero (vector).

CMLT (zero):

Compare signed Less than zero (vector).

CMHI (register):

Compare unsigned Higher (vector).

CMHS (register):

Compare unsigned Higher or Same (vector).

B.

cond: Branch conditionally.

Conditional Compare (immediate).

Conditional Compare (register).

Conditional Compare Negative (immediate).

Conditional Compare Negative (register).

CINC:

Conditional Increment: an alias of CSINC.

CINV:

Conditional Invert: an alias of CSINV.

CNEG:

Conditional Negate: an alias of CSNEG.

FCCMP: Floating-point

Conditional quiet Compare (scalar).

FCSEL: Floating-point

Conditional Select (scalar).

Conditional Select Increment.

Conditional Select Invert.

Conditional Select Negation.

Conditional Select.

CSETM:

Conditional Set Mask: an alias of CSINV.

CSET:

Conditional Set: an alias of CSINC.

FCCMPE: Floating-point

Conditional signaling Compare (scalar).

B.cond: Branch

conditionally.

FMOV (general): Floating-point Move to or from general-purpose register without

conversion.

FMOV (register): Floating-point Move register without

conversion.

FCVT: Floating-point

Convert precision (scalar).

SCVTF (scalar, fixed-point): Signed fixed-point

Convert to Floating-point (scalar).

SCVTF (scalar, integer): Signed integer

Convert to Floating-point (scalar).

UCVTF (scalar, fixed-point): Unsigned fixed-point

Convert to Floating-point (scalar).

UCVTF (scalar, integer): Unsigned integer

Convert to Floating-point (scalar).

SCVTF (vector, fixed-point): Signed fixed-point

Convert to Floating-point (vector).

SCVTF (vector, integer): Signed integer

Convert to Floating-point (vector).

UCVTF (vector, fixed-point): Unsigned fixed-point

Convert to Floating-point (vector).

UCVTF (vector, integer): Unsigned integer

Convert to Floating-point (vector).

FCVTL, FCVTL2: Floating-point

Convert to higher precision Long (vector).

FCVTN, FCVTN2: Floating-point

Convert to lower precision Narrow (vector).

FCVTXN, FCVTXN2: Floating-point

Convert to lower precision Narrow, rounding to odd (vector).

Convert to Signed fixed-point, rounding toward Zero (scalar).

FCVTZS (vector, fixed-point): Floating-point

Convert to Signed fixed-point, rounding toward Zero (vector).

FCVTAS (scalar): Floating-point

Convert to Signed integer, rounding to nearest with ties to Away (scalar).

FCVTAS (vector): Floating-point

Convert to Signed integer, rounding to nearest with ties to Away (vector).

FCVTNS (scalar): Floating-point

Convert to Signed integer, rounding to nearest with ties to even (scalar).

FCVTNS (vector): Floating-point

Convert to Signed integer, rounding to nearest with ties to even (vector).

FCVTMS (scalar): Floating-point

Convert to Signed integer, rounding toward Minus infinity (scalar).

FCVTMS (vector): Floating-point

Convert to Signed integer, rounding toward Minus infinity (vector).

FCVTPS (scalar): Floating-point

Convert to Signed integer, rounding toward Plus infinity (scalar).

FCVTPS (vector): Floating-point

Convert to Signed integer, rounding toward Plus infinity (vector).

FCVTZS (scalar, integer): Floating-point

Convert to Signed integer, rounding toward Zero (scalar).

FCVTZS (vector, integer): Floating-point

Convert to Signed integer, rounding toward Zero (vector).

Convert to Unsigned fixed-point, rounding toward Zero (scalar).

FCVTZU (vector, fixed-point): Floating-point

Convert to Unsigned fixed-point, rounding toward Zero (vector).

FCVTAU (scalar): Floating-point

Convert to Unsigned integer, rounding to nearest with ties to Away (scalar).

FCVTAU (vector): Floating-point

Convert to Unsigned integer, rounding to nearest with ties to Away (vector).

FCVTNU (scalar): Floating-point

Convert to Unsigned integer, rounding to nearest with ties to even (scalar).

FCVTNU (vector): Floating-point

Convert to Unsigned integer, rounding to nearest with ties to even (vector).

FCVTMU (scalar): Floating-point

Convert to Unsigned integer, rounding toward Minus infinity (scalar).

FCVTMU (vector): Floating-point

Convert to Unsigned integer, rounding toward Minus infinity (vector).

FCVTPU (scalar): Floating-point

Convert to Unsigned integer, rounding toward Plus infinity (scalar).

FCVTPU (vector): Floating-point

Convert to Unsigned integer, rounding toward Plus infinity (vector).

FCVTZU (scalar, integer): Floating-point

Convert to Unsigned integer, rounding toward Zero (scalar).

FCVTZU (vector, integer): Floating-point

Convert to Unsigned integer, rounding toward Zero (vector).

CLS (vector):

Count Leading Sign bits (vector).

CLS:

Count leading sign bits.

CLZ (vector):

Count Leading Zero bits (vector).

CLZ:

Count leading zero bits.

CNT: Population

Count per byte.

CRC32 checksum.

CRC32C checksum.

CRC32CH, CRC32CW, CRC32CX: CRC32C checksum.

CRC32CW, CRC32CX: CRC32C checksum.

CRC32CX: CRC32C checksum.

CRC32H, CRC32W, CRC32X: CRC32 checksum.

CRC32W, CRC32X: CRC32 checksum.

CRC32X: CRC32 checksum.

CSEL: Conditional Select.

CSET: Conditional Set: an alias of CSINC.

CSETM: Conditional Set Mask: an alias of CSINV.

CINC: Conditional Increment: an alias of

CSINC.

CSET: Conditional Set: an alias of

CSINC.

CSINC: Conditional Select Increment.

CINV: Conditional Invert: an alias of

CSINV.

CSETM: Conditional Set Mask: an alias of

CSINV.

CSINV: Conditional Select Invert.

CNEG: Conditional Negate: an alias of

CSNEG.

CSNEG: Conditional Select Negation.

CSYNC: Profiling Synchronization Barrier.

FRINTI (scalar): Floating-point Round to Integral, using

current rounding mode (scalar).

FRINTX (scalar): Floating-point Round to Integral exact, using

current rounding mode (scalar).

FRINTI (vector): Floating-point Round to Integral, using

current rounding mode (vector).

FRINTX (vector): Floating-point Round to Integral exact, using

current rounding mode (vector).

DC:

DMB:

Data Memory Barrier.

DSB:

Data Synchronization Barrier.

DC: Data Cache operation: an alias of SYS.

DCPS1: Debug Change PE State to EL1..

DCPS2: Debug Change PE State to EL2..

DCPS3: Debug Change PE State to EL3.

Debug Change PE State to EL1..

Debug Change PE State to EL2..

Debug Change PE State to EL3.

DRPS:

Debug restore process state.

AESD: AES single round

decryption.

FABD: Floating-point Absolute

Difference (vector).

UABD: Unsigned Absolute

Difference (vector).

SABAL, SABAL2: Signed Absolute

difference and Accumulate Long.

UABAL, UABAL2: Unsigned Absolute

difference and Accumulate Long.

SABA: Signed Absolute

difference and Accumulate.

UABA: Unsigned Absolute

difference and Accumulate.

SABDL, SABDL2: Signed Absolute

Difference Long.

UABDL, UABDL2: Unsigned Absolute

Difference Long.

SABD: Signed Absolute

Difference.

FDIV (scalar): Floating-point

Divide (scalar).

FDIV (vector): Floating-point

Divide (vector).

SDIV: Signed

Divide.

UDIV: Unsigned

Divide.

DMB: Data Memory Barrier.

STADD, STADDL: Atomic add on word or

doubleword in memory, without return.

STCLR, STCLRL: Atomic bit clear on word or

doubleword in memory, without return.

STEOR, STEORL: Atomic exclusive OR on word or

doubleword in memory, without return.

STSET, STSETL: Atomic bit set on word or

doubleword in memory, without return.

STSMAX, STSMAXL: Atomic signed maximum on word or

doubleword in memory, without return.

STSMIN, STSMINL: Atomic signed minimum on word or

doubleword in memory, without return.

STUMAX, STUMAXL: Atomic unsigned maximum on word or

doubleword in memory, without return.

STUMIN, STUMINL: Atomic unsigned minimum on word or

doubleword in memory, without return.

CAS, CASA, CASAL, CASL: Compare and Swap word or

doubleword in memory.

LDADD, LDADDA, LDADDAL, LDADDL: Atomic add on word or

doubleword in memory.

LDCLR, LDCLRA, LDCLRAL, LDCLRL: Atomic bit clear on word or

doubleword in memory.

LDEOR, LDEORA, LDEORAL, LDEORL: Atomic exclusive OR on word or

doubleword in memory.

LDSET, LDSETA, LDSETAL, LDSETL: Atomic bit set on word or

doubleword in memory.

LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL: Atomic signed maximum on word or

doubleword in memory.

LDSMIN, LDSMINA, LDSMINAL, LDSMINL: Atomic signed minimum on word or

doubleword in memory.

LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL: Atomic unsigned maximum on word or

doubleword in memory.

LDUMIN, LDUMINA, LDUMINAL, LDUMINL: Atomic unsigned minimum on word or

doubleword in memory.

SWP, SWPA, SWPAL, SWPL: Swap word or

doubleword in memory.

REV64: Reverse elements in 64-bit

doublewords (vector).

CASP, CASPA, CASPAL, CASPL: Compare and Swap Pair of words or

doublewords in memory.

SQRDMLAH (by element): Signed Saturating Rounding

Doubling Multiply Accumulate returning High Half (by element).

SQRDMLAH (vector): Signed Saturating Rounding

Doubling Multiply Accumulate returning High Half (vector).

SQDMULL, SQDMULL2 (by element): Signed saturating

Doubling Multiply Long (by element).

SQDMULL, SQDMULL2 (vector): Signed saturating

Doubling Multiply Long.

SQDMULH (by element): Signed saturating

Doubling Multiply returning High half (by element).

SQRDMULH (by element): Signed saturating Rounding

Doubling Multiply returning High half (by element).

SQDMULH (vector): Signed saturating

Doubling Multiply returning High half.

SQRDMULH (vector): Signed saturating Rounding

Doubling Multiply returning High half.

SQRDMLSH (by element): Signed Saturating Rounding

Doubling Multiply Subtract returning High Half (by element).

SQRDMLSH (vector): Signed Saturating Rounding

Doubling Multiply Subtract returning High Half (vector).

SQDMLAL, SQDMLAL2 (by element): Signed saturating

Doubling Multiply-Add Long (by element).

SQDMLAL, SQDMLAL2 (vector): Signed saturating

Doubling Multiply-Add Long.

SQDMLSL, SQDMLSL2 (by element): Signed saturating

Doubling Multiply-Subtract Long (by element).

SQDMLSL, SQDMLSL2 (vector): Signed saturating

Doubling Multiply-Subtract Long.

DRPS: Debug restore process state.

DSB: Data Synchronization Barrier.

MOV (scalar): Move vector element to scalar: an alias of

DUP (element).

DUP (element): Duplicate vector element to vector or scalar.

DUP (general): Duplicate general-purpose register to vector.

DUP (general):

Duplicate general-purpose register to vector.

DUP (element):

Duplicate vector element to vector or scalar.

DCPS1: Debug Change PE State to

DCPS2: Debug Change PE State to

EL2..

DCPS3: Debug Change PE State to

EL3.

INS (element): Insert vector

element from another vector element.

INS (general): Insert vector

element from general-purpose register.

SHLL, SHLL2: Shift Left Long (by

element size).

LD1R: Load one single-

element structure and Replicate to all lanes (of one register).

ST1 (single structure): Store a single-

element structure from one lane of one register.

LD1 (single structure): Load one single-

element structure to one lane of one register.

ST1 (multiple structures): Store multiple single-

element structures from one, two, three, or four registers.

LD1 (multiple structures): Load multiple single-

element structures to one, two, three, or four registers.

MOV (element): Move vector

element to another vector element: an alias of INS (element).

SMOV: Signed Move vector

element to general-purpose register.

UMOV: Unsigned Move vector

element to general-purpose register.

MOV (to general): Move vector

element to general-purpose register: an alias of UMOV.

MOV (scalar): Move vector

element to scalar: an alias of DUP (element).

DUP (element): Duplicate vector

element to vector or scalar.

FMLA (by element): Floating-point fused Multiply-Add to accumulator (by

element).

FMLS (by element): Floating-point fused Multiply-Subtract from accumulator (by

element).

FMUL (by element): Floating-point Multiply (by

element).

FMULX (by element): Floating-point Multiply extended (by

element).

MLA (by element): Multiply-Add to accumulator (vector, by

element).

MLS (by element): Multiply-Subtract from accumulator (vector, by

element).

MOV (element): Move vector element to another vector element: an alias of INS (

element).

MOV (scalar): Move vector element to scalar: an alias of DUP (

element).

MUL (by element): Multiply (vector, by

element).

SMLAL, SMLAL2 (by element): Signed Multiply-Add Long (vector, by

element).

SMLSL, SMLSL2 (by element): Signed Multiply-Subtract Long (vector, by

element).

SMULL, SMULL2 (by element): Signed Multiply Long (vector, by

element).

SQDMLAL, SQDMLAL2 (by element): Signed saturating Doubling Multiply-Add Long (by

element).

SQDMLSL, SQDMLSL2 (by element): Signed saturating Doubling Multiply-Subtract Long (by

element).

SQDMULH (by element): Signed saturating Doubling Multiply returning High half (by

element).

SQDMULL, SQDMULL2 (by element): Signed saturating Doubling Multiply Long (by

element).

SQRDMLAH (by element): Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by

element).

SQRDMLSH (by element): Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by

element).

SQRDMULH (by element): Signed saturating Rounding Doubling Multiply returning High half (by

element).

UMLAL, UMLAL2 (by element): Unsigned Multiply-Add Long (vector, by

element).

UMLSL, UMLSL2 (by element): Unsigned Multiply-Subtract Long (vector, by

element).

UMULL, UMULL2 (by element): Unsigned Multiply Long (vector, by

element).

DUP (

element): Duplicate vector element to vector or scalar.

FMLA (by

element): Floating-point fused Multiply-Add to accumulator (by element).

FMLS (by

element): Floating-point fused Multiply-Subtract from accumulator (by element).

FMUL (by

element): Floating-point Multiply (by element).

FMULX (by

element): Floating-point Multiply extended (by element).

INS (

element): Insert vector element from another vector element.

MOV (

element): Move vector element to another vector element: an alias of INS (element).

element): Multiply (vector, by element).

element): Multiply-Add to accumulator (vector, by element).

element): Multiply-Subtract from accumulator (vector, by element).

element): Signed Multiply Long (vector, by element).

element): Signed Multiply-Add Long (vector, by element).

element): Signed Multiply-Subtract Long (vector, by element).

element): Signed saturating Doubling Multiply Long (by element).

SQDMULH (by

element): Signed saturating Doubling Multiply returning High half (by element).

element): Signed saturating Doubling Multiply-Add Long (by element).

element): Signed saturating Doubling Multiply-Subtract Long (by element).

SQRDMLAH (by

element): Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element).

SQRDMULH (by

element): Signed saturating Rounding Doubling Multiply returning High half (by element).

SQRDMLSH (by

element): Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element).

element): Unsigned Multiply Long (vector, by element).

element): Unsigned Multiply-Add Long (vector, by element).

element): Unsigned Multiply-Subtract Long (vector, by element).

INS (element): Insert vector element from another vector

element.

MOV (element): Move vector element to another vector

element: an alias of INS (element).

MOV (from general): Move general-purpose register to a vector

element: an alias of INS (general).

ADDP (scalar): Add Pair of

elements (scalar).

FADDP (scalar): Floating-point Add Pair of

elements (scalar).

FMAXNMP (scalar): Floating-point Maximum Number of Pair of

elements (scalar).

FMAXP (scalar): Floating-point Maximum of Pair of

elements (scalar).

FMINNMP (scalar): Floating-point Minimum Number of Pair of

elements (scalar).

FMINP (scalar): Floating-point Minimum of Pair of

elements (scalar).

REV16 (vector): Reverse

elements in 16-bit halfwords (vector).

REV32 (vector): Reverse

elements in 32-bit words (vector).

REV64: Reverse

elements in 64-bit doublewords (vector).

AESE: AES single round

encryption.

BFXIL: Bitfield extract and insert at low

end: an alias of BFM.

EON (shifted register): Bitwise Exclusive OR NOT (shifted register).

EOR (immediate): Bitwise Exclusive OR (immediate).

EOR (shifted register): Bitwise Exclusive OR (shifted register).

EOR (vector): Bitwise Exclusive OR (vector).

CMEQ (register): Compare bitwise

Equal (vector).

CMGE (register): Compare signed Greater than or

Equal (vector).

FACGE: Floating-point Absolute Compare Greater than or

Equal (vector).

FCMEQ (register): Floating-point Compare

Equal (vector).

FCMGE (register): Floating-point Compare Greater than or

Equal (vector).

CMEQ (zero): Compare bitwise

Equal to zero (vector).

CMGE (zero): Compare signed Greater than or

Equal to zero (vector).

CMLE (zero): Compare signed Less than or

Equal to zero (vector).

FCMEQ (zero): Floating-point Compare

Equal to zero (vector).

FCMGE (zero): Floating-point Compare Greater than or

Equal to zero (vector).

FCMLE (zero): Floating-point Compare Less than or

Equal to zero (vector).

ERET: Exception Return.

ESB:

Error Synchronization Barrier.

ESB: Error Synchronization Barrier.

FRECPE: Floating-point Reciprocal

Estimate.

FRSQRTE: Floating-point Reciprocal Square Root

Estimate.

URECPE: Unsigned Reciprocal

Estimate.

URSQRTE: Unsigned Reciprocal Square Root

Estimate.

FCVTNS (scalar): Floating-point Convert to Signed integer, rounding to nearest with ties to

even (scalar).

FCVTNU (scalar): Floating-point Convert to Unsigned integer, rounding to nearest with ties to

even (scalar).

FRINTN (scalar): Floating-point Round to Integral, to nearest with ties to

even (scalar).

FCVTNS (vector): Floating-point Convert to Signed integer, rounding to nearest with ties to

even (vector).

FCVTNU (vector): Floating-point Convert to Unsigned integer, rounding to nearest with ties to

even (vector).

FRINTN (vector): Floating-point Round to Integral, to nearest with ties to

even (vector).

SEVL: Send

Event Local.

SEV: Send

Event.

WFE: Wait For

Event.

FRINTX (scalar): Floating-point Round to Integral

exact, using current rounding mode (scalar).

FRINTX (vector): Floating-point Round to Integral

exact, using current rounding mode (vector).

ERET:

Exception Return.

EOR (immediate): Bitwise

Exclusive OR (immediate).

Exclusive OR (shifted register).

EOR (vector): Bitwise

Exclusive OR (vector).

Exclusive OR NOT (shifted register).

exclusive OR on byte in memory, without return.

exclusive OR on byte in memory.

exclusive OR on halfword in memory, without return.

exclusive OR on halfword in memory.

STEOR, STEORL: Atomic

exclusive OR on word or doubleword in memory, without return.

exclusive OR on word or doubleword in memory.

LDAXP: Load-Acquire

Exclusive Pair of Registers.

LDXP: Load

Exclusive Pair of Registers.

STLXP: Store-Release

Exclusive Pair of registers.

STXP: Store

Exclusive Pair of registers.

LDAXRB: Load-Acquire

Exclusive Register Byte.

LDXRB: Load

Exclusive Register Byte.

STLXRB: Store-Release

Exclusive Register Byte.

STXRB: Store

Exclusive Register Byte.

LDAXRH: Load-Acquire

Exclusive Register Halfword.

LDXRH: Load

Exclusive Register Halfword.

STLXRH: Store-Release

Exclusive Register Halfword.

STXRH: Store

Exclusive Register Halfword.

LDAXR: Load-Acquire

Exclusive Register.

LDXR: Load

Exclusive Register.

STLXR: Store-Release

Exclusive Register.

STXR: Store

Exclusive Register.

CLREX: Clear

Exclusive.

FRECPX: Floating-point Reciprocal

exponent (scalar).

EXT: Extract vector from pair of vectors.

SXTB: Signed

Extend Byte: an alias of SBFM.

UXTB: Unsigned

Extend Byte: an alias of UBFM.

SXTH: Sign

Extend Halfword: an alias of SBFM.

UXTH: Unsigned

Extend Halfword: an alias of UBFM.

SXTL, SXTL2: Signed

extend Long: an alias of SSHLL, SSHLL2.

UXTL, UXTL2: Unsigned

extend Long: an alias of USHLL, USHLL2.

SXTW: Sign

Extend Word: an alias of SBFM.

FMULX (by element): Floating-point Multiply

extended (by element).

extended register), setting flags.

extended register), setting flags.

extended register).

CMN (extended register): Compare Negative (extended register): an alias of ADDS (

extended register).

CMP (extended register): Compare (extended register): an alias of SUBS (

extended register).

extended register).

extended register): Add (extended register), setting flags.

extended register): Add (extended register).

CMN (extended register): Compare Negative (

extended register): an alias of ADDS (extended register).

CMP (extended register): Compare (

extended register): an alias of SUBS (extended register).

CMP (

extended register): Compare (extended register): an alias of SUBS (extended register).

CMN (

extended register): Compare Negative (extended register): an alias of ADDS (extended register).

extended register): Subtract (extended register), setting flags.

extended register): Subtract (extended register).

FMULX: Floating-point Multiply

extended.

TBX: Table vector lookup

extension.

ROR (immediate): Rotate right (immediate): an alias of

EXTR.

EXTR: Extract register.

BFXIL: Bitfield

extract and insert at low end: an alias of BFM.

SQXTN, SQXTN2: Signed saturating

extract Narrow.

UQXTN, UQXTN2: Unsigned saturating

extract Narrow.

XTN, XTN2:

Extract Narrow.

EXTR:

Extract register.

SQXTUN, SQXTUN2: Signed saturating

extract Unsigned Narrow.

EXT:

Extract vector from pair of vectors.

SBFX: Signed Bitfield

Extract: an alias of SBFM.

UBFX: Unsigned Bitfield

Extract: an alias of UBFM.

FABS (scalar): Floating-point Absolute value (scalar).

FABS (vector): Floating-point Absolute value (vector).

FACGE: Floating-point Absolute Compare Greater than or Equal (vector).

FACGT: Floating-point Absolute Compare Greater than (vector).

FADD (scalar): Floating-point Add (scalar).

FADD (vector): Floating-point Add (vector).

FADDP (scalar): Floating-point Add Pair of elements (scalar).

FADDP (vector): Floating-point Add Pairwise (vector).

BIF: Bitwise Insert if

False.

FCCMP: Floating-point Conditional quiet Compare (scalar).

FCCMPE: Floating-point Conditional signaling Compare (scalar).

FCMEQ (register): Floating-point Compare Equal (vector).

FCMEQ (zero): Floating-point Compare Equal to zero (vector).

FCMGE (register): Floating-point Compare Greater than or Equal (vector).

FCMGE (zero): Floating-point Compare Greater than or Equal to zero (vector).

FCMGT (register): Floating-point Compare Greater than (vector).

FCMGT (zero): Floating-point Compare Greater than zero (vector).

FCMLE (zero): Floating-point Compare Less than or Equal to zero (vector).

FCMLT (zero): Floating-point Compare Less than zero (vector).

FCMP: Floating-point quiet Compare (scalar).

FCMPE: Floating-point signaling Compare (scalar).

FCSEL: Floating-point Conditional Select (scalar).

FCVT: Floating-point Convert precision (scalar).

FCVTAS (scalar): Floating-point Convert to Signed integer, rounding to nearest with ties to Away (scalar).

FCVTAS (vector): Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector).

FCVTAU (scalar): Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (scalar).

FCVTAU (vector): Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector).

FCVTL, FCVTL2: Floating-point Convert to higher precision Long (vector).

FCVTL,

FCVTL2: Floating-point Convert to higher precision Long (vector).

FCVTMS (scalar): Floating-point Convert to Signed integer, rounding toward Minus infinity (scalar).

FCVTMS (vector): Floating-point Convert to Signed integer, rounding toward Minus infinity (vector).

FCVTMU (scalar): Floating-point Convert to Unsigned integer, rounding toward Minus infinity (scalar).

FCVTMU (vector): Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector).

FCVTN, FCVTN2: Floating-point Convert to lower precision Narrow (vector).

FCVTN,

FCVTN2: Floating-point Convert to lower precision Narrow (vector).

FCVTNS (scalar): Floating-point Convert to Signed integer, rounding to nearest with ties to even (scalar).

FCVTNS (vector): Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector).

FCVTNU (scalar): Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (scalar).

FCVTNU (vector): Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector).

FCVTPS (scalar): Floating-point Convert to Signed integer, rounding toward Plus infinity (scalar).

FCVTPS (vector): Floating-point Convert to Signed integer, rounding toward Plus infinity (vector).

FCVTPU (scalar): Floating-point Convert to Unsigned integer, rounding toward Plus infinity (scalar).

FCVTPU (vector): Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector).

FCVTXN, FCVTXN2: Floating-point Convert to lower precision Narrow, rounding to odd (vector).

FCVTXN,

FCVTXN2: Floating-point Convert to lower precision Narrow, rounding to odd (vector).

FCVTZS (scalar, fixed-point): Floating-point Convert to Signed fixed-point, rounding toward Zero (scalar).

FCVTZS (scalar, integer): Floating-point Convert to Signed integer, rounding toward Zero (scalar).

FCVTZS (vector, fixed-point): Floating-point Convert to Signed fixed-point, rounding toward Zero (vector).

FCVTZS (vector, integer): Floating-point Convert to Signed integer, rounding toward Zero (vector).

FCVTZU (scalar, fixed-point): Floating-point Convert to Unsigned fixed-point, rounding toward Zero (scalar).

FCVTZU (scalar, integer): Floating-point Convert to Unsigned integer, rounding toward Zero (scalar).

FCVTZU (vector, fixed-point): Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector).

FCVTZU (vector, integer): Floating-point Convert to Unsigned integer, rounding toward Zero (vector).

FDIV (scalar): Floating-point Divide (scalar).

FDIV (vector): Floating-point Divide (vector).

SHA1H: SHA1

fixed rotate.

fixed-point Convert to Floating-point (scalar).

fixed-point Convert to Floating-point (scalar).

SCVTF (vector, fixed-point): Signed

fixed-point Convert to Floating-point (vector).

UCVTF (vector, fixed-point): Unsigned

fixed-point Convert to Floating-point (vector).

fixed-point): Floating-point Convert to Signed fixed-point, rounding toward Zero (scalar).

FCVTZS (vector,

fixed-point): Floating-point Convert to Signed fixed-point, rounding toward Zero (vector).

fixed-point): Floating-point Convert to Unsigned fixed-point, rounding toward Zero (scalar).

FCVTZU (vector,

fixed-point): Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector).

fixed-point): Signed fixed-point Convert to Floating-point (scalar).

SCVTF (vector,

fixed-point): Signed fixed-point Convert to Floating-point (vector).

fixed-point): Unsigned fixed-point Convert to Floating-point (scalar).

UCVTF (vector,

fixed-point): Unsigned fixed-point Convert to Floating-point (vector).

FCVTZS (scalar, fixed-point): Floating-point Convert to Signed

fixed-point, rounding toward Zero (scalar).

FCVTZU (scalar, fixed-point): Floating-point Convert to Unsigned

fixed-point, rounding toward Zero (scalar).

FCVTZS (vector, fixed-point): Floating-point Convert to Signed

fixed-point, rounding toward Zero (vector).

FCVTZU (vector, fixed-point): Floating-point Convert to Unsigned

fixed-point, rounding toward Zero (vector).

ADCS: Add with Carry, setting

flags.

ADDS (extended register): Add (extended register), setting

flags.

ADDS (immediate): Add (immediate), setting

flags.

ADDS (shifted register): Add (shifted register), setting

flags.

ANDS (immediate): Bitwise AND (immediate), setting

flags.

ANDS (shifted register): Bitwise AND (shifted register), setting

flags.

BICS (shifted register): Bitwise Bit Clear (shifted register), setting

flags.

SBCS: Subtract with Carry, setting

flags.

SUBS (extended register): Subtract (extended register), setting

flags.

SUBS (immediate): Subtract (immediate), setting

flags.

SUBS (shifted register): Subtract (shifted register), setting

flags.

NGCS: Negate with Carry, setting

flags: an alias of SBCS.

NEGS: Negate, setting

flags: an alias of SUBS (shifted register).

SCVTF (scalar, fixed-point): Signed fixed-point Convert to

Floating-point (scalar).

SCVTF (scalar, integer): Signed integer Convert to

Floating-point (scalar).

UCVTF (scalar, fixed-point): Unsigned fixed-point Convert to

Floating-point (scalar).

UCVTF (scalar, integer): Unsigned integer Convert to

Floating-point (scalar).

SCVTF (vector, fixed-point): Signed fixed-point Convert to

Floating-point (vector).

SCVTF (vector, integer): Signed integer Convert to

Floating-point (vector).

UCVTF (vector, fixed-point): Unsigned fixed-point Convert to

Floating-point (vector).

UCVTF (vector, integer): Unsigned integer Convert to

Floating-point (vector).

FACGT:

Floating-point Absolute Compare Greater than (vector).

FACGE:

Floating-point Absolute Compare Greater than or Equal (vector).

FABD:

Floating-point Absolute Difference (vector).

Floating-point Absolute value (scalar).

FABS (vector):

Floating-point Absolute value (vector).

Floating-point Add (scalar).

FADD (vector):

Floating-point Add (vector).

Floating-point Add Pair of elements (scalar).

FADDP (vector):

Floating-point Add Pairwise (vector).

FCMEQ (register):

Floating-point Compare Equal (vector).

FCMEQ (zero):

Floating-point Compare Equal to zero (vector).

FCMGT (register):

Floating-point Compare Greater than (vector).

FCMGE (register):

Floating-point Compare Greater than or Equal (vector).

FCMGE (zero):

Floating-point Compare Greater than or Equal to zero (vector).

FCMGT (zero):

Floating-point Compare Greater than zero (vector).

FCMLE (zero):

Floating-point Compare Less than or Equal to zero (vector).

FCMLT (zero):

Floating-point Compare Less than zero (vector).

Floating-point Conditional quiet Compare (scalar).

FCSEL:

Floating-point Conditional Select (scalar).

Floating-point Conditional signaling Compare (scalar).

FCVT:

Floating-point Convert precision (scalar).

FCVTL, FCVTL2:

Floating-point Convert to higher precision Long (vector).

FCVTN, FCVTN2:

Floating-point Convert to lower precision Narrow (vector).

FCVTXN, FCVTXN2:

Floating-point Convert to lower precision Narrow, rounding to odd (vector).

Floating-point Convert to Signed fixed-point, rounding toward Zero (scalar).

FCVTZS (vector, fixed-point):

Floating-point Convert to Signed fixed-point, rounding toward Zero (vector).

Floating-point Convert to Signed integer, rounding to nearest with ties to Away (scalar).

FCVTAS (vector):

Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector).

Floating-point Convert to Signed integer, rounding to nearest with ties to even (scalar).

FCVTNS (vector):

Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector).

Floating-point Convert to Signed integer, rounding toward Minus infinity (scalar).

FCVTMS (vector):

Floating-point Convert to Signed integer, rounding toward Minus infinity (vector).

Floating-point Convert to Signed integer, rounding toward Plus infinity (scalar).

FCVTPS (vector):

Floating-point Convert to Signed integer, rounding toward Plus infinity (vector).

Floating-point Convert to Signed integer, rounding toward Zero (scalar).

FCVTZS (vector, integer):

Floating-point Convert to Signed integer, rounding toward Zero (vector).

Floating-point Convert to Unsigned fixed-point, rounding toward Zero (scalar).

FCVTZU (vector, fixed-point):

Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector).

Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (scalar).

FCVTAU (vector):

Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector).

Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (scalar).

FCVTNU (vector):

Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector).

Floating-point Convert to Unsigned integer, rounding toward Minus infinity (scalar).

FCVTMU (vector):

Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector).

Floating-point Convert to Unsigned integer, rounding toward Plus infinity (scalar).

FCVTPU (vector):

Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector).

Floating-point Convert to Unsigned integer, rounding toward Zero (scalar).

FCVTZU (vector, integer):

Floating-point Convert to Unsigned integer, rounding toward Zero (vector).

FDIV (scalar):

Floating-point Divide (scalar).

FDIV (vector):

Floating-point Divide (vector).

Floating-point fused Multiply-Add (scalar).

FMLA (by element):

Floating-point fused Multiply-Add to accumulator (by element).

FMLA (vector):

Floating-point fused Multiply-Add to accumulator (vector).

Floating-point Fused Multiply-Subtract (scalar).

FMLS (by element):

Floating-point fused Multiply-Subtract from accumulator (by element).

FMLS (vector):

Floating-point fused Multiply-Subtract from accumulator (vector).

Floating-point Maximum (scalar).

FMAX (vector):

Floating-point Maximum (vector).

Floating-point Maximum across Vector.

Floating-point Maximum Number (scalar).

FMAXNM (vector):

Floating-point Maximum Number (vector).

Floating-point Maximum Number across Vector.

Floating-point Maximum Number of Pair of elements (scalar).

FMAXNMP (vector):

Floating-point Maximum Number Pairwise (vector).

Floating-point Maximum of Pair of elements (scalar).

FMAXP (vector):

Floating-point Maximum Pairwise (vector).

Floating-point Minimum (scalar).

FMIN (vector):

Floating-point minimum (vector).

Floating-point Minimum across Vector.

Floating-point Minimum Number (scalar).

FMINNM (vector):

Floating-point Minimum Number (vector).

Floating-point Minimum Number across Vector.

Floating-point Minimum Number of Pair of elements (scalar).

FMINNMP (vector):

Floating-point Minimum Number Pairwise (vector).

Floating-point Minimum of Pair of elements (scalar).

FMINP (vector):

Floating-point Minimum Pairwise (vector).

FMOV (scalar, immediate):

Floating-point move immediate (scalar).

Floating-point move immediate (vector).

Floating-point Move register without conversion.

Floating-point Move to or from general-purpose register without conversion.

FMUL (by element):

Floating-point Multiply (by element).

Floating-point Multiply (scalar).

FMUL (vector):

Floating-point Multiply (vector).

FMULX (by element):

Floating-point Multiply extended (by element).

FMULX:

Floating-point Multiply extended.

Floating-point Multiply-Negate (scalar).

Floating-point Negate (scalar).

FNEG (vector):

Floating-point Negate (vector).

Floating-point Negated fused Multiply-Add (scalar).

Floating-point Negated fused Multiply-Subtract (scalar).

FCMP:

Floating-point quiet Compare (scalar).

FRECPE:

Floating-point Reciprocal Estimate.

FRECPX:

Floating-point Reciprocal exponent (scalar).

FRSQRTE:

Floating-point Reciprocal Square Root Estimate.

FRSQRTS:

Floating-point Reciprocal Square Root Step.

FRECPS:

Floating-point Reciprocal Step.

Floating-point Round to Integral exact, using current rounding mode (scalar).

FRINTX (vector):

Floating-point Round to Integral exact, using current rounding mode (vector).

Floating-point Round to Integral, to nearest with ties to Away (scalar).

FRINTA (vector):

Floating-point Round to Integral, to nearest with ties to Away (vector).

Floating-point Round to Integral, to nearest with ties to even (scalar).

FRINTN (vector):

Floating-point Round to Integral, to nearest with ties to even (vector).

Floating-point Round to Integral, toward Minus infinity (scalar).

FRINTM (vector):

Floating-point Round to Integral, toward Minus infinity (vector).

Floating-point Round to Integral, toward Plus infinity (scalar).

FRINTP (vector):

Floating-point Round to Integral, toward Plus infinity (vector).

Floating-point Round to Integral, toward Zero (scalar).

FRINTZ (vector):

Floating-point Round to Integral, toward Zero (vector).

Floating-point Round to Integral, using current rounding mode (scalar).

FRINTI (vector):

Floating-point Round to Integral, using current rounding mode (vector).

FCMPE:

Floating-point signaling Compare (scalar).

Floating-point Square Root (scalar).

FSQRT (vector):

Floating-point Square Root (vector).

Floating-point Subtract (scalar).

FSUB (vector):

Floating-point Subtract (vector).

FMADD: Floating-point fused Multiply-Add (scalar).

FMAX (scalar): Floating-point Maximum (scalar).

FMAX (vector): Floating-point Maximum (vector).

FMAXNM (scalar): Floating-point Maximum Number (scalar).

FMAXNM (vector): Floating-point Maximum Number (vector).

FMAXNMP (scalar): Floating-point Maximum Number of Pair of elements (scalar).

FMAXNMP (vector): Floating-point Maximum Number Pairwise (vector).

FMAXNMV: Floating-point Maximum Number across Vector.

FMAXP (scalar): Floating-point Maximum of Pair of elements (scalar).

FMAXP (vector): Floating-point Maximum Pairwise (vector).

FMAXV: Floating-point Maximum across Vector.

FMIN (scalar): Floating-point Minimum (scalar).

FMIN (vector): Floating-point minimum (vector).

FMINNM (scalar): Floating-point Minimum Number (scalar).

FMINNM (vector): Floating-point Minimum Number (vector).

FMINNMP (scalar): Floating-point Minimum Number of Pair of elements (scalar).

FMINNMP (vector): Floating-point Minimum Number Pairwise (vector).

FMINNMV: Floating-point Minimum Number across Vector.

FMINP (scalar): Floating-point Minimum of Pair of elements (scalar).

FMINP (vector): Floating-point Minimum Pairwise (vector).

FMINV: Floating-point Minimum across Vector.

FMLA (by element): Floating-point fused Multiply-Add to accumulator (by element).

FMLA (vector): Floating-point fused Multiply-Add to accumulator (vector).

FMLS (by element): Floating-point fused Multiply-Subtract from accumulator (by element).

FMLS (vector): Floating-point fused Multiply-Subtract from accumulator (vector).

FMOV (general): Floating-point Move to or from general-purpose register without conversion.

FMOV (register): Floating-point Move register without conversion.

FMOV (scalar, immediate): Floating-point move immediate (scalar).

FMOV (vector, immediate): Floating-point move immediate (vector).

FMSUB: Floating-point Fused Multiply-Subtract (scalar).

FMUL (by element): Floating-point Multiply (by element).

FMUL (scalar): Floating-point Multiply (scalar).

FMUL (vector): Floating-point Multiply (vector).

FMULX (by element): Floating-point Multiply extended (by element).

FMULX: Floating-point Multiply extended.

FNEG (scalar): Floating-point Negate (scalar).

FNEG (vector): Floating-point Negate (vector).

FNMADD: Floating-point Negated fused Multiply-Add (scalar).

FNMSUB: Floating-point Negated fused Multiply-Subtract (scalar).

FNMUL (scalar): Floating-point Multiply-Negate (scalar).

WFE: Wait

For Event.

WFI: Wait

For Interrupt.

Form PC-relative address to 4KB page.

ADR:

Form PC-relative address.

LD1 (multiple structures): Load multiple single-element structures to one, two, three, or

four registers.

LD4 (multiple structures): Load multiple 4-element structures to

four registers.

LD4 (single structure): Load single 4-element structure to one lane of

four registers.

LD4R: Load single 4-element structure and Replicate to all lanes of

four registers.

ST1 (multiple structures): Store multiple single-element structures from one, two, three, or

four registers.

ST4 (multiple structures): Store multiple 4-element structures from

four registers.

ST4 (single structure): Store single 4-element structure from one lane of

four registers.

FP Register (immediate offset).

FP register (immediate offset).

LDR (literal, SIMD&FP): Load SIMD&

FP Register (PC-relative literal).

FP Register (register offset).

FP register (register offset).

LDUR (SIMD&FP): Load SIMD&

FP Register (unscaled offset).

STUR (SIMD&FP): Store SIMD&

FP register (unscaled offset).

LDNP (SIMD&FP): Load Pair of SIMD&

FP registers, with Non-temporal hint.

STNP (SIMD&FP): Store Pair of SIMD&

FP registers, with Non-temporal hint.

LDP (SIMD&FP): Load Pair of SIMD&

FP registers.

STP (SIMD&FP): Store Pair of SIMD&

FP registers.

FP): Load Pair of SIMD&FP registers, with Non-temporal hint.

FP): Load Pair of SIMD&FP registers.

FP): Load SIMD&FP Register (immediate offset).

LDR (literal, SIMD&

FP): Load SIMD&FP Register (PC-relative literal).

FP): Load SIMD&FP Register (register offset).

FP): Load SIMD&FP Register (unscaled offset).

FP): Store Pair of SIMD&FP registers, with Non-temporal hint.

FP): Store Pair of SIMD&FP registers.

FP): Store SIMD&FP register (immediate offset).

FP): Store SIMD&FP register (register offset).

FP): Store SIMD&FP register (unscaled offset).

FRECPE: Floating-point Reciprocal Estimate.

FRECPS: Floating-point Reciprocal Step.

FRECPX: Floating-point Reciprocal exponent (scalar).

FRINTA (scalar): Floating-point Round to Integral, to nearest with ties to Away (scalar).

FRINTA (vector): Floating-point Round to Integral, to nearest with ties to Away (vector).

FRINTI (scalar): Floating-point Round to Integral, using current rounding mode (scalar).

FRINTI (vector): Floating-point Round to Integral, using current rounding mode (vector).

FRINTM (scalar): Floating-point Round to Integral, toward Minus infinity (scalar).

FRINTM (vector): Floating-point Round to Integral, toward Minus infinity (vector).

FRINTN (scalar): Floating-point Round to Integral, to nearest with ties to even (scalar).

FRINTN (vector): Floating-point Round to Integral, to nearest with ties to even (vector).

FRINTP (scalar): Floating-point Round to Integral, toward Plus infinity (scalar).

FRINTP (vector): Floating-point Round to Integral, toward Plus infinity (vector).

FRINTX (scalar): Floating-point Round to Integral exact, using current rounding mode (scalar).

FRINTX (vector): Floating-point Round to Integral exact, using current rounding mode (vector).

FRINTZ (scalar): Floating-point Round to Integral, toward Zero (scalar).

FRINTZ (vector): Floating-point Round to Integral, toward Zero (vector).

FRSQRTE: Floating-point Reciprocal Square Root Estimate.

FRSQRTS: Floating-point Reciprocal Square Root Step.

FSQRT (scalar): Floating-point Square Root (scalar).

FSQRT (vector): Floating-point Square Root (vector).

FSUB (scalar): Floating-point Subtract (scalar).

FSUB (vector): Floating-point Subtract (vector).

FMADD: Floating-point

fused Multiply-Add (scalar).

FNMADD: Floating-point Negated

fused Multiply-Add (scalar).

FMLA (by element): Floating-point

fused Multiply-Add to accumulator (by element).

FMLA (vector): Floating-point

fused Multiply-Add to accumulator (vector).

FMSUB: Floating-point

Fused Multiply-Subtract (scalar).

FNMSUB: Floating-point Negated

fused Multiply-Subtract (scalar).

FMLS (by element): Floating-point

fused Multiply-Subtract from accumulator (by element).

FMLS (vector): Floating-point

fused Multiply-Subtract from accumulator (vector).

MOV (from general): Move general-purpose register to a vector element: an alias of INS (

DUP (

general): Duplicate general-purpose register to vector.

general): Floating-point Move to or from general-purpose register without conversion.

INS (

general): Insert vector element from general-purpose register.

MOV (from

general): Move general-purpose register to a vector element: an alias of INS (general).

MOV (to

general): Move vector element to general-purpose register: an alias of UMOV.

MOV (from general): Move

general-purpose register to a vector element: an alias of INS (general).

general-purpose register to System Register.

DUP (general): Duplicate

general-purpose register to vector.

FMOV (general): Floating-point Move to or from

general-purpose register without conversion.

INS (general): Insert vector element from

general-purpose register.

SMOV: Signed Move vector element to

general-purpose register.

UMOV: Unsigned Move vector element to

general-purpose register.

MOV (to general): Move vector element to

general-purpose register: an alias of UMOV.

CMGT (register): Compare signed

Greater than (vector).

FACGT: Floating-point Absolute Compare

Greater than (vector).

FCMGT (register): Floating-point Compare

Greater than (vector).

CMGE (register): Compare signed

Greater than or Equal (vector).

FACGE: Floating-point Absolute Compare

Greater than or Equal (vector).

FCMGE (register): Floating-point Compare

Greater than or Equal (vector).

CMGE (zero): Compare signed

Greater than or Equal to zero (vector).

FCMGE (zero): Floating-point Compare

Greater than or Equal to zero (vector).

CMGT (zero): Compare signed

Greater than zero (vector).

FCMGT (zero): Floating-point Compare

Greater than zero (vector).

SQDMULH (by element): Signed saturating Doubling Multiply returning High

SQRDMLAH (by element): Signed Saturating Rounding Doubling Multiply Accumulate returning High

Half (by element).

SQRDMLSH (by element): Signed Saturating Rounding Doubling Multiply Subtract returning High

Half (by element).

SQRDMULH (by element): Signed saturating Rounding Doubling Multiply returning High

half (by element).

SQRDMLAH (vector): Signed Saturating Rounding Doubling Multiply Accumulate returning High

Half (vector).

SQRDMLSH (vector): Signed Saturating Rounding Doubling Multiply Subtract returning High

Half (vector).

SQDMULH (vector): Signed saturating Doubling Multiply returning High

half.

SQRDMULH (vector): Signed saturating Rounding Doubling Multiply returning High

half.

LDRH (immediate): Load Register

Halfword (immediate).

LDRSH (immediate): Load Register Signed

Halfword (immediate).

STRH (immediate): Store Register

Halfword (immediate).

LDRH (register): Load Register

Halfword (register).

LDRSH (register): Load Register Signed

Halfword (register).

STRH (register): Store Register

Halfword (register).

LDTRH: Load Register

Halfword (unprivileged).

LDTRSH: Load Register Signed

Halfword (unprivileged).

STTRH: Store Register

Halfword (unprivileged).

LDURH: Load Register

Halfword (unscaled).

LDURSH: Load Register Signed

Halfword (unscaled).

STURH: Store Register

Halfword (unscaled).

STADDH, STADDLH: Atomic add on

halfword in memory, without return.

STCLRH, STCLRLH: Atomic bit clear on

halfword in memory, without return.

STEORH, STEORLH: Atomic exclusive OR on

halfword in memory, without return.

STSETH, STSETLH: Atomic bit set on

halfword in memory, without return.

STSMAXH, STSMAXLH: Atomic signed maximum on

halfword in memory, without return.

STSMINH, STSMINLH: Atomic signed minimum on

halfword in memory, without return.

STUMAXH, STUMAXLH: Atomic unsigned maximum on

halfword in memory, without return.

STUMINH, STUMINLH: Atomic unsigned minimum on

halfword in memory, without return.

CASH, CASAH, CASALH, CASLH: Compare and Swap

halfword in memory.

halfword in memory.

halfword in memory.

LDEORH, LDEORAH, LDEORALH, LDEORLH: Atomic exclusive OR on

halfword in memory.

halfword in memory.

LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH: Atomic signed maximum on

halfword in memory.

LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH: Atomic signed minimum on

halfword in memory.

LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH: Atomic unsigned maximum on

halfword in memory.

LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH: Atomic unsigned minimum on

halfword in memory.

halfword in memory.

LDARH: Load-Acquire Register

Halfword.

LDAXRH: Load-Acquire Exclusive Register

Halfword.

LDLARH: Load LOAcquire Register

Halfword.

LDXRH: Load Exclusive Register

Halfword.

STLLRH: Store LORelease Register

Halfword.

STLRH: Store-Release Register

Halfword.

STLXRH: Store-Release Exclusive Register

Halfword.

STXRH: Store Exclusive Register

Halfword.

SXTH: Sign Extend

Halfword: an alias of SBFM.

UXTH: Unsigned Extend

Halfword: an alias of UBFM.

REV16 (vector): Reverse elements in 16-bit

halfwords (vector).

REV16: Reverse bytes in 16-bit

halfwords.

HLT:

Halt instruction.

SHADD: Signed

Halving Add.

SRHADD: Signed Rounding

Halving Add.

UHADD: Unsigned

Halving Add.

URHADD: Unsigned Rounding

Halving Add.

SHSUB: Signed

Halving Subtract.

UHSUB: Unsigned

Halving Subtract.

SHA1C: SHA1

hash update (choose).

SHA1M: SHA1

hash update (majority).

SHA1P: SHA1

hash update (parity).

SHA256H: SHA256

hash update (part 1).

SHA256H2: SHA256

hash update (part 2).

SQDMULH (by element): Signed saturating Doubling Multiply returning

High half (by element).

SQRDMLAH (by element): Signed Saturating Rounding Doubling Multiply Accumulate returning

High Half (by element).

SQRDMLSH (by element): Signed Saturating Rounding Doubling Multiply Subtract returning

High Half (by element).

SQRDMULH (by element): Signed saturating Rounding Doubling Multiply returning

High half (by element).

SQRDMLAH (vector): Signed Saturating Rounding Doubling Multiply Accumulate returning

High Half (vector).

SQRDMLSH (vector): Signed Saturating Rounding Doubling Multiply Subtract returning

High Half (vector).

SQDMULH (vector): Signed saturating Doubling Multiply returning

High half.

SQRDMULH (vector): Signed saturating Rounding Doubling Multiply returning

High half.

ADDHN, ADDHN2: Add returning

High Narrow.

RADDHN, RADDHN2: Rounding Add returning

High Narrow.

RSUBHN, RSUBHN2: Rounding Subtract returning

High Narrow.

SUBHN, SUBHN2: Subtract returning

High Narrow.

SMULH: Signed Multiply

High.

UMULH: Unsigned Multiply

High.

CMHI (register): Compare unsigned

Higher (vector).

CMHS (register): Compare unsigned

Higher or Same (vector).

FCVTL, FCVTL2: Floating-point Convert to

higher precision Long (vector).

Hint instruction.

LDNP (SIMD&FP): Load Pair of SIMD&FP registers, with Non-temporal

hint.

LDNP: Load Pair of Registers, with non-temporal

hint.

STNP (SIMD&FP): Store Pair of SIMD&FP registers, with Non-temporal

hint.

STNP: Store Pair of Registers, with non-temporal

hint.

HINT: Hint instruction.

HLT: Halt instruction.

HVC: Hypervisor Call.

HVC:

Hypervisor Call.

FMOV (scalar, immediate): Floating-point move

immediate (scalar).

FMOV (vector, immediate): Floating-point move

immediate (vector).

MOVI: Move

Immediate (vector).

MVNI: Move inverted

Immediate (vector).

LDR (immediate, SIMD&FP): Load SIMD&FP Register (

immediate offset).

STR (immediate, SIMD&FP): Store SIMD&FP register (

immediate offset).

MSR (immediate): Move

immediate value to Special Register.

immediate), setting flags.

ANDS (immediate): Bitwise AND (

immediate), setting flags.

SUBS (immediate): Subtract (

immediate), setting flags.

immediate).

AND (immediate): Bitwise AND (

immediate).

BIC (vector, immediate): Bitwise bit Clear (vector,

immediate).

CCMN (immediate): Conditional Compare Negative (

immediate).

CCMP (immediate): Conditional Compare (

immediate).

CMN (immediate): Compare Negative (immediate): an alias of ADDS (

immediate).

CMP (immediate): Compare (immediate): an alias of SUBS (

immediate).

EOR (immediate): Bitwise Exclusive OR (

immediate).

LDR (immediate): Load Register (

immediate).

LDRB (immediate): Load Register Byte (

immediate).

LDRH (immediate): Load Register Halfword (

immediate).

LDRSB (immediate): Load Register Signed Byte (

immediate).

LDRSH (immediate): Load Register Signed Halfword (

immediate).

LDRSW (immediate): Load Register Signed Word (

immediate).

MOV (bitmask immediate): Move (bitmask immediate): an alias of ORR (

immediate).

MOV (to/from SP): Move between register and stack pointer: an alias of ADD (

immediate).

ORR (immediate): Bitwise OR (

immediate).

ORR (vector, immediate): Bitwise inclusive OR (vector,

immediate).

PRFM (immediate): Prefetch Memory (

immediate).

RSHRN, RSHRN2: Rounding Shift Right Narrow (

immediate).

SHL: Shift Left (

immediate).

SHRN, SHRN2: Shift Right Narrow (

immediate).

SLI: Shift Left and Insert (

immediate).

SQRSHRN, SQRSHRN2: Signed saturating Rounded Shift Right Narrow (

immediate).

SQRSHRUN, SQRSHRUN2: Signed saturating Rounded Shift Right Unsigned Narrow (

immediate).

SQSHL (immediate): Signed saturating Shift Left (

immediate).

SQSHLU: Signed saturating Shift Left Unsigned (

immediate).

SQSHRN, SQSHRN2: Signed saturating Shift Right Narrow (

immediate).

SQSHRUN, SQSHRUN2: Signed saturating Shift Right Unsigned Narrow (

immediate).

SRI: Shift Right and Insert (

immediate).

SRSHR: Signed Rounding Shift Right (

immediate).

SRSRA: Signed Rounding Shift Right and Accumulate (

immediate).

SSHLL, SSHLL2: Signed Shift Left Long (

immediate).

SSHR: Signed Shift Right (

immediate).

SSRA: Signed Shift Right and Accumulate (

immediate).

STR (immediate): Store Register (

immediate).

STRB (immediate): Store Register Byte (

immediate).

STRH (immediate): Store Register Halfword (

immediate).

SUB (immediate): Subtract (

immediate).

TST (immediate): Test bits (immediate): an alias of ANDS (

immediate).

UQRSHRN, UQRSHRN2: Unsigned saturating Rounded Shift Right Narrow (

immediate).

UQSHL (immediate): Unsigned saturating Shift Left (

immediate).

UQSHRN, UQSHRN2: Unsigned saturating Shift Right Narrow (

immediate).

URSHR: Unsigned Rounding Shift Right (

immediate).

URSRA: Unsigned Rounding Shift Right and Accumulate (

immediate).

USHLL, USHLL2: Unsigned Shift Left Long (

immediate).

USHR: Unsigned Shift Right (

immediate).

USRA: Unsigned Shift Right and Accumulate (

immediate).

immediate): Add (immediate), setting flags.

immediate): Add (immediate).

CMN (immediate): Compare Negative (

immediate): an alias of ADDS (immediate).

TST (immediate): Test bits (

immediate): an alias of ANDS (immediate).

ROR (immediate): Rotate right (

immediate): an alias of EXTR.

MOV (inverted wide immediate): Move (inverted wide

immediate): an alias of MOVN.

MOV (wide immediate): Move (wide

immediate): an alias of MOVZ.

MOV (bitmask immediate): Move (bitmask

immediate): an alias of ORR (immediate).

ASR (immediate): Arithmetic Shift Right (

immediate): an alias of SBFM.

CMP (immediate): Compare (

immediate): an alias of SUBS (immediate).

LSL (immediate): Logical Shift Left (

immediate): an alias of UBFM.

LSR (immediate): Logical Shift Right (

immediate): an alias of UBFM.

ASR (

immediate): Arithmetic Shift Right (immediate): an alias of SBFM.

immediate): Bitwise AND (immediate), setting flags.

immediate): Bitwise AND (immediate).

immediate): Bitwise bit Clear (vector, immediate).

immediate): Bitwise Exclusive OR (immediate).

immediate): Bitwise inclusive OR (vector, immediate).

immediate): Bitwise OR (immediate).

CMP (

immediate): Compare (immediate): an alias of SUBS (immediate).

CMN (

immediate): Compare Negative (immediate): an alias of ADDS (immediate).

immediate): Conditional Compare (immediate).

immediate): Conditional Compare Negative (immediate).

FMOV (scalar,

immediate): Floating-point move immediate (scalar).

immediate): Floating-point move immediate (vector).

immediate): Load Register (immediate).

immediate): Load Register Byte (immediate).

immediate): Load Register Halfword (immediate).

immediate): Load Register Signed Byte (immediate).

immediate): Load Register Signed Halfword (immediate).

immediate): Load Register Signed Word (immediate).

LSL (

immediate): Logical Shift Left (immediate): an alias of UBFM.

LSR (

immediate): Logical Shift Right (immediate): an alias of UBFM.

MOV (bitmask

immediate): Move (bitmask immediate): an alias of ORR (immediate).

MOV (inverted wide

immediate): Move (inverted wide immediate): an alias of MOVN.

MOV (wide

immediate): Move (wide immediate): an alias of MOVZ.

MSR (

immediate): Move immediate value to Special Register.

immediate): Prefetch Memory (immediate).

ROR (

immediate): Rotate right (immediate): an alias of EXTR.

SQSHL (

immediate): Signed saturating Shift Left (immediate).

immediate): Store Register (immediate).

immediate): Store Register Byte (immediate).

immediate): Store Register Halfword (immediate).

immediate): Subtract (immediate), setting flags.

immediate): Subtract (immediate).

TST (

immediate): Test bits (immediate): an alias of ANDS (immediate).

UQSHL (

immediate): Unsigned saturating Shift Left (immediate).

immediate, SIMD&FP): Load SIMD&FP Register (immediate offset).

immediate, SIMD&FP): Store SIMD&FP register (immediate offset).

inclusive OR (vector, immediate).

inclusive OR (vector, register).

ORN (vector): Bitwise

inclusive OR NOT (vector).

CSINC: Conditional Select

Increment.

CINC: Conditional

Increment: an alias of CSINC.

FCVTMS (scalar): Floating-point Convert to Signed integer, rounding toward Minus

infinity (scalar).

FCVTMU (scalar): Floating-point Convert to Unsigned integer, rounding toward Minus

infinity (scalar).

FCVTPS (scalar): Floating-point Convert to Signed integer, rounding toward Plus

infinity (scalar).

FCVTPU (scalar): Floating-point Convert to Unsigned integer, rounding toward Plus

infinity (scalar).

FRINTM (scalar): Floating-point Round to Integral, toward Minus

infinity (scalar).

FRINTP (scalar): Floating-point Round to Integral, toward Plus

infinity (scalar).

FCVTMS (vector): Floating-point Convert to Signed integer, rounding toward Minus

infinity (vector).

FCVTMU (vector): Floating-point Convert to Unsigned integer, rounding toward Minus

infinity (vector).

FCVTPS (vector): Floating-point Convert to Signed integer, rounding toward Plus

infinity (vector).

FCVTPU (vector): Floating-point Convert to Unsigned integer, rounding toward Plus

infinity (vector).

FRINTM (vector): Floating-point Round to Integral, toward Minus

infinity (vector).

FRINTP (vector): Floating-point Round to Integral, toward Plus

infinity (vector).

MOV (element): Move vector element to another vector element: an alias of

INS (element).

INS (element): Insert vector element from another vector element.

MOV (from general): Move general-purpose register to a vector element: an alias of

INS (general).

INS (general): Insert vector element from general-purpose register.

SLI: Shift Left and

Insert (immediate).

SRI: Shift Right and

Insert (immediate).

BFXIL: Bitfield extract and

insert at low end: an alias of BFM.

BIF: Bitwise

Insert if False.

BIT: Bitwise

Insert if True.

SBFIZ: Signed Bitfield

Insert in Zero: an alias of SBFM.

UBFIZ: Unsigned Bitfield

Insert in Zero: an alias of UBFM.

INS (element):

Insert vector element from another vector element.

INS (general):

Insert vector element from general-purpose register.

BFI: Bitfield

Insert: an alias of BFM.

IC:

Instruction Cache operation: an alias of SYS.

ISB:

Instruction Synchronization Barrier.

SYSL: System

instruction with result.

BRK: Breakpoint

instruction.

HINT: Hint

instruction.

HLT: Halt

instruction.

SYS: System

instruction.

integer Convert to Floating-point (scalar).

integer Convert to Floating-point (scalar).

SCVTF (vector, integer): Signed

integer Convert to Floating-point (vector).

UCVTF (vector, integer): Unsigned

integer Convert to Floating-point (vector).

integer): Floating-point Convert to Signed integer, rounding toward Zero (scalar).

FCVTZS (vector,

integer): Floating-point Convert to Signed integer, rounding toward Zero (vector).

integer): Floating-point Convert to Unsigned integer, rounding toward Zero (scalar).

FCVTZU (vector,

integer): Floating-point Convert to Unsigned integer, rounding toward Zero (vector).

integer): Signed integer Convert to Floating-point (scalar).

SCVTF (vector,

integer): Signed integer Convert to Floating-point (vector).

integer): Unsigned integer Convert to Floating-point (scalar).

UCVTF (vector,

integer): Unsigned integer Convert to Floating-point (vector).

FCVTAS (scalar): Floating-point Convert to Signed

integer, rounding to nearest with ties to Away (scalar).

FCVTAU (scalar): Floating-point Convert to Unsigned

integer, rounding to nearest with ties to Away (scalar).

FCVTAS (vector): Floating-point Convert to Signed

integer, rounding to nearest with ties to Away (vector).

FCVTAU (vector): Floating-point Convert to Unsigned

integer, rounding to nearest with ties to Away (vector).

FCVTNS (scalar): Floating-point Convert to Signed

integer, rounding to nearest with ties to even (scalar).

FCVTNU (scalar): Floating-point Convert to Unsigned

integer, rounding to nearest with ties to even (scalar).

FCVTNS (vector): Floating-point Convert to Signed

integer, rounding to nearest with ties to even (vector).

FCVTNU (vector): Floating-point Convert to Unsigned

integer, rounding to nearest with ties to even (vector).

FCVTMS (scalar): Floating-point Convert to Signed

integer, rounding toward Minus infinity (scalar).

FCVTMU (scalar): Floating-point Convert to Unsigned

integer, rounding toward Minus infinity (scalar).

FCVTMS (vector): Floating-point Convert to Signed

integer, rounding toward Minus infinity (vector).

FCVTMU (vector): Floating-point Convert to Unsigned

integer, rounding toward Minus infinity (vector).

FCVTPS (scalar): Floating-point Convert to Signed

integer, rounding toward Plus infinity (scalar).

FCVTPU (scalar): Floating-point Convert to Unsigned

integer, rounding toward Plus infinity (scalar).

FCVTPS (vector): Floating-point Convert to Signed

integer, rounding toward Plus infinity (vector).

FCVTPU (vector): Floating-point Convert to Unsigned

integer, rounding toward Plus infinity (vector).

FCVTZS (scalar, integer): Floating-point Convert to Signed

integer, rounding toward Zero (scalar).

FCVTZU (scalar, integer): Floating-point Convert to Unsigned

integer, rounding toward Zero (scalar).

FCVTZS (vector, integer): Floating-point Convert to Signed

integer, rounding toward Zero (vector).

FCVTZU (vector, integer): Floating-point Convert to Unsigned

integer, rounding toward Zero (vector).

FRINTX (scalar): Floating-point Round to

Integral exact, using current rounding mode (scalar).

FRINTX (vector): Floating-point Round to

Integral exact, using current rounding mode (vector).

FRINTA (scalar): Floating-point Round to

Integral, to nearest with ties to Away (scalar).

FRINTA (vector): Floating-point Round to

Integral, to nearest with ties to Away (vector).

FRINTN (scalar): Floating-point Round to

Integral, to nearest with ties to even (scalar).

FRINTN (vector): Floating-point Round to

Integral, to nearest with ties to even (vector).

FRINTM (scalar): Floating-point Round to

Integral, toward Minus infinity (scalar).

FRINTM (vector): Floating-point Round to

Integral, toward Minus infinity (vector).

FRINTP (scalar): Floating-point Round to

Integral, toward Plus infinity (scalar).

FRINTP (vector): Floating-point Round to

Integral, toward Plus infinity (vector).

FRINTZ (scalar): Floating-point Round to

Integral, toward Zero (scalar).

FRINTZ (vector): Floating-point Round to

Integral, toward Zero (vector).

FRINTI (scalar): Floating-point Round to

Integral, using current rounding mode (scalar).

FRINTI (vector): Floating-point Round to

Integral, using current rounding mode (vector).

WFI: Wait For

Interrupt.

TLBI: TLB

Invalidate operation: an alias of SYS.

AESIMC: AES

inverse mix columns.

CSINV: Conditional Select

Invert.

CINV: Conditional

Invert: an alias of CSINV.

MVNI: Move

inverted Immediate (vector).

MOV (inverted wide immediate): Move (

inverted wide immediate): an alias of MOVN.

MOV (

inverted wide immediate): Move (inverted wide immediate): an alias of MOVN.

ISB: Instruction Synchronization Barrier.

ADRP: Form PC-relative address to 4

MOVK: Move wide with

keep.

LD4 (single structure): Load single 4-element structure to one

ST4 (single structure): Store single 4-element structure from one

lane of four registers.

LD1 (single structure): Load one single-element structure to one

lane of one register.

ST1 (single structure): Store a single-element structure from one

lane of one register.

LD3 (single structure): Load single 3-element structure to one

lane of three registers).

ST3 (single structure): Store single 3-element structure from one

lane of three registers.

LD2 (single structure): Load single 2-element structure to one

lane of two registers.

ST2 (single structure): Store single 2-element structure from one

lane of two registers.

LD1R: Load one single-element structure and Replicate to all

lanes (of one register).

LD4R: Load single 4-element structure and Replicate to all

lanes of four registers.

LD3R: Load single 3-element structure and Replicate to all

lanes of three registers.

LD2R: Load single 2-element structure and Replicate to all

lanes of two registers.

LD1 (multiple structures): Load multiple single-element structures to one, two, three, or four registers.

LD1 (single structure): Load one single-element structure to one lane of one register.

LD1R: Load one single-element structure and Replicate to all lanes (of one register).

LD2 (multiple structures): Load multiple 2-element structures to two registers.

LD2 (single structure): Load single 2-element structure to one lane of two registers.

LD2R: Load single 2-element structure and Replicate to all lanes of two registers.

LD3 (multiple structures): Load multiple 3-element structures to three registers.

LD3 (single structure): Load single 3-element structure to one lane of three registers).

LD3R: Load single 3-element structure and Replicate to all lanes of three registers.

LD4 (multiple structures): Load multiple 4-element structures to four registers.

LD4 (single structure): Load single 4-element structure to one lane of four registers.

LD4R: Load single 4-element structure and Replicate to all lanes of four registers.

LDADD, LDADDA, LDADDAL, LDADDL: Atomic add on word or doubleword in memory.

LDADDA, LDADDAL, LDADDL: Atomic add on word or doubleword in memory.

LDADDAB, LDADDALB, LDADDLB: Atomic add on byte in memory.

LDADDAH, LDADDALH, LDADDLH: Atomic add on halfword in memory.

LDADDAL, LDADDL: Atomic add on word or doubleword in memory.

LDADDALB, LDADDLB: Atomic add on byte in memory.

LDADDALH, LDADDLH: Atomic add on halfword in memory.

LDADDB, LDADDAB, LDADDALB, LDADDLB: Atomic add on byte in memory.

LDADDH, LDADDAH, LDADDALH, LDADDLH: Atomic add on halfword in memory.

LDADDL: Atomic add on word or doubleword in memory.

LDADDLB: Atomic add on byte in memory.

LDADDLH: Atomic add on halfword in memory.

LDAR: Load-Acquire Register.

LDARB: Load-Acquire Register Byte.

LDARH: Load-Acquire Register Halfword.

LDAXP: Load-Acquire Exclusive Pair of Registers.

LDAXR: Load-Acquire Exclusive Register.

LDAXRB: Load-Acquire Exclusive Register Byte.

LDAXRH: Load-Acquire Exclusive Register Halfword.

LDCLR, LDCLRA, LDCLRAL, LDCLRL: Atomic bit clear on word or doubleword in memory.

LDCLRA, LDCLRAL, LDCLRL: Atomic bit clear on word or doubleword in memory.

LDCLRAB, LDCLRALB, LDCLRLB: Atomic bit clear on byte in memory.

LDCLRAH, LDCLRALH, LDCLRLH: Atomic bit clear on halfword in memory.

LDCLRAL, LDCLRL: Atomic bit clear on word or doubleword in memory.

LDCLRALB, LDCLRLB: Atomic bit clear on byte in memory.

LDCLRALH, LDCLRLH: Atomic bit clear on halfword in memory.

LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB: Atomic bit clear on byte in memory.

LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH: Atomic bit clear on halfword in memory.

LDCLRL: Atomic bit clear on word or doubleword in memory.

LDCLRLB: Atomic bit clear on byte in memory.

LDCLRLH: Atomic bit clear on halfword in memory.

LDEOR, LDEORA, LDEORAL, LDEORL: Atomic exclusive OR on word or doubleword in memory.

LDEORA, LDEORAL, LDEORL: Atomic exclusive OR on word or doubleword in memory.

LDEORAB, LDEORALB, LDEORLB: Atomic exclusive OR on byte in memory.

LDEORAH, LDEORALH, LDEORLH: Atomic exclusive OR on halfword in memory.

LDEORAL, LDEORL: Atomic exclusive OR on word or doubleword in memory.

LDEORALB, LDEORLB: Atomic exclusive OR on byte in memory.

LDEORALH, LDEORLH: Atomic exclusive OR on halfword in memory.

LDEORB, LDEORAB, LDEORALB, LDEORLB: Atomic exclusive OR on byte in memory.

LDEORH, LDEORAH, LDEORALH, LDEORLH: Atomic exclusive OR on halfword in memory.

LDEORL: Atomic exclusive OR on word or doubleword in memory.

LDEORLB: Atomic exclusive OR on byte in memory.

LDEORLH: Atomic exclusive OR on halfword in memory.

LDLAR: Load LOAcquire Register.

LDLARB: Load LOAcquire Register Byte.

LDLARH: Load LOAcquire Register Halfword.

LDNP (SIMD&FP): Load Pair of SIMD&FP registers, with Non-temporal hint.

LDNP: Load Pair of Registers, with non-temporal hint.

LDP (SIMD&FP): Load Pair of SIMD&FP registers.

LDP: Load Pair of Registers.

LDPSW: Load Pair of Registers Signed Word.

LDR (immediate): Load Register (immediate).

LDR (immediate, SIMD&FP): Load SIMD&FP Register (immediate offset).

LDR (literal): Load Register (literal).

LDR (literal, SIMD&FP): Load SIMD&FP Register (PC-relative literal).

LDR (register): Load Register (register).

LDR (register, SIMD&FP): Load SIMD&FP Register (register offset).

LDRB (immediate): Load Register Byte (immediate).

LDRB (register): Load Register Byte (register).

LDRH (immediate): Load Register Halfword (immediate).

LDRH (register): Load Register Halfword (register).

LDRSB (immediate): Load Register Signed Byte (immediate).

LDRSB (register): Load Register Signed Byte (register).

LDRSH (immediate): Load Register Signed Halfword (immediate).

LDRSH (register): Load Register Signed Halfword (register).

LDRSW (immediate): Load Register Signed Word (immediate).

LDRSW (literal): Load Register Signed Word (literal).

LDRSW (register): Load Register Signed Word (register).

LDSET, LDSETA, LDSETAL, LDSETL: Atomic bit set on word or doubleword in memory.

LDSETA, LDSETAL, LDSETL: Atomic bit set on word or doubleword in memory.

LDSETAB, LDSETALB, LDSETLB: Atomic bit set on byte in memory.

LDSETAH, LDSETALH, LDSETLH: Atomic bit set on halfword in memory.

LDSETAL, LDSETL: Atomic bit set on word or doubleword in memory.

LDSETALB, LDSETLB: Atomic bit set on byte in memory.

LDSETALH, LDSETLH: Atomic bit set on halfword in memory.

LDSETB, LDSETAB, LDSETALB, LDSETLB: Atomic bit set on byte in memory.

LDSETH, LDSETAH, LDSETALH, LDSETLH: Atomic bit set on halfword in memory.

LDSETL: Atomic bit set on word or doubleword in memory.

LDSETLB: Atomic bit set on byte in memory.

LDSETLH: Atomic bit set on halfword in memory.

LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL: Atomic signed maximum on word or doubleword in memory.

LDSMAXA, LDSMAXAL, LDSMAXL: Atomic signed maximum on word or doubleword in memory.

LDSMAXAB, LDSMAXALB, LDSMAXLB: Atomic signed maximum on byte in memory.

LDSMAXAH, LDSMAXALH, LDSMAXLH: Atomic signed maximum on halfword in memory.

LDSMAXAL, LDSMAXL: Atomic signed maximum on word or doubleword in memory.

LDSMAXALB, LDSMAXLB: Atomic signed maximum on byte in memory.

LDSMAXALH, LDSMAXLH: Atomic signed maximum on halfword in memory.

LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB: Atomic signed maximum on byte in memory.

LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH: Atomic signed maximum on halfword in memory.

LDSMAXL: Atomic signed maximum on word or doubleword in memory.

LDSMAXLB: Atomic signed maximum on byte in memory.

LDSMAXLH: Atomic signed maximum on halfword in memory.

LDSMIN, LDSMINA, LDSMINAL, LDSMINL: Atomic signed minimum on word or doubleword in memory.

LDSMINA, LDSMINAL, LDSMINL: Atomic signed minimum on word or doubleword in memory.

LDSMINAB, LDSMINALB, LDSMINLB: Atomic signed minimum on byte in memory.

LDSMINAH, LDSMINALH, LDSMINLH: Atomic signed minimum on halfword in memory.

LDSMINAL, LDSMINL: Atomic signed minimum on word or doubleword in memory.

LDSMINALB, LDSMINLB: Atomic signed minimum on byte in memory.

LDSMINALH, LDSMINLH: Atomic signed minimum on halfword in memory.

LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB: Atomic signed minimum on byte in memory.

LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH: Atomic signed minimum on halfword in memory.

LDSMINL: Atomic signed minimum on word or doubleword in memory.

LDSMINLB: Atomic signed minimum on byte in memory.

LDSMINLH: Atomic signed minimum on halfword in memory.

LDTR: Load Register (unprivileged).

LDTRB: Load Register Byte (unprivileged).

LDTRH: Load Register Halfword (unprivileged).

LDTRSB: Load Register Signed Byte (unprivileged).

LDTRSH: Load Register Signed Halfword (unprivileged).

LDTRSW: Load Register Signed Word (unprivileged).

LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL: Atomic unsigned maximum on word or doubleword in memory.

LDUMAXA, LDUMAXAL, LDUMAXL: Atomic unsigned maximum on word or doubleword in memory.

LDUMAXAB, LDUMAXALB, LDUMAXLB: Atomic unsigned maximum on byte in memory.

LDUMAXAH, LDUMAXALH, LDUMAXLH: Atomic unsigned maximum on halfword in memory.

LDUMAXAL, LDUMAXL: Atomic unsigned maximum on word or doubleword in memory.

LDUMAXALB, LDUMAXLB: Atomic unsigned maximum on byte in memory.

LDUMAXALH, LDUMAXLH: Atomic unsigned maximum on halfword in memory.

LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB: Atomic unsigned maximum on byte in memory.

LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH: Atomic unsigned maximum on halfword in memory.

LDUMAXL: Atomic unsigned maximum on word or doubleword in memory.

LDUMAXLB: Atomic unsigned maximum on byte in memory.

LDUMAXLH: Atomic unsigned maximum on halfword in memory.

LDUMIN, LDUMINA, LDUMINAL, LDUMINL: Atomic unsigned minimum on word or doubleword in memory.

LDUMINA, LDUMINAL, LDUMINL: Atomic unsigned minimum on word or doubleword in memory.

LDUMINAB, LDUMINALB, LDUMINLB: Atomic unsigned minimum on byte in memory.

LDUMINAH, LDUMINALH, LDUMINLH: Atomic unsigned minimum on halfword in memory.

LDUMINAL, LDUMINL: Atomic unsigned minimum on word or doubleword in memory.

LDUMINALB, LDUMINLB: Atomic unsigned minimum on byte in memory.

LDUMINALH, LDUMINLH: Atomic unsigned minimum on halfword in memory.

LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB: Atomic unsigned minimum on byte in memory.

LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH: Atomic unsigned minimum on halfword in memory.

LDUMINL: Atomic unsigned minimum on word or doubleword in memory.

LDUMINLB: Atomic unsigned minimum on byte in memory.

LDUMINLH: Atomic unsigned minimum on halfword in memory.

LDUR (SIMD&FP): Load SIMD&FP Register (unscaled offset).

LDUR: Load Register (unscaled).

LDURB: Load Register Byte (unscaled).

LDURH: Load Register Halfword (unscaled).

LDURSB: Load Register Signed Byte (unscaled).

LDURSH: Load Register Signed Halfword (unscaled).

LDURSW: Load Register Signed Word (unscaled).

LDXP: Load Exclusive Pair of Registers.

LDXR: Load Exclusive Register.

LDXRB: Load Exclusive Register Byte.

LDXRH: Load Exclusive Register Halfword.

CLS (vector): Count

Leading Sign bits (vector).

CLS: Count

leading sign bits.

CLZ (vector): Count

Leading Zero bits (vector).

CLZ: Count

leading zero bits.

BFC: Bitfield Clear,

leaving other bits unchanged: an alias of BFM.

SHL: Shift

Left (immediate).

SQSHL (immediate): Signed saturating Shift

Left (immediate).

UQSHL (immediate): Unsigned saturating Shift

Left (immediate).

LSL (immediate): Logical Shift

Left (immediate): an alias of UBFM.

SQRSHL: Signed saturating Rounding Shift

Left (register).

SQSHL (register): Signed saturating Shift

Left (register).

SRSHL: Signed Rounding Shift

Left (register).

SSHL: Signed Shift

Left (register).

UQRSHL: Unsigned saturating Rounding Shift

Left (register).

UQSHL (register): Unsigned saturating Shift

Left (register).

URSHL: Unsigned Rounding Shift

Left (register).

USHL: Unsigned Shift

Left (register).

LSL (register): Logical Shift

Left (register): an alias of LSLV.

SLI: Shift

Left and Insert (immediate).

SHLL, SHLL2: Shift

Left Long (by element size).

SSHLL, SSHLL2: Signed Shift

Left Long (immediate).

USHLL, USHLL2: Unsigned Shift

Left Long (immediate).

SQSHLU: Signed saturating Shift

Left Unsigned (immediate).

LSLV: Logical Shift

Left Variable.

CMLE (zero): Compare signed

Less than or Equal to zero (vector).

FCMLE (zero): Floating-point Compare

Less than or Equal to zero (vector).

CMLT (zero): Compare signed

Less than zero (vector).

FCMLT (zero): Floating-point Compare

Less than zero (vector).

BLR: Branch with

Link to Register.

BL: Branch with

Link.

LDR (literal): Load Register (

literal).

LDR (literal, SIMD&FP): Load SIMD&FP Register (PC-relative

literal).

LDRSW (literal): Load Register Signed Word (

literal).

PRFM (literal): Prefetch Memory (

literal).

LDR (

literal): Load Register (literal).

literal): Load Register Signed Word (literal).

literal): Prefetch Memory (literal).

LDR (

literal, SIMD&FP): Load SIMD&FP Register (PC-relative literal).

Load Exclusive Pair of Registers.

Load Exclusive Register Byte.

Load Exclusive Register Halfword.

Load Exclusive Register.

Load LOAcquire Register Byte.

Load LOAcquire Register Halfword.

Load LOAcquire Register.

Load multiple 2-element structures to two registers.

Load multiple 3-element structures to three registers.

Load multiple 4-element structures to four registers.

Load multiple single-element structures to one, two, three, or four registers.

Load one single-element structure and Replicate to all lanes (of one register).

Load one single-element structure to one lane of one register.

Load Pair of Registers Signed Word.

Load Pair of Registers, with non-temporal hint.

LDP:

Load Pair of Registers.

Load Pair of SIMD&FP registers, with Non-temporal hint.

Load Pair of SIMD&FP registers.

Load Register (immediate).

LDR (literal):

Load Register (literal).

Load Register (register).

Load Register (unprivileged).

Load Register (unscaled).

Load Register Byte (immediate).

Load Register Byte (register).

Load Register Byte (unprivileged).

Load Register Byte (unscaled).

Load Register Halfword (immediate).

Load Register Halfword (register).

Load Register Halfword (unprivileged).

Load Register Halfword (unscaled).

Load Register Signed Byte (immediate).

Load Register Signed Byte (register).

Load Register Signed Byte (unprivileged).

Load Register Signed Byte (unscaled).

Load Register Signed Halfword (immediate).

Load Register Signed Halfword (register).

Load Register Signed Halfword (unprivileged).

Load Register Signed Halfword (unscaled).

Load Register Signed Word (immediate).

Load Register Signed Word (literal).

Load Register Signed Word (register).

Load Register Signed Word (unprivileged).

Load Register Signed Word (unscaled).

Load SIMD&FP Register (immediate offset).

LDR (literal, SIMD&FP):

Load SIMD&FP Register (PC-relative literal).

Load SIMD&FP Register (register offset).

Load SIMD&FP Register (unscaled offset).

Load single 2-element structure and Replicate to all lanes of two registers.

Load single 2-element structure to one lane of two registers.

Load single 3-element structure and Replicate to all lanes of three registers.

Load single 3-element structure to one lane of three registers).

Load single 4-element structure and Replicate to all lanes of four registers.

Load single 4-element structure to one lane of four registers.

Load-Acquire Exclusive Pair of Registers.

Load-Acquire Exclusive Register Byte.

Load-Acquire Exclusive Register Halfword.

Load-Acquire Exclusive Register.

Load-Acquire Register Byte.

Load-Acquire Register Halfword.

Load-Acquire Register.

SEVL: Send Event

Local.

LSL (immediate):

Logical Shift Left (immediate): an alias of UBFM.

LSL (register):

Logical Shift Left (register): an alias of LSLV.

LSLV:

Logical Shift Left Variable.

LSR (immediate):

Logical Shift Right (immediate): an alias of UBFM.

LSR (register):

Logical Shift Right (register): an alias of LSRV.

LSRV:

Logical Shift Right Variable.

SHLL, SHLL2: Shift Left

Long (by element size).

SQDMLAL, SQDMLAL2 (by element): Signed saturating Doubling Multiply-Add

Long (by element).

SQDMLSL, SQDMLSL2 (by element): Signed saturating Doubling Multiply-Subtract

Long (by element).

SQDMULL, SQDMULL2 (by element): Signed saturating Doubling Multiply

Long (by element).

SSHLL, SSHLL2: Signed Shift Left

Long (immediate).

USHLL, USHLL2: Unsigned Shift Left

Long (immediate).

FCVTL, FCVTL2: Floating-point Convert to higher precision

Long (vector).

SADDL, SADDL2: Signed Add

Long (vector).

SMLAL, SMLAL2 (vector): Signed Multiply-Add

Long (vector).

SMLSL, SMLSL2 (vector): Signed Multiply-Subtract

Long (vector).

SMULL, SMULL2 (vector): Signed Multiply

Long (vector).

UADDL, UADDL2: Unsigned Add

Long (vector).

UMLAL, UMLAL2 (vector): Unsigned Multiply-Add

Long (vector).

UMLSL, UMLSL2 (vector): Unsigned Multiply-Subtract

Long (vector).

UMULL, UMULL2 (vector): Unsigned Multiply

long (vector).

SMLAL, SMLAL2 (by element): Signed Multiply-Add

Long (vector, by element).

SMLSL, SMLSL2 (by element): Signed Multiply-Subtract

Long (vector, by element).

SMULL, SMULL2 (by element): Signed Multiply

Long (vector, by element).

UMLAL, UMLAL2 (by element): Unsigned Multiply-Add

Long (vector, by element).

UMLSL, UMLSL2 (by element): Unsigned Multiply-Subtract

Long (vector, by element).

UMULL, UMULL2 (by element): Unsigned Multiply

Long (vector, by element).

SADDLV: Signed Add

Long across Vector.

UADDLV: Unsigned sum

Long across Vector.

SADALP: Signed Add and Accumulate

Long Pairwise.

SADDLP: Signed Add

Long Pairwise.

UADALP: Unsigned Add and Accumulate

Long Pairwise.

UADDLP: Unsigned Add

Long Pairwise.

PMULL, PMULL2: Polynomial Multiply

Long.

SABAL, SABAL2: Signed Absolute difference and Accumulate

Long.

SABDL, SABDL2: Signed Absolute Difference

Long.

SMADDL: Signed Multiply-Add

Long.

SMSUBL: Signed Multiply-Subtract

Long.

SQDMLAL, SQDMLAL2 (vector): Signed saturating Doubling Multiply-Add

Long.

SQDMLSL, SQDMLSL2 (vector): Signed saturating Doubling Multiply-Subtract

Long.

SQDMULL, SQDMULL2 (vector): Signed saturating Doubling Multiply

Long.

SSUBL, SSUBL2: Signed Subtract

Long.

UABAL, UABAL2: Unsigned Absolute difference and Accumulate

Long.

UABDL, UABDL2: Unsigned Absolute Difference

Long.

UMADDL: Unsigned Multiply-Add

Long.

UMSUBL: Unsigned Multiply-Subtract

Long.

USUBL, USUBL2: Unsigned Subtract

Long.

SMULL: Signed Multiply

Long: an alias of SMADDL.

SMNEGL: Signed Multiply-Negate

Long: an alias of SMSUBL.

SXTL, SXTL2: Signed extend

Long: an alias of SSHLL, SSHLL2.

UMULL: Unsigned Multiply

Long: an alias of UMADDL.

UMNEGL: Unsigned Multiply-Negate

Long: an alias of UMSUBL.

UXTL, UXTL2: Unsigned extend

Long: an alias of USHLL, USHLL2.

TBX: Table vector

lookup extension.

TBL: Table vector

Lookup.

BFXIL: Bitfield extract and insert at

low end: an alias of BFM.

FCVTN, FCVTN2: Floating-point Convert to

lower precision Narrow (vector).

FCVTXN, FCVTXN2: Floating-point Convert to

lower precision Narrow, rounding to odd (vector).

LSL (immediate): Logical Shift Left (immediate): an alias of UBFM.

LSL (register): Logical Shift Left (register): an alias of LSLV.

LSL (register): Logical Shift Left (register): an alias of

LSLV.

LSLV: Logical Shift Left Variable.

LSR (immediate): Logical Shift Right (immediate): an alias of UBFM.

LSR (register): Logical Shift Right (register): an alias of LSRV.

LSR (register): Logical Shift Right (register): an alias of

LSRV.

LSRV: Logical Shift Right Variable.

MUL: Multiply: an alias of

MADD: Multiply-Add.

SHA1M: SHA1 hash update (

majority).

CSETM: Conditional Set

Mask: an alias of CSINV.

FMAX (scalar): Floating-point

Maximum (scalar).

FMAX (vector): Floating-point

Maximum (vector).

SMAX: Signed

Maximum (vector).

UMAX: Unsigned

Maximum (vector).

FMAXV: Floating-point

Maximum across Vector.

SMAXV: Signed

Maximum across Vector.

UMAXV: Unsigned

Maximum across Vector.

FMAXNM (scalar): Floating-point

Maximum Number (scalar).

FMAXNM (vector): Floating-point

Maximum Number (vector).

FMAXNMV: Floating-point

Maximum Number across Vector.

FMAXNMP (scalar): Floating-point

Maximum Number of Pair of elements (scalar).

FMAXNMP (vector): Floating-point

Maximum Number Pairwise (vector).

FMAXP (scalar): Floating-point

Maximum of Pair of elements (scalar).

STSMAXB, STSMAXLB: Atomic signed

maximum on byte in memory, without return.

STUMAXB, STUMAXLB: Atomic unsigned

maximum on byte in memory, without return.

maximum on byte in memory.

maximum on byte in memory.

STSMAXH, STSMAXLH: Atomic signed

maximum on halfword in memory, without return.

STUMAXH, STUMAXLH: Atomic unsigned

maximum on halfword in memory, without return.

maximum on halfword in memory.

maximum on halfword in memory.

STSMAX, STSMAXL: Atomic signed

maximum on word or doubleword in memory, without return.

STUMAX, STUMAXL: Atomic unsigned

maximum on word or doubleword in memory, without return.

maximum on word or doubleword in memory.

maximum on word or doubleword in memory.

FMAXP (vector): Floating-point

Maximum Pairwise (vector).

SMAXP: Signed

Maximum Pairwise.

UMAXP: Unsigned

Maximum Pairwise.

PRFM (immediate): Prefetch

Memory (immediate).

PRFM (literal): Prefetch

Memory (literal).

PRFM (register): Prefetch

Memory (register).

Memory (unscaled offset).

DMB: Data

Memory Barrier.

STADD, STADDL: Atomic add on word or doubleword in

memory, without return.

STADDB, STADDLB: Atomic add on byte in

memory, without return.

STADDH, STADDLH: Atomic add on halfword in

memory, without return.

STCLR, STCLRL: Atomic bit clear on word or doubleword in

memory, without return.

STCLRB, STCLRLB: Atomic bit clear on byte in

memory, without return.

STCLRH, STCLRLH: Atomic bit clear on halfword in

memory, without return.

STEOR, STEORL: Atomic exclusive OR on word or doubleword in

memory, without return.

STEORB, STEORLB: Atomic exclusive OR on byte in

memory, without return.

STEORH, STEORLH: Atomic exclusive OR on halfword in

memory, without return.

STSET, STSETL: Atomic bit set on word or doubleword in

memory, without return.

STSETB, STSETLB: Atomic bit set on byte in

memory, without return.

STSETH, STSETLH: Atomic bit set on halfword in

memory, without return.

STSMAX, STSMAXL: Atomic signed maximum on word or doubleword in

memory, without return.

STSMAXB, STSMAXLB: Atomic signed maximum on byte in

memory, without return.

STSMAXH, STSMAXLH: Atomic signed maximum on halfword in

memory, without return.

STSMIN, STSMINL: Atomic signed minimum on word or doubleword in

memory, without return.

STSMINB, STSMINLB: Atomic signed minimum on byte in

memory, without return.

STSMINH, STSMINLH: Atomic signed minimum on halfword in

memory, without return.

STUMAX, STUMAXL: Atomic unsigned maximum on word or doubleword in

memory, without return.

STUMAXB, STUMAXLB: Atomic unsigned maximum on byte in

memory, without return.

STUMAXH, STUMAXLH: Atomic unsigned maximum on halfword in

memory, without return.

STUMIN, STUMINL: Atomic unsigned minimum on word or doubleword in

memory, without return.

STUMINB, STUMINLB: Atomic unsigned minimum on byte in

memory, without return.

STUMINH, STUMINLH: Atomic unsigned minimum on halfword in

memory, without return.

CAS, CASA, CASAL, CASL: Compare and Swap word or doubleword in

memory.

CASB, CASAB, CASALB, CASLB: Compare and Swap byte in

memory.

CASH, CASAH, CASALH, CASLH: Compare and Swap halfword in

memory.

CASP, CASPA, CASPAL, CASPL: Compare and Swap Pair of words or doublewords in

memory.

LDADD, LDADDA, LDADDAL, LDADDL: Atomic add on word or doubleword in

memory.

LDADDB, LDADDAB, LDADDALB, LDADDLB: Atomic add on byte in

memory.

LDADDH, LDADDAH, LDADDALH, LDADDLH: Atomic add on halfword in

memory.

LDCLR, LDCLRA, LDCLRAL, LDCLRL: Atomic bit clear on word or doubleword in

memory.

LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB: Atomic bit clear on byte in

memory.

LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH: Atomic bit clear on halfword in

memory.

LDEOR, LDEORA, LDEORAL, LDEORL: Atomic exclusive OR on word or doubleword in

memory.

LDEORB, LDEORAB, LDEORALB, LDEORLB: Atomic exclusive OR on byte in

memory.

LDEORH, LDEORAH, LDEORALH, LDEORLH: Atomic exclusive OR on halfword in

memory.

LDSET, LDSETA, LDSETAL, LDSETL: Atomic bit set on word or doubleword in

memory.

LDSETB, LDSETAB, LDSETALB, LDSETLB: Atomic bit set on byte in

memory.

LDSETH, LDSETAH, LDSETALH, LDSETLH: Atomic bit set on halfword in

memory.

LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL: Atomic signed maximum on word or doubleword in

memory.

LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB: Atomic signed maximum on byte in

memory.

LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH: Atomic signed maximum on halfword in

memory.

LDSMIN, LDSMINA, LDSMINAL, LDSMINL: Atomic signed minimum on word or doubleword in

memory.

LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB: Atomic signed minimum on byte in

memory.

LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH: Atomic signed minimum on halfword in

memory.

LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL: Atomic unsigned maximum on word or doubleword in

memory.

LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB: Atomic unsigned maximum on byte in

memory.

LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH: Atomic unsigned maximum on halfword in

memory.

LDUMIN, LDUMINA, LDUMINAL, LDUMINL: Atomic unsigned minimum on word or doubleword in

memory.

LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB: Atomic unsigned minimum on byte in

memory.

LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH: Atomic unsigned minimum on halfword in

memory.

SWP, SWPA, SWPAL, SWPL: Swap word or doubleword in

memory.

memory.

SWPH, SWPAH, SWPALH, SWPLH: Swap halfword in

memory.

FMIN (scalar): Floating-point

Minimum (scalar).

FMIN (vector): Floating-point

minimum (vector).

SMIN: Signed

Minimum (vector).

UMIN: Unsigned

Minimum (vector).

FMINV: Floating-point

Minimum across Vector.

SMINV: Signed

Minimum across Vector.

UMINV: Unsigned

Minimum across Vector.

FMINNM (scalar): Floating-point

Minimum Number (scalar).

FMINNM (vector): Floating-point

Minimum Number (vector).

FMINNMV: Floating-point

Minimum Number across Vector.

FMINNMP (scalar): Floating-point

Minimum Number of Pair of elements (scalar).

FMINNMP (vector): Floating-point

Minimum Number Pairwise (vector).

FMINP (scalar): Floating-point

Minimum of Pair of elements (scalar).

STSMINB, STSMINLB: Atomic signed

minimum on byte in memory, without return.

STUMINB, STUMINLB: Atomic unsigned

minimum on byte in memory, without return.

minimum on byte in memory.

minimum on byte in memory.

STSMINH, STSMINLH: Atomic signed

minimum on halfword in memory, without return.

STUMINH, STUMINLH: Atomic unsigned

minimum on halfword in memory, without return.

minimum on halfword in memory.

minimum on halfword in memory.

STSMIN, STSMINL: Atomic signed

minimum on word or doubleword in memory, without return.

STUMIN, STUMINL: Atomic unsigned

minimum on word or doubleword in memory, without return.

minimum on word or doubleword in memory.

minimum on word or doubleword in memory.

FMINP (vector): Floating-point

Minimum Pairwise (vector).

SMINP: Signed

Minimum Pairwise.

UMINP: Unsigned

Minimum Pairwise.

FCVTMS (scalar): Floating-point Convert to Signed integer, rounding toward

Minus infinity (scalar).

FCVTMU (scalar): Floating-point Convert to Unsigned integer, rounding toward

Minus infinity (scalar).

FRINTM (scalar): Floating-point Round to Integral, toward

Minus infinity (scalar).

FCVTMS (vector): Floating-point Convert to Signed integer, rounding toward

Minus infinity (vector).

FCVTMU (vector): Floating-point Convert to Unsigned integer, rounding toward

Minus infinity (vector).

FRINTM (vector): Floating-point Round to Integral, toward

Minus infinity (vector).

AESIMC: AES inverse

mix columns.

AESMC: AES

mix columns.

MLA (by element): Multiply-Add to accumulator (vector, by element).

MLA (vector): Multiply-Add to accumulator (vector).

MLS (by element): Multiply-Subtract from accumulator (vector, by element).

MLS (vector): Multiply-Subtract from accumulator (vector).

MNEG: Multiply-Negate: an alias of MSUB.

FRINTI (scalar): Floating-point Round to Integral, using current rounding

mode (scalar).

FRINTX (scalar): Floating-point Round to Integral exact, using current rounding

mode (scalar).

FRINTI (vector): Floating-point Round to Integral, using current rounding

mode (vector).

FRINTX (vector): Floating-point Round to Integral exact, using current rounding

mode (vector).

SMC: Secure

Monitor Call.

MOV (bitmask immediate): Move (bitmask immediate): an alias of ORR (immediate).

MOV (element): Move vector element to another vector element: an alias of INS (element).

MOV (from general): Move general-purpose register to a vector element: an alias of INS (general).

MOV (inverted wide immediate): Move (inverted wide immediate): an alias of MOVN.

MOV (register): Move (register): an alias of ORR (shifted register).

MOV (scalar): Move vector element to scalar: an alias of DUP (element).

MOV (to general): Move vector element to general-purpose register: an alias of UMOV.

MOV (to/from SP): Move between register and stack pointer: an alias of ADD (immediate).

MOV (vector): Move vector: an alias of ORR (vector, register).

MOV (wide immediate): Move (wide immediate): an alias of MOVZ.

MOV (bitmask immediate):

Move (bitmask immediate): an alias of ORR (immediate).

MOV (inverted wide immediate):

Move (inverted wide immediate): an alias of MOVN.

MOV (register):

Move (register): an alias of ORR (shifted register).

MOV (wide immediate):

Move (wide immediate): an alias of MOVZ.

MOV (to/from SP):

Move between register and stack pointer: an alias of ADD (immediate).

MOV (from general):

Move general-purpose register to a vector element: an alias of INS (general).

Move general-purpose register to System Register.

FMOV (scalar, immediate): Floating-point

move immediate (scalar).

FMOV (vector, immediate): Floating-point

move immediate (vector).

MOVI:

Move Immediate (vector).

MSR (immediate):

Move immediate value to Special Register.

Move inverted Immediate (vector).

FMOV (register): Floating-point

Move register without conversion.

MRS:

Move System Register.

FMOV (general): Floating-point

Move to or from general-purpose register without conversion.

MOV (element):

Move vector element to another vector element: an alias of INS (element).

SMOV: Signed

Move vector element to general-purpose register.

UMOV: Unsigned

Move vector element to general-purpose register.

MOV (to general):

Move vector element to general-purpose register: an alias of UMOV.

MOV (scalar):

Move vector element to scalar: an alias of DUP (element).

MOV (vector):

Move vector: an alias of ORR (vector, register).

Move wide with keep.

Move wide with NOT.

Move wide with zero.

BFM: Bitfield

Move.

SBFM: Signed Bitfield

Move.

UBFM: Unsigned Bitfield

Move.

MOVI: Move Immediate (vector).

MOVK: Move wide with keep.

MOV (inverted wide immediate): Move (inverted wide immediate): an alias of

MOVN.

MOVN: Move wide with NOT.

MOV (wide immediate): Move (wide immediate): an alias of

MOVZ.

MOVZ: Move wide with zero.

MRS: Move System Register.

MSR (immediate): Move immediate value to Special Register.

MSR (register): Move general-purpose register to System Register.

MNEG: Multiply-Negate: an alias of

MSUB.

MSUB: Multiply-Subtract.

MUL (by element): Multiply (vector, by element).

MUL (vector): Multiply (vector).

MUL: Multiply: an alias of MADD.

multiple 2-element structures from two registers.

multiple 2-element structures to two registers.

multiple 3-element structures from three registers.

multiple 3-element structures to three registers.

multiple 4-element structures from four registers.

multiple 4-element structures to four registers.

multiple single-element structures from one, two, three, or four registers.

multiple single-element structures to one, two, three, or four registers.

multiple structures): Load multiple 2-element structures to two registers.

multiple structures): Load multiple 3-element structures to three registers.

multiple structures): Load multiple 4-element structures to four registers.

multiple structures): Load multiple single-element structures to one, two, three, or four registers.

multiple structures): Store multiple 2-element structures from two registers.

multiple structures): Store multiple 3-element structures from three registers.

multiple structures): Store multiple 4-element structures from four registers.

multiple structures): Store multiple single-element structures from one, two, three, or four registers.

FMUL (by element): Floating-point

Multiply (by element).

FMUL (scalar): Floating-point

Multiply (scalar).

FMUL (vector): Floating-point

Multiply (vector).

Multiply (vector).

Multiply (vector, by element).

SQRDMLAH (by element): Signed Saturating Rounding Doubling

Multiply Accumulate returning High Half (by element).

SQRDMLAH (vector): Signed Saturating Rounding Doubling

Multiply Accumulate returning High Half (vector).

FMULX (by element): Floating-point

Multiply extended (by element).

FMULX: Floating-point

Multiply extended.

SMULH: Signed

Multiply High.

UMULH: Unsigned

Multiply High.

SQDMULL, SQDMULL2 (by element): Signed saturating Doubling

Multiply Long (by element).

Multiply Long (vector).

Multiply long (vector).

Multiply Long (vector, by element).

Multiply Long (vector, by element).

PMULL, PMULL2: Polynomial

Multiply Long.

SQDMULL, SQDMULL2 (vector): Signed saturating Doubling

Multiply Long.

SMULL: Signed

Multiply Long: an alias of SMADDL.

UMULL: Unsigned

Multiply Long: an alias of UMADDL.

SQDMULH (by element): Signed saturating Doubling

Multiply returning High half (by element).

SQRDMULH (by element): Signed saturating Rounding Doubling

Multiply returning High half (by element).

SQDMULH (vector): Signed saturating Doubling

Multiply returning High half.

SQRDMULH (vector): Signed saturating Rounding Doubling

Multiply returning High half.

SQRDMLSH (by element): Signed Saturating Rounding Doubling

Multiply Subtract returning High Half (by element).

SQRDMLSH (vector): Signed Saturating Rounding Doubling

Multiply Subtract returning High Half (vector).

FMADD: Floating-point fused

Multiply-Add (scalar).

FNMADD: Floating-point Negated fused

Multiply-Add (scalar).

SQDMLAL, SQDMLAL2 (by element): Signed saturating Doubling

Multiply-Add Long (by element).

Multiply-Add Long (vector).

Multiply-Add Long (vector).

Multiply-Add Long (vector, by element).

Multiply-Add Long (vector, by element).

SMADDL: Signed

Multiply-Add Long.

SQDMLAL, SQDMLAL2 (vector): Signed saturating Doubling

Multiply-Add Long.

UMADDL: Unsigned

Multiply-Add Long.

FMLA (by element): Floating-point fused

Multiply-Add to accumulator (by element).

FMLA (vector): Floating-point fused

Multiply-Add to accumulator (vector).

Multiply-Add to accumulator (vector).

Multiply-Add to accumulator (vector, by element).

Multiply-Add.

FNMUL (scalar): Floating-point

Multiply-Negate (scalar).

SMNEGL: Signed

Multiply-Negate Long: an alias of SMSUBL.

UMNEGL: Unsigned

Multiply-Negate Long: an alias of UMSUBL.

MNEG:

Multiply-Negate: an alias of MSUB.

FMSUB: Floating-point Fused

Multiply-Subtract (scalar).

FNMSUB: Floating-point Negated fused

Multiply-Subtract (scalar).

FMLS (by element): Floating-point fused

Multiply-Subtract from accumulator (by element).

FMLS (vector): Floating-point fused

Multiply-Subtract from accumulator (vector).

Multiply-Subtract from accumulator (vector).

Multiply-Subtract from accumulator (vector, by element).

SQDMLSL, SQDMLSL2 (by element): Signed saturating Doubling

Multiply-Subtract Long (by element).

Multiply-Subtract Long (vector).

Multiply-Subtract Long (vector).

Multiply-Subtract Long (vector, by element).

Multiply-Subtract Long (vector, by element).

SMSUBL: Signed

Multiply-Subtract Long.

SQDMLSL, SQDMLSL2 (vector): Signed saturating Doubling

Multiply-Subtract Long.

UMSUBL: Unsigned

Multiply-Subtract Long.

Multiply-Subtract.

PMUL: Polynomial

Multiply.

MUL:

Multiply: an alias of MADD.

MVN: Bitwise NOT (vector): an alias of NOT.

MVN: Bitwise NOT: an alias of ORN (shifted register).

MVNI: Move inverted Immediate (vector).

RSHRN, RSHRN2: Rounding Shift Right

SHRN, SHRN2: Shift Right

Narrow (immediate).

SQRSHRN, SQRSHRN2: Signed saturating Rounded Shift Right

Narrow (immediate).

SQRSHRUN, SQRSHRUN2: Signed saturating Rounded Shift Right Unsigned

Narrow (immediate).

SQSHRN, SQSHRN2: Signed saturating Shift Right

Narrow (immediate).

SQSHRUN, SQSHRUN2: Signed saturating Shift Right Unsigned

Narrow (immediate).

UQRSHRN, UQRSHRN2: Unsigned saturating Rounded Shift Right

Narrow (immediate).

UQSHRN, UQSHRN2: Unsigned saturating Shift Right

Narrow (immediate).

FCVTN, FCVTN2: Floating-point Convert to lower precision

Narrow (vector).

FCVTXN, FCVTXN2: Floating-point Convert to lower precision

Narrow, rounding to odd (vector).

ADDHN, ADDHN2: Add returning High

Narrow.

RADDHN, RADDHN2: Rounding Add returning High

Narrow.

RSUBHN, RSUBHN2: Rounding Subtract returning High

Narrow.

SQXTN, SQXTN2: Signed saturating extract

Narrow.

SQXTUN, SQXTUN2: Signed saturating extract Unsigned

Narrow.

SUBHN, SUBHN2: Subtract returning High

Narrow.

UQXTN, UQXTN2: Unsigned saturating extract

Narrow.

XTN, XTN2: Extract

Narrow.

FCVTAS (scalar): Floating-point Convert to Signed integer, rounding to

nearest with ties to Away (scalar).

FCVTAU (scalar): Floating-point Convert to Unsigned integer, rounding to

nearest with ties to Away (scalar).

FRINTA (scalar): Floating-point Round to Integral, to

nearest with ties to Away (scalar).

FCVTAS (vector): Floating-point Convert to Signed integer, rounding to

nearest with ties to Away (vector).

FCVTAU (vector): Floating-point Convert to Unsigned integer, rounding to

nearest with ties to Away (vector).

FRINTA (vector): Floating-point Round to Integral, to

nearest with ties to Away (vector).

FCVTNS (scalar): Floating-point Convert to Signed integer, rounding to

nearest with ties to even (scalar).

FCVTNU (scalar): Floating-point Convert to Unsigned integer, rounding to

nearest with ties to even (scalar).

FRINTN (scalar): Floating-point Round to Integral, to

nearest with ties to even (scalar).

FCVTNS (vector): Floating-point Convert to Signed integer, rounding to

nearest with ties to even (vector).

FCVTNU (vector): Floating-point Convert to Unsigned integer, rounding to

nearest with ties to even (vector).

FRINTN (vector): Floating-point Round to Integral, to

nearest with ties to even (vector).

NEG (shifted register): Negate (shifted register): an alias of SUB (shifted register).

NEG (vector): Negate (vector).

FNEG (scalar): Floating-point

Negate (scalar).

FNMUL (scalar): Floating-point Multiply-

Negate (scalar).

NEG (shifted register):

Negate (shifted register): an alias of SUB (shifted register).

FNEG (vector): Floating-point

Negate (vector).

NEG (vector):

Negate (vector).

SMNEGL: Signed Multiply-

Negate Long: an alias of SMSUBL.

UMNEGL: Unsigned Multiply-

Negate Long: an alias of UMSUBL.

NGCS:

Negate with Carry, setting flags: an alias of SBCS.

NGC:

Negate with Carry: an alias of SBC.

NEGS:

Negate, setting flags: an alias of SUBS (shifted register).

SQNEG: Signed saturating

Negate.

CNEG: Conditional

Negate: an alias of CSNEG.

MNEG: Multiply-

Negate: an alias of MSUB.

FNMADD: Floating-point

Negated fused Multiply-Add (scalar).

FNMSUB: Floating-point

Negated fused Multiply-Subtract (scalar).

CSNEG: Conditional Select

Negation.

CMN (extended register): Compare

Negative (extended register): an alias of ADDS (extended register).

CCMN (immediate): Conditional Compare

Negative (immediate).

CMN (immediate): Compare

Negative (immediate): an alias of ADDS (immediate).

CCMN (register): Conditional Compare

Negative (register).

CMN (shifted register): Compare

Negative (shifted register): an alias of ADDS (shifted register).

NEGS: Negate, setting flags: an alias of SUBS (shifted register).

NGC: Negate with Carry: an alias of SBC.

NGCS: Negate with Carry, setting flags: an alias of SBCS.

NOP:

No Operation.

LDNP (SIMD&FP): Load Pair of SIMD&FP registers, with

Non-temporal hint.

LDNP: Load Pair of Registers, with

non-temporal hint.

STNP (SIMD&FP): Store Pair of SIMD&FP registers, with

Non-temporal hint.

STNP: Store Pair of Registers, with

non-temporal hint.

CMTST: Compare bitwise Test bits

nonzero (vector).

CBNZ: Compare and Branch on

Nonzero.

TBNZ: Test bit and Branch if

Nonzero.

NOP: No Operation.

EON (shifted register): Bitwise Exclusive OR

NOT (shifted register).

NOT (shifted register).

NOT: Bitwise

NOT (vector).

ORN (vector): Bitwise inclusive OR

NOT (vector).

MVN: Bitwise

NOT (vector): an alias of NOT.

MOVN: Move wide with

NOT.

MVN: Bitwise NOT (vector): an alias of

NOT.

MVN: Bitwise

NOT: an alias of ORN (shifted register).

NOT: Bitwise NOT (vector).

FMAXNM (scalar): Floating-point Maximum

Number (scalar).

FMINNM (scalar): Floating-point Minimum

Number (scalar).

FMAXNM (vector): Floating-point Maximum

Number (vector).

FMINNM (vector): Floating-point Minimum

Number (vector).

FMAXNMV: Floating-point Maximum

Number across Vector.

FMINNMV: Floating-point Minimum

Number across Vector.

FMAXNMP (scalar): Floating-point Maximum

Number of Pair of elements (scalar).

FMINNMP (scalar): Floating-point Minimum

Number of Pair of elements (scalar).

FMAXNMP (vector): Floating-point Maximum

Number Pairwise (vector).

FMINNMP (vector): Floating-point Minimum

Number Pairwise (vector).

FCVTXN, FCVTXN2: Floating-point Convert to lower precision Narrow, rounding to

LDR (immediate, SIMD&FP): Load SIMD&FP Register (immediate

offset).

LDR (register, SIMD&FP): Load SIMD&FP Register (register

offset).

LDUR (SIMD&FP): Load SIMD&FP Register (unscaled

offset).

PRFM (unscaled offset): Prefetch Memory (unscaled

offset).

STR (immediate, SIMD&FP): Store SIMD&FP register (immediate

offset).

STR (register, SIMD&FP): Store SIMD&FP register (register

offset).

STUR (SIMD&FP): Store SIMD&FP register (unscaled

offset).

offset): Prefetch Memory (unscaled offset).

STADDB, STADDLB: Atomic add

on byte in memory, without return.

STCLRB, STCLRLB: Atomic bit clear

on byte in memory, without return.

STEORB, STEORLB: Atomic exclusive OR

on byte in memory, without return.

STSETB, STSETLB: Atomic bit set

on byte in memory, without return.

STSMAXB, STSMAXLB: Atomic signed maximum

on byte in memory, without return.

STSMINB, STSMINLB: Atomic signed minimum

on byte in memory, without return.

STUMAXB, STUMAXLB: Atomic unsigned maximum

on byte in memory, without return.

STUMINB, STUMINLB: Atomic unsigned minimum

on byte in memory, without return.

on byte in memory.

on byte in memory.

on byte in memory.

on byte in memory.

on byte in memory.

on byte in memory.

LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB: Atomic unsigned maximum

on byte in memory.

LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB: Atomic unsigned minimum

on byte in memory.

STADDH, STADDLH: Atomic add

on halfword in memory, without return.

STCLRH, STCLRLH: Atomic bit clear

on halfword in memory, without return.

STEORH, STEORLH: Atomic exclusive OR

on halfword in memory, without return.

STSETH, STSETLH: Atomic bit set

on halfword in memory, without return.

STSMAXH, STSMAXLH: Atomic signed maximum

on halfword in memory, without return.

STSMINH, STSMINLH: Atomic signed minimum

on halfword in memory, without return.

STUMAXH, STUMAXLH: Atomic unsigned maximum

on halfword in memory, without return.

STUMINH, STUMINLH: Atomic unsigned minimum

on halfword in memory, without return.

on halfword in memory.

on halfword in memory.

on halfword in memory.

on halfword in memory.

on halfword in memory.

on halfword in memory.

LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH: Atomic unsigned maximum

on halfword in memory.

LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH: Atomic unsigned minimum

on halfword in memory.

CBNZ: Compare and Branch

on Nonzero.

STADD, STADDL: Atomic add

on word or doubleword in memory, without return.

STCLR, STCLRL: Atomic bit clear

on word or doubleword in memory, without return.

STEOR, STEORL: Atomic exclusive OR

on word or doubleword in memory, without return.

STSET, STSETL: Atomic bit set

on word or doubleword in memory, without return.

STSMAX, STSMAXL: Atomic signed maximum

on word or doubleword in memory, without return.

STSMIN, STSMINL: Atomic signed minimum

on word or doubleword in memory, without return.

STUMAX, STUMAXL: Atomic unsigned maximum

on word or doubleword in memory, without return.

STUMIN, STUMINL: Atomic unsigned minimum

on word or doubleword in memory, without return.

on word or doubleword in memory.

on word or doubleword in memory.

LDEOR, LDEORA, LDEORAL, LDEORL: Atomic exclusive OR

on word or doubleword in memory.

on word or doubleword in memory.

LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL: Atomic signed maximum

on word or doubleword in memory.

LDSMIN, LDSMINA, LDSMINAL, LDSMINL: Atomic signed minimum

on word or doubleword in memory.

LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL: Atomic unsigned maximum

on word or doubleword in memory.

LDUMIN, LDUMINA, LDUMINAL, LDUMINL: Atomic unsigned minimum

on word or doubleword in memory.

CBZ: Compare and Branch

on Zero.

LD4 (single structure): Load single 4-element structure to

one lane of four registers.

ST4 (single structure): Store single 4-element structure from

one lane of four registers.

LD1 (single structure): Load one single-element structure to

one lane of one register.

ST1 (single structure): Store a single-element structure from

one lane of one register.

LD3 (single structure): Load single 3-element structure to

one lane of three registers).

ST3 (single structure): Store single 3-element structure from

one lane of three registers.

LD2 (single structure): Load single 2-element structure to

one lane of two registers.

ST2 (single structure): Store single 2-element structure from

one lane of two registers.

LD1R: Load one single-element structure and Replicate to all lanes (of

one register).

LD1 (single structure): Load one single-element structure to one lane of

one register.

ST1 (single structure): Store a single-element structure from one lane of

one register.

LD1R: Load

one single-element structure and Replicate to all lanes (of one register).

one single-element structure to one lane of one register.

LD1 (multiple structures): Load multiple single-element structures to

one, two, three, or four registers.

ST1 (multiple structures): Store multiple single-element structures from

one, two, three, or four registers.

NOP: No

Operation.

DC: Data Cache

operation: an alias of SYS.

IC: Instruction Cache

operation: an alias of SYS.

TLBI: TLB Invalidate

operation: an alias of SYS.

EOR (immediate): Bitwise Exclusive

OR (immediate).

ORR (immediate): Bitwise

OR (immediate).

EOR (shifted register): Bitwise Exclusive

OR (shifted register).

OR (shifted register).

EOR (vector): Bitwise Exclusive

OR (vector).

ORR (vector, immediate): Bitwise inclusive

OR (vector, immediate).

ORR (vector, register): Bitwise inclusive

OR (vector, register).

EON (shifted register): Bitwise Exclusive

OR NOT (shifted register).

OR NOT (shifted register).

ORN (vector): Bitwise inclusive

OR NOT (vector).

STEORB, STEORLB: Atomic exclusive

OR on byte in memory, without return.

OR on byte in memory.

STEORH, STEORLH: Atomic exclusive

OR on halfword in memory, without return.

OR on halfword in memory.

STEOR, STEORL: Atomic exclusive

OR on word or doubleword in memory, without return.

OR on word or doubleword in memory.

RBIT (vector): Reverse Bit

order (vector).

MVN: Bitwise NOT: an alias of

ORN (shifted register).

ORN (shifted register): Bitwise OR NOT (shifted register).

ORN (vector): Bitwise inclusive OR NOT (vector).

MOV (bitmask immediate): Move (bitmask immediate): an alias of

ORR (immediate).

ORR (immediate): Bitwise OR (immediate).

MOV (register): Move (register): an alias of

ORR (shifted register).

ORR (shifted register): Bitwise OR (shifted register).

ORR (vector, immediate): Bitwise inclusive OR (vector, immediate).

MOV (vector): Move vector: an alias of

ORR (vector, register).

ORR (vector, register): Bitwise inclusive OR (vector, register).

BFC: Bitfield Clear, leaving

other bits unchanged: an alias of BFM.

ADRP: Form PC-relative address to 4KB

ADDP (scalar): Add

Pair of elements (scalar).

FADDP (scalar): Floating-point Add

Pair of elements (scalar).

FMAXNMP (scalar): Floating-point Maximum Number of

Pair of elements (scalar).

FMAXP (scalar): Floating-point Maximum of

Pair of elements (scalar).

FMINNMP (scalar): Floating-point Minimum Number of

Pair of elements (scalar).

FMINP (scalar): Floating-point Minimum of

Pair of elements (scalar).

LDPSW: Load

Pair of Registers Signed Word.

LDNP: Load

Pair of Registers, with non-temporal hint.

STNP: Store

Pair of Registers, with non-temporal hint.

LDAXP: Load-Acquire Exclusive

Pair of Registers.

LDP: Load

Pair of Registers.

LDXP: Load Exclusive

Pair of Registers.

STLXP: Store-Release Exclusive

Pair of registers.

STP: Store

Pair of Registers.

STXP: Store Exclusive

Pair of registers.

Pair of SIMD&FP registers, with Non-temporal hint.

Pair of SIMD&FP registers, with Non-temporal hint.

Pair of SIMD&FP registers.

Pair of SIMD&FP registers.

EXT: Extract vector from

pair of vectors.

CASP, CASPA, CASPAL, CASPL: Compare and Swap

Pair of words or doublewords in memory.

ADDP (vector): Add

Pairwise (vector).

FADDP (vector): Floating-point Add

Pairwise (vector).

FMAXNMP (vector): Floating-point Maximum Number

Pairwise (vector).

FMAXP (vector): Floating-point Maximum

Pairwise (vector).

FMINNMP (vector): Floating-point Minimum Number

Pairwise (vector).

FMINP (vector): Floating-point Minimum

Pairwise (vector).

SADALP: Signed Add and Accumulate Long

Pairwise.

SADDLP: Signed Add Long

Pairwise.

SMAXP: Signed Maximum

Pairwise.

SMINP: Signed Minimum

Pairwise.

UADALP: Unsigned Add and Accumulate Long

Pairwise.

UADDLP: Unsigned Add Long

Pairwise.

UMAXP: Unsigned Maximum

Pairwise.

UMINP: Unsigned Minimum

Pairwise.

SHA1P: SHA1 hash update (

parity).

SHA256H: SHA256 hash update (

part 1).

SHA256H2: SHA256 hash update (

part 2).

ADRP: Form

PC-relative address to 4KB page.

ADR: Form

PC-relative address.

LDR (literal, SIMD&FP): Load SIMD&FP Register (

PC-relative literal).

DCPS1: Debug Change

PE State to EL1..

DCPS2: Debug Change

PE State to EL2..

DCPS3: Debug Change

PE State to EL3.

CNT: Population Count

per byte.

FCVTPS (scalar): Floating-point Convert to Signed integer, rounding toward

Plus infinity (scalar).

FCVTPU (scalar): Floating-point Convert to Unsigned integer, rounding toward

Plus infinity (scalar).

FRINTP (scalar): Floating-point Round to Integral, toward

Plus infinity (scalar).

FCVTPS (vector): Floating-point Convert to Signed integer, rounding toward

Plus infinity (vector).

FCVTPU (vector): Floating-point Convert to Unsigned integer, rounding toward

Plus infinity (vector).

FRINTP (vector): Floating-point Round to Integral, toward

Plus infinity (vector).

PMUL: Polynomial Multiply.

PMULL, PMULL2: Polynomial Multiply Long.

PMULL,

PMULL2: Polynomial Multiply Long.

SCVTF (scalar, fixed-point): Signed fixed-point Convert to Floating-

point (scalar).

SCVTF (scalar, integer): Signed integer Convert to Floating-

point (scalar).

UCVTF (scalar, fixed-point): Unsigned fixed-point Convert to Floating-

point (scalar).

UCVTF (scalar, integer): Unsigned integer Convert to Floating-

point (scalar).

SCVTF (vector, fixed-point): Signed fixed-point Convert to Floating-

point (vector).

SCVTF (vector, integer): Signed integer Convert to Floating-

point (vector).

UCVTF (vector, fixed-point): Unsigned fixed-point Convert to Floating-

point (vector).

UCVTF (vector, integer): Unsigned integer Convert to Floating-

point (vector).

FACGT: Floating-

point Absolute Compare Greater than (vector).

FACGE: Floating-

point Absolute Compare Greater than or Equal (vector).

FABD: Floating-

point Absolute Difference (vector).

FABS (scalar): Floating-

point Absolute value (scalar).

FABS (vector): Floating-

point Absolute value (vector).

FADD (scalar): Floating-

point Add (scalar).

FADD (vector): Floating-

point Add (vector).

FADDP (scalar): Floating-

point Add Pair of elements (scalar).

FADDP (vector): Floating-

point Add Pairwise (vector).

FCMEQ (register): Floating-

point Compare Equal (vector).

FCMEQ (zero): Floating-

point Compare Equal to zero (vector).

FCMGT (register): Floating-

point Compare Greater than (vector).

FCMGE (register): Floating-

point Compare Greater than or Equal (vector).

FCMGE (zero): Floating-

point Compare Greater than or Equal to zero (vector).

FCMGT (zero): Floating-

point Compare Greater than zero (vector).

FCMLE (zero): Floating-

point Compare Less than or Equal to zero (vector).

FCMLT (zero): Floating-

point Compare Less than zero (vector).

FCCMP: Floating-

point Conditional quiet Compare (scalar).

FCSEL: Floating-

point Conditional Select (scalar).

FCCMPE: Floating-

point Conditional signaling Compare (scalar).

FCVT: Floating-

point Convert precision (scalar).

point Convert to Floating-point (scalar).

point Convert to Floating-point (scalar).

SCVTF (vector, fixed-point): Signed fixed-

point Convert to Floating-point (vector).

UCVTF (vector, fixed-point): Unsigned fixed-

point Convert to Floating-point (vector).

FCVTL, FCVTL2: Floating-

point Convert to higher precision Long (vector).

FCVTN, FCVTN2: Floating-

point Convert to lower precision Narrow (vector).

FCVTXN, FCVTXN2: Floating-

point Convert to lower precision Narrow, rounding to odd (vector).

point Convert to Signed fixed-point, rounding toward Zero (scalar).

FCVTZS (vector, fixed-point): Floating-

point Convert to Signed fixed-point, rounding toward Zero (vector).

FCVTAS (scalar): Floating-

point Convert to Signed integer, rounding to nearest with ties to Away (scalar).

FCVTAS (vector): Floating-

point Convert to Signed integer, rounding to nearest with ties to Away (vector).

FCVTNS (scalar): Floating-

point Convert to Signed integer, rounding to nearest with ties to even (scalar).

FCVTNS (vector): Floating-

point Convert to Signed integer, rounding to nearest with ties to even (vector).

FCVTMS (scalar): Floating-

point Convert to Signed integer, rounding toward Minus infinity (scalar).

FCVTMS (vector): Floating-

point Convert to Signed integer, rounding toward Minus infinity (vector).

FCVTPS (scalar): Floating-

point Convert to Signed integer, rounding toward Plus infinity (scalar).

FCVTPS (vector): Floating-

point Convert to Signed integer, rounding toward Plus infinity (vector).

point Convert to Signed integer, rounding toward Zero (scalar).

FCVTZS (vector, integer): Floating-

point Convert to Signed integer, rounding toward Zero (vector).

point Convert to Unsigned fixed-point, rounding toward Zero (scalar).

FCVTZU (vector, fixed-point): Floating-

point Convert to Unsigned fixed-point, rounding toward Zero (vector).

FCVTAU (scalar): Floating-

point Convert to Unsigned integer, rounding to nearest with ties to Away (scalar).

FCVTAU (vector): Floating-

point Convert to Unsigned integer, rounding to nearest with ties to Away (vector).

FCVTNU (scalar): Floating-

point Convert to Unsigned integer, rounding to nearest with ties to even (scalar).

FCVTNU (vector): Floating-

point Convert to Unsigned integer, rounding to nearest with ties to even (vector).

FCVTMU (scalar): Floating-

point Convert to Unsigned integer, rounding toward Minus infinity (scalar).

FCVTMU (vector): Floating-

point Convert to Unsigned integer, rounding toward Minus infinity (vector).

FCVTPU (scalar): Floating-

point Convert to Unsigned integer, rounding toward Plus infinity (scalar).

FCVTPU (vector): Floating-

point Convert to Unsigned integer, rounding toward Plus infinity (vector).

point Convert to Unsigned integer, rounding toward Zero (scalar).

FCVTZU (vector, integer): Floating-

point Convert to Unsigned integer, rounding toward Zero (vector).

FDIV (scalar): Floating-

point Divide (scalar).

FDIV (vector): Floating-

point Divide (vector).

FMADD: Floating-

point fused Multiply-Add (scalar).

FMLA (by element): Floating-

point fused Multiply-Add to accumulator (by element).

FMLA (vector): Floating-

point fused Multiply-Add to accumulator (vector).

FMSUB: Floating-

point Fused Multiply-Subtract (scalar).

FMLS (by element): Floating-

point fused Multiply-Subtract from accumulator (by element).

FMLS (vector): Floating-

point fused Multiply-Subtract from accumulator (vector).

FMAX (scalar): Floating-

point Maximum (scalar).

FMAX (vector): Floating-

point Maximum (vector).

FMAXV: Floating-

point Maximum across Vector.

FMAXNM (scalar): Floating-

point Maximum Number (scalar).

FMAXNM (vector): Floating-

point Maximum Number (vector).

FMAXNMV: Floating-

point Maximum Number across Vector.

FMAXNMP (scalar): Floating-

point Maximum Number of Pair of elements (scalar).

FMAXNMP (vector): Floating-

point Maximum Number Pairwise (vector).

FMAXP (scalar): Floating-

point Maximum of Pair of elements (scalar).

FMAXP (vector): Floating-

point Maximum Pairwise (vector).

FMIN (scalar): Floating-

point Minimum (scalar).

FMIN (vector): Floating-

point minimum (vector).

FMINV: Floating-

point Minimum across Vector.

FMINNM (scalar): Floating-

point Minimum Number (scalar).

FMINNM (vector): Floating-

point Minimum Number (vector).

FMINNMV: Floating-

point Minimum Number across Vector.

FMINNMP (scalar): Floating-

point Minimum Number of Pair of elements (scalar).

FMINNMP (vector): Floating-

point Minimum Number Pairwise (vector).

FMINP (scalar): Floating-

point Minimum of Pair of elements (scalar).

FMINP (vector): Floating-

point Minimum Pairwise (vector).

FMOV (scalar, immediate): Floating-

point move immediate (scalar).

point move immediate (vector).

FMOV (register): Floating-

point Move register without conversion.

FMOV (general): Floating-

point Move to or from general-purpose register without conversion.

FMUL (by element): Floating-

point Multiply (by element).

FMUL (scalar): Floating-

point Multiply (scalar).

FMUL (vector): Floating-

point Multiply (vector).

FMULX (by element): Floating-

point Multiply extended (by element).

FMULX: Floating-

point Multiply extended.

FNMUL (scalar): Floating-

point Multiply-Negate (scalar).

FNEG (scalar): Floating-

point Negate (scalar).

FNEG (vector): Floating-

point Negate (vector).

FNMADD: Floating-

point Negated fused Multiply-Add (scalar).

FNMSUB: Floating-

point Negated fused Multiply-Subtract (scalar).

FCMP: Floating-

point quiet Compare (scalar).

FRECPE: Floating-

point Reciprocal Estimate.

FRECPX: Floating-

point Reciprocal exponent (scalar).

FRSQRTE: Floating-

point Reciprocal Square Root Estimate.

FRSQRTS: Floating-

point Reciprocal Square Root Step.

FRECPS: Floating-

point Reciprocal Step.

FRINTX (scalar): Floating-

point Round to Integral exact, using current rounding mode (scalar).

FRINTX (vector): Floating-

point Round to Integral exact, using current rounding mode (vector).

FRINTA (scalar): Floating-

point Round to Integral, to nearest with ties to Away (scalar).

FRINTA (vector): Floating-

point Round to Integral, to nearest with ties to Away (vector).

FRINTN (scalar): Floating-

point Round to Integral, to nearest with ties to even (scalar).

FRINTN (vector): Floating-

point Round to Integral, to nearest with ties to even (vector).

FRINTM (scalar): Floating-

point Round to Integral, toward Minus infinity (scalar).

FRINTM (vector): Floating-

point Round to Integral, toward Minus infinity (vector).

FRINTP (scalar): Floating-

point Round to Integral, toward Plus infinity (scalar).

FRINTP (vector): Floating-

point Round to Integral, toward Plus infinity (vector).

FRINTZ (scalar): Floating-

point Round to Integral, toward Zero (scalar).

FRINTZ (vector): Floating-

point Round to Integral, toward Zero (vector).

FRINTI (scalar): Floating-

point Round to Integral, using current rounding mode (scalar).

FRINTI (vector): Floating-

point Round to Integral, using current rounding mode (vector).

FCMPE: Floating-

point signaling Compare (scalar).

FSQRT (scalar): Floating-

point Square Root (scalar).

FSQRT (vector): Floating-

point Square Root (vector).

FSUB (scalar): Floating-

point Subtract (scalar).

FSUB (vector): Floating-

point Subtract (vector).

point): Floating-point Convert to Signed fixed-point, rounding toward Zero (scalar).

FCVTZS (vector, fixed-

point): Floating-point Convert to Signed fixed-point, rounding toward Zero (vector).

point): Floating-point Convert to Unsigned fixed-point, rounding toward Zero (scalar).

FCVTZU (vector, fixed-

point): Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector).

point): Signed fixed-point Convert to Floating-point (scalar).

SCVTF (vector, fixed-

point): Signed fixed-point Convert to Floating-point (vector).

point): Unsigned fixed-point Convert to Floating-point (scalar).

UCVTF (vector, fixed-

point): Unsigned fixed-point Convert to Floating-point (vector).

FCVTZS (scalar, fixed-point): Floating-point Convert to Signed fixed-

point, rounding toward Zero (scalar).

FCVTZU (scalar, fixed-point): Floating-point Convert to Unsigned fixed-

point, rounding toward Zero (scalar).

FCVTZS (vector, fixed-point): Floating-point Convert to Signed fixed-

point, rounding toward Zero (vector).

FCVTZU (vector, fixed-point): Floating-point Convert to Unsigned fixed-

point, rounding toward Zero (vector).

MOV (to/from SP): Move between register and stack

pointer: an alias of ADD (immediate).

PMULL, PMULL2:

Polynomial Multiply Long.

Polynomial Multiply.

CNT:

Population Count per byte.

FCVT: Floating-point Convert

precision (scalar).

FCVTL, FCVTL2: Floating-point Convert to higher

precision Long (vector).

FCVTN, FCVTN2: Floating-point Convert to lower

precision Narrow (vector).

FCVTXN, FCVTXN2: Floating-point Convert to lower

precision Narrow, rounding to odd (vector).

Prefetch Memory (immediate).

Prefetch Memory (literal).

Prefetch Memory (register).

Prefetch Memory (unscaled offset).

PRFM (immediate): Prefetch Memory (immediate).

PRFM (literal): Prefetch Memory (literal).

PRFM (register): Prefetch Memory (register).

PRFM (unscaled offset): Prefetch Memory (unscaled offset).

TRN1: Transpose vectors (

primary).

UZP1: Unzip vectors (

primary).

ZIP1: Zip vectors (

primary).

DRPS: Debug restore

process state.

Profiling Synchronization Barrier.

PSB CSYNC: Profiling Synchronization Barrier.

MOV (from general): Move general-

purpose register to a vector element: an alias of INS (general).

MSR (register): Move general-

purpose register to System Register.

DUP (general): Duplicate general-

purpose register to vector.

FMOV (general): Floating-point Move to or from general-

purpose register without conversion.

INS (general): Insert vector element from general-

purpose register.

SMOV: Signed Move vector element to general-

purpose register.

UMOV: Unsigned Move vector element to general-

purpose register.

MOV (to general): Move vector element to general-

purpose register: an alias of UMOV.

FCCMP: Floating-point Conditional

FCMP: Floating-point

quiet Compare (scalar).

RADDHN,

RADDHN2: Rounding Add returning High Narrow.

RBIT (vector): Reverse Bit order (vector).

RBIT: Reverse Bits.

FRECPE: Floating-point

Reciprocal Estimate.

URECPE: Unsigned

Reciprocal Estimate.

FRECPX: Floating-point

Reciprocal exponent (scalar).

FRSQRTE: Floating-point

Reciprocal Square Root Estimate.

URSQRTE: Unsigned

Reciprocal Square Root Estimate.

FRSQRTS: Floating-point

Reciprocal Square Root Step.

FRECPS: Floating-point

Reciprocal Step.

Register (immediate offset).

Register (immediate).

Register (immediate).

LDR (literal): Load

Register (literal).

LDR (literal, SIMD&FP): Load SIMD&FP

Register (PC-relative literal).

Register (register offset).

Register (register).

Register (register).

LDTR: Load

Register (unprivileged).

STTR: Store

Register (unprivileged).

LDUR (SIMD&FP): Load SIMD&FP

Register (unscaled offset).

LDUR: Load

Register (unscaled).

STUR: Store

Register (unscaled).

Register Byte (immediate).

Register Byte (immediate).

Register Byte (register).

Register Byte (register).

LDTRB: Load

Register Byte (unprivileged).

STTRB: Store

Register Byte (unprivileged).

LDURB: Load

Register Byte (unscaled).

STURB: Store

Register Byte (unscaled).

LDARB: Load-Acquire

Register Byte.

LDAXRB: Load-Acquire Exclusive

Register Byte.

LDLARB: Load LOAcquire

Register Byte.

LDXRB: Load Exclusive

Register Byte.

STLLRB: Store LORelease

Register Byte.

STLRB: Store-Release

Register Byte.

STLXRB: Store-Release Exclusive

Register Byte.

STXRB: Store Exclusive

Register Byte.

Register Halfword (immediate).

Register Halfword (immediate).

Register Halfword (register).

Register Halfword (register).

LDTRH: Load

Register Halfword (unprivileged).

STTRH: Store

Register Halfword (unprivileged).

LDURH: Load

Register Halfword (unscaled).

STURH: Store

Register Halfword (unscaled).

LDARH: Load-Acquire

Register Halfword.

LDAXRH: Load-Acquire Exclusive

Register Halfword.

LDLARH: Load LOAcquire

Register Halfword.

LDXRH: Load Exclusive

Register Halfword.

STLLRH: Store LORelease

Register Halfword.

STLRH: Store-Release

Register Halfword.

STLXRH: Store-Release Exclusive

Register Halfword.

STXRH: Store Exclusive

Register Halfword.

Register Signed Byte (immediate).

Register Signed Byte (register).

LDTRSB: Load

Register Signed Byte (unprivileged).

LDURSB: Load

Register Signed Byte (unscaled).

Register Signed Halfword (immediate).

Register Signed Halfword (register).

LDTRSH: Load

Register Signed Halfword (unprivileged).

LDURSH: Load

Register Signed Halfword (unscaled).

Register Signed Word (immediate).

Register Signed Word (literal).

Register Signed Word (register).

LDTRSW: Load

Register Signed Word (unprivileged).

LDURSW: Load

Register Signed Word (unscaled).

BLR: Branch with Link to

Register.

BR: Branch to

Register.

LDAR: Load-Acquire

Register.

LDAXR: Load-Acquire Exclusive

Register.

LDLAR: Load LOAcquire

Register.

LDXR: Load Exclusive

Register.

MRS: Move System

Register.

MSR (immediate): Move immediate value to Special

Register.

MSR (register): Move general-purpose register to System

Register.

STLLR: Store LORelease

Register.

STLR: Store-Release

Register.

STLXR: Store-Release Exclusive

Register.

STXR: Store Exclusive

Register.

LDPSW: Load Pair of

Registers Signed Word.

LDNP: Load Pair of

Registers, with non-temporal hint.

STNP: Store Pair of

Registers, with non-temporal hint.

LDAXP: Load-Acquire Exclusive Pair of

Registers.

LDP: Load Pair of

Registers.

LDXP: Load Exclusive Pair of

Registers.

STP: Store Pair of

Registers.

STLXP: Store-

Release Exclusive Pair of registers.

STLXRB: Store-

Release Exclusive Register Byte.

STLXRH: Store-

Release Exclusive Register Halfword.

STLXR: Store-

Release Exclusive Register.

STLLRB: Store LO

Release Register Byte.

STLRB: Store-

Release Register Byte.

STLLRH: Store LO

Release Register Halfword.

STLRH: Store-

Release Register Halfword.

STLLR: Store LO

Release Register.

STLR: Store-

Release Register.

LD1R: Load one single-element structure and

Replicate to all lanes (of one register).

LD4R: Load single 4-element structure and

Replicate to all lanes of four registers.

LD3R: Load single 3-element structure and

Replicate to all lanes of three registers.

LD2R: Load single 2-element structure and

Replicate to all lanes of two registers.

DRPS: Debug

restore process state.

SYSL: System instruction with

result.

RET: Return from subroutine.

RET:

Return from subroutine.

ERET: Exception

Return.

STADD, STADDL: Atomic add on word or doubleword in memory, without

return.

STADDB, STADDLB: Atomic add on byte in memory, without

return.

STADDH, STADDLH: Atomic add on halfword in memory, without

return.

STCLR, STCLRL: Atomic bit clear on word or doubleword in memory, without

return.

STCLRB, STCLRLB: Atomic bit clear on byte in memory, without

return.

STCLRH, STCLRLH: Atomic bit clear on halfword in memory, without

return.

STEOR, STEORL: Atomic exclusive OR on word or doubleword in memory, without

return.

STEORB, STEORLB: Atomic exclusive OR on byte in memory, without

return.

STEORH, STEORLH: Atomic exclusive OR on halfword in memory, without

return.

STSET, STSETL: Atomic bit set on word or doubleword in memory, without

return.

STSETB, STSETLB: Atomic bit set on byte in memory, without

return.

STSETH, STSETLH: Atomic bit set on halfword in memory, without

return.

STSMAX, STSMAXL: Atomic signed maximum on word or doubleword in memory, without

return.

STSMAXB, STSMAXLB: Atomic signed maximum on byte in memory, without

return.

STSMAXH, STSMAXLH: Atomic signed maximum on halfword in memory, without

return.

STSMIN, STSMINL: Atomic signed minimum on word or doubleword in memory, without

return.

STSMINB, STSMINLB: Atomic signed minimum on byte in memory, without

return.

STSMINH, STSMINLH: Atomic signed minimum on halfword in memory, without

return.

STUMAX, STUMAXL: Atomic unsigned maximum on word or doubleword in memory, without

return.

STUMAXB, STUMAXLB: Atomic unsigned maximum on byte in memory, without

return.

STUMAXH, STUMAXLH: Atomic unsigned maximum on halfword in memory, without

return.

STUMIN, STUMINL: Atomic unsigned minimum on word or doubleword in memory, without

return.

STUMINB, STUMINLB: Atomic unsigned minimum on byte in memory, without

return.

STUMINH, STUMINLH: Atomic unsigned minimum on halfword in memory, without

return.

SQDMULH (by element): Signed saturating Doubling Multiply

returning High half (by element).

SQRDMLAH (by element): Signed Saturating Rounding Doubling Multiply Accumulate

returning High Half (by element).

SQRDMLSH (by element): Signed Saturating Rounding Doubling Multiply Subtract

returning High Half (by element).

SQRDMULH (by element): Signed saturating Rounding Doubling Multiply

returning High half (by element).

SQRDMLAH (vector): Signed Saturating Rounding Doubling Multiply Accumulate

returning High Half (vector).

SQRDMLSH (vector): Signed Saturating Rounding Doubling Multiply Subtract

returning High Half (vector).

SQDMULH (vector): Signed saturating Doubling Multiply

returning High half.

SQRDMULH (vector): Signed saturating Rounding Doubling Multiply

returning High half.

ADDHN, ADDHN2: Add

returning High Narrow.

RADDHN, RADDHN2: Rounding Add

returning High Narrow.

RSUBHN, RSUBHN2: Rounding Subtract

returning High Narrow.

SUBHN, SUBHN2: Subtract

returning High Narrow.

REV64: Reverse Bytes: an alias of

REV.

REV16 (vector): Reverse elements in 16-bit halfwords (vector).

REV16: Reverse bytes in 16-bit halfwords.

REV32 (vector): Reverse elements in 32-bit words (vector).

REV32: Reverse bytes in 32-bit words.

REV64: Reverse Bytes: an alias of REV.

REV64: Reverse elements in 64-bit doublewords (vector).

REV: Reverse Bytes.

RBIT (vector):

Reverse Bit order (vector).

RBIT:

Reverse Bits.

Reverse bytes in 16-bit halfwords.

Reverse bytes in 32-bit words.

REV:

Reverse Bytes.

REV64:

Reverse Bytes: an alias of REV.

Reverse elements in 16-bit halfwords (vector).

Reverse elements in 32-bit words (vector).

Reverse elements in 64-bit doublewords (vector).

SRSHR: Signed Rounding Shift

Right (immediate).

SSHR: Signed Shift

Right (immediate).

URSHR: Unsigned Rounding Shift

Right (immediate).

USHR: Unsigned Shift

Right (immediate).

ROR (immediate): Rotate

right (immediate): an alias of EXTR.

ASR (immediate): Arithmetic Shift

Right (immediate): an alias of SBFM.

LSR (immediate): Logical Shift

Right (immediate): an alias of UBFM.

ASR (register): Arithmetic Shift

Right (register): an alias of ASRV.

LSR (register): Logical Shift

Right (register): an alias of LSRV.

ROR (register): Rotate

Right (register): an alias of RORV.

SRSRA: Signed Rounding Shift

Right and Accumulate (immediate).

SSRA: Signed Shift

Right and Accumulate (immediate).

URSRA: Unsigned Rounding Shift

Right and Accumulate (immediate).

USRA: Unsigned Shift

Right and Accumulate (immediate).

SRI: Shift

Right and Insert (immediate).

RSHRN, RSHRN2: Rounding Shift

Right Narrow (immediate).

SHRN, SHRN2: Shift

Right Narrow (immediate).

SQRSHRN, SQRSHRN2: Signed saturating Rounded Shift

Right Narrow (immediate).

SQSHRN, SQSHRN2: Signed saturating Shift

Right Narrow (immediate).

UQRSHRN, UQRSHRN2: Unsigned saturating Rounded Shift

Right Narrow (immediate).

UQSHRN, UQSHRN2: Unsigned saturating Shift

Right Narrow (immediate).

SQRSHRUN, SQRSHRUN2: Signed saturating Rounded Shift

Right Unsigned Narrow (immediate).

SQSHRUN, SQSHRUN2: Signed saturating Shift

Right Unsigned Narrow (immediate).

ASRV: Arithmetic Shift

Right Variable.

LSRV: Logical Shift

Right Variable.

RORV: Rotate

Right Variable.

FSQRT (scalar): Floating-point Square

Root (scalar).

FSQRT (vector): Floating-point Square

Root (vector).

FRSQRTE: Floating-point Reciprocal Square

Root Estimate.

URSQRTE: Unsigned Reciprocal Square

Root Estimate.

FRSQRTS: Floating-point Reciprocal Square

Root Step.

ROR (immediate): Rotate right (immediate): an alias of EXTR.

ROR (register): Rotate Right (register): an alias of RORV.

ROR (register): Rotate Right (register): an alias of

RORV.

RORV: Rotate Right Variable.

ROR (immediate):

Rotate right (immediate): an alias of EXTR.

ROR (register):

Rotate Right (register): an alias of RORV.

RORV:

Rotate Right Variable.

SHA1H: SHA1 fixed

rotate.

AESD: AES single

round decryption.

AESE: AES single

round encryption.

FRINTX (scalar): Floating-point

Round to Integral exact, using current rounding mode (scalar).

FRINTX (vector): Floating-point

Round to Integral exact, using current rounding mode (vector).

FRINTA (scalar): Floating-point

Round to Integral, to nearest with ties to Away (scalar).

FRINTA (vector): Floating-point

Round to Integral, to nearest with ties to Away (vector).

FRINTN (scalar): Floating-point

Round to Integral, to nearest with ties to even (scalar).

FRINTN (vector): Floating-point

Round to Integral, to nearest with ties to even (vector).

FRINTM (scalar): Floating-point

Round to Integral, toward Minus infinity (scalar).

FRINTM (vector): Floating-point

Round to Integral, toward Minus infinity (vector).

FRINTP (scalar): Floating-point

Round to Integral, toward Plus infinity (scalar).

FRINTP (vector): Floating-point

Round to Integral, toward Plus infinity (vector).

FRINTZ (scalar): Floating-point

Round to Integral, toward Zero (scalar).

FRINTZ (vector): Floating-point

Round to Integral, toward Zero (vector).

FRINTI (scalar): Floating-point

Round to Integral, using current rounding mode (scalar).

FRINTI (vector): Floating-point

Round to Integral, using current rounding mode (vector).

SQRSHRN, SQRSHRN2: Signed saturating

Rounded Shift Right Narrow (immediate).

UQRSHRN, UQRSHRN2: Unsigned saturating

Rounded Shift Right Narrow (immediate).

SQRSHRUN, SQRSHRUN2: Signed saturating

Rounded Shift Right Unsigned Narrow (immediate).

RADDHN, RADDHN2:

Rounding Add returning High Narrow.

SQRDMLAH (by element): Signed Saturating

Rounding Doubling Multiply Accumulate returning High Half (by element).

SQRDMLAH (vector): Signed Saturating

Rounding Doubling Multiply Accumulate returning High Half (vector).

SQRDMULH (by element): Signed saturating

Rounding Doubling Multiply returning High half (by element).

SQRDMULH (vector): Signed saturating

Rounding Doubling Multiply returning High half.

SQRDMLSH (by element): Signed Saturating

Rounding Doubling Multiply Subtract returning High Half (by element).

SQRDMLSH (vector): Signed Saturating

Rounding Doubling Multiply Subtract returning High Half (vector).

SRHADD: Signed

Rounding Halving Add.

URHADD: Unsigned

Rounding Halving Add.

FRINTI (scalar): Floating-point Round to Integral, using current

rounding mode (scalar).

FRINTX (scalar): Floating-point Round to Integral exact, using current

rounding mode (scalar).

FRINTI (vector): Floating-point Round to Integral, using current

rounding mode (vector).

FRINTX (vector): Floating-point Round to Integral exact, using current

rounding mode (vector).

SQRSHL: Signed saturating

Rounding Shift Left (register).

SRSHL: Signed

Rounding Shift Left (register).

UQRSHL: Unsigned saturating

Rounding Shift Left (register).

URSHL: Unsigned

Rounding Shift Left (register).

SRSHR: Signed

Rounding Shift Right (immediate).

URSHR: Unsigned

Rounding Shift Right (immediate).

SRSRA: Signed

Rounding Shift Right and Accumulate (immediate).

URSRA: Unsigned

Rounding Shift Right and Accumulate (immediate).

RSHRN, RSHRN2:

Rounding Shift Right Narrow (immediate).

RSUBHN, RSUBHN2:

Rounding Subtract returning High Narrow.

FCVTAS (scalar): Floating-point Convert to Signed integer,

rounding to nearest with ties to Away (scalar).

FCVTAU (scalar): Floating-point Convert to Unsigned integer,

rounding to nearest with ties to Away (scalar).

FCVTAS (vector): Floating-point Convert to Signed integer,

rounding to nearest with ties to Away (vector).

FCVTAU (vector): Floating-point Convert to Unsigned integer,

rounding to nearest with ties to Away (vector).

FCVTNS (scalar): Floating-point Convert to Signed integer,

rounding to nearest with ties to even (scalar).

FCVTNU (scalar): Floating-point Convert to Unsigned integer,

rounding to nearest with ties to even (scalar).

FCVTNS (vector): Floating-point Convert to Signed integer,

rounding to nearest with ties to even (vector).

FCVTNU (vector): Floating-point Convert to Unsigned integer,

rounding to nearest with ties to even (vector).

FCVTXN, FCVTXN2: Floating-point Convert to lower precision Narrow,

rounding to odd (vector).

FCVTMS (scalar): Floating-point Convert to Signed integer,

rounding toward Minus infinity (scalar).

FCVTMU (scalar): Floating-point Convert to Unsigned integer,

rounding toward Minus infinity (scalar).

FCVTMS (vector): Floating-point Convert to Signed integer,

rounding toward Minus infinity (vector).

FCVTMU (vector): Floating-point Convert to Unsigned integer,

rounding toward Minus infinity (vector).

FCVTPS (scalar): Floating-point Convert to Signed integer,

rounding toward Plus infinity (scalar).

FCVTPU (scalar): Floating-point Convert to Unsigned integer,

rounding toward Plus infinity (scalar).

FCVTPS (vector): Floating-point Convert to Signed integer,

rounding toward Plus infinity (vector).

FCVTPU (vector): Floating-point Convert to Unsigned integer,

rounding toward Plus infinity (vector).

FCVTZS (scalar, fixed-point): Floating-point Convert to Signed fixed-point,

rounding toward Zero (scalar).

FCVTZS (scalar, integer): Floating-point Convert to Signed integer,

rounding toward Zero (scalar).

FCVTZU (scalar, fixed-point): Floating-point Convert to Unsigned fixed-point,

rounding toward Zero (scalar).

FCVTZU (scalar, integer): Floating-point Convert to Unsigned integer,

rounding toward Zero (scalar).

FCVTZS (vector, fixed-point): Floating-point Convert to Signed fixed-point,

rounding toward Zero (vector).

FCVTZS (vector, integer): Floating-point Convert to Signed integer,

rounding toward Zero (vector).

FCVTZU (vector, fixed-point): Floating-point Convert to Unsigned fixed-point,

rounding toward Zero (vector).

FCVTZU (vector, integer): Floating-point Convert to Unsigned integer,

rounding toward Zero (vector).

RSHRN, RSHRN2: Rounding Shift Right Narrow (immediate).

RSHRN,

RSHRN2: Rounding Shift Right Narrow (immediate).

RSUBHN, RSUBHN2: Rounding Subtract returning High Narrow.

RSUBHN,

RSUBHN2: Rounding Subtract returning High Narrow.

SABA: Signed Absolute difference and Accumulate.

SABAL, SABAL2: Signed Absolute difference and Accumulate Long.

SABAL2: Signed Absolute difference and Accumulate Long.

SABD: Signed Absolute Difference.

SABDL, SABDL2: Signed Absolute Difference Long.

SABDL2: Signed Absolute Difference Long.

SADALP: Signed Add and Accumulate Long Pairwise.

SADDL, SADDL2: Signed Add Long (vector).

SADDL,

SADDL2: Signed Add Long (vector).

SADDLP: Signed Add Long Pairwise.

SADDLV: Signed Add Long across Vector.

SADDW, SADDW2: Signed Add Wide.

SADDW,

SADDW2: Signed Add Wide.

CMHS (register): Compare unsigned Higher or

Same (vector).

SQABS: Signed

saturating Absolute value.

USQADD: Unsigned

saturating Accumulate of Signed value.

SUQADD: Signed

saturating Accumulate of Unsigned value.

SQADD: Signed

saturating Add.

UQADD: Unsigned

saturating Add.

saturating Doubling Multiply Long (by element).

saturating Doubling Multiply Long.

SQDMULH (by element): Signed

saturating Doubling Multiply returning High half (by element).

SQDMULH (vector): Signed

saturating Doubling Multiply returning High half.

saturating Doubling Multiply-Add Long (by element).

saturating Doubling Multiply-Add Long.

saturating Doubling Multiply-Subtract Long (by element).

saturating Doubling Multiply-Subtract Long.

SQXTN, SQXTN2: Signed

saturating extract Narrow.

UQXTN, UQXTN2: Unsigned

saturating extract Narrow.

SQXTUN, SQXTUN2: Signed

saturating extract Unsigned Narrow.

SQNEG: Signed

saturating Negate.

SQRSHRN, SQRSHRN2: Signed

saturating Rounded Shift Right Narrow (immediate).

UQRSHRN, UQRSHRN2: Unsigned

saturating Rounded Shift Right Narrow (immediate).

SQRSHRUN, SQRSHRUN2: Signed

saturating Rounded Shift Right Unsigned Narrow (immediate).

SQRDMLAH (by element): Signed

Saturating Rounding Doubling Multiply Accumulate returning High Half (by element).

SQRDMLAH (vector): Signed

Saturating Rounding Doubling Multiply Accumulate returning High Half (vector).

SQRDMULH (by element): Signed

saturating Rounding Doubling Multiply returning High half (by element).

SQRDMULH (vector): Signed

saturating Rounding Doubling Multiply returning High half.

SQRDMLSH (by element): Signed

Saturating Rounding Doubling Multiply Subtract returning High Half (by element).

SQRDMLSH (vector): Signed

Saturating Rounding Doubling Multiply Subtract returning High Half (vector).

SQRSHL: Signed

saturating Rounding Shift Left (register).

UQRSHL: Unsigned

saturating Rounding Shift Left (register).

SQSHL (immediate): Signed

saturating Shift Left (immediate).

UQSHL (immediate): Unsigned

saturating Shift Left (immediate).

SQSHL (register): Signed

saturating Shift Left (register).

UQSHL (register): Unsigned

saturating Shift Left (register).

SQSHLU: Signed

saturating Shift Left Unsigned (immediate).

SQSHRN, SQSHRN2: Signed

saturating Shift Right Narrow (immediate).

UQSHRN, UQSHRN2: Unsigned

saturating Shift Right Narrow (immediate).

SQSHRUN, SQSHRUN2: Signed

saturating Shift Right Unsigned Narrow (immediate).

SQSUB: Signed

saturating Subtract.

UQSUB: Unsigned

saturating Subtract.

NGC: Negate with Carry: an alias of

SBC.

SBC: Subtract with Carry.

NGCS: Negate with Carry, setting flags: an alias of

SBCS.

SBCS: Subtract with Carry, setting flags.

SBFIZ: Signed Bitfield Insert in Zero: an alias of SBFM.

ASR (immediate): Arithmetic Shift Right (immediate): an alias of

SBFM.

SBFIZ: Signed Bitfield Insert in Zero: an alias of

SBFM.

SBFX: Signed Bitfield Extract: an alias of

SBFM.

SXTB: Signed Extend Byte: an alias of

SBFM.

SXTH: Sign Extend Halfword: an alias of

SBFM.

SXTW: Sign Extend Word: an alias of

SBFM.

SBFM: Signed Bitfield Move.

SBFX: Signed Bitfield Extract: an alias of SBFM.

ADDP (scalar): Add Pair of elements (

scalar).

FABS (scalar): Floating-point Absolute value (

scalar).

FADD (scalar): Floating-point Add (

scalar).

FADDP (scalar): Floating-point Add Pair of elements (

scalar).

FCCMP: Floating-point Conditional quiet Compare (

scalar).

FCCMPE: Floating-point Conditional signaling Compare (

scalar).

FCMP: Floating-point quiet Compare (

scalar).

FCMPE: Floating-point signaling Compare (

scalar).

FCSEL: Floating-point Conditional Select (

scalar).

FCVT: Floating-point Convert precision (

scalar).

FCVTAS (scalar): Floating-point Convert to Signed integer, rounding to nearest with ties to Away (

scalar).

FCVTAU (scalar): Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (

scalar).

FCVTMS (scalar): Floating-point Convert to Signed integer, rounding toward Minus infinity (

scalar).

FCVTMU (scalar): Floating-point Convert to Unsigned integer, rounding toward Minus infinity (

scalar).

FCVTNS (scalar): Floating-point Convert to Signed integer, rounding to nearest with ties to even (

scalar).

FCVTNU (scalar): Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (

scalar).

FCVTPS (scalar): Floating-point Convert to Signed integer, rounding toward Plus infinity (

scalar).

FCVTPU (scalar): Floating-point Convert to Unsigned integer, rounding toward Plus infinity (

scalar).

FCVTZS (scalar, fixed-point): Floating-point Convert to Signed fixed-point, rounding toward Zero (

scalar).

FCVTZS (scalar, integer): Floating-point Convert to Signed integer, rounding toward Zero (

scalar).

FCVTZU (scalar, fixed-point): Floating-point Convert to Unsigned fixed-point, rounding toward Zero (

scalar).

FCVTZU (scalar, integer): Floating-point Convert to Unsigned integer, rounding toward Zero (

scalar).

FDIV (scalar): Floating-point Divide (

scalar).

FMADD: Floating-point fused Multiply-Add (

scalar).

FMAX (scalar): Floating-point Maximum (

scalar).

FMAXNM (scalar): Floating-point Maximum Number (

scalar).

FMAXNMP (scalar): Floating-point Maximum Number of Pair of elements (

scalar).

FMAXP (scalar): Floating-point Maximum of Pair of elements (

scalar).

FMIN (scalar): Floating-point Minimum (

scalar).

FMINNM (scalar): Floating-point Minimum Number (

scalar).

FMINNMP (scalar): Floating-point Minimum Number of Pair of elements (

scalar).

FMINP (scalar): Floating-point Minimum of Pair of elements (

scalar).

FMOV (scalar, immediate): Floating-point move immediate (

scalar).

FMSUB: Floating-point Fused Multiply-Subtract (

scalar).

FMUL (scalar): Floating-point Multiply (

scalar).

FNEG (scalar): Floating-point Negate (

scalar).

FNMADD: Floating-point Negated fused Multiply-Add (

scalar).

FNMSUB: Floating-point Negated fused Multiply-Subtract (

scalar).

FNMUL (scalar): Floating-point Multiply-Negate (

scalar).

FRECPX: Floating-point Reciprocal exponent (

scalar).

FRINTA (scalar): Floating-point Round to Integral, to nearest with ties to Away (

scalar).

FRINTI (scalar): Floating-point Round to Integral, using current rounding mode (

scalar).

FRINTM (scalar): Floating-point Round to Integral, toward Minus infinity (

scalar).

FRINTN (scalar): Floating-point Round to Integral, to nearest with ties to even (

scalar).

FRINTP (scalar): Floating-point Round to Integral, toward Plus infinity (

scalar).

FRINTX (scalar): Floating-point Round to Integral exact, using current rounding mode (

scalar).

FRINTZ (scalar): Floating-point Round to Integral, toward Zero (

scalar).

FSQRT (scalar): Floating-point Square Root (

scalar).

FSUB (scalar): Floating-point Subtract (

scalar).

SCVTF (scalar, fixed-point): Signed fixed-point Convert to Floating-point (

scalar).

SCVTF (scalar, integer): Signed integer Convert to Floating-point (

scalar).

UCVTF (scalar, fixed-point): Unsigned fixed-point Convert to Floating-point (

scalar).

UCVTF (scalar, integer): Unsigned integer Convert to Floating-point (

scalar).

ADDP (

scalar): Add Pair of elements (scalar).

scalar): Floating-point Absolute value (scalar).

scalar): Floating-point Add (scalar).

scalar): Floating-point Add Pair of elements (scalar).

scalar): Floating-point Convert to Signed integer, rounding to nearest with ties to Away (scalar).

scalar): Floating-point Convert to Signed integer, rounding to nearest with ties to even (scalar).

scalar): Floating-point Convert to Signed integer, rounding toward Minus infinity (scalar).

scalar): Floating-point Convert to Signed integer, rounding toward Plus infinity (scalar).

scalar): Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (scalar).

scalar): Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (scalar).

scalar): Floating-point Convert to Unsigned integer, rounding toward Minus infinity (scalar).

scalar): Floating-point Convert to Unsigned integer, rounding toward Plus infinity (scalar).

FDIV (

scalar): Floating-point Divide (scalar).

scalar): Floating-point Maximum (scalar).

scalar): Floating-point Maximum Number (scalar).

scalar): Floating-point Maximum Number of Pair of elements (scalar).

scalar): Floating-point Maximum of Pair of elements (scalar).

scalar): Floating-point Minimum (scalar).

scalar): Floating-point Minimum Number (scalar).

scalar): Floating-point Minimum Number of Pair of elements (scalar).

scalar): Floating-point Minimum of Pair of elements (scalar).

scalar): Floating-point Multiply (scalar).

scalar): Floating-point Multiply-Negate (scalar).

scalar): Floating-point Negate (scalar).

scalar): Floating-point Round to Integral exact, using current rounding mode (scalar).

scalar): Floating-point Round to Integral, to nearest with ties to Away (scalar).

scalar): Floating-point Round to Integral, to nearest with ties to even (scalar).

scalar): Floating-point Round to Integral, toward Minus infinity (scalar).

scalar): Floating-point Round to Integral, toward Plus infinity (scalar).

scalar): Floating-point Round to Integral, toward Zero (scalar).

scalar): Floating-point Round to Integral, using current rounding mode (scalar).

scalar): Floating-point Square Root (scalar).

scalar): Floating-point Subtract (scalar).

MOV (

scalar): Move vector element to scalar: an alias of DUP (element).

scalar, fixed-point): Floating-point Convert to Signed fixed-point, rounding toward Zero (scalar).

scalar, fixed-point): Floating-point Convert to Unsigned fixed-point, rounding toward Zero (scalar).

scalar, fixed-point): Signed fixed-point Convert to Floating-point (scalar).

scalar, fixed-point): Unsigned fixed-point Convert to Floating-point (scalar).

FMOV (

scalar, immediate): Floating-point move immediate (scalar).

scalar, integer): Floating-point Convert to Signed integer, rounding toward Zero (scalar).

scalar, integer): Floating-point Convert to Unsigned integer, rounding toward Zero (scalar).

scalar, integer): Signed integer Convert to Floating-point (scalar).

scalar, integer): Unsigned integer Convert to Floating-point (scalar).

DUP (element): Duplicate vector element to vector or

scalar.

MOV (scalar): Move vector element to

scalar: an alias of DUP (element).

SHA1SU0: SHA1

schedule update 0.

SHA256SU0: SHA256

schedule update 0.

SHA1SU1: SHA1

schedule update 1.

SHA256SU1: SHA256

schedule update 1.

SCVTF (scalar, fixed-point): Signed fixed-point Convert to Floating-point (scalar).

SCVTF (scalar, integer): Signed integer Convert to Floating-point (scalar).

SCVTF (vector, fixed-point): Signed fixed-point Convert to Floating-point (vector).

SCVTF (vector, integer): Signed integer Convert to Floating-point (vector).

SDIV: Signed Divide.

TRN2: Transpose vectors (

secondary).

UZP2: Unzip vectors (

secondary).

ZIP2: Zip vectors (

secondary).

SMC:

Secure Monitor Call.

FCSEL: Floating-point Conditional

Select (scalar).

CSINC: Conditional

Select Increment.

CSINV: Conditional

Select Invert.

CSNEG: Conditional

Select Negation.

BSL: Bitwise

Select.

CSEL: Conditional

Select.

Send Event Local.

SEV:

Send Event.

CSETM: Conditional

Set Mask: an alias of CSINV.

STSETB, STSETLB: Atomic bit

set on byte in memory, without return.

set on byte in memory.

STSETH, STSETLH: Atomic bit

set on halfword in memory, without return.

set on halfword in memory.

STSET, STSETL: Atomic bit

set on word or doubleword in memory, without return.

set on word or doubleword in memory.

CSET: Conditional

Set: an alias of CSINC.

SEV: Send Event.

SEVL: Send Event Local.

SHA1H:

SHA1 fixed rotate.

SHA1 hash update (choose).

SHA1 hash update (majority).

SHA1 hash update (parity).

SHA1 schedule update 0.

SHA1SU1:

SHA1 schedule update 1.

SHA1C: SHA1 hash update (choose).

SHA1H: SHA1 fixed rotate.

SHA1M: SHA1 hash update (majority).

SHA1P: SHA1 hash update (parity).

SHA1SU0: SHA1 schedule update 0.

SHA1SU1: SHA1 schedule update 1.

SHA256 hash update (part 1).

SHA256 hash update (part 2).

SHA256 schedule update 0.

SHA256 schedule update 1.

SHA256H2: SHA256 hash update (part 2).

SHA256H: SHA256 hash update (part 1).

SHA256SU0: SHA256 schedule update 0.

SHA256SU1: SHA256 schedule update 1.

SHADD: Signed Halving Add.

SHL:

Shift Left (immediate).

SQSHL (immediate): Signed saturating

Shift Left (immediate).

UQSHL (immediate): Unsigned saturating

Shift Left (immediate).

LSL (immediate): Logical

Shift Left (immediate): an alias of UBFM.

SQRSHL: Signed saturating Rounding

Shift Left (register).

SQSHL (register): Signed saturating

Shift Left (register).

SRSHL: Signed Rounding

Shift Left (register).

SSHL: Signed

Shift Left (register).

UQRSHL: Unsigned saturating Rounding

Shift Left (register).

UQSHL (register): Unsigned saturating

Shift Left (register).

URSHL: Unsigned Rounding

Shift Left (register).

USHL: Unsigned

Shift Left (register).

LSL (register): Logical

Shift Left (register): an alias of LSLV.

SLI:

Shift Left and Insert (immediate).

SHLL, SHLL2:

Shift Left Long (by element size).

SSHLL, SSHLL2: Signed

Shift Left Long (immediate).

USHLL, USHLL2: Unsigned

Shift Left Long (immediate).

SQSHLU: Signed saturating

Shift Left Unsigned (immediate).

LSLV: Logical

Shift Left Variable.

SRSHR: Signed Rounding

Shift Right (immediate).

SSHR: Signed

Shift Right (immediate).

URSHR: Unsigned Rounding

Shift Right (immediate).

USHR: Unsigned

Shift Right (immediate).

ASR (immediate): Arithmetic

Shift Right (immediate): an alias of SBFM.

LSR (immediate): Logical

Shift Right (immediate): an alias of UBFM.

ASR (register): Arithmetic

Shift Right (register): an alias of ASRV.

LSR (register): Logical

Shift Right (register): an alias of LSRV.

SRSRA: Signed Rounding

Shift Right and Accumulate (immediate).

SSRA: Signed

Shift Right and Accumulate (immediate).

URSRA: Unsigned Rounding

Shift Right and Accumulate (immediate).

USRA: Unsigned

Shift Right and Accumulate (immediate).

SRI:

Shift Right and Insert (immediate).

RSHRN, RSHRN2: Rounding

Shift Right Narrow (immediate).

SHRN, SHRN2:

Shift Right Narrow (immediate).

SQRSHRN, SQRSHRN2: Signed saturating Rounded

Shift Right Narrow (immediate).

SQSHRN, SQSHRN2: Signed saturating

Shift Right Narrow (immediate).

UQRSHRN, UQRSHRN2: Unsigned saturating Rounded

Shift Right Narrow (immediate).

UQSHRN, UQSHRN2: Unsigned saturating

Shift Right Narrow (immediate).

SQRSHRUN, SQRSHRUN2: Signed saturating Rounded

Shift Right Unsigned Narrow (immediate).

SQSHRUN, SQSHRUN2: Signed saturating

Shift Right Unsigned Narrow (immediate).

ASRV: Arithmetic

Shift Right Variable.

LSRV: Logical

Shift Right Variable.

shifted register), setting flags.

shifted register), setting flags.

BICS (shifted register): Bitwise Bit Clear (

shifted register), setting flags.

shifted register), setting flags.

shifted register).

AND (shifted register): Bitwise AND (

shifted register).

BIC (shifted register): Bitwise Bit Clear (

shifted register).

CMN (shifted register): Compare Negative (shifted register): an alias of ADDS (

shifted register).

CMP (shifted register): Compare (shifted register): an alias of SUBS (

shifted register).

EON (shifted register): Bitwise Exclusive OR NOT (

shifted register).

EOR (shifted register): Bitwise Exclusive OR (

shifted register).

MOV (register): Move (register): an alias of ORR (

shifted register).

MVN: Bitwise NOT: an alias of ORN (

shifted register).

NEG (shifted register): Negate (shifted register): an alias of SUB (

shifted register).

NEGS: Negate, setting flags: an alias of SUBS (

shifted register).

ORN (shifted register): Bitwise OR NOT (

shifted register).

shifted register).

shifted register).

TST (shifted register): Test (shifted register): an alias of ANDS (

shifted register).

shifted register): Add (shifted register), setting flags.

shifted register): Add (shifted register).

CMN (shifted register): Compare Negative (

shifted register): an alias of ADDS (shifted register).

TST (shifted register): Test (

shifted register): an alias of ANDS (shifted register).

NEG (shifted register): Negate (

shifted register): an alias of SUB (shifted register).

CMP (shifted register): Compare (

shifted register): an alias of SUBS (shifted register).

shifted register): Bitwise AND (shifted register), setting flags.

shifted register): Bitwise AND (shifted register).

shifted register): Bitwise Bit Clear (shifted register), setting flags.

shifted register): Bitwise Bit Clear (shifted register).

shifted register): Bitwise Exclusive OR (shifted register).

shifted register): Bitwise Exclusive OR NOT (shifted register).

shifted register): Bitwise OR (shifted register).

shifted register): Bitwise OR NOT (shifted register).

CMP (

shifted register): Compare (shifted register): an alias of SUBS (shifted register).

CMN (

shifted register): Compare Negative (shifted register): an alias of ADDS (shifted register).

NEG (

shifted register): Negate (shifted register): an alias of SUB (shifted register).

shifted register): Subtract (shifted register), setting flags.

shifted register): Subtract (shifted register).

TST (

shifted register): Test (shifted register): an alias of ANDS (shifted register).

SHL: Shift Left (immediate).

SHLL, SHLL2: Shift Left Long (by element size).

SHLL,

SHLL2: Shift Left Long (by element size).

SHRN, SHRN2: Shift Right Narrow (immediate).

SHRN,

SHRN2: Shift Right Narrow (immediate).

SHSUB: Signed Halving Subtract.

CLS (vector): Count Leading

Sign bits (vector).

CLS: Count leading

sign bits.

SXTH:

Sign Extend Halfword: an alias of SBFM.

SXTW:

Sign Extend Word: an alias of SBFM.

FCCMPE: Floating-point Conditional

signaling Compare (scalar).

FCMPE: Floating-point

signaling Compare (scalar).

Signed Absolute difference and Accumulate Long.

Signed Absolute difference and Accumulate.

Signed Absolute Difference Long.

Signed Absolute Difference.

Signed Add and Accumulate Long Pairwise.

SADDL, SADDL2:

Signed Add Long (vector).

SADDLV:

Signed Add Long across Vector.

Signed Add Long Pairwise.

SADDW, SADDW2:

Signed Add Wide.

SBFX:

Signed Bitfield Extract: an alias of SBFM.

SBFIZ:

Signed Bitfield Insert in Zero: an alias of SBFM.

Signed Bitfield Move.

LDRSB (immediate): Load Register

Signed Byte (immediate).

LDRSB (register): Load Register

Signed Byte (register).

LDTRSB: Load Register

Signed Byte (unprivileged).

LDURSB: Load Register

Signed Byte (unscaled).

Signed Divide.

SXTB:

Signed Extend Byte: an alias of SBFM.

SXTL, SXTL2:

Signed extend Long: an alias of SSHLL, SSHLL2.

Signed fixed-point Convert to Floating-point (scalar).

SCVTF (vector, fixed-point):

Signed fixed-point Convert to Floating-point (vector).

FCVTZS (scalar, fixed-point): Floating-point Convert to

Signed fixed-point, rounding toward Zero (scalar).

FCVTZS (vector, fixed-point): Floating-point Convert to

Signed fixed-point, rounding toward Zero (vector).

CMGT (register): Compare

signed Greater than (vector).

CMGE (register): Compare

signed Greater than or Equal (vector).

CMGE (zero): Compare

signed Greater than or Equal to zero (vector).

CMGT (zero): Compare

signed Greater than zero (vector).

LDRSH (immediate): Load Register

Signed Halfword (immediate).

LDRSH (register): Load Register

Signed Halfword (register).

LDTRSH: Load Register

Signed Halfword (unprivileged).

LDURSH: Load Register

Signed Halfword (unscaled).

SHADD:

Signed Halving Add.

SHSUB:

Signed Halving Subtract.

Signed integer Convert to Floating-point (scalar).

SCVTF (vector, integer):

Signed integer Convert to Floating-point (vector).

FCVTAS (scalar): Floating-point Convert to

Signed integer, rounding to nearest with ties to Away (scalar).

FCVTAS (vector): Floating-point Convert to

Signed integer, rounding to nearest with ties to Away (vector).

FCVTNS (scalar): Floating-point Convert to

Signed integer, rounding to nearest with ties to even (scalar).

FCVTNS (vector): Floating-point Convert to

Signed integer, rounding to nearest with ties to even (vector).

FCVTMS (scalar): Floating-point Convert to

Signed integer, rounding toward Minus infinity (scalar).

FCVTMS (vector): Floating-point Convert to

Signed integer, rounding toward Minus infinity (vector).

FCVTPS (scalar): Floating-point Convert to

Signed integer, rounding toward Plus infinity (scalar).

FCVTPS (vector): Floating-point Convert to

Signed integer, rounding toward Plus infinity (vector).

FCVTZS (scalar, integer): Floating-point Convert to

Signed integer, rounding toward Zero (scalar).

FCVTZS (vector, integer): Floating-point Convert to

Signed integer, rounding toward Zero (vector).

CMLE (zero): Compare

signed Less than or Equal to zero (vector).

CMLT (zero): Compare

signed Less than zero (vector).

SMAX:

Signed Maximum (vector).

SMAXV:

Signed Maximum across Vector.

signed maximum on byte in memory, without return.

signed maximum on byte in memory.

signed maximum on halfword in memory, without return.

signed maximum on halfword in memory.

signed maximum on word or doubleword in memory, without return.

signed maximum on word or doubleword in memory.

SMAXP:

Signed Maximum Pairwise.

SMIN:

Signed Minimum (vector).

SMINV:

Signed Minimum across Vector.

signed minimum on byte in memory, without return.

signed minimum on byte in memory.

signed minimum on halfword in memory, without return.

signed minimum on halfword in memory.

signed minimum on word or doubleword in memory, without return.

signed minimum on word or doubleword in memory.

SMINP:

Signed Minimum Pairwise.

SMOV:

Signed Move vector element to general-purpose register.

Signed Multiply High.

Signed Multiply Long (vector).

Signed Multiply Long (vector, by element).

SMULL:

Signed Multiply Long: an alias of SMADDL.

Signed Multiply-Add Long (vector).

Signed Multiply-Add Long (vector, by element).

Signed Multiply-Add Long.

SMNEGL:

Signed Multiply-Negate Long: an alias of SMSUBL.

Signed Multiply-Subtract Long (vector).

Signed Multiply-Subtract Long (vector, by element).

Signed Multiply-Subtract Long.

Signed Rounding Halving Add.

SRSHL:

Signed Rounding Shift Left (register).

SRSHR:

Signed Rounding Shift Right (immediate).

SRSRA:

Signed Rounding Shift Right and Accumulate (immediate).

SQABS:

Signed saturating Absolute value.

SUQADD:

Signed saturating Accumulate of Unsigned value.

SQADD:

Signed saturating Add.

Signed saturating Doubling Multiply Long (by element).

Signed saturating Doubling Multiply Long.

SQDMULH (by element):

Signed saturating Doubling Multiply returning High half (by element).

SQDMULH (vector):

Signed saturating Doubling Multiply returning High half.

Signed saturating Doubling Multiply-Add Long (by element).

Signed saturating Doubling Multiply-Add Long.

Signed saturating Doubling Multiply-Subtract Long (by element).

Signed saturating Doubling Multiply-Subtract Long.

SQXTN, SQXTN2:

Signed saturating extract Narrow.

SQXTUN, SQXTUN2:

Signed saturating extract Unsigned Narrow.

SQNEG:

Signed saturating Negate.

SQRSHRN, SQRSHRN2:

Signed saturating Rounded Shift Right Narrow (immediate).

SQRSHRUN, SQRSHRUN2:

Signed saturating Rounded Shift Right Unsigned Narrow (immediate).

SQRDMLAH (by element):

Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element).

SQRDMLAH (vector):

Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (vector).

SQRDMULH (by element):

Signed saturating Rounding Doubling Multiply returning High half (by element).

SQRDMULH (vector):

Signed saturating Rounding Doubling Multiply returning High half.

SQRDMLSH (by element):

Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element).

SQRDMLSH (vector):

Signed Saturating Rounding Doubling Multiply Subtract returning High Half (vector).

SQRSHL:

Signed saturating Rounding Shift Left (register).

SQSHL (immediate):

Signed saturating Shift Left (immediate).

SQSHL (register):

Signed saturating Shift Left (register).

SQSHLU:

Signed saturating Shift Left Unsigned (immediate).

SQSHRN, SQSHRN2:

Signed saturating Shift Right Narrow (immediate).

SQSHRUN, SQSHRUN2:

Signed saturating Shift Right Unsigned Narrow (immediate).

SQSUB:

Signed saturating Subtract.

SSHL:

Signed Shift Left (register).

SSHLL, SSHLL2:

Signed Shift Left Long (immediate).

SSHR:

Signed Shift Right (immediate).

SSRA:

Signed Shift Right and Accumulate (immediate).

SSUBL, SSUBL2:

Signed Subtract Long.

SSUBW, SSUBW2:

Signed Subtract Wide.

USQADD: Unsigned saturating Accumulate of

Signed value.

LDRSW (immediate): Load Register

Signed Word (immediate).

LDRSW (literal): Load Register

Signed Word (literal).

LDRSW (register): Load Register

Signed Word (register).

LDTRSW: Load Register

Signed Word (unprivileged).

LDURSW: Load Register

Signed Word (unscaled).

LDPSW: Load Pair of Registers

Signed Word.

SIMD&FP Register (immediate offset).

SIMD&FP register (immediate offset).

LDR (literal, SIMD&FP): Load

SIMD&FP Register (PC-relative literal).

SIMD&FP Register (register offset).

SIMD&FP register (register offset).

SIMD&FP Register (unscaled offset).

SIMD&FP register (unscaled offset).

LDNP (SIMD&FP): Load Pair of

SIMD&FP registers, with Non-temporal hint.

STNP (SIMD&FP): Store Pair of

SIMD&FP registers, with Non-temporal hint.

LDP (SIMD&FP): Load Pair of

SIMD&FP registers.

STP (SIMD&FP): Store Pair of

SIMD&FP registers.

SIMD&FP): Load Pair of SIMD&FP registers, with Non-temporal hint.

SIMD&FP): Load Pair of SIMD&FP registers.

SIMD&FP): Load SIMD&FP Register (immediate offset).

LDR (literal,

SIMD&FP): Load SIMD&FP Register (PC-relative literal).

SIMD&FP): Load SIMD&FP Register (register offset).

SIMD&FP): Load SIMD&FP Register (unscaled offset).

SIMD&FP): Store Pair of SIMD&FP registers, with Non-temporal hint.

SIMD&FP): Store Pair of SIMD&FP registers.

SIMD&FP): Store SIMD&FP register (immediate offset).

SIMD&FP): Store SIMD&FP register (register offset).

SIMD&FP): Store SIMD&FP register (unscaled offset).

LD2R: Load

single 2-element structure and Replicate to all lanes of two registers.

single 2-element structure from one lane of two registers.

single 2-element structure to one lane of two registers.

LD3R: Load

single 3-element structure and Replicate to all lanes of three registers.

single 3-element structure from one lane of three registers.

single 3-element structure to one lane of three registers).

LD4R: Load

single 4-element structure and Replicate to all lanes of four registers.

single 4-element structure from one lane of four registers.

single 4-element structure to one lane of four registers.

AESD: AES

single round decryption.

AESE: AES

single round encryption.

single structure): Load one single-element structure to one lane of one register.

single structure): Load single 2-element structure to one lane of two registers.

single structure): Load single 3-element structure to one lane of three registers).

single structure): Load single 4-element structure to one lane of four registers.

single structure): Store a single-element structure from one lane of one register.

single structure): Store single 2-element structure from one lane of two registers.

single structure): Store single 3-element structure from one lane of three registers.

single structure): Store single 4-element structure from one lane of four registers.

LD1R: Load one

single-element structure and Replicate to all lanes (of one register).

single-element structure from one lane of one register.

single-element structure to one lane of one register.

ST1 (multiple structures): Store multiple

single-element structures from one, two, three, or four registers.

single-element structures to one, two, three, or four registers.

SHLL, SHLL2: Shift Left Long (by element

size).

SLI: Shift Left and Insert (immediate).

SMULL: Signed Multiply Long: an alias of

SMADDL.

SMADDL: Signed Multiply-Add Long.

SMAX: Signed Maximum (vector).

SMAXP: Signed Maximum Pairwise.

SMAXV: Signed Maximum across Vector.

SMC: Secure Monitor Call.

SMIN: Signed Minimum (vector).

SMINP: Signed Minimum Pairwise.

SMINV: Signed Minimum across Vector.

SMLAL, SMLAL2 (by element): Signed Multiply-Add Long (vector, by element).

SMLAL, SMLAL2 (vector): Signed Multiply-Add Long (vector).

SMLAL2 (by element): Signed Multiply-Add Long (vector, by element).

SMLAL2 (vector): Signed Multiply-Add Long (vector).

SMLSL, SMLSL2 (by element): Signed Multiply-Subtract Long (vector, by element).

SMLSL, SMLSL2 (vector): Signed Multiply-Subtract Long (vector).

SMLSL2 (by element): Signed Multiply-Subtract Long (vector, by element).

SMLSL2 (vector): Signed Multiply-Subtract Long (vector).

SMNEGL: Signed Multiply-Negate Long: an alias of SMSUBL.

SMOV: Signed Move vector element to general-purpose register.

SMNEGL: Signed Multiply-Negate Long: an alias of

SMSUBL.

SMSUBL: Signed Multiply-Subtract Long.

SMULH: Signed Multiply High.

SMULL, SMULL2 (by element): Signed Multiply Long (vector, by element).

SMULL, SMULL2 (vector): Signed Multiply Long (vector).

SMULL2 (by element): Signed Multiply Long (vector, by element).

SMULL2 (vector): Signed Multiply Long (vector).

SMULL: Signed Multiply Long: an alias of SMADDL.

MOV (to/from

SP): Move between register and stack pointer: an alias of ADD (immediate).

MSR (immediate): Move immediate value to

Special Register.

SQABS: Signed saturating Absolute value.

SQADD: Signed saturating Add.

SQDMLAL, SQDMLAL2 (by element): Signed saturating Doubling Multiply-Add Long (by element).

SQDMLAL, SQDMLAL2 (vector): Signed saturating Doubling Multiply-Add Long.

SQDMLAL2 (by element): Signed saturating Doubling Multiply-Add Long (by element).

SQDMLAL2 (vector): Signed saturating Doubling Multiply-Add Long.

SQDMLSL, SQDMLSL2 (by element): Signed saturating Doubling Multiply-Subtract Long (by element).

SQDMLSL, SQDMLSL2 (vector): Signed saturating Doubling Multiply-Subtract Long.

SQDMLSL2 (by element): Signed saturating Doubling Multiply-Subtract Long (by element).

SQDMLSL2 (vector): Signed saturating Doubling Multiply-Subtract Long.

SQDMULH (by element): Signed saturating Doubling Multiply returning High half (by element).

SQDMULH (vector): Signed saturating Doubling Multiply returning High half.

SQDMULL, SQDMULL2 (by element): Signed saturating Doubling Multiply Long (by element).

SQDMULL, SQDMULL2 (vector): Signed saturating Doubling Multiply Long.

SQDMULL2 (by element): Signed saturating Doubling Multiply Long (by element).

SQDMULL2 (vector): Signed saturating Doubling Multiply Long.

SQNEG: Signed saturating Negate.

SQRDMLAH (by element): Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element).

SQRDMLAH (vector): Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (vector).

SQRDMLSH (by element): Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element).

SQRDMLSH (vector): Signed Saturating Rounding Doubling Multiply Subtract returning High Half (vector).

SQRDMULH (by element): Signed saturating Rounding Doubling Multiply returning High half (by element).

SQRDMULH (vector): Signed saturating Rounding Doubling Multiply returning High half.

SQRSHL: Signed saturating Rounding Shift Left (register).

SQRSHRN, SQRSHRN2: Signed saturating Rounded Shift Right Narrow (immediate).

SQRSHRN,

SQRSHRN2: Signed saturating Rounded Shift Right Narrow (immediate).

SQRSHRUN, SQRSHRUN2: Signed saturating Rounded Shift Right Unsigned Narrow (immediate).

SQRSHRUN,

SQRSHRUN2: Signed saturating Rounded Shift Right Unsigned Narrow (immediate).

SQSHL (immediate): Signed saturating Shift Left (immediate).

SQSHL (register): Signed saturating Shift Left (register).

SQSHLU: Signed saturating Shift Left Unsigned (immediate).

SQSHRN, SQSHRN2: Signed saturating Shift Right Narrow (immediate).

SQSHRN,

SQSHRN2: Signed saturating Shift Right Narrow (immediate).

SQSHRUN, SQSHRUN2: Signed saturating Shift Right Unsigned Narrow (immediate).

SQSHRUN,

SQSHRUN2: Signed saturating Shift Right Unsigned Narrow (immediate).

SQSUB: Signed saturating Subtract.

FSQRT (scalar): Floating-point

Square Root (scalar).

FSQRT (vector): Floating-point

Square Root (vector).

FRSQRTE: Floating-point Reciprocal

Square Root Estimate.

URSQRTE: Unsigned Reciprocal

Square Root Estimate.

FRSQRTS: Floating-point Reciprocal

Square Root Step.

SQXTN, SQXTN2: Signed saturating extract Narrow.

SQXTN,

SQXTN2: Signed saturating extract Narrow.

SQXTUN, SQXTUN2: Signed saturating extract Unsigned Narrow.

SQXTUN,

SQXTUN2: Signed saturating extract Unsigned Narrow.

SRHADD: Signed Rounding Halving Add.

SRI: Shift Right and Insert (immediate).

SRSHL: Signed Rounding Shift Left (register).

SRSHR: Signed Rounding Shift Right (immediate).

SRSRA: Signed Rounding Shift Right and Accumulate (immediate).

SSHL: Signed Shift Left (register).

SXTL, SXTL2: Signed extend Long: an alias of

SSHLL, SSHLL2.

SSHLL, SSHLL2: Signed Shift Left Long (immediate).

SXTL, SXTL2: Signed extend Long: an alias of SSHLL,

SSHLL2.

SSHLL,

SSHLL2: Signed Shift Left Long (immediate).

SSHR: Signed Shift Right (immediate).

SSRA: Signed Shift Right and Accumulate (immediate).

SSUBL, SSUBL2: Signed Subtract Long.

SSUBL,

SSUBL2: Signed Subtract Long.

SSUBW, SSUBW2: Signed Subtract Wide.

SSUBW,

SSUBW2: Signed Subtract Wide.

ST1 (multiple structures): Store multiple single-element structures from one, two, three, or four registers.

ST1 (single structure): Store a single-element structure from one lane of one register.

ST2 (multiple structures): Store multiple 2-element structures from two registers.

ST2 (single structure): Store single 2-element structure from one lane of two registers.

ST3 (multiple structures): Store multiple 3-element structures from three registers.

ST3 (single structure): Store single 3-element structure from one lane of three registers.

ST4 (multiple structures): Store multiple 4-element structures from four registers.

ST4 (single structure): Store single 4-element structure from one lane of four registers.

MOV (to/from SP): Move between register and

stack pointer: an alias of ADD (immediate).

STADD, STADDL: Atomic add on word or doubleword in memory, without return.

STADDB, STADDLB: Atomic add on byte in memory, without return.

STADDH, STADDLH: Atomic add on halfword in memory, without return.

STADDL: Atomic add on word or doubleword in memory, without return.

STADDLB: Atomic add on byte in memory, without return.

STADDLH: Atomic add on halfword in memory, without return.

DCPS1: Debug Change PE

State to EL1..

DCPS2: Debug Change PE

State to EL2..

DCPS3: Debug Change PE

State to EL3.

DRPS: Debug restore process

state.

STCLR, STCLRL: Atomic bit clear on word or doubleword in memory, without return.

STCLRB, STCLRLB: Atomic bit clear on byte in memory, without return.

STCLRH, STCLRLH: Atomic bit clear on halfword in memory, without return.

STCLRL: Atomic bit clear on word or doubleword in memory, without return.

STCLRLB: Atomic bit clear on byte in memory, without return.

STCLRLH: Atomic bit clear on halfword in memory, without return.

STEOR, STEORL: Atomic exclusive OR on word or doubleword in memory, without return.

STEORB, STEORLB: Atomic exclusive OR on byte in memory, without return.

STEORH, STEORLH: Atomic exclusive OR on halfword in memory, without return.

STEORL: Atomic exclusive OR on word or doubleword in memory, without return.

STEORLB: Atomic exclusive OR on byte in memory, without return.

STEORLH: Atomic exclusive OR on halfword in memory, without return.

FRECPS: Floating-point Reciprocal

Step.

FRSQRTS: Floating-point Reciprocal Square Root

Step.

STLLR: Store LORelease Register.

STLLRB: Store LORelease Register Byte.

STLLRH: Store LORelease Register Halfword.

STLR: Store-Release Register.

STLRB: Store-Release Register Byte.

STLRH: Store-Release Register Halfword.

STLXP: Store-Release Exclusive Pair of registers.

STLXR: Store-Release Exclusive Register.

STLXRB: Store-Release Exclusive Register Byte.

STLXRH: Store-Release Exclusive Register Halfword.

STNP (SIMD&FP): Store Pair of SIMD&FP registers, with Non-temporal hint.

STNP: Store Pair of Registers, with non-temporal hint.

Store a single-element structure from one lane of one register.

Store Exclusive Pair of registers.

Store Exclusive Register Byte.

Store Exclusive Register Halfword.

Store Exclusive Register.

Store LORelease Register Byte.

Store LORelease Register Halfword.

Store LORelease Register.

Store multiple 2-element structures from two registers.

Store multiple 3-element structures from three registers.

Store multiple 4-element structures from four registers.

Store multiple single-element structures from one, two, three, or four registers.

Store Pair of Registers, with non-temporal hint.

STP:

Store Pair of Registers.

Store Pair of SIMD&FP registers, with Non-temporal hint.

Store Pair of SIMD&FP registers.

Store Register (immediate).

Store Register (register).

Store Register (unprivileged).

Store Register (unscaled).

Store Register Byte (immediate).

Store Register Byte (register).

Store Register Byte (unprivileged).

Store Register Byte (unscaled).

Store Register Halfword (immediate).

Store Register Halfword (register).

Store Register Halfword (unprivileged).

Store Register Halfword (unscaled).

Store SIMD&FP register (immediate offset).

Store SIMD&FP register (register offset).

Store SIMD&FP register (unscaled offset).

Store single 2-element structure from one lane of two registers.

Store single 3-element structure from one lane of three registers.

Store single 4-element structure from one lane of four registers.

Store-Release Exclusive Pair of registers.

Store-Release Exclusive Register Byte.

Store-Release Exclusive Register Halfword.

Store-Release Exclusive Register.

Store-Release Register Byte.

Store-Release Register Halfword.

Store-Release Register.

STP (SIMD&FP): Store Pair of SIMD&FP registers.

STP: Store Pair of Registers.

STR (immediate): Store Register (immediate).

STR (immediate, SIMD&FP): Store SIMD&FP register (immediate offset).

STR (register): Store Register (register).

STR (register, SIMD&FP): Store SIMD&FP register (register offset).

STRB (immediate): Store Register Byte (immediate).

STRB (register): Store Register Byte (register).

STRH (immediate): Store Register Halfword (immediate).

STRH (register): Store Register Halfword (register).

LD1R: Load one single-element

structure and Replicate to all lanes (of one register).

LD4R: Load single 4-element

structure and Replicate to all lanes of four registers.

LD3R: Load single 3-element

structure and Replicate to all lanes of three registers.

LD2R: Load single 2-element

structure and Replicate to all lanes of two registers.

ST4 (single structure): Store single 4-element

structure from one lane of four registers.

ST1 (single structure): Store a single-element

structure from one lane of one register.

ST3 (single structure): Store single 3-element

structure from one lane of three registers.

ST2 (single structure): Store single 2-element

structure from one lane of two registers.

LD4 (single structure): Load single 4-element

structure to one lane of four registers.

LD1 (single structure): Load one single-element

structure to one lane of one register.

LD3 (single structure): Load single 3-element

structure to one lane of three registers).

LD2 (single structure): Load single 2-element

structure to one lane of two registers.

structure): Load one single-element structure to one lane of one register.

structure): Load single 2-element structure to one lane of two registers.

structure): Load single 3-element structure to one lane of three registers).

structure): Load single 4-element structure to one lane of four registers.

structure): Store a single-element structure from one lane of one register.

structure): Store single 2-element structure from one lane of two registers.

structure): Store single 3-element structure from one lane of three registers.

structure): Store single 4-element structure from one lane of four registers.

ST4 (multiple structures): Store multiple 4-element

structures from four registers.

ST1 (multiple structures): Store multiple single-element

structures from one, two, three, or four registers.

ST3 (multiple structures): Store multiple 3-element

structures from three registers.

ST2 (multiple structures): Store multiple 2-element

structures from two registers.

LD4 (multiple structures): Load multiple 4-element

structures to four registers.

LD1 (multiple structures): Load multiple single-element

structures to one, two, three, or four registers.

LD3 (multiple structures): Load multiple 3-element

structures to three registers.

LD2 (multiple structures): Load multiple 2-element

structures to two registers.

structures): Load multiple 2-element structures to two registers.

structures): Load multiple 3-element structures to three registers.

structures): Load multiple 4-element structures to four registers.

structures): Load multiple single-element structures to one, two, three, or four registers.

structures): Store multiple 2-element structures from two registers.

structures): Store multiple 3-element structures from three registers.

structures): Store multiple 4-element structures from four registers.

structures): Store multiple single-element structures from one, two, three, or four registers.

STSET, STSETL: Atomic bit set on word or doubleword in memory, without return.

STSETB, STSETLB: Atomic bit set on byte in memory, without return.

STSETH, STSETLH: Atomic bit set on halfword in memory, without return.

STSETL: Atomic bit set on word or doubleword in memory, without return.

STSETLB: Atomic bit set on byte in memory, without return.

STSETLH: Atomic bit set on halfword in memory, without return.

STSMAX, STSMAXL: Atomic signed maximum on word or doubleword in memory, without return.

STSMAXB, STSMAXLB: Atomic signed maximum on byte in memory, without return.

STSMAXH, STSMAXLH: Atomic signed maximum on halfword in memory, without return.

STSMAXL: Atomic signed maximum on word or doubleword in memory, without return.

STSMAXLB: Atomic signed maximum on byte in memory, without return.

STSMAXLH: Atomic signed maximum on halfword in memory, without return.

STSMIN, STSMINL: Atomic signed minimum on word or doubleword in memory, without return.

STSMINB, STSMINLB: Atomic signed minimum on byte in memory, without return.

STSMINH, STSMINLH: Atomic signed minimum on halfword in memory, without return.

STSMINL: Atomic signed minimum on word or doubleword in memory, without return.

STSMINLB: Atomic signed minimum on byte in memory, without return.

STSMINLH: Atomic signed minimum on halfword in memory, without return.

STTR: Store Register (unprivileged).

STTRB: Store Register Byte (unprivileged).

STTRH: Store Register Halfword (unprivileged).

STUMAX, STUMAXL: Atomic unsigned maximum on word or doubleword in memory, without return.

STUMAXB, STUMAXLB: Atomic unsigned maximum on byte in memory, without return.

STUMAXH, STUMAXLH: Atomic unsigned maximum on halfword in memory, without return.

STUMAXL: Atomic unsigned maximum on word or doubleword in memory, without return.

STUMAXLB: Atomic unsigned maximum on byte in memory, without return.

STUMAXLH: Atomic unsigned maximum on halfword in memory, without return.

STUMIN, STUMINL: Atomic unsigned minimum on word or doubleword in memory, without return.

STUMINB, STUMINLB: Atomic unsigned minimum on byte in memory, without return.

STUMINH, STUMINLH: Atomic unsigned minimum on halfword in memory, without return.

STUMINL: Atomic unsigned minimum on word or doubleword in memory, without return.

STUMINLB: Atomic unsigned minimum on byte in memory, without return.

STUMINLH: Atomic unsigned minimum on halfword in memory, without return.

STUR (SIMD&FP): Store SIMD&FP register (unscaled offset).

STUR: Store Register (unscaled).

STURB: Store Register Byte (unscaled).

STURH: Store Register Halfword (unscaled).

STXP: Store Exclusive Pair of registers.

STXR: Store Exclusive Register.

STXRB: Store Exclusive Register Byte.

STXRH: Store Exclusive Register Halfword.

SUB (extended register): Subtract (extended register).

SUB (immediate): Subtract (immediate).

NEG (shifted register): Negate (shifted register): an alias of

SUB (shifted register).

SUB (shifted register): Subtract (shifted register).

SUB (vector): Subtract (vector).

SUBHN, SUBHN2: Subtract returning High Narrow.

SUBHN,

SUBHN2: Subtract returning High Narrow.

RET: Return from

subroutine.

CMP (extended register): Compare (extended register): an alias of

SUBS (extended register).

SUBS (extended register): Subtract (extended register), setting flags.

CMP (immediate): Compare (immediate): an alias of

SUBS (immediate).

SUBS (immediate): Subtract (immediate), setting flags.

CMP (shifted register): Compare (shifted register): an alias of

SUBS (shifted register).

NEGS: Negate, setting flags: an alias of

SUBS (shifted register).

SUBS (shifted register): Subtract (shifted register), setting flags.

Subtract (extended register), setting flags.

Subtract (extended register).

Subtract (immediate), setting flags.

Subtract (immediate).

FMSUB: Floating-point Fused Multiply-

Subtract (scalar).

FNMSUB: Floating-point Negated fused Multiply-

Subtract (scalar).

FSUB (scalar): Floating-point

Subtract (scalar).

Subtract (shifted register), setting flags.

Subtract (shifted register).

FSUB (vector): Floating-point

Subtract (vector).

SUB (vector):

Subtract (vector).

FMLS (by element): Floating-point fused Multiply-

Subtract from accumulator (by element).

FMLS (vector): Floating-point fused Multiply-

Subtract from accumulator (vector).

MLS (vector): Multiply-

Subtract from accumulator (vector).

MLS (by element): Multiply-

Subtract from accumulator (vector, by element).

SQDMLSL, SQDMLSL2 (by element): Signed saturating Doubling Multiply-

Subtract Long (by element).

SMLSL, SMLSL2 (vector): Signed Multiply-

Subtract Long (vector).

UMLSL, UMLSL2 (vector): Unsigned Multiply-

Subtract Long (vector).

SMLSL, SMLSL2 (by element): Signed Multiply-

Subtract Long (vector, by element).

UMLSL, UMLSL2 (by element): Unsigned Multiply-

Subtract Long (vector, by element).

SMSUBL: Signed Multiply-

Subtract Long.

SQDMLSL, SQDMLSL2 (vector): Signed saturating Doubling Multiply-

Subtract Long.

SSUBL, SSUBL2: Signed

Subtract Long.

UMSUBL: Unsigned Multiply-

Subtract Long.

USUBL, USUBL2: Unsigned

Subtract Long.

SQRDMLSH (by element): Signed Saturating Rounding Doubling Multiply

Subtract returning High Half (by element).

SQRDMLSH (vector): Signed Saturating Rounding Doubling Multiply

Subtract returning High Half (vector).

RSUBHN, RSUBHN2: Rounding

Subtract returning High Narrow.

SUBHN, SUBHN2:

Subtract returning High Narrow.

SSUBW, SSUBW2: Signed

Subtract Wide.

USUBW, USUBW2: Unsigned

Subtract Wide.

Subtract with Carry, setting flags.

SBC:

Subtract with Carry.

MSUB: Multiply-

Subtract.

SHSUB: Signed Halving

Subtract.

SQSUB: Signed saturating

Subtract.

UHSUB: Unsigned Halving

Subtract.

UQSUB: Unsigned saturating

Subtract.

UADDLV: Unsigned

sum Long across Vector.

SVC:

Supervisor Call.

SUQADD: Signed saturating Accumulate of Unsigned value.

SVC: Supervisor Call.

Swap byte in memory.

Swap byte in memory.

Swap halfword in memory.

Swap halfword in memory.

Swap Pair of words or doublewords in memory.

CAS, CASA, CASAL, CASL: Compare and

Swap word or doubleword in memory.

Swap word or doubleword in memory.

SWP, SWPA, SWPAL, SWPL: Swap word or doubleword in memory.

SWPA, SWPAL, SWPL: Swap word or doubleword in memory.

SWPAB, SWPALB, SWPLB: Swap byte in memory.

SWPAH, SWPALH, SWPLH: Swap halfword in memory.

SWPAL, SWPL: Swap word or doubleword in memory.

SWPALB, SWPLB: Swap byte in memory.

SWPALH, SWPLH: Swap halfword in memory.

SWPB, SWPAB, SWPALB, SWPLB: Swap byte in memory.

SWPH, SWPAH, SWPALH, SWPLH: Swap halfword in memory.

SWPL: Swap word or doubleword in memory.

SWPLB: Swap byte in memory.

SWPLH: Swap halfword in memory.

SXTB: Signed Extend Byte: an alias of SBFM.

SXTH: Sign Extend Halfword: an alias of SBFM.

SXTL, SXTL2: Signed extend Long: an alias of SSHLL, SSHLL2.

SXTL,

SXTL2: Signed extend Long: an alias of SSHLL, SSHLL2.

SXTW: Sign Extend Word: an alias of SBFM.

DSB: Data

Synchronization Barrier.

ESB: Error

Synchronization Barrier.

ISB: Instruction

Synchronization Barrier.

PSB CSYNC: Profiling

Synchronization Barrier.

AT: Address Translate: an alias of

SYS.

DC: Data Cache operation: an alias of

SYS.

IC: Instruction Cache operation: an alias of

SYS.

TLBI: TLB Invalidate operation: an alias of

SYS.

SYS: System instruction.

SYSL: System instruction with result.

System instruction with result.

SYS:

System instruction.

MRS: Move

System Register.

MSR (register): Move general-purpose register to

System Register.

TBX:

TBL:

Table vector Lookup.

TBL: Table vector Lookup.

TBNZ: Test bit and Branch if Nonzero.

TBX: Table vector lookup extension.

TBZ: Test bit and Branch if Zero.

LDNP (SIMD&FP): Load Pair of SIMD&FP registers, with Non-

temporal hint.

LDNP: Load Pair of Registers, with non-

temporal hint.

STNP (SIMD&FP): Store Pair of SIMD&FP registers, with Non-

temporal hint.

STNP: Store Pair of Registers, with non-

temporal hint.

TST (shifted register):

Test (shifted register): an alias of ANDS (shifted register).

Test bit and Branch if Nonzero.

TBZ:

Test bit and Branch if Zero.

TST (immediate):

Test bits (immediate): an alias of ANDS (immediate).

CMTST: Compare bitwise

Test bits nonzero (vector).

LD3 (single structure): Load single 3-element structure to one lane of

three registers).

LD3 (multiple structures): Load multiple 3-element structures to

three registers.

LD3R: Load single 3-element structure and Replicate to all lanes of

three registers.

ST3 (multiple structures): Store multiple 3-element structures from

three registers.

ST3 (single structure): Store single 3-element structure from one lane of

three registers.

LD1 (multiple structures): Load multiple single-element structures to one, two,

three, or four registers.

ST1 (multiple structures): Store multiple single-element structures from one, two,

three, or four registers.

FCVTAS (scalar): Floating-point Convert to Signed integer, rounding to nearest with

ties to Away (scalar).

FCVTAU (scalar): Floating-point Convert to Unsigned integer, rounding to nearest with

ties to Away (scalar).

FRINTA (scalar): Floating-point Round to Integral, to nearest with

ties to Away (scalar).

FCVTAS (vector): Floating-point Convert to Signed integer, rounding to nearest with

ties to Away (vector).

FCVTAU (vector): Floating-point Convert to Unsigned integer, rounding to nearest with

ties to Away (vector).

FRINTA (vector): Floating-point Round to Integral, to nearest with

ties to Away (vector).

FCVTNS (scalar): Floating-point Convert to Signed integer, rounding to nearest with

ties to even (scalar).

FCVTNU (scalar): Floating-point Convert to Unsigned integer, rounding to nearest with

ties to even (scalar).

FRINTN (scalar): Floating-point Round to Integral, to nearest with

ties to even (scalar).

FCVTNS (vector): Floating-point Convert to Signed integer, rounding to nearest with

ties to even (vector).

FCVTNU (vector): Floating-point Convert to Unsigned integer, rounding to nearest with

ties to even (vector).

FRINTN (vector): Floating-point Round to Integral, to nearest with

ties to even (vector).

TLBI:

TLB Invalidate operation: an alias of SYS.

TLBI: TLB Invalidate operation: an alias of SYS.

FCVTMS (scalar): Floating-point Convert to Signed integer, rounding

toward Minus infinity (scalar).

FCVTMU (scalar): Floating-point Convert to Unsigned integer, rounding

toward Minus infinity (scalar).

FRINTM (scalar): Floating-point Round to Integral,

toward Minus infinity (scalar).

FCVTMS (vector): Floating-point Convert to Signed integer, rounding

toward Minus infinity (vector).

FCVTMU (vector): Floating-point Convert to Unsigned integer, rounding

toward Minus infinity (vector).

FRINTM (vector): Floating-point Round to Integral,

toward Minus infinity (vector).

FCVTPS (scalar): Floating-point Convert to Signed integer, rounding

toward Plus infinity (scalar).

FCVTPU (scalar): Floating-point Convert to Unsigned integer, rounding

toward Plus infinity (scalar).

FRINTP (scalar): Floating-point Round to Integral,

toward Plus infinity (scalar).

FCVTPS (vector): Floating-point Convert to Signed integer, rounding

toward Plus infinity (vector).

FCVTPU (vector): Floating-point Convert to Unsigned integer, rounding

toward Plus infinity (vector).

FRINTP (vector): Floating-point Round to Integral,

toward Plus infinity (vector).

FCVTZS (scalar, fixed-point): Floating-point Convert to Signed fixed-point, rounding

toward Zero (scalar).

FCVTZS (scalar, integer): Floating-point Convert to Signed integer, rounding

toward Zero (scalar).

FCVTZU (scalar, fixed-point): Floating-point Convert to Unsigned fixed-point, rounding

toward Zero (scalar).

FCVTZU (scalar, integer): Floating-point Convert to Unsigned integer, rounding

toward Zero (scalar).

FRINTZ (scalar): Floating-point Round to Integral,

toward Zero (scalar).

FCVTZS (vector, fixed-point): Floating-point Convert to Signed fixed-point, rounding

toward Zero (vector).

FCVTZS (vector, integer): Floating-point Convert to Signed integer, rounding

toward Zero (vector).

FCVTZU (vector, fixed-point): Floating-point Convert to Unsigned fixed-point, rounding

toward Zero (vector).

FCVTZU (vector, integer): Floating-point Convert to Unsigned integer, rounding

toward Zero (vector).

FRINTZ (vector): Floating-point Round to Integral,

toward Zero (vector).

AT: Address

Translate: an alias of SYS.

TRN1:

Transpose vectors (primary).

TRN2:

Transpose vectors (secondary).

TRN1: Transpose vectors (primary).

TRN2: Transpose vectors (secondary).

BIT: Bitwise Insert if

True.

TST (immediate): Test bits (immediate): an alias of ANDS (immediate).

TST (shifted register): Test (shifted register): an alias of ANDS (shifted register).

LD2 (multiple structures): Load multiple 2-element structures to

two registers.

LD2 (single structure): Load single 2-element structure to one lane of

two registers.

LD2R: Load single 2-element structure and Replicate to all lanes of

two registers.

ST2 (multiple structures): Store multiple 2-element structures from

two registers.

ST2 (single structure): Store single 2-element structure from one lane of

two registers.

LD1 (multiple structures): Load multiple single-element structures to one,

two, three, or four registers.

ST1 (multiple structures): Store multiple single-element structures from one,

two, three, or four registers.

UABA: Unsigned Absolute difference and Accumulate.

UABAL, UABAL2: Unsigned Absolute difference and Accumulate Long.

UABAL2: Unsigned Absolute difference and Accumulate Long.

UABD: Unsigned Absolute Difference (vector).

UABDL, UABDL2: Unsigned Absolute Difference Long.

UABDL2: Unsigned Absolute Difference Long.

UADALP: Unsigned Add and Accumulate Long Pairwise.

UADDL, UADDL2: Unsigned Add Long (vector).

UADDL,

UADDL2: Unsigned Add Long (vector).

UADDLP: Unsigned Add Long Pairwise.

UADDLV: Unsigned sum Long across Vector.

UADDW, UADDW2: Unsigned Add Wide.

UADDW,

UADDW2: Unsigned Add Wide.

UBFIZ: Unsigned Bitfield Insert in Zero: an alias of UBFM.

LSL (immediate): Logical Shift Left (immediate): an alias of

UBFM.

LSR (immediate): Logical Shift Right (immediate): an alias of

UBFM.

UBFIZ: Unsigned Bitfield Insert in Zero: an alias of

UBFM.

UBFX: Unsigned Bitfield Extract: an alias of

UBFM.

UXTB: Unsigned Extend Byte: an alias of

UBFM.

UXTH: Unsigned Extend Halfword: an alias of

UBFM.

UBFM: Unsigned Bitfield Move.

UBFX: Unsigned Bitfield Extract: an alias of UBFM.

UCVTF (scalar, fixed-point): Unsigned fixed-point Convert to Floating-point (scalar).

UCVTF (scalar, integer): Unsigned integer Convert to Floating-point (scalar).

UCVTF (vector, fixed-point): Unsigned fixed-point Convert to Floating-point (vector).

UCVTF (vector, integer): Unsigned integer Convert to Floating-point (vector).

UDIV: Unsigned Divide.

UHADD: Unsigned Halving Add.

UHSUB: Unsigned Halving Subtract.

UMULL: Unsigned Multiply Long: an alias of

UMADDL.

UMADDL: Unsigned Multiply-Add Long.

UMAX: Unsigned Maximum (vector).

UMAXP: Unsigned Maximum Pairwise.

UMAXV: Unsigned Maximum across Vector.

UMIN: Unsigned Minimum (vector).

UMINP: Unsigned Minimum Pairwise.

UMINV: Unsigned Minimum across Vector.

UMLAL, UMLAL2 (by element): Unsigned Multiply-Add Long (vector, by element).

UMLAL, UMLAL2 (vector): Unsigned Multiply-Add Long (vector).

UMLAL2 (by element): Unsigned Multiply-Add Long (vector, by element).

UMLAL2 (vector): Unsigned Multiply-Add Long (vector).

UMLSL, UMLSL2 (by element): Unsigned Multiply-Subtract Long (vector, by element).

UMLSL, UMLSL2 (vector): Unsigned Multiply-Subtract Long (vector).

UMLSL2 (by element): Unsigned Multiply-Subtract Long (vector, by element).

UMLSL2 (vector): Unsigned Multiply-Subtract Long (vector).

UMNEGL: Unsigned Multiply-Negate Long: an alias of UMSUBL.

MOV (to general): Move vector element to general-purpose register: an alias of

UMOV.

UMOV: Unsigned Move vector element to general-purpose register.

UMNEGL: Unsigned Multiply-Negate Long: an alias of

UMSUBL.

UMSUBL: Unsigned Multiply-Subtract Long.

UMULH: Unsigned Multiply High.

UMULL, UMULL2 (by element): Unsigned Multiply Long (vector, by element).

UMULL, UMULL2 (vector): Unsigned Multiply long (vector).

UMULL2 (by element): Unsigned Multiply Long (vector, by element).

UMULL2 (vector): Unsigned Multiply long (vector).

UMULL: Unsigned Multiply Long: an alias of UMADDL.

BFC: Bitfield Clear, leaving other bits

unchanged: an alias of BFM.

LDTR: Load Register (

unprivileged).

LDTRB: Load Register Byte (

unprivileged).

LDTRH: Load Register Halfword (

unprivileged).

LDTRSB: Load Register Signed Byte (

unprivileged).

LDTRSH: Load Register Signed Halfword (

unprivileged).

LDTRSW: Load Register Signed Word (

unprivileged).

STTR: Store Register (

unprivileged).

STTRB: Store Register Byte (

unprivileged).

STTRH: Store Register Halfword (

unprivileged).

LDUR (SIMD&FP): Load SIMD&FP Register (

unscaled offset).

PRFM (unscaled offset): Prefetch Memory (

unscaled offset).

STUR (SIMD&FP): Store SIMD&FP register (

unscaled offset).

unscaled offset): Prefetch Memory (unscaled offset).

LDUR: Load Register (

unscaled).

LDURB: Load Register Byte (

unscaled).

LDURH: Load Register Halfword (

unscaled).

LDURSB: Load Register Signed Byte (

unscaled).

LDURSH: Load Register Signed Halfword (

unscaled).

LDURSW: Load Register Signed Word (

unscaled).

STUR: Store Register (

unscaled).

STURB: Store Register Byte (

unscaled).

STURH: Store Register Halfword (

unscaled).

SQSHLU: Signed saturating Shift Left

Unsigned (immediate).

Unsigned Absolute Difference (vector).

Unsigned Absolute difference and Accumulate Long.

Unsigned Absolute difference and Accumulate.

Unsigned Absolute Difference Long.

Unsigned Add and Accumulate Long Pairwise.

UADDL, UADDL2:

Unsigned Add Long (vector).

Unsigned Add Long Pairwise.

UADDW, UADDW2:

Unsigned Add Wide.

UBFX:

Unsigned Bitfield Extract: an alias of UBFM.

UBFIZ:

Unsigned Bitfield Insert in Zero: an alias of UBFM.

Unsigned Bitfield Move.

Unsigned Divide.

UXTB:

Unsigned Extend Byte: an alias of UBFM.

UXTH:

Unsigned Extend Halfword: an alias of UBFM.

UXTL, UXTL2:

Unsigned extend Long: an alias of USHLL, USHLL2.

Unsigned fixed-point Convert to Floating-point (scalar).

UCVTF (vector, fixed-point):

Unsigned fixed-point Convert to Floating-point (vector).

FCVTZU (scalar, fixed-point): Floating-point Convert to

Unsigned fixed-point, rounding toward Zero (scalar).

FCVTZU (vector, fixed-point): Floating-point Convert to

Unsigned fixed-point, rounding toward Zero (vector).

UHADD:

Unsigned Halving Add.

UHSUB:

Unsigned Halving Subtract.

CMHI (register): Compare

unsigned Higher (vector).

CMHS (register): Compare

unsigned Higher or Same (vector).

Unsigned integer Convert to Floating-point (scalar).

UCVTF (vector, integer):

Unsigned integer Convert to Floating-point (vector).

FCVTAU (scalar): Floating-point Convert to

Unsigned integer, rounding to nearest with ties to Away (scalar).

FCVTAU (vector): Floating-point Convert to

Unsigned integer, rounding to nearest with ties to Away (vector).

FCVTNU (scalar): Floating-point Convert to

Unsigned integer, rounding to nearest with ties to even (scalar).

FCVTNU (vector): Floating-point Convert to

Unsigned integer, rounding to nearest with ties to even (vector).

FCVTMU (scalar): Floating-point Convert to

Unsigned integer, rounding toward Minus infinity (scalar).

FCVTMU (vector): Floating-point Convert to

Unsigned integer, rounding toward Minus infinity (vector).

FCVTPU (scalar): Floating-point Convert to

Unsigned integer, rounding toward Plus infinity (scalar).

FCVTPU (vector): Floating-point Convert to

Unsigned integer, rounding toward Plus infinity (vector).

FCVTZU (scalar, integer): Floating-point Convert to

Unsigned integer, rounding toward Zero (scalar).

FCVTZU (vector, integer): Floating-point Convert to

Unsigned integer, rounding toward Zero (vector).

UMAX:

Unsigned Maximum (vector).

UMAXV:

Unsigned Maximum across Vector.

unsigned maximum on byte in memory, without return.

unsigned maximum on byte in memory.

unsigned maximum on halfword in memory, without return.

unsigned maximum on halfword in memory.

unsigned maximum on word or doubleword in memory, without return.

unsigned maximum on word or doubleword in memory.

UMAXP:

Unsigned Maximum Pairwise.

UMIN:

Unsigned Minimum (vector).

UMINV:

Unsigned Minimum across Vector.

unsigned minimum on byte in memory, without return.

unsigned minimum on byte in memory.

unsigned minimum on halfword in memory, without return.

unsigned minimum on halfword in memory.

unsigned minimum on word or doubleword in memory, without return.

unsigned minimum on word or doubleword in memory.

UMINP:

Unsigned Minimum Pairwise.

UMOV:

Unsigned Move vector element to general-purpose register.

Unsigned Multiply High.

Unsigned Multiply long (vector).

Unsigned Multiply Long (vector, by element).

UMULL:

Unsigned Multiply Long: an alias of UMADDL.

Unsigned Multiply-Add Long (vector).

Unsigned Multiply-Add Long (vector, by element).

Unsigned Multiply-Add Long.

UMNEGL:

Unsigned Multiply-Negate Long: an alias of UMSUBL.

Unsigned Multiply-Subtract Long (vector).

Unsigned Multiply-Subtract Long (vector, by element).

Unsigned Multiply-Subtract Long.

SQRSHRUN, SQRSHRUN2: Signed saturating Rounded Shift Right

Unsigned Narrow (immediate).

SQSHRUN, SQSHRUN2: Signed saturating Shift Right

Unsigned Narrow (immediate).

SQXTUN, SQXTUN2: Signed saturating extract

Unsigned Narrow.

URECPE:

Unsigned Reciprocal Estimate.

URSQRTE:

Unsigned Reciprocal Square Root Estimate.

Unsigned Rounding Halving Add.

URSHL:

Unsigned Rounding Shift Left (register).

URSHR:

Unsigned Rounding Shift Right (immediate).

URSRA:

Unsigned Rounding Shift Right and Accumulate (immediate).

USQADD:

Unsigned saturating Accumulate of Signed value.

UQADD:

Unsigned saturating Add.

UQXTN, UQXTN2:

Unsigned saturating extract Narrow.

UQRSHRN, UQRSHRN2:

Unsigned saturating Rounded Shift Right Narrow (immediate).

UQRSHL:

Unsigned saturating Rounding Shift Left (register).

UQSHL (immediate):

Unsigned saturating Shift Left (immediate).

UQSHL (register):

Unsigned saturating Shift Left (register).

UQSHRN, UQSHRN2:

Unsigned saturating Shift Right Narrow (immediate).

UQSUB:

Unsigned saturating Subtract.

USHL:

Unsigned Shift Left (register).

USHLL, USHLL2:

Unsigned Shift Left Long (immediate).

USHR:

Unsigned Shift Right (immediate).

USRA:

Unsigned Shift Right and Accumulate (immediate).

USUBL, USUBL2:

Unsigned Subtract Long.

USUBW, USUBW2:

Unsigned Subtract Wide.

UADDLV:

Unsigned sum Long across Vector.

SUQADD: Signed saturating Accumulate of

Unsigned value.

UZP1:

Unzip vectors (primary).

UZP2:

Unzip vectors (secondary).

SHA1C: SHA1 hash

update (choose).

SHA1M: SHA1 hash

update (majority).

SHA1P: SHA1 hash

update (parity).

SHA256H: SHA256 hash

update (part 1).

SHA256H2: SHA256 hash

update (part 2).

SHA1SU0: SHA1 schedule

update 0.

SHA256SU0: SHA256 schedule

update 0.

SHA1SU1: SHA1 schedule

update 1.

SHA256SU1: SHA256 schedule

update 1.

UQADD: Unsigned saturating Add.

UQRSHL: Unsigned saturating Rounding Shift Left (register).

UQRSHRN, UQRSHRN2: Unsigned saturating Rounded Shift Right Narrow (immediate).

UQRSHRN,

UQRSHRN2: Unsigned saturating Rounded Shift Right Narrow (immediate).

UQSHL (immediate): Unsigned saturating Shift Left (immediate).

UQSHL (register): Unsigned saturating Shift Left (register).

UQSHRN, UQSHRN2: Unsigned saturating Shift Right Narrow (immediate).

UQSHRN,

UQSHRN2: Unsigned saturating Shift Right Narrow (immediate).

UQSUB: Unsigned saturating Subtract.

UQXTN, UQXTN2: Unsigned saturating extract Narrow.

UQXTN,

UQXTN2: Unsigned saturating extract Narrow.

URECPE: Unsigned Reciprocal Estimate.

URHADD: Unsigned Rounding Halving Add.

URSHL: Unsigned Rounding Shift Left (register).

URSHR: Unsigned Rounding Shift Right (immediate).

URSQRTE: Unsigned Reciprocal Square Root Estimate.

URSRA: Unsigned Rounding Shift Right and Accumulate (immediate).

USHL: Unsigned Shift Left (register).

UXTL, UXTL2: Unsigned extend Long: an alias of

USHLL, USHLL2.

USHLL, USHLL2: Unsigned Shift Left Long (immediate).

UXTL, UXTL2: Unsigned extend Long: an alias of USHLL,

USHLL2.

USHLL,

USHLL2: Unsigned Shift Left Long (immediate).

USHR: Unsigned Shift Right (immediate).

FRINTI (scalar): Floating-point Round to Integral,

using current rounding mode (scalar).

FRINTX (scalar): Floating-point Round to Integral exact,

using current rounding mode (scalar).

FRINTI (vector): Floating-point Round to Integral,

using current rounding mode (vector).

FRINTX (vector): Floating-point Round to Integral exact,

using current rounding mode (vector).

USQADD: Unsigned saturating Accumulate of Signed value.

USRA: Unsigned Shift Right and Accumulate (immediate).

USUBL, USUBL2: Unsigned Subtract Long.

USUBL,

USUBL2: Unsigned Subtract Long.

USUBW, USUBW2: Unsigned Subtract Wide.

USUBW,

USUBW2: Unsigned Subtract Wide.

UXTB: Unsigned Extend Byte: an alias of UBFM.

UXTH: Unsigned Extend Halfword: an alias of UBFM.

UXTL, UXTL2: Unsigned extend Long: an alias of USHLL, USHLL2.

UXTL,

UXTL2: Unsigned extend Long: an alias of USHLL, USHLL2.

UZP1: Unzip vectors (primary).

UZP2: Unzip vectors (secondary).

ASRV: Arithmetic Shift Right

LSLV: Logical Shift Left

Variable.

LSRV: Logical Shift Right

Variable.

RORV: Rotate Right

Variable.

INS (element): Insert

vector element from another vector element.

INS (general): Insert

vector element from general-purpose register.

MOV (element): Move

vector element to another vector element: an alias of INS (element).

SMOV: Signed Move

vector element to general-purpose register.

UMOV: Unsigned Move

vector element to general-purpose register.

MOV (to general): Move

vector element to general-purpose register: an alias of UMOV.

MOV (scalar): Move

vector element to scalar: an alias of DUP (element).

DUP (element): Duplicate

vector element to vector or scalar.

INS (element): Insert vector element from another

vector element.

MOV (element): Move vector element to another

vector element: an alias of INS (element).

MOV (from general): Move general-purpose register to a

vector element: an alias of INS (general).

EXT: Extract

vector from pair of vectors.

TBX: Table

vector lookup extension.

TBL: Table

vector Lookup.

DUP (element): Duplicate vector element to

vector or scalar.

ABS: Absolute value (

vector).

ADD (vector): Add (

vector).

ADDP (vector): Add Pairwise (

vector).

AND (vector): Bitwise AND (

vector).

CLS (vector): Count Leading Sign bits (

vector).

CLZ (vector): Count Leading Zero bits (

vector).

CMEQ (register): Compare bitwise Equal (

vector).

CMEQ (zero): Compare bitwise Equal to zero (

vector).

CMGE (register): Compare signed Greater than or Equal (

vector).

CMGE (zero): Compare signed Greater than or Equal to zero (

vector).

CMGT (register): Compare signed Greater than (

vector).

CMGT (zero): Compare signed Greater than zero (

vector).

CMHI (register): Compare unsigned Higher (

vector).

CMHS (register): Compare unsigned Higher or Same (

vector).

CMLE (zero): Compare signed Less than or Equal to zero (

vector).

CMLT (zero): Compare signed Less than zero (

vector).

CMTST: Compare bitwise Test bits nonzero (

vector).

EOR (vector): Bitwise Exclusive OR (

vector).

FABD: Floating-point Absolute Difference (

vector).

FABS (vector): Floating-point Absolute value (

vector).

FACGE: Floating-point Absolute Compare Greater than or Equal (

vector).

FACGT: Floating-point Absolute Compare Greater than (

vector).

FADD (vector): Floating-point Add (

vector).

FADDP (vector): Floating-point Add Pairwise (

vector).

FCMEQ (register): Floating-point Compare Equal (

vector).

FCMEQ (zero): Floating-point Compare Equal to zero (

vector).

FCMGE (register): Floating-point Compare Greater than or Equal (

vector).

FCMGE (zero): Floating-point Compare Greater than or Equal to zero (

vector).

FCMGT (register): Floating-point Compare Greater than (

vector).

FCMGT (zero): Floating-point Compare Greater than zero (

vector).

FCMLE (zero): Floating-point Compare Less than or Equal to zero (

vector).

FCMLT (zero): Floating-point Compare Less than zero (

vector).

FCVTAS (vector): Floating-point Convert to Signed integer, rounding to nearest with ties to Away (

vector).

FCVTAU (vector): Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (

vector).

FCVTL, FCVTL2: Floating-point Convert to higher precision Long (

vector).

FCVTMS (vector): Floating-point Convert to Signed integer, rounding toward Minus infinity (

vector).

FCVTMU (vector): Floating-point Convert to Unsigned integer, rounding toward Minus infinity (

vector).

FCVTN, FCVTN2: Floating-point Convert to lower precision Narrow (

vector).

FCVTNS (vector): Floating-point Convert to Signed integer, rounding to nearest with ties to even (

vector).

FCVTNU (vector): Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (

vector).

FCVTPS (vector): Floating-point Convert to Signed integer, rounding toward Plus infinity (

vector).

FCVTPU (vector): Floating-point Convert to Unsigned integer, rounding toward Plus infinity (

vector).

FCVTXN, FCVTXN2: Floating-point Convert to lower precision Narrow, rounding to odd (

vector).

FCVTZS (vector, fixed-point): Floating-point Convert to Signed fixed-point, rounding toward Zero (

vector).

FCVTZS (vector, integer): Floating-point Convert to Signed integer, rounding toward Zero (

vector).

FCVTZU (vector, fixed-point): Floating-point Convert to Unsigned fixed-point, rounding toward Zero (

vector).

FCVTZU (vector, integer): Floating-point Convert to Unsigned integer, rounding toward Zero (

vector).

FDIV (vector): Floating-point Divide (

vector).

FMAX (vector): Floating-point Maximum (

vector).

FMAXNM (vector): Floating-point Maximum Number (

vector).

FMAXNMP (vector): Floating-point Maximum Number Pairwise (

vector).

FMAXP (vector): Floating-point Maximum Pairwise (

vector).

FMIN (vector): Floating-point minimum (

vector).

FMINNM (vector): Floating-point Minimum Number (

vector).

FMINNMP (vector): Floating-point Minimum Number Pairwise (

vector).

FMINP (vector): Floating-point Minimum Pairwise (

vector).

FMLA (vector): Floating-point fused Multiply-Add to accumulator (

vector).

FMLS (vector): Floating-point fused Multiply-Subtract from accumulator (

vector).

FMOV (vector, immediate): Floating-point move immediate (

vector).

FMUL (vector): Floating-point Multiply (

vector).

FNEG (vector): Floating-point Negate (

vector).

FRINTA (vector): Floating-point Round to Integral, to nearest with ties to Away (

vector).

FRINTI (vector): Floating-point Round to Integral, using current rounding mode (

vector).

FRINTM (vector): Floating-point Round to Integral, toward Minus infinity (

vector).

FRINTN (vector): Floating-point Round to Integral, to nearest with ties to even (

vector).

FRINTP (vector): Floating-point Round to Integral, toward Plus infinity (

vector).

FRINTX (vector): Floating-point Round to Integral exact, using current rounding mode (

vector).

FRINTZ (vector): Floating-point Round to Integral, toward Zero (

vector).

FSQRT (vector): Floating-point Square Root (

vector).

FSUB (vector): Floating-point Subtract (

vector).

MLA (vector): Multiply-Add to accumulator (

vector).

MLS (vector): Multiply-Subtract from accumulator (

vector).

MOVI: Move Immediate (

vector).

MUL (vector): Multiply (

vector).

MVNI: Move inverted Immediate (

vector).

NEG (vector): Negate (

vector).

NOT: Bitwise NOT (

vector).

ORN (vector): Bitwise inclusive OR NOT (

vector).

RBIT (vector): Reverse Bit order (

vector).

REV16 (vector): Reverse elements in 16-bit halfwords (

vector).

REV32 (vector): Reverse elements in 32-bit words (

vector).

REV64: Reverse elements in 64-bit doublewords (

vector).

SADDL, SADDL2: Signed Add Long (

vector).

SCVTF (vector, fixed-point): Signed fixed-point Convert to Floating-point (

vector).

SCVTF (vector, integer): Signed integer Convert to Floating-point (

vector).

SMAX: Signed Maximum (

vector).

SMIN: Signed Minimum (

vector).

SMLAL, SMLAL2 (vector): Signed Multiply-Add Long (

vector).

SMLSL, SMLSL2 (vector): Signed Multiply-Subtract Long (

vector).

SMULL, SMULL2 (vector): Signed Multiply Long (

vector).

SQRDMLAH (vector): Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (

vector).

SQRDMLSH (vector): Signed Saturating Rounding Doubling Multiply Subtract returning High Half (

vector).

SUB (vector): Subtract (

vector).

UABD: Unsigned Absolute Difference (

vector).

UADDL, UADDL2: Unsigned Add Long (

vector).

UCVTF (vector, fixed-point): Unsigned fixed-point Convert to Floating-point (

vector).

UCVTF (vector, integer): Unsigned integer Convert to Floating-point (

vector).

UMAX: Unsigned Maximum (

vector).

UMIN: Unsigned Minimum (

vector).

UMLAL, UMLAL2 (vector): Unsigned Multiply-Add Long (

vector).

UMLSL, UMLSL2 (vector): Unsigned Multiply-Subtract Long (

vector).

UMULL, UMULL2 (vector): Unsigned Multiply long (

vector).

ADD (

vector): Add (vector).

ADDP (

vector): Add Pairwise (vector).

MVN: Bitwise NOT (

vector): an alias of NOT.

vector): Bitwise AND (vector).

vector): Bitwise Exclusive OR (vector).

vector): Bitwise inclusive OR NOT (vector).

CLS (

vector): Count Leading Sign bits (vector).

CLZ (

vector): Count Leading Zero bits (vector).

FABS (

vector): Floating-point Absolute value (vector).

FADD (

vector): Floating-point Add (vector).

FADDP (

vector): Floating-point Add Pairwise (vector).

FCVTAS (

vector): Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector).

FCVTNS (

vector): Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector).

FCVTMS (

vector): Floating-point Convert to Signed integer, rounding toward Minus infinity (vector).

FCVTPS (

vector): Floating-point Convert to Signed integer, rounding toward Plus infinity (vector).

FCVTAU (

vector): Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector).

FCVTNU (

vector): Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector).

FCVTMU (

vector): Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector).

FCVTPU (

vector): Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector).

FDIV (

vector): Floating-point Divide (vector).

FMLA (

vector): Floating-point fused Multiply-Add to accumulator (vector).

FMLS (

vector): Floating-point fused Multiply-Subtract from accumulator (vector).

FMAX (

vector): Floating-point Maximum (vector).

FMAXNM (

vector): Floating-point Maximum Number (vector).

FMAXNMP (

vector): Floating-point Maximum Number Pairwise (vector).

FMAXP (

vector): Floating-point Maximum Pairwise (vector).

FMIN (

vector): Floating-point minimum (vector).

FMINNM (

vector): Floating-point Minimum Number (vector).

FMINNMP (

vector): Floating-point Minimum Number Pairwise (vector).

FMINP (

vector): Floating-point Minimum Pairwise (vector).

FMUL (

vector): Floating-point Multiply (vector).

FNEG (

vector): Floating-point Negate (vector).

FRINTX (

vector): Floating-point Round to Integral exact, using current rounding mode (vector).

FRINTA (

vector): Floating-point Round to Integral, to nearest with ties to Away (vector).

FRINTN (

vector): Floating-point Round to Integral, to nearest with ties to even (vector).

FRINTM (

vector): Floating-point Round to Integral, toward Minus infinity (vector).

FRINTP (

vector): Floating-point Round to Integral, toward Plus infinity (vector).

FRINTZ (

vector): Floating-point Round to Integral, toward Zero (vector).

FRINTI (

vector): Floating-point Round to Integral, using current rounding mode (vector).

FSQRT (

vector): Floating-point Square Root (vector).

FSUB (

vector): Floating-point Subtract (vector).

MOV (

vector): Move vector: an alias of ORR (vector, register).

vector): Multiply (vector).

vector): Multiply-Add to accumulator (vector).

vector): Multiply-Subtract from accumulator (vector).

NEG (

vector): Negate (vector).

RBIT (

vector): Reverse Bit order (vector).

vector): Reverse elements in 16-bit halfwords (vector).

vector): Reverse elements in 32-bit words (vector).

vector): Signed Multiply Long (vector).

vector): Signed Multiply-Add Long (vector).

vector): Signed Multiply-Subtract Long (vector).

vector): Signed saturating Doubling Multiply Long.

SQDMULH (

vector): Signed saturating Doubling Multiply returning High half.

vector): Signed saturating Doubling Multiply-Add Long.

vector): Signed saturating Doubling Multiply-Subtract Long.

SQRDMLAH (

vector): Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (vector).

SQRDMULH (

vector): Signed saturating Rounding Doubling Multiply returning High half.

SQRDMLSH (

vector): Signed Saturating Rounding Doubling Multiply Subtract returning High Half (vector).

SUB (

vector): Subtract (vector).

vector): Unsigned Multiply long (vector).

vector): Unsigned Multiply-Add Long (vector).

vector): Unsigned Multiply-Subtract Long (vector).

MLA (by element): Multiply-Add to accumulator (

vector, by element).

MLS (by element): Multiply-Subtract from accumulator (

vector, by element).

MUL (by element): Multiply (

vector, by element).

SMLAL, SMLAL2 (by element): Signed Multiply-Add Long (

vector, by element).

SMLSL, SMLSL2 (by element): Signed Multiply-Subtract Long (

vector, by element).

SMULL, SMULL2 (by element): Signed Multiply Long (

vector, by element).

UMLAL, UMLAL2 (by element): Unsigned Multiply-Add Long (

vector, by element).

UMLSL, UMLSL2 (by element): Unsigned Multiply-Subtract Long (

vector, by element).

UMULL, UMULL2 (by element): Unsigned Multiply Long (

vector, by element).

FCVTZS (

vector, fixed-point): Floating-point Convert to Signed fixed-point, rounding toward Zero (vector).

FCVTZU (

vector, fixed-point): Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector).

SCVTF (

vector, fixed-point): Signed fixed-point Convert to Floating-point (vector).

UCVTF (

vector, fixed-point): Unsigned fixed-point Convert to Floating-point (vector).

BIC (vector, immediate): Bitwise bit Clear (

vector, immediate).

ORR (vector, immediate): Bitwise inclusive OR (

vector, immediate).

vector, immediate): Bitwise bit Clear (vector, immediate).

vector, immediate): Bitwise inclusive OR (vector, immediate).

vector, immediate): Floating-point move immediate (vector).

FCVTZS (

vector, integer): Floating-point Convert to Signed integer, rounding toward Zero (vector).

FCVTZU (

vector, integer): Floating-point Convert to Unsigned integer, rounding toward Zero (vector).

SCVTF (

vector, integer): Signed integer Convert to Floating-point (vector).

UCVTF (

vector, integer): Unsigned integer Convert to Floating-point (vector).

BIC (vector, register): Bitwise bit Clear (

vector, register).

MOV (vector): Move vector: an alias of ORR (

vector, register).

ORR (vector, register): Bitwise inclusive OR (

vector, register).

vector, register): Bitwise bit Clear (vector, register).

vector, register): Bitwise inclusive OR (vector, register).

ADDV: Add across

Vector.

DUP (general): Duplicate general-purpose register to

vector.

FMAXNMV: Floating-point Maximum Number across

Vector.

FMAXV: Floating-point Maximum across

Vector.

FMINNMV: Floating-point Minimum Number across

Vector.

FMINV: Floating-point Minimum across

Vector.

SADDLV: Signed Add Long across

Vector.

SMAXV: Signed Maximum across

Vector.

SMINV: Signed Minimum across

Vector.

UADDLV: Unsigned sum Long across

Vector.

UMAXV: Unsigned Maximum across

Vector.

UMINV: Unsigned Minimum across

Vector.

MOV (vector): Move

vector: an alias of ORR (vector, register).

TRN1: Transpose

vectors (primary).

UZP1: Unzip

vectors (primary).

ZIP1: Zip

vectors (primary).

TRN2: Transpose

vectors (secondary).

UZP2: Unzip

vectors (secondary).

ZIP2: Zip

vectors (secondary).

EXT: Extract vector from pair of

vectors.

WFE:

WFI:

Wait For Interrupt.

WFE: Wait For Event.

WFI: Wait For Interrupt.

MOV (inverted wide immediate): Move (inverted

wide immediate): an alias of MOVN.

MOV (wide immediate): Move (

wide immediate): an alias of MOVZ.

MOV (inverted

wide immediate): Move (inverted wide immediate): an alias of MOVN.

MOV (

wide immediate): Move (wide immediate): an alias of MOVZ.

MOVK: Move

wide with keep.

MOVN: Move

wide with NOT.

MOVZ: Move

wide with zero.

SADDW, SADDW2: Signed Add

Wide.

SSUBW, SSUBW2: Signed Subtract

Wide.

UADDW, UADDW2: Unsigned Add

Wide.

USUBW, USUBW2: Unsigned Subtract

Wide.

FMOV (general): Floating-point Move to or from general-purpose register

without conversion.

FMOV (register): Floating-point Move register

without conversion.

STADD, STADDL: Atomic add on word or doubleword in memory,

without return.

STADDB, STADDLB: Atomic add on byte in memory,

without return.

STADDH, STADDLH: Atomic add on halfword in memory,

without return.

STCLR, STCLRL: Atomic bit clear on word or doubleword in memory,

without return.

STCLRB, STCLRLB: Atomic bit clear on byte in memory,

without return.

STCLRH, STCLRLH: Atomic bit clear on halfword in memory,

without return.

STEOR, STEORL: Atomic exclusive OR on word or doubleword in memory,

without return.

STEORB, STEORLB: Atomic exclusive OR on byte in memory,

without return.

STEORH, STEORLH: Atomic exclusive OR on halfword in memory,

without return.

STSET, STSETL: Atomic bit set on word or doubleword in memory,

without return.

STSETB, STSETLB: Atomic bit set on byte in memory,

without return.

STSETH, STSETLH: Atomic bit set on halfword in memory,

without return.

STSMAX, STSMAXL: Atomic signed maximum on word or doubleword in memory,

without return.

STSMAXB, STSMAXLB: Atomic signed maximum on byte in memory,

without return.

STSMAXH, STSMAXLH: Atomic signed maximum on halfword in memory,

without return.

STSMIN, STSMINL: Atomic signed minimum on word or doubleword in memory,

without return.

STSMINB, STSMINLB: Atomic signed minimum on byte in memory,

without return.

STSMINH, STSMINLH: Atomic signed minimum on halfword in memory,

without return.

STUMAX, STUMAXL: Atomic unsigned maximum on word or doubleword in memory,

without return.

STUMAXB, STUMAXLB: Atomic unsigned maximum on byte in memory,

without return.

STUMAXH, STUMAXLH: Atomic unsigned maximum on halfword in memory,

without return.

STUMIN, STUMINL: Atomic unsigned minimum on word or doubleword in memory,

without return.

STUMINB, STUMINLB: Atomic unsigned minimum on byte in memory,

without return.

STUMINH, STUMINLH: Atomic unsigned minimum on halfword in memory,

without return.

LDRSW (immediate): Load Register Signed

Word (immediate).

LDRSW (literal): Load Register Signed

Word (literal).

LDRSW (register): Load Register Signed

Word (register).

LDTRSW: Load Register Signed

Word (unprivileged).

LDURSW: Load Register Signed

Word (unscaled).

STADD, STADDL: Atomic add on

word or doubleword in memory, without return.

STCLR, STCLRL: Atomic bit clear on

word or doubleword in memory, without return.

STEOR, STEORL: Atomic exclusive OR on

word or doubleword in memory, without return.

STSET, STSETL: Atomic bit set on

word or doubleword in memory, without return.

STSMAX, STSMAXL: Atomic signed maximum on

word or doubleword in memory, without return.

STSMIN, STSMINL: Atomic signed minimum on

word or doubleword in memory, without return.

STUMAX, STUMAXL: Atomic unsigned maximum on

word or doubleword in memory, without return.

STUMIN, STUMINL: Atomic unsigned minimum on

word or doubleword in memory, without return.

CAS, CASA, CASAL, CASL: Compare and Swap

word or doubleword in memory.

word or doubleword in memory.

LDCLR, LDCLRA, LDCLRAL, LDCLRL: Atomic bit clear on

word or doubleword in memory.

LDEOR, LDEORA, LDEORAL, LDEORL: Atomic exclusive OR on

word or doubleword in memory.

LDSET, LDSETA, LDSETAL, LDSETL: Atomic bit set on

word or doubleword in memory.

LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL: Atomic signed maximum on

word or doubleword in memory.

LDSMIN, LDSMINA, LDSMINAL, LDSMINL: Atomic signed minimum on

word or doubleword in memory.

LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL: Atomic unsigned maximum on

word or doubleword in memory.

LDUMIN, LDUMINA, LDUMINAL, LDUMINL: Atomic unsigned minimum on

word or doubleword in memory.

word or doubleword in memory.

LDPSW: Load Pair of Registers Signed

Word.

SXTW: Sign Extend

Word: an alias of SBFM.

REV32 (vector): Reverse elements in 32-bit

words (vector).

CASP, CASPA, CASPAL, CASPL: Compare and Swap Pair of

words or doublewords in memory.

REV32: Reverse bytes in 32-bit

words.

XTN,

XTN2: Extract Narrow.

YIELD: YIELD.

FCVTZS (scalar, fixed-point): Floating-point Convert to Signed fixed-point, rounding toward

FCVTZS (scalar, integer): Floating-point Convert to Signed integer, rounding toward

Zero (scalar).

FCVTZU (scalar, fixed-point): Floating-point Convert to Unsigned fixed-point, rounding toward

Zero (scalar).

FCVTZU (scalar, integer): Floating-point Convert to Unsigned integer, rounding toward

Zero (scalar).

FRINTZ (scalar): Floating-point Round to Integral, toward

Zero (scalar).

CMEQ (zero): Compare bitwise Equal to

zero (vector).

CMGE (zero): Compare signed Greater than or Equal to

zero (vector).

CMGT (zero): Compare signed Greater than

zero (vector).

CMLE (zero): Compare signed Less than or Equal to

zero (vector).

CMLT (zero): Compare signed Less than

zero (vector).

FCMEQ (zero): Floating-point Compare Equal to

zero (vector).

FCMGE (zero): Floating-point Compare Greater than or Equal to

zero (vector).

FCMGT (zero): Floating-point Compare Greater than

zero (vector).

FCMLE (zero): Floating-point Compare Less than or Equal to

zero (vector).

FCMLT (zero): Floating-point Compare Less than

zero (vector).

FCVTZS (vector, fixed-point): Floating-point Convert to Signed fixed-point, rounding toward

Zero (vector).

FCVTZS (vector, integer): Floating-point Convert to Signed integer, rounding toward

Zero (vector).

FCVTZU (vector, fixed-point): Floating-point Convert to Unsigned fixed-point, rounding toward

Zero (vector).

FCVTZU (vector, integer): Floating-point Convert to Unsigned integer, rounding toward

Zero (vector).

FRINTZ (vector): Floating-point Round to Integral, toward

Zero (vector).

CLZ (vector): Count Leading

Zero bits (vector).

CLZ: Count leading

zero bits.

CMEQ (

zero): Compare bitwise Equal to zero (vector).

CMGE (

zero): Compare signed Greater than or Equal to zero (vector).

CMGT (

zero): Compare signed Greater than zero (vector).

CMLE (

zero): Compare signed Less than or Equal to zero (vector).

CMLT (

zero): Compare signed Less than zero (vector).

FCMEQ (

zero): Floating-point Compare Equal to zero (vector).

FCMGE (

zero): Floating-point Compare Greater than or Equal to zero (vector).

FCMGT (

zero): Floating-point Compare Greater than zero (vector).

FCMLE (

zero): Floating-point Compare Less than or Equal to zero (vector).

FCMLT (

zero): Floating-point Compare Less than zero (vector).

CBZ: Compare and Branch on

Zero.

MOVZ: Move wide with

zero.

TBZ: Test bit and Branch if

Zero.

SBFIZ: Signed Bitfield Insert in

Zero: an alias of SBFM.

UBFIZ: Unsigned Bitfield Insert in

Zero: an alias of UBFM.

ZIP1:

Zip vectors (primary).

ZIP2:

Zip vectors (secondary).

ZIP1: Zip vectors (primary).

ZIP2: Zip vectors (secondary).


Internal version only: isa v25.07, AdvSIMD v23.0, pseudocode v31.3

Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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