ISA_v83A_A64_xml_00bet6.1 (old)htmldiff from-ISA_v83A_A64_xml_00bet6.1(new) ISA_v84A_A64_xml_00bet7

SHA1H

SHA1 fixed rotate.

SHA1 fixed rotate.

313029282726252423222120191817161514131211109876543210
0101111000101000000010RnRd

Advanced SIMD

SHA1H <Sd>, <Sn>

integer d = UInt(Rd); integer n = UInt(Rn); if !HaveSHA1ExtHaveCryptoExt() then UnallocatedEncoding();

Assembler Symbols

<Sd>

Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Sn>

Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field.

Operation

AArch64.CheckFPAdvSIMDEnabledCheckCryptoEnabled64(); bits(32) operand = V[n]; // read element [0] only, [1-3] zeroed V[d] = ROL(operand, 30);

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v29.05v27.02, AdvSIMD v26.0, pseudocode v35.3v34.2.2 ; Build timestamp: 2018-06-16T092018-03-28T19:4555

Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.

ISA_v83A_A64_xml_00bet6.1 (old)htmldiff from-ISA_v83A_A64_xml_00bet6.1(new) ISA_v84A_A64_xml_00bet7