ISA_v83A_A64_xml_00bet6.1 (old) | htmldiff from-ISA_v83A_A64_xml_00bet6.1 | (new) ISA_v84A_A64_xml_00bet7 |
Floating-point Minimum Number across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values.
NaNs are handled according to the IEEE 754-2008 standard. If one vector element is numeric and the other is a quiet NaN, the result of the comparison is the numerical value, otherwise the result is identical to FMIN (scalar).
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 2 classes: Half-precision and Single-precision and double-precision
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | Rn | Rd | ||||||||
o1 |
if !HaveFP16Ext() then UnallocatedEncoding(); integer d = UInt(Rd); integer n = UInt(Rn); integer esize = 16; integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; ReduceOp op = if o1 == '1' then ReduceOp_FMINNUM else ReduceOp_FMAXNUM;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | Q | 1 | 0 | 1 | 1 | 1 | 0 | 1 | sz | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | Rn | Rd | ||||||||
o1 |
integer d = UInt(Rd); integer n = UInt(Rn); if sz:Q != '01' then ReservedValue(); // .4S only integer esize = 32 << UInt(sz); integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; ReduceOp op = if o1 == '1' then ReduceOp_FMINNUM else ReduceOp_FMAXNUM;
<V> | For the half-precision variant: is the destination width specifier, H. | ||||||||||||
sz:
|
<d> | Is the number of the SIMD&FP destination register, encoded in the "Rd" field. |
<Vn> | Is the name of the SIMD&FP source register, encoded in the "Rn" field. |
<T> |
Q:
| ||||||||||||||||||||||||
Q:sz:
|
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; V[d] = Reduce(op, operand, esize);
Internal version only: isa v29.05v27.02, AdvSIMD v26.0, pseudocode v35.3v34.2.2
; Build timestamp: 2018-06-16T092018-03-28T19:4555
Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.
ISA_v83A_A64_xml_00bet6.1 (old) | htmldiff from-ISA_v83A_A64_xml_00bet6.1 | (new) ISA_v84A_A64_xml_00bet7 |