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SQDMULH (by element)

Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

The results are truncated. For rounded results, see SQRDMULH.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 2 classes: Scalar and Vector

Scalar

313029282726252423222120191817161514131211109876543210
01011111sizeLMRm1100H0RnRd
op

Scalar

SQDMULH <V><d>, <V><n>, <Vm>.<Ts>[<index>]

integer idxdsize = if H == '1' then 128 else 64; integer index; bit Rmhi; case size of when '01' index = UInt(H:L:M); Rmhi = '0'; when '10' index = UInt(H:L); Rmhi = M; otherwise UnallocatedEncoding(); integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rmhi:Rm); integer esize = 8 << UInt(size); integer datasize = esize; integer elements = 1; boolean round = (op == '1');

Vector

313029282726252423222120191817161514131211109876543210
0Q001111sizeLMRm1100H0RnRd
op

Vector

SQDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]

integer idxdsize = if H == '1' then 128 else 64; integer index; bit Rmhi; case size of when '01' index = UInt(H:L:M); Rmhi = '0'; when '10' index = UInt(H:L); Rmhi = M; otherwise UnallocatedEncoding(); integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rmhi:Rm); integer esize = 8 << UInt(size); integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; boolean round = (op == '1');

Assembler Symbols

<V> Is a width specifier, encoded in size:
size<V>
00RESERVED
01H
10S
11RESERVED
Is a width specifier, encoded in size:
size<V>
00RESERVED
01H
10S
11RESERVED
<d>

Is the number of the SIMD&FP destination register, encoded in the "Rd" field.

<n>

Is the number of the first SIMD&FP source register, encoded in the "Rn" field.

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T> Is an arrangement specifier, encoded in size:Q:
sizeQ<T>
00xRESERVED
0104H
0118H
1002S
1014S
11xRESERVED
Is an arrangement specifier, encoded in size:Q:
sizeQ<T>
00xRESERVED
0104H
0118H
1002S
1014S
11xRESERVED
<Vn>

Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm> Is the name of the second SIMD&FP source register, encoded in size:M:Rm:
size<Vm>
00RESERVED
010:Rm
10M:Rm
11RESERVED
Restricted to V0-V15 when element size <Ts> is H.
Is the name of the second SIMD&FP source register, encoded in size:M:Rm:
size<Vm>
00RESERVED
010:Rm
10M:Rm
11RESERVED
Restricted to V0-V15 when element size <Ts> is H.
<Ts> Is an element size specifier, encoded in size:
size<Ts>
00RESERVED
01H
10S
11RESERVED
Is an element size specifier, encoded in size:
size<Ts>
00RESERVED
01H
10S
11RESERVED
<index> Is the element index, encoded in size:L:H:M:
size<index>
00RESERVED
01H:L:M
10H:L
11RESERVED
Is the element index, encoded in size:L:H:M:
size<index>
00RESERVED
01H:L:M
10H:L
11RESERVED

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(idxdsize) operand2 = V[m]; bits(datasize) result; integer round_const = if round then 1 << (esize - 1) else 0; integer element1; integer element2; integer product; boolean sat; element2 = SInt(Elem[operand2, index, esize]); for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); product = (2 * element1 * element2) + round_const; // The following only saturates if element1 and element2 equal -(2^(esize-1)) (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize); if sat then FPSR.QC = '1'; V[d] = result;


Internal version only: isa v29.05v27.02, AdvSIMD v26.0, pseudocode v35.3v34.2.2 ; Build timestamp: 2018-06-16T092018-03-28T19:4555

Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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