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Physical Speculative Store Bypass Barrier is a memory barrier which prevents speculative loads from bypassing earlier stores to the same physical address.
The semantics of the Physical Speculative Store Bypass Barrier are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
CRm | opc |
MemBarrierOp op;
MBReqDomain domain;
MBReqTypes types;
case opc of
when '00' op = MemBarrierOp_DSB;
when '01' op = MemBarrierOp_DMB;
when '10' op = MemBarrierOp_ISB;
otherwise UnallocatedEncoding();
case CRm<3:2> of
when '00' domain = MBReqDomain_OuterShareable;
when '01' domain = MBReqDomain_Nonshareable;
when '10' domain = MBReqDomain_InnerShareable;
when '11' domain = MBReqDomain_FullSystem;
case CRm<1:0> of
when '01' types = MBReqTypes_Reads;
when '10' types = MBReqTypes_Writes;
when '11' types = MBReqTypes_All;
otherwise
if CRm<3:2> == '00' then
op = MemBarrierOp_SSBB;
elsif CRm<3:2> == '01' then
op = MemBarrierOp_PSSBB;
else
types = MBReqTypes_All;
domain = MBReqDomain_FullSystem// Empty.;
case op of
when MemBarrierOp_DSBDataSynchronizationBarrier(domain, types);
when MemBarrierOp_DMBDataMemoryBarrier(domain, types);
when MemBarrierOp_ISBInstructionSynchronizationBarrier();
when MemBarrierOp_SSBBSpeculativeSynchronizationBarrierToVA();
when MemBarrierOp_PSSBBSpeculativeSynchronizationBarrierToPA();
Internal version only: isa v29.05, AdvSIMD v26.0, pseudocode v35.3
; Build timestamp: 2018-06-16T09:5845
Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.
ISA_v84A_A64_xml_00bet7 (old) | htmldiff from-ISA_v84A_A64_xml_00bet7 | (new) ISA_v84A_A64_xml_00bet7_OPT |