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Bitfield Insert copies aany bitfieldnumber of <width>low-order bits from a source register into the leastsame significantnumber bits of theadjacent sourcebits registerat toany bit position <lsb>in of the destination register, leaving the other destination bits unchanged.
This is an alias of BFM. This means:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
sf | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | N | immr | imms | != 11111 | Rd | ||||||||||||||||||
opc | Rn |
BFI <Wd>, <Wn>, #<lsb>, #<width>
is equivalent to
BFM <Wd>, <Wn>, #(-<lsb> MOD 32), #(<width>-1)
and is the preferred disassembly when UInt(imms) < UInt(immr).
BFI <Xd>, <Xn>, #<lsb>, #<width>
is equivalent to
BFM <Xd>, <Xn>, #(-<lsb> MOD 64), #(<width>-1)
and is the preferred disassembly when UInt(imms) < UInt(immr).
<Wd> | Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. |
<Wn> | Is the 32-bit name of the general-purpose source register, encoded in the "Rn" field. |
<Xd> | Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field. |
<Xn> | Is the 64-bit name of the general-purpose source register, encoded in the "Rn" field. |
<width> | For the 32-bit variant: is the width of the bitfield, in the range 1 to 32-<lsb>. |
For the 64-bit variant: is the width of the bitfield, in the range 1 to 64-<lsb>. |
The description of BFM gives the operational pseudocode for this instruction.
If PSTATE.DIT is 1:
Internal version only: isa v29.05v27.02, AdvSIMD v26.0, pseudocode v35.3v34.2.2
; Build timestamp: 2018-06-16T092018-03-28T19:4555
Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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