A64 ISA XML for ARMv8.4
(00bet7)
15th June 2018
1. Introduction
This is the 00bet7
release of the A64 ISA XML for ARMv8.4.
The Proprietary Notice
gives details of the terms and conditions under which this package
is provided.
If you have comments on the content of this package, please send
them by e-mail to
support-aarchv8@arm.com.
Give:
- The title, "A64 ISA XML for ARMv8.4".
- The version, "00bet7".
- A concise explanation of your comments.
2. Contents
3. Release Notes
Change history
The following general changes are made:
-
Added support for ARMv8.4.
-
Added SSBB and PSSBB.
-
The Permuted Index is removed.
The following changes are made to the instruction definitions:
-
Crypto instructions from ARMv8.2-SHA and ARMv8.2-SM are corrected
to add a call to AArch64.CheckFPAdvSIMDEnabled() at the start, to
check the accessibility of SIMD&FP registers.
-
All crypto instructions are adjusted such that the calls to
functions HaveCryptoExt(), HaveCryptoExt2() and HaveChCryptoExt()
are replaced with calls to new functions, each describing one
family of crypto instructions.
The following changes are made to the Shared Pseudocode:
-
A comment is added to FPMax() and FPMin() functions, to clarify
that the use of FPRound() is needed to cover the case where there
is a trapped underflow exception for a denormalized number even
though the result is exact.
-
The function AArch64. CheckPermission() is corrected for
permission checking during Stage 1 address translation is adjusted
to specify that DC maintenance instructions operating by VA cannot
fault from Stage 1 translation, other than DC IVAC, which requires
write permission, and operations executed at EL0, which require
read permission.
-
The function AArch64.TranslationTableWalk() is corrected for page
table walk during address translation, to determine the reserved
value of physical address size in TCR_ELx.IPS as an
IMPLEMENTATION_DEFINED choice between a value of '101' or '110'.
-
The function PMPCSR[] related to PC Sample-based Profiling is
adjusted to specify the cases where PMVIDSR.VMID is UNKNOWN.
-
The function AArch64.TranslationTableWalk() is adjusted such that
Bit[6] of the address translation Block and Page descriptor, which
is AP[1], is treated as '0' irrespective of the actual programmed
value when HCR_EL2.{NV, NV1} == {1,1} for first stage only.
-
The function AArch32.FirstStageTranslate() is adjusted to revert
the override effect of HCR.DC on SCTLR.M when executing in
Non-secure EL1 or EL0 mode, if EL2 is not present. This is because
HCR does not exist if EL2 is not present.
-
The function CheckSystemAccessEL2Traps() is adjusted to trap the
access to system registers ID_ISAR6 and TTBCR2, when accessed from
EL0 or EL1, when control bit HCR.TID3 or any bit amongst HCR.TVM
or HCR.TVRM is set respectively.
Known issues
-
The PC Sample-based Profiling Extension is not fully described, so
the changes to this area in ARMv8.2 are not implemented.
-
The encoding diagram for "LSL (immediate)" shows the field "imms"
in bits[15:10] as "!= x11111". This is incorrect because the 64
bit variant permits the value "011111", therefore this condition
will be removed.
-
The description for HINT overlaps with other defined instructions.