ISA_v84A_A64_xml_00bet7 (old) | htmldiff from-ISA_v84A_A64_xml_00bet7 | (new) ISA_v84A_A64_xml_00bet7_OPT |
Hint instruction is for the instruction set space that is reserved for architectural hint instructions.
Some encodings described here are not allocated in this revision of the architecture, and behave as NOPs. These encodings might be allocated to other hint functionality in future revisions of the architecture and therefore must not be used by software.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | CRm | op2 | 1 | 1 | 1 | 1 | 1 |
HINT #<imm>
SystemHintOp op;
case CRm:op2 of
when '0000 000' op = SystemHintOp_NOP;
when '0000 001' op = SystemHintOp_YIELD;
when '0000 010' op = SystemHintOp_WFE;
when '0000 011' op = SystemHintOp_WFI;
when '0000 100' op = SystemHintOp_SEV;
when '0000 101' op = SystemHintOp_SEVL;
when '0000 111'
SEE "XPACLRI";
when '0001 xxx'
SEE "PACIA1716, PACIB1716, AUTIA1716, AUTIB1716";
when '0010 000'
if !HaveRASExt() then EndOfInstruction(); // Instruction executes as NOP
op = SystemHintOp_ESB;
when '0010 001'
if !HaveStatisticalProfiling() then EndOfInstruction(); // Instruction executes as NOP
op = SystemHintOp_PSB;
when '0010 010'
if !HaveSelfHostedTrace() then EndOfInstruction(); // Instruction executes as NOP
op = SystemHintOp_TSB;
when '0010 100'
op = SystemHintOp_CSDB;
when '0011 xxx'
SEE "PACIAZ, PACIASP, PACIBZ, PACIBSP, AUTIAZ, AUTIASP, AUTIBZ, AUTIBSP";
otherwise EndOfInstruction();(); // Instruction executes as NOP
case op of when SystemHintOp_YIELDHint_Yield(); when SystemHintOp_WFE if IsEventRegisterSet() then ClearEventRegister(); else if PSTATE.EL == EL0 then // Check for traps described by the OS which may be EL1 or EL2. AArch64.CheckForWFxTrap(EL1, TRUE); if EL2Enabled() && PSTATE.EL IN {EL0, EL1} && !IsInHost() then // Check for traps described by the Hypervisor. AArch64.CheckForWFxTrap(EL2, TRUE); if HaveEL(EL3) && PSTATE.EL != EL3 then // Check for traps described by the Secure Monitor. AArch64.CheckForWFxTrap(EL3, TRUE); WaitForEvent(); when SystemHintOp_WFI if !InterruptPending() then if PSTATE.EL == EL0 then // Check for traps described by the OS which may be EL1 or EL2. AArch64.CheckForWFxTrap(EL1, FALSE); if EL2Enabled() && PSTATE.EL IN {EL0, EL1} && !IsInHost() then // Check for traps described by the Hypervisor. AArch64.CheckForWFxTrap(EL2, FALSE); if HaveEL(EL3) && PSTATE.EL != EL3 then // Check for traps described by the Secure Monitor. AArch64.CheckForWFxTrap(EL3, FALSE); WaitForInterrupt(); when SystemHintOp_SEVSendEvent(); when SystemHintOp_SEVLSendEventLocal(); when SystemHintOp_ESBSynchronizeErrors(); AArch64.ESBOperation(); if EL2Enabled() && PSTATE.EL IN {EL0, EL1} then AArch64.vESBOperation(); TakeUnmaskedSErrorInterrupts(); when SystemHintOp_PSBProfilingSynchronizationBarrier(); when SystemHintOp_TSB TraceSynchronizationBarrier(); when SystemHintOp_CSDBConsumptionOfSpeculativeDataBarrier(); otherwise // do nothing
Internal version only: isa v29.05, AdvSIMD v26.0, pseudocode v35.3
; Build timestamp: 2018-06-16T09:5845
Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.
ISA_v84A_A64_xml_00bet7 (old) | htmldiff from-ISA_v84A_A64_xml_00bet7 | (new) ISA_v84A_A64_xml_00bet7_OPT |