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FSQRT (vector)

Floating-point Square Root (vector). This instruction calculates the square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 2 classes: Half-precision and Single-precision and double-precision

Half-precision
(ARMv8.2)

313029282726252423222120191817161514131211109876543210
0Q10111011111001111110RnRd

Half-precision

FSQRT <Vd>.<T>, <Vn>.<T>

if !HaveFP16Ext() then UnallocatedEncoding(); integer d = UInt(Rd); integer n = UInt(Rn); integer esize = 16; integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize;

Single-precision and double-precision

313029282726252423222120191817161514131211109876543210
0Q1011101sz100001111110RnRd

Single-precision and double-precision

FSQRT <Vd>.<T>, <Vn>.<T>

integer d = UInt(Rd); integer n = UInt(Rn); if sz:Q == '10' then ReservedValue(); integer esize = 32 << UInt(sz); integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize;

Assembler Symbols

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T> For the half-precision variant: is an arrangement specifier, encoded in Q:
Q<T>
04H
18H
For the half-precision variant: is an arrangement specifier, encoded in Q:
Q<T>
04H
18H
For the single-precision and double-precision variant: is an arrangement specifier, encoded in sz:Q:
szQ<T>
002S
014S
10RESERVED
112D
For the single-precision and double-precision variant: is an arrangement specifier, encoded in sz:Q:
szQ<T>
002S
014S
10RESERVED
112D
<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(esize) element; for e = 0 to elements-1 element = Elem[operand, e, esize]; Elem[result, e, esize] = FPSqrt(element, FPCR); V[d] = result;


Internal version only: isa v29.05v27.02, AdvSIMD v26.0, pseudocode v35.3v34.2.2 ; Build timestamp: 2018-06-16T092018-03-28T19:4555

Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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