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SHA512SU1

SHA512 Schedule Update 1 takes the values from the three source SIMD&FP registers and produces a 128-bit output value that combines the gamma1 functions of two iterations of the SHA512 schedule update that are performed after the first 16 iterations within a block. It returns this value to the destination SIMD&FP register.

This instruction is implemented only when ARMv8.2-SHA is implemented.

Advanced SIMD
(ARMv8.2)

313029282726252423222120191817161514131211109876543210
11001110011Rm100010RnRd

Advanced SIMD

SHA512SU1 <Vd>.2D, <Vn>.2D, <Vm>.2D

if !HaveSHA512ExtHaveCryptoExt2() then UnallocatedEncoding(); integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm);

Assembler Symbols

<Vd>

Is the name of the SIMD&FP source and destination register, encoded in the "Rd" field.

<Vn>

Is the name of the second SIMD&FP source register, encoded in the "Rn" field.

<Vm>

Is the name of the third SIMD&FP source register, encoded in the "Rm" field.

Operation

AArch64.CheckFPAdvSIMDEnabled(); bits(64) sig1; bits(128) Vtmp; bits(128) X = V[n]; bits(128) Y = V[m]; bits(128) W = V[d]; sig1 = ROR(X<127:64>, 19) EOR ROR(X<127:64>,61) EOR '000000':X<127:70>; Vtmp<127:64> = W<127:64> + sig1 + Y<127:64>; sig1 = ROR(X<63:0>, 19) EOR ROR(X<63:0>,61) EOR '000000':X<63:6>; Vtmp<63:0> = W<63:0> + sig1 + Y<63:0>; V[d] = Vtmp;

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v29.05v27.02, AdvSIMD v26.0, pseudocode v35.3v34.2.2 ; Build timestamp: 2018-06-16T092018-03-28T19:4555

Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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