ISA_v84A_A64_xml_00bet7 (old) | htmldiff from-ISA_v84A_A64_xml_00bet7 | (new) ISA_v84A_A64_xml_00bet7_OPT |
Move immediate value to Special Register moves an immediate value to selected bits of the PSTATE. For more information, see Process state, PSTATE.
The bits that can be written are D, A, I, F, and SP. This set of bits is expanded in extensions to the architecture as follows:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | op1 | 0 | 1 | 0 | 0 | CRm | op2 | 1 | 1 | 1 | 1 | 1 |
MSR <pstatefield>, #<imm>
AArch64.CheckSystemAccess('00', op1, '0100', CRm, op2, '11111', '0');('00', op1, '0100', CRm, op2, '11111', '0');
bits(4) operand = CRm;
PSTATEField field;
case op1:op2 of
when '000 000'
SEE "CFINV";
when '000 011'
if !HaveUAOExt() then
UnallocatedEncoding();
field = PSTATEField_UAO;
when '000 100'
if !HavePANExt() then
UnallocatedEncoding();
field = PSTATEField_PAN;
when '000 101' field = PSTATEField_SP;
when '011 010'
if !HaveDITExt() then
UnallocatedEncoding();
field = PSTATEField_DIT;
when '011 110' field = PSTATEField_DAIFSet;
when '011 111' field = PSTATEField_DAIFClr;
otherwise UnallocatedEncoding();
// Check that an AArch64 MSR/MRS access to the DAIF flags is permitted
if op1 == '011' && PSTATE.EL == EL0 && (IsInHost() || SCTLR_EL1.UMA == '0') then
AArch64.SystemRegisterTrap(EL1, '00', op2, op1, '0100', '11111', CRm, '0');
<imm> | Is a 4-bit unsigned immediate, in the range 0 to 15, encoded in the "CRm" field. |
case field of
when PSTATEField_SP
PSTATE.SP = CRm<0>;
PSTATE.SP = operand<0>;
when PSTATEField_DAIFSet
PSTATE.D = PSTATE.D OR CRm<3>;
PSTATE.A = PSTATE.A OR CRm<2>;
PSTATE.I = PSTATE.I OR CRm<1>;
PSTATE.F = PSTATE.F OR CRm<0>;
PSTATE.D = PSTATE.D OR operand<3>;
PSTATE.A = PSTATE.A OR operand<2>;
PSTATE.I = PSTATE.I OR operand<1>;
PSTATE.F = PSTATE.F OR operand<0>;
when PSTATEField_DAIFClr
PSTATE.D = PSTATE.D AND NOT(CRm<3>);
PSTATE.A = PSTATE.A AND NOT(CRm<2>);
PSTATE.I = PSTATE.I AND NOT(CRm<1>);
PSTATE.F = PSTATE.F AND NOT(CRm<0>);
PSTATE.D = PSTATE.D AND NOT(operand<3>);
PSTATE.A = PSTATE.A AND NOT(operand<2>);
PSTATE.I = PSTATE.I AND NOT(operand<1>);
PSTATE.F = PSTATE.F AND NOT(operand<0>);
when PSTATEField_PAN
PSTATE.PAN = CRm<0>;
PSTATE.PAN = operand<0>;
when PSTATEField_UAO
PSTATE.UAO = CRm<0>;
PSTATE.UAO = operand<0>;
when PSTATEField_DIT
PSTATE.DIT = CRm<0>;PSTATE.DIT = operand<0>;
Internal version only: isa v29.05, AdvSIMD v26.0, pseudocode v35.3
; Build timestamp: 2018-06-16T09:5845
Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.
ISA_v84A_A64_xml_00bet7 (old) | htmldiff from-ISA_v84A_A64_xml_00bet7 | (new) ISA_v84A_A64_xml_00bet7_OPT |