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STNP

Store Pair of Registers, with non-temporal hint, calculates an address from a base register value and an immediate offset, and stores two 32-bit words or two 64-bit doublewords to the calculated address, from two registers. For information about memory accesses, see Load/Store addressing modes. For information about Non-temporal pair instructions, see Load/Store Non-temporal pair.

313029282726252423222120191817161514131211109876543210
x010100000imm7Rt2RnRt
opcL

32-bit (opc == 00)

STNP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]

64-bit (opc == 10)

STNP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]

boolean wback = FALSE; boolean postindex = FALSE;

Assembler Symbols

<Wt1>

Is the 32-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.

<Wt2>

Is the 32-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.

<Xt1>

Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.

<Xt2>

Is the 64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<imm>

For the 32-bit variant: is the optional signed immediate byte offset, a multiple of 4 in the range -256 to 252, defaulting to 0 and encoded in the "imm7" field as <imm>/4.

For the 64-bit variant: is the optional signed immediate byte offset, a multiple of 8 in the range -512 to 504, defaulting to 0 and encoded in the "imm7" field as <imm>/8.

Shared Decode

integer n = UInt(Rn); integer t = UInt(Rt); integer t2 = UInt(Rt2); AccType acctype = AccType_STREAM; MemOp memop = if L == '1' then MemOp_LOAD else MemOp_STORE; if opc<0> == '1' then UnallocatedEncoding(); integer scale = 2 + UInt(opc<1>); integer datasize = 8 << scale; bits(64) offset = LSL(SignExtend(imm7, 64), scale);

Operation

bits(64) address; bits(datasize) data1; bits(datasize) data2; constant integer dbytes = datasize DIV 8; boolean rt_unknown = FALSE; if memop == MemOp_LOAD && t == t2 then Constraint c = ConstrainUnpredictable(Unpredictable_LDPOVERLAP); assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_UNKNOWN rt_unknown = TRUE; // result is UNKNOWN when Constraint_UNDEF UnallocatedEncoding(); when Constraint_NOP EndOfInstruction(); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n]; if ! postindex then address = address + offset; case memop of when MemOp_STORE if rt_unknown && t == n then data1 = bits(datasize) UNKNOWN; else data1 = X[t]; if rt_unknown && t2 == n then data2 = bits(datasize) UNKNOWN; else data2 = X[t2]; Mem[address + 0 , dbytes, acctype] = data1; Mem[address + dbytes, dbytes, acctype] = data2; when MemOp_LOAD data1 = Mem[address + 0 , dbytes, acctype]; data2 = Mem[address + dbytes, dbytes, acctype]; if rt_unknown then data1 = bits(datasize) UNKNOWN; data2 = bits(datasize) UNKNOWN; X[t] = data1; X[t2] = data2; if wback then if postindex then address = address + offset; if n == 31 then SP[] = address; else X[n] = address;

Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.


Internal version only: isa v29.05v27.02, AdvSIMD v26.0, pseudocode v35.3v34.2.2 ; Build timestamp: 2018-06-16T092018-03-28T19:4555

Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.

ISA_v83A_A64_xml_00bet6.1 (old)htmldiff from-ISA_v83A_A64_xml_00bet6.1(new) ISA_v84A_A64_xml_00bet7