STR (register, SIMD&FP)
Store SIMD&FP register (register offset). This instruction stores a single SIMD&FP register to memory. The address that is used for the store is calculated from a base register value and an offset register value. The offset can be optionally shifted and extended.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
size | 1 | 1 | 1 | 1 | 0 | 0 | x | 0 | 1 | Rm | option | S | 1 | 0 | Rn | Rt |
| | | | opc | | | | | | | |
boolean wback = FALSE;
boolean postindex = FALSE;
integer scale = UInt(opc<1>:size);
if scale > 4 then UnallocatedEncoding();
if option<1> == '0' then UnallocatedEncoding(); // sub-word index
ExtendType extend_type = DecodeRegExtend(option);
integer shift = if S == '1' then scale else 0;
Assembler Symbols
<Bt> | Is the 8-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. |
<Dt> | Is the 64-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. |
<Ht> | Is the 16-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. |
<Qt> | Is the 128-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. |
<St> | Is the 32-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. |
<Xn|SP> | Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
<Wm> | When option<0> is set to 0, is the 32-bit name of the general-purpose index register, encoded in the "Rm" field. |
<Xm> | When option<0> is set to 1, is the 64-bit name of the general-purpose index register, encoded in the "Rm" field. |
<extend> |
For the 8-bit variant: is the index extend specifier,
encoded in
option
:
option | <extend> |
---|
010 | UXTW | 110 | SXTW | 111 | SXTX |
For the 8-bit variant: is the index extend specifier,
encoded in
option :
option | <extend> |
---|
010 | UXTW | 110 | SXTW | 111 | SXTX |
|
|
For the 128-bit, 16-bit, 32-bit and 64-bit variant: is the index extend/shift specifier, defaulting to LSL, and which must be omitted for the LSL option when <amount> is omitted.
encoded in
option
:
option | <extend> |
---|
010 | UXTW | 011 | LSL | 110 | SXTW | 111 | SXTX |
For the 128-bit, 16-bit, 32-bit and 64-bit variant: is the index extend/shift specifier, defaulting to LSL, and which must be omitted for the LSL option when <amount> is omitted.
encoded in
option :
option | <extend> |
---|
010 | UXTW | 011 | LSL | 110 | SXTW | 111 | SXTX |
|
<amount> | For the 8-bit variant: is the index shift amount, it must be #0, encoded in "S" as 0 if omitted, or as 1 if present. |
|
For the 16-bit variant: is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is
encoded in
S
:
For the 16-bit variant: is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is
encoded in
S :
|
|
For the 32-bit variant: is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is
encoded in
S
:
For the 32-bit variant: is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is
encoded in
S :
|
|
For the 64-bit variant: is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is
encoded in
S
:
For the 64-bit variant: is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is
encoded in
S :
|
|
For the 128-bit variant: is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is
encoded in
S
:
For the 128-bit variant: is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is
encoded in
S :
|
Operation
bits(64) offset = ExtendReg(m, extend_type, shift);
CheckFPAdvSIMDEnabled64();
bits(64) address;
bits(datasize) data;
if n == 31 then
CheckSPAlignment();
address = SP[];
else
address = X[n];
if ! postindex then
address = address + offset;
case memop of
when MemOp_STORE
data = V[t];
Mem[address, datasize DIV 8, acctype] = data;
when MemOp_LOAD
data = Mem[address, datasize DIV 8, acctype];
V[t] = data;
if wback then
if postindex then
address = address + offset;
if n == 31 then
SP[] = address;
else
X[n] = address;
Operational information
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: isa v29.05v27.02, AdvSIMD v26.0, pseudocode v35.3v34.2.2
; Build timestamp: 2018-06-16T092018-03-28T19:4555
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