LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH

Atomic bit clear on halfword in memory atomically loads a 16-bit halfword from memory, performs a bitwise AND with the complement of the value held in a register on it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register.

For more information about memory ordering semantics see Load-Acquire, Store-Release.

For information about memory accesses see Load/Store addressing modes.

This instruction is used by the alias STCLRH, STCLRLH.

Integer
(ARMv8.1)

313029282726252423222120191817161514131211109876543210
01111000AR1Rs000100RnRt
sizeopc

LDCLRAH (A == 1 && R == 0)

LDCLRAH <Ws>, <Wt>, [<Xn|SP>]

LDCLRALH (A == 1 && R == 1)

LDCLRALH <Ws>, <Wt>, [<Xn|SP>]

LDCLRH (A == 0 && R == 0)

LDCLRH <Ws>, <Wt>, [<Xn|SP>]

LDCLRLH (A == 0 && R == 1)

LDCLRLH <Ws>, <Wt>, [<Xn|SP>]

if !HaveAtomicExt() then UnallocatedEncoding(); integer t = UInt(Rt); integer n = UInt(Rn); integer s = UInt(Rs); AccType ldacctype = if A == '1' && Rt != '11111' then AccType_ORDEREDRW else AccType_ATOMICRW; AccType stacctype = if R == '1' then AccType_ORDEREDRW else AccType_ATOMICRW;

Assembler Symbols

<Ws>

Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

<Wt>

Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

Alias Conditions

AliasIs preferred when
STCLRH, STCLRLHA == '0' && Rt == '11111'

Operation

bits(64) address; bits(16) value; bits(16) data; bits(16) result; value = X[s]; if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n]; // All observers in the shareability domain observe the // following load and store atomically. data = Mem[address, 2, ldacctype]; result = data AND NOT(value); Mem[address, 2, stacctype] = result; if t != 31 then X[t] = ZeroExtend(data, 32);

Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.


Internal version only: isa v29.05, AdvSIMD v26.0, pseudocode v35.3 ; Build timestamp: 2018-06-16T09:58

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