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USQADD

Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.

If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 2 classes: Scalar and Vector

Scalar

313029282726252423222120191817161514131211109876543210
01111110size100000001110RnRd
U

Scalar

USQADD <V><d>, <V><n>

integer d = UInt(Rd); integer n = UInt(Rn); integer esize = 8 << UInt(size); integer datasize = esize; integer elements = 1; boolean unsigned = (U == '1');

Vector

313029282726252423222120191817161514131211109876543210
0Q101110size100000001110RnRd
U

Vector

USQADD <Vd>.<T>, <Vn>.<T>

integer d = UInt(Rd); integer n = UInt(Rn); if size:Q == '110' then ReservedValue(); integer esize = 8 << UInt(size); integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; boolean unsigned = (U == '1');

Assembler Symbols

<V> Is a width specifier, encoded in size:
size<V>
00B
01H
10S
11D
Is a width specifier, encoded in size:
size<V>
00B
01H
10S
11D
<d>

Is the number of the SIMD&FP destination register, encoded in the "Rd" field.

<n>

Is the number of the SIMD&FP source register, encoded in the "Rn" field.

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T> Is an arrangement specifier, encoded in size:Q:
sizeQ<T>
0008B
00116B
0104H
0118H
1002S
1014S
110RESERVED
1112D
Is an arrangement specifier, encoded in size:Q:
sizeQ<T>
0008B
00116B
0104H
0118H
1002S
1014S
110RESERVED
1112D
<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n]; bits(datasize) result; bits(datasize) operand2 = V[d]; integer op1; integer op2; boolean sat; for e = 0 to elements-1 op1 = Int(Elem[operand, e, esize], !unsigned); op2 = Int(Elem[operand2, e, esize], unsigned); (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned); if sat then FPSR.QC = '1'; V[d] = result;


Internal version only: isa v29.05v27.02, AdvSIMD v26.0, pseudocode v35.3v34.2.2 ; Build timestamp: 2018-06-16T092018-03-28T19:4555

Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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