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Floating-point Compare Equal (vector). This instruction compares each floating-point value from the first source SIMD&FP register, with the corresponding floating-point value from the second source SIMD&FP register, and if the comparison is equal sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 4 classes: Scalar half precision , Scalar single-precision and double-precision , Vector half precision and Vector single-precision and double-precision
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0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | Rm | 0 | 0 | 1 | 0 | 0 | 1 | Rn | Rd | ||||||||||||
U | E | ac |
if !HaveFP16Ext() then UnallocatedEncoding(); integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); integer esize = 16; integer datasize = esize; integer elements = 1; CompareOp cmp; boolean abs; case E:U:ac of when '000' cmp = CompareOp_EQ; abs = FALSE; when '010' cmp = CompareOp_GE; abs = FALSE; when '011' cmp = CompareOp_GE; abs = TRUE; when '110' cmp = CompareOp_GT; abs = FALSE; when '111' cmp = CompareOp_GT; abs = TRUE; otherwise UnallocatedEncoding();
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0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | sz | 1 | Rm | 1 | 1 | 1 | 0 | 0 | 1 | Rn | Rd | ||||||||||||
U | E | ac |
integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); integer esize = 32 << UInt(sz); integer datasize = esize; integer elements = 1; CompareOp cmp; boolean abs; case E:U:ac of when '000' cmp = CompareOp_EQ; abs = FALSE; when '010' cmp = CompareOp_GE; abs = FALSE; when '011' cmp = CompareOp_GE; abs = TRUE; when '110' cmp = CompareOp_GT; abs = FALSE; when '111' cmp = CompareOp_GT; abs = TRUE; otherwise UnallocatedEncoding();
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0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | Rm | 0 | 0 | 1 | 0 | 0 | 1 | Rn | Rd | ||||||||||||
U | E | ac |
if !HaveFP16Ext() then UnallocatedEncoding(); integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); integer esize = 16; integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; CompareOp cmp; boolean abs; case E:U:ac of when '000' cmp = CompareOp_EQ; abs = FALSE; when '010' cmp = CompareOp_GE; abs = FALSE; when '011' cmp = CompareOp_GE; abs = TRUE; when '110' cmp = CompareOp_GT; abs = FALSE; when '111' cmp = CompareOp_GT; abs = TRUE; otherwise UnallocatedEncoding();
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0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | 0 | sz | 1 | Rm | 1 | 1 | 1 | 0 | 0 | 1 | Rn | Rd | ||||||||||||
U | E | ac |
integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); if sz:Q == '10' then ReservedValue(); integer esize = 32 << UInt(sz); integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; CompareOp cmp; boolean abs; case E:U:ac of when '000' cmp = CompareOp_EQ; abs = FALSE; when '010' cmp = CompareOp_GE; abs = FALSE; when '011' cmp = CompareOp_GE; abs = TRUE; when '110' cmp = CompareOp_GT; abs = FALSE; when '111' cmp = CompareOp_GT; abs = TRUE; otherwise UnallocatedEncoding();
<Hd> | Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Hn> | Is the 16-bit name of the first SIMD&FP source register, encoded in the "Rn" field. |
<Hm> | Is the 16-bit name of the second SIMD&FP source register, encoded in the "Rm" field. |
<V> |
sz:
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<d> | Is the number of the SIMD&FP destination register, in the "Rd" field. |
<n> | Is the number of the first SIMD&FP source register, encoded in the "Rn" field. |
<m> | Is the number of the second SIMD&FP source register, encoded in the "Rm" field. |
<Vd> | Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
<T> |
Q:
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sz:Q:
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<Vn> | Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
<Vm> | Is the name of the second SIMD&FP source register, encoded in the "Rm" field. |
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2; boolean test_passed; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; element2 = Elem[operand2, e, esize]; if abs then element1 = FPAbs(element1); element2 = FPAbs(element2); case cmp of when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR); when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR); when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR); Elem[result, e, esize] = if test_passed then Ones() else Zeros(); V[d] = result;
Internal version only: isa v29.05v27.02, AdvSIMD v26.0, pseudocode v35.3v34.2.2
; Build timestamp: 2018-06-16T092018-03-28T19:4555
Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.
ISA_v83A_A64_xml_00bet6.1 (old) | htmldiff from-ISA_v83A_A64_xml_00bet6.1 | (new) ISA_v84A_A64_xml_00bet7 |