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DC

Data Cache operation. For more information, see .

This is an alias of SYS. This means:

313029282726252423222120191817161514131211109876543210
1101010100001op10111CRmop2Rt
LCRn

System

DC <dc_op>, <Xt>

is equivalent to

SYS #<op1>, C7, <Cm>, #<op2>, <Xt>

and is the preferred disassembly when SysOp(op1,'0111',CRm,op2) == Sys_DC.

Assembler Symbols

<dc_op> Is a DC instruction name, as listed for the DC system instruction group, encoded in op1:CRm:op2:
op1CRmop2<dc_op>Architectural Feature
0000110001IVAC -
0000110010ISW -
0001010010CSW -
0001110010CISW -
0110100001ZVA -
0111010001CVAC -
0111011001CVAU -
0111100001CVAP ARMv8.2-DCPoP
0111110001CIVAC -
Is a DC instruction name, as listed for the DC system instruction group, encoded in op1:CRm:op2:
op1CRmop2<dc_op>Architectural Feature
0000110001IVAC -
0000110010ISW -
0001010010CSW -
0001110010CISW -
0110100001ZVA -
0111010001CVAC -
0111011001CVAU -
0111100001CVAP ARMv8.2-DCPoP
0111110001CIVAC -
<op1>

Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op1" field.

<Cm>

Is a name 'Cm', with 'm' in the range 0 to 15, encoded in the "CRm" field.

<op2>

Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op2" field.

<Xt>

Is the 64-bit name of the general-purpose source register, encoded in the "Rt" field.

Operation

The description of SYS gives the operational pseudocode for this instruction.


Internal version only: isa v29.05v27.02, AdvSIMD v26.0, pseudocode v35.3v34.2.2 ; Build timestamp: 2018-06-16T092018-03-28T19:4555

Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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