LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH -- A64

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LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH

Atomic signed minimum on halfword in memory atomically loads a 16-bit halfword from memory, compares it against the value held in a register, and stores the smaller value back to memory, treating the values as signed numbers. The value initially loaded from memory is returned in the destination register.

If the destination register is not WZR, LDSMINAH and LDSMINALH load from memory with acquire semantics.
LDSMINLH and LDSMINALH store to memory with release semantics.
LDSMINH has no memory ordering requirements.

For more information about memory ordering semantics see Load-Acquire, Store-Release.

For information about memory accesses see Load/Store addressing modes.

This instruction is used by the alias STSMINH, STSMINLH.

Integer
(ARMv8.1)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	1	1	0	0	0	A	R	1	Rs					0	1	0	1	0	0	Rn					Rt
size																	opc

LDSMINAH (A == 1 && R == 0)

LDSMINAH <Ws>, <Wt>, [<Xn|SP>]

LDSMINALH (A == 1 && R == 1)

LDSMINALH <Ws>, <Wt>, [<Xn|SP>]

LDSMINH (A == 0 && R == 0)

LDSMINH <Ws>, <Wt>, [<Xn|SP>]

LDSMINLH (A == 0 && R == 1)

LDSMINLH <Ws>, <Wt>, [<Xn|SP>]

if !HaveAtomicExt() then UnallocatedEncoding(); integer t = UInt(Rt); integer n = UInt(Rn); integer s = UInt(Rs); integer datasize = 8 << UInt(size); integer regsize = if datasize == 64 then 64 else 32; AccType ldacctype = if A == '1' && Rt != '11111' then AccType_ORDEREDRW else AccType_ATOMICRW; AccType stacctype = if R == '1' then AccType_ORDEREDRW else AccType_ATOMICRW; MemAtomicOp op; case opc of when '000' op = MemAtomicOp_ADD; when '001' op = MemAtomicOp_BIC; when '010' op = MemAtomicOp_EOR; when '011' op = MemAtomicOp_ORR; when '100' op = MemAtomicOp_SMAX; when '101' op = MemAtomicOp_SMIN; when '110' op = MemAtomicOp_UMAX; when '111' op = MemAtomicOp_UMIN;

Assembler Symbols

<Ws>	Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

<Wt>	Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

Alias Conditions

Alias	Is preferred when
STSMINH, STSMINLH	A == '0' && Rt == '11111'

Operation

bits(64) address; bits(datasize) value; bits(datasize) data; bits(datasize) result; value = X[s]; if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n]; // All observers in the shareability domain observe the // following load and store atomically. data = Mem[address, datasize DIV 8, ldacctype]; case op of when MemAtomicOp_ADD result = data + value; when MemAtomicOp_BIC result = data AND NOT(value); when MemAtomicOp_EOR result = data EOR value; when MemAtomicOp_ORR result = data OR value; when MemAtomicOp_SMAX result = if SInt(data) > SInt(value) then data else value; when MemAtomicOp_SMIN result = if SInt(data) > SInt(value) then value else data; when MemAtomicOp_UMAX result = if UInt(data) > UInt(value) then data else value; when MemAtomicOp_UMIN result = if UInt(data) > UInt(value) then value else data; Mem[address, datasize DIV 8, stacctype] = result; if t != 31 then X[t] = ZeroExtend(data, regsize);

Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.

Internal version only: isa v29.05~~v27.02~~, AdvSIMD v26.0, pseudocode v35.3~~v34.2.2~~ ; Build timestamp: 2018-06-16T09~~2018-03-28T19~~:4555

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