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DUP (element)

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

This instruction is used by the alias MOV (scalar).

It has encodings from 2 classes: Scalar and Vector

Scalar

313029282726252423222120191817161514131211109876543210
01011110000imm5000001RnRd

Scalar

DUP <V><d>, <Vn>.<T>[<index>]

integer d = UInt(Rd); integer n = UInt(Rn); integer size = LowestSetBit(imm5); if size > 3 then UnallocatedEncoding(); integer index = UInt(imm5<4:size+1>); integer idxdsize = if imm5<4> == '1' then 128 else 64; integer esize = 8 << size; integer datasize = esize; integer elements = 1;

Vector

313029282726252423222120191817161514131211109876543210
0Q001110000imm5000001RnRd

Vector

DUP <Vd>.<T>, <Vn>.<Ts>[<index>]

integer d = UInt(Rd); integer n = UInt(Rn); integer size = LowestSetBit(imm5); if size > 3 then UnallocatedEncoding(); integer index = UInt(imm5<4:size+1>); integer idxdsize = if imm5<4> == '1' then 128 else 64; if size == 3 && Q == '0' then ReservedValue(); integer esize = 8 << size; integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize;

Assembler Symbols

<T> For the scalar variant: is the element width specifier, encoded in imm5:
imm5<T>
x0000RESERVED
xxxx1B
xxx10H
xx100S
x1000D
For the scalar variant: is the element width specifier, encoded in imm5:
imm5<T>
x0000RESERVED
xxxx1B
xxx10H
xx100S
x1000D
For the vector variant: is an arrangement specifier, encoded in imm5:Q:
imm5Q<T>
x0000xRESERVED
xxxx108B
xxxx1116B
xxx1004H
xxx1018H
xx10002S
xx10014S
x10000RESERVED
x100012D
For the vector variant: is an arrangement specifier, encoded in imm5:Q:
imm5Q<T>
x0000xRESERVED
xxxx108B
xxxx1116B
xxx1004H
xxx1018H
xx10002S
xx10014S
x10000RESERVED
x100012D
<Ts> Is an element size specifier, encoded in imm5:
imm5<Ts>
x0000RESERVED
xxxx1B
xxx10H
xx100S
x1000D
Is an element size specifier, encoded in imm5:
imm5<Ts>
x0000RESERVED
xxxx1B
xxx10H
xx100S
x1000D
<V> Is the destination width specifier, encoded in imm5:
imm5<V>
x0000RESERVED
xxxx1B
xxx10H
xx100S
x1000D
Is the destination width specifier, encoded in imm5:
imm5<V>
x0000RESERVED
xxxx1B
xxx10H
xx100S
x1000D
<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<index> Is the element index encoded in imm5:
imm5<index>
x0000RESERVED
xxxx1imm5<4:1>
xxx10imm5<4:2>
xx100imm5<4:3>
x1000imm5<4>
Is the element index encoded in imm5:
imm5<index>
x0000RESERVED
xxxx1imm5<4:1>
xxx10imm5<4:2>
xx100imm5<4:3>
x1000imm5<4>
<d>

Is the number of the SIMD&FP destination register, encoded in the "Rd" field.

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

Operation

CheckFPAdvSIMDEnabled64(); bits(idxdsize) operand = V[n]; bits(datasize) result; bits(esize) element; element = Elem[operand, index, esize]; for e = 0 to elements-1 Elem[result, e, esize] = element; V[d] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v29.05v27.02, AdvSIMD v26.0, pseudocode v35.3v34.2.2 ; Build timestamp: 2018-06-16T092018-03-28T19:4555

Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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