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BFXIL

Bitfield Extractextract and Insertinsert Lowat low end copies aany bitfieldnumber of <width>low-order bits starting from bita positionsource <lsb>register ininto the sourcesame registernumber toof adjacent bits at the leastlow significantend bitsin of the destination register, leaving the other destination bits unchanged.

This is an alias of BFM. This means:

313029282726252423222120191817161514131211109876543210
sf01100110NimmrimmsRnRd
opc

32-bit (sf == 0 && N == 0)

BFXIL <Wd>, <Wn>, #<lsb>, #<width>

is equivalent to

BFM <Wd>, <Wn>, #<lsb>, #(<lsb>+<width>-1)

and is the preferred disassembly when UInt(imms) >= UInt(immr).

64-bit (sf == 1 && N == 1)

BFXIL <Xd>, <Xn>, #<lsb>, #<width>

is equivalent to

BFM <Xd>, <Xn>, #<lsb>, #(<lsb>+<width>-1)

and is the preferred disassembly when UInt(imms) >= UInt(immr).

Assembler Symbols

<Wd>

Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Wn>

Is the 32-bit name of the general-purpose source register, encoded in the "Rn" field.

<Xd>

Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Xn>

Is the 64-bit name of the general-purpose source register, encoded in the "Rn" field.

<lsb>

For the 32-bit variant: is the bit number of the lsb of the source bitfield, in the range 0 to 31.

For the 64-bit variant: is the bit number of the lsb of the source bitfield, in the range 0 to 63.

<width>

For the 32-bit variant: is the width of the bitfield, in the range 1 to 32-<lsb>.

For the 64-bit variant: is the width of the bitfield, in the range 1 to 64-<lsb>.

Operation

The description of BFM gives the operational pseudocode for this instruction.

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v29.05v27.02, AdvSIMD v26.0, pseudocode v35.3v34.2.2 ; Build timestamp: 2018-06-16T092018-03-28T19:4555

Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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