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Floating-point Complex Multiply Accumulate.
This instruction operates on complex numbers that are represented in SIMD&FP registers as pairs of elements, with the more significant element holding the imaginary part of the number and the less significant element holding the real part of the number. Each element holds a floating-point value. It performs the following computation on the corresponding complex number element pairs from the two source registers and the destination register:
The multiplication and addition operations are performed as a fused multiply-add, without any intermediate rounding.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | Q | 1 | 0 | 1 | 1 | 1 | 0 | size | 0 | Rm | 1 | 1 | 0 | rot | 1 | Rn | Rd |
if !HaveFCADDExt() then UnallocatedEncoding(); integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); if size == '00' then ReservedValue(); if Q == '0' && size == '11' then ReservedValue(); integer esize = 8 << UInt(size); if !HaveFP16Ext() && esize == 16 then ReservedValue(); integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize;
<Vd> | Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
<T> |
size:Q:
|
<Vn> | Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
<Vm> | Is the name of the second SIMD&FP source register, encoded in the "Rm" field. |
<rotate> |
rot:
|
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; bits(esize) element1; bits(esize) element2; bits(esize) element3; bits(esize) element4; for e = 0 to (elements DIV 2) -1 case rot of when '00' element1 = Elem[operand2, e*2, esize]; element2 = Elem[operand1, e*2, esize]; element3 = Elem[operand2, e*2+1, esize]; element4 = Elem[operand1, e*2, esize]; when '01' element1 = FPNeg(Elem[operand2, e*2+1, esize]); element2 = Elem[operand1, e*2+1, esize]; element3 = Elem[operand2, e*2, esize]; element4 = Elem[operand1, e*2+1, esize]; when '10' element1 = FPNeg(Elem[operand2, e*2, esize]); element2 = Elem[operand1, e*2, esize]; element3 = FPNeg(Elem[operand2, e*2+1, esize]); element4 = Elem[operand1, e*2, esize]; when '11' element1 = Elem[operand2, e*2+1, esize]; element2 = Elem[operand1, e*2+1, esize]; element3 = FPNeg(Elem[operand2, e*2, esize]); element4 = Elem[operand1, e*2+1, esize]; Elem[result, e*2, esize] = FPMulAdd(Elem[operand3, e*2, esize], element2, element1, FPCR); Elem[result, e*2+1, esize] = FPMulAdd(Elem[operand3, e*2+1, esize], element4, element3, FPCR); V[d] = result;
Internal version only: isa v29.05v27.02, AdvSIMD v26.0, pseudocode v35.3v34.2.2
; Build timestamp: 2018-06-16T092018-03-28T19:4555
Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.
ISA_v83A_A64_xml_00bet6.1 (old) | htmldiff from-ISA_v83A_A64_xml_00bet6.1 | (new) ISA_v84A_A64_xml_00bet7 |