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FRINTP (scalar)

Floating-point Round to Integral, toward Plus infinity (scalar). This instruction rounds a floating-point value in the SIMD&FP source register to an integral floating-point value of the same size using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.

A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

313029282726252423222120191817161514131211109876543210
00011110type100100110000RnRd
rmode

Half-precision (type == 11)
(ARMv8.2)

FRINTP <Hd>, <Hn>

Single-precision (type == 00)

FRINTP <Sd>, <Sn>

Double-precision (type == 01)

FRINTP <Dd>, <Dn>

integer d = UInt(Rd); integer n = UInt(Rn); integer datasize; case type of when '00' datasize = 32; when '01' datasize = 64; when '10' UnallocatedEncoding(); when '11' if HaveFP16Ext() then datasize = 16; else UnallocatedEncoding(); boolean exact = FALSE; FPRounding rounding; case rmode of when '0xx' rounding = FPDecodeRounding(rmode<1:0>); when '100' rounding = FPRounding_TIEAWAY; when '101' UnallocatedEncoding(); when '110' rounding = FPRoundingMode(FPCR); exact = TRUE; when '111' rounding = FPRoundingMode(FPCR);

Assembler Symbols

<Dd>

Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Dn>

Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

<Hd>

Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Hn>

Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field.

<Sd>

Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Sn>

Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field.

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) result; bits(datasize) operand = V[n]; result = FPRoundInt(operand, FPCR, rounding, exact); V[d] = result;


Internal version only: isa v29.05v27.02, AdvSIMD v26.0, pseudocode v35.3v34.2.2 ; Build timestamp: 2018-06-16T092018-03-28T19:4555

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