Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 4 classes: Scalar, half-precision , Scalar, single-precision and double-precision , Vector, half-precision and Vector, single-precision and double-precision
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0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | L | M | Rm | 1 | 0 | 0 | 1 | H | 0 | Rn | Rd | |||||||||||
U |
if !HaveFP16Ext() then UnallocatedEncoding(); integer idxdsize = if H == '1' then 128 else 64; integer index; index = UInt(H:L:M); integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); integer esize = 16; integer datasize = esize; integer elements = 1; boolean mulx_op = (U == '1');
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0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | sz | L | M | Rm | 1 | 0 | 0 | 1 | H | 0 | Rn | Rd | |||||||||||
U |
integer idxdsize = if H == '1' then 128 else 64; integer index; bit Rmhi = M; case sz:L of when '0x' index = UInt(H:L); when '10' index = UInt(H); when '11' UnallocatedEncoding(); integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rmhi:Rm); integer esize = 32 << UInt(sz); integer datasize = esize; integer elements = 1; boolean mulx_op = (U == '1');
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0 | Q | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | L | M | Rm | 1 | 0 | 0 | 1 | H | 0 | Rn | Rd | |||||||||||
U |
if !HaveFP16Ext() then UnallocatedEncoding(); integer idxdsize = if H == '1' then 128 else 64; integer index; index = UInt(H:L:M); integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); integer esize = 16; integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; boolean mulx_op = (U == '1');
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0 | Q | 1 | 0 | 1 | 1 | 1 | 1 | 1 | sz | L | M | Rm | 1 | 0 | 0 | 1 | H | 0 | Rn | Rd | |||||||||||
U |
integer idxdsize = if H == '1' then 128 else 64; integer index; bit Rmhi = M; case sz:L of when '0x' index = UInt(H:L); when '10' index = UInt(H); when '11' UnallocatedEncoding(); integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rmhi:Rm); if sz:Q == '10' then ReservedValue(); integer esize = 32 << UInt(sz); integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; boolean mulx_op = (U == '1');
<Hd> |
Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Hn> |
Is the 16-bit name of the first SIMD&FP source register, encoded in the "Rn" field. |
<V> |
Is a width specifier,
encoded in
sz:
|
<d> |
Is the number of the SIMD&FP destination register, encoded in the "Rd" field. |
<n> |
Is the number of the first SIMD&FP source register, encoded in the "Rn" field. |
<Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
<T> |
For the vector, half-precision variant: is an arrangement specifier,
encoded in
Q:
| |||||||||||||||
For the vector, single-precision and double-precision variant: is an arrangement specifier,
encoded in
Q:sz:
|
<Vn> |
Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
<Ts> |
Is an element size specifier,
encoded in
sz:
|
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(idxdsize) operand2 = V[m]; bits(datasize) result; bits(esize) element1; bits(esize) element2 = Elem[operand2, index, esize]; for e = 0 to elements-1 element1 = Elem[operand1, e, esize]; if mulx_op then Elem[result, e, esize] = FPMulX(element1, element2, FPCR); else Elem[result, e, esize] = FPMul(element1, element2, FPCR); V[d] = result;
Internal version only: isa v27.02, AdvSIMD v26.0, pseudocode v34.2.2 ; Build timestamp: 2018-03-28T19:55
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