A64 ISA XML for ARMv8.5
(00bet8)
13th September 2018
1. Introduction
This is the 00bet8
release of the A64 ISA XML for ARMv8.5.
The Proprietary Notice
gives details of the terms and conditions under which this package
is provided.
If you have comments on the content of this package, please send
them by e-mail to
support-aarchv8@arm.com.
Give:
- The title, "A64 ISA XML for ARMv8.5".
- The version, "00bet8".
- A concise explanation of your comments.
2. Contents
3. Release Notes
Change history
The following general changes are made:
-
Added support for ARMv8.5.
The following changes are made to the instruction definitions:
-
The decode pseudocode for the LDTR/STTR instructions is corrected
to add the missing behaviour of the PSTATE.UAO bit, and the
behaviour when executed at EL2 with HCR_EL2.<E2H,TGE> ==
'11'.
-
The UDF instruction is added that guarantees an Undefined
Instruction exception.
The following changes are made to the Shared Pseudocode:
-
The function AArch64.TranslationTableWalk() is corrected to
reflect the fact that if TxSZ is programmed to a value smaller
than the effective minimum value when ARMv8.2-LVA is supported,
then any use of the TxSZ value generates a stage 1 level 0
Translation fault. This is corrected for each exception level.
-
The function AArch64.TranslationTableWalk() is corrected to
include the check for current translation regime when evaluating
the value of variable 'apply_nvnv1_efect'.
-
The function CheckPermission() is adjusted to correctly describe
the generation of permission fault for a data or unified cache
maintenance instruction that operates by VA.
-
The function AArch64.CheckPermission() is corrected to remove the
reference to variable 'ispriv' that does not exist. Also, the
function AArch64.CheckS2Permission() is corrected to describe the
missing behaviour that an enabled DC instruction executed at EL0
generates a Permission fault if the specified address does not
have read access at EL0.
-
The function AArch64.TakeException() is adjusted to add the effect
of nested virtualisation with HCR_EL2.<NV,NV1> = '10', when
any exception taken from EL1 to EL1 causes the SPSR_EL1.M[3:2] to
set to '10' not '01'.
-
The definition and the calls to function CalculateBottomPACBit()
are adjusted to remove the redundant function argument.
-
The function AArch64.FPTrappedException() is adjusted to reflect
the relaxation in the architecture to the values in the
ESR_ELx.ISS fields for an exception from a trapped floating-point
exception.
Known issues
-
The PC Sample-based Profiling Extension is not fully described, so
the changes to this area in ARMv8.2 are not implemented.
-
The encoding diagram for "LSL (immediate)" shows the field "imms"
in bits[15:10] as "!= x11111". This is incorrect because the 64
bit variant permits the value "011111", therefore this condition
will be removed.
-
The description for HINT overlaps with other defined instructions.
-
Register offset loads/stores have not been updated to have the
effects of the Memory Tagging Extension. This will be corrected in
a future release. The predicate used to generate the argument
passed to SetNotTagCheckedInstruction() is incorrect for some
instructions. The architectural rules are that when tag checking
is enabled, all load and store instructions are Tag Checked other
than:
- Instructions which directly read or write an allocation tag.
- Instructions which use a non-writeback SP{+imm} addressing mode.
- Literal loads.
- Prefetch instructions.
-
LDRAA, LDRAB are missing SetNotTagCheckedInstruction. This will be
corrected in a future release. The architectural rules are that
when tag checking is enabled, all load and store instructions are
Tag Checked other than:
- Instructions which directly read or write an allocation tag.
- Instructions which use a non-writeback SP{+imm} addressing mode.
- Literal loads.
- Prefetch instructions.