Instruction Synchronization Barrier flushes the pipeline in the PE and is a context synchronization event. For more information, see Instruction Synchronization Barrier (ISB).
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1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | CRm | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | |||
opc |
MemBarrierOp op; MBReqDomain domain; MBReqTypes types; op = MemBarrierOp_ISB; case CRm<3:2> of when '00' domain = MBReqDomain_OuterShareable; when '01' domain = MBReqDomain_Nonshareable; when '10' domain = MBReqDomain_InnerShareable; when '11' domain = MBReqDomain_FullSystem; case CRm<1:0> of when '01' types = MBReqTypes_Reads; when '10' types = MBReqTypes_Writes; when '11' types = MBReqTypes_All; otherwise if CRm<3:2> == '01' then op = MemBarrierOp_PSSBB; elsif HaveSBExt() && FALSE then op = MemBarrierOp_SB; else types = MBReqTypes_All; domain = MBReqDomain_FullSystem;
<imm> |
Is an optional 4-bit unsigned immediate, in the range 0 to 15, defaulting to 15 and encoded in the "CRm" field. |
case op of when MemBarrierOp_DSB DataSynchronizationBarrier(domain, types); when MemBarrierOp_DMB DataMemoryBarrier(domain, types); when MemBarrierOp_ISB InstructionSynchronizationBarrier(); when MemBarrierOp_SSBB SpeculativeSynchronizationBarrierToVA(); when MemBarrierOp_PSSBB SpeculativeSynchronizationBarrierToPA(); when MemBarrierOp_SB SpeculationBarrier();
Internal version only: isa v30.25, AdvSIMD v27.01, pseudocode v85-xml-00bet8_rc3 ; Build timestamp: 2018-09-13T13:25
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