SQSHLU
Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.
If saturation occurs, the cumulative saturation bit FPSR.QC is set.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 2 classes:
Scalar
and
Vector
Scalar
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | != 0000 | immb | 0 | 1 | 1 | 0 | 0 | 1 | Rn | Rd |
| U | | immh | | | op | | | | |
integer d = UInt(Rd);
integer n = UInt(Rn);
if immh == '0000' then UNDEFINED;
integer esize = 8 <<if immh == '0000' then ReservedValue();
integer esize = 8 << HighestSetBit(immh);
integer datasize = esize;
integer elements = 1;
integer shift = UInt(immh:immb) - esize;
boolean src_unsigned;
boolean dst_unsigned;
case op:U of
when '00' UnallocatedEncoding(immh:immb) - esize;
boolean src_unsigned;
boolean dst_unsigned;
case op:U of
when '00' UNDEFINED;
();
when '01' src_unsigned = FALSE; dst_unsigned = TRUE;
when '10' src_unsigned = FALSE; dst_unsigned = FALSE;
when '11' src_unsigned = TRUE; dst_unsigned = TRUE;
Vector
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | Q | 1 | 0 | 1 | 1 | 1 | 1 | 0 | != 0000 | immb | 0 | 1 | 1 | 0 | 0 | 1 | Rn | Rd |
| | U | | immh | | | op | | | | |
integer d = UInt(Rd);
integer n = UInt(Rn);
if immh == '0000' then SEE(asimdimm);
if immh<3>:Q == '10' then UNDEFINED;
integer esize = 8 <<if immh<3>:Q == '10' then ReservedValue();
integer esize = 8 << HighestSetBit(immh);
integer datasize = if Q == '1' then 128 else 64;
integer elements = datasize DIV esize;
integer shift = UInt(immh:immb) - esize;
boolean src_unsigned;
boolean dst_unsigned;
case op:U of
when '00' UnallocatedEncoding(immh:immb) - esize;
boolean src_unsigned;
boolean dst_unsigned;
case op:U of
when '00' UNDEFINED;
();
when '01' src_unsigned = FALSE; dst_unsigned = TRUE;
when '10' src_unsigned = FALSE; dst_unsigned = FALSE;
when '11' src_unsigned = TRUE; dst_unsigned = TRUE;
Assembler Symbols
<V> |
Is a width specifier,
encoded in
immh :
immh | <V> |
---|
0000 | RESERVED | 0001 | B | 001x | H | 01xx | S | 1xxx | D |
|
<d> | Is the number of the SIMD&FP destination register, in the "Rd" field. |
<n> | Is the number of the first SIMD&FP source register, encoded in the "Rn" field. |
<Vd> | Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
<T> |
Is an arrangement specifier,
encoded in
immh:Q :
|
<Vn> | Is the name of the SIMD&FP source register, encoded in the "Rn" field. |
<shift> |
For the scalar variant: is the left shift amount, in the range 0 to the operand width in bits minus 1,
encoded in
immh:immb :
immh | <shift> |
---|
0000 | RESERVED | 0001 | (UInt(immh:immb)-8) | 001x | (UInt(immh:immb)-16) | 01xx | (UInt(immh:immb)-32) | 1xxx | (UInt(immh:immb)-64) |
|
|
For the vector variant: is the left shift amount, in the range 0 to the element width in bits minus 1,
encoded in
immh:immb :
|
Operation
CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;
integer element;
boolean sat;
for e = 0 to elements-1
element = Int(Elem[operand, e, esize], src_unsigned) << shift;
(Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned);
if sat then FPSR.QC = '1';
V[d] = result;
Internal version only: isa v30.25v29.05, AdvSIMD v27.01v26.0, pseudocode v85-xml-00bet8_rc3v35.3
; Build timestamp: 2018-09-13T132018-06-16T09:0445
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