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Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. For a truncating shift, see SSHL.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 2 classes: Scalar and Vector
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0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | size | 1 | Rm | 0 | 1 | 0 | 1 | 0 | 1 | Rn | Rd | |||||||||||||
U | R | S |
integer d = UInt(Rd);
integer n = UInt(Rn);
integer m = UInt(Rm);
integer esize = 8 << UInt(size);
integer datasize = esize;
integer elements = 1;
boolean unsigned = (U == '1');
boolean rounding = (R == '1');
boolean saturating = (S == '1');
if S == '0' && size != '11' then UNDEFINED;if S == '0' && size != '11' thenReservedValue();
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0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | size | 1 | Rm | 0 | 1 | 0 | 1 | 0 | 1 | Rn | Rd | |||||||||||||
U | R | S |
integer d = UInt(Rd);
integer n = UInt(Rn);
integer m = UInt(Rm);
if size:Q == '110' then UNDEFINED;
integer esize = 8 <<if size:Q == '110' then ReservedValue();
integer esize = 8 << UInt(size);
integer datasize = if Q == '1' then 128 else 64;
integer elements = datasize DIV esize;
boolean unsigned = (U == '1');
boolean rounding = (R == '1');
boolean saturating = (S == '1');
<V> |
Is a width specifier,
encoded in
size:
|
<d> | Is the number of the SIMD&FP destination register, in the "Rd" field. |
<n> | Is the number of the first SIMD&FP source register, encoded in the "Rn" field. |
<m> | Is the number of the second SIMD&FP source register, encoded in the "Rm" field. |
<Vd> | Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
<T> |
Is an arrangement specifier,
encoded in
size:Q:
|
<Vn> | Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
<Vm> | Is the name of the second SIMD&FP source register, encoded in the "Rm" field. |
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) result; integer round_const = 0; integer shift; integer element; boolean sat; for e = 0 to elements-1 shift = SInt(Elem[operand2, e, esize]<7:0>); if rounding then round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift; if saturating then (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned); if sat then FPSR.QC = '1'; else Elem[result, e, esize] = element<esize-1:0>; V[d] = result;
Internal version only: isa v30.25v29.05, AdvSIMD v27.01v26.0, pseudocode v85-xml-00bet8_rc3v35.3
; Build timestamp: 2018-09-13T132018-06-16T09:0445
Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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