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SHA1H

SHA1 fixed rotate.

313029282726252423222120191817161514131211109876543210
0101111000101000000010RnRd

Advanced SIMD

SHA1H <Sd>, <Sn>

integer d = UInt(Rd); integer n = UInt(Rn); if !HaveSHA1Ext() then UNDEFINED;() thenUnallocatedEncoding();

Assembler Symbols

<Sd>

Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Sn>

Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field.

Operation

AArch64.CheckFPAdvSIMDEnabled(); bits(32) operand = V[n]; // read element [0] only, [1-3] zeroed V[d] = ROL(operand, 30);

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v30.25v29.05, AdvSIMD v27.01v26.0, pseudocode v85-xml-00bet8_rc3v35.3 ; Build timestamp: 2018-09-13T132018-06-16T09:0445

Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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