(old) | htmldiff from- | (new) |
Bitwise AND (shifted register), setting flags, performs a bitwise AND of a register value and an optionally-shifted register value, and writes the result to the destination register. It updates the condition flags based on the result.
This instruction is used by the alias TST (shifted register).
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
sf | 1 | 1 | 0 | 1 | 0 | 1 | 0 | shift | 0 | Rm | imm6 | Rn | Rd | ||||||||||||||||||
opc | N |
integer d = UInt(Rd);
integer n = UInt(Rn);
integer m = UInt(Rm);
integer datasize = if sf == '1' then 64 else 32;
boolean setflags;
LogicalOp op;
case opc of
when '00' op = LogicalOp_AND; setflags = FALSE;
when '01' op = LogicalOp_ORR; setflags = FALSE;
when '10' op = LogicalOp_EOR; setflags = FALSE;
when '11' op = LogicalOp_AND; setflags = TRUE;
if sf == '0' && imm6<5> == '1' then UNDEFINED;if sf == '0' && imm6<5> == '1' then
ReservedValue();
ShiftType shift_type = DecodeShift(shift);
integer shift_amount = UInt(imm6);
boolean invert = (N == '1');
<Wd> | Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. |
<Wn> | Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field. |
<Wm> | Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field. |
<Xd> | Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field. |
<Xn> | Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field. |
<Xm> | Is the 64-bit name of the second general-purpose source register, encoded in the "Rm" field. |
<shift> |
Is the optional shift to be applied to the final source, defaulting to LSL and
encoded in
shift:
|
Alias | Is preferred when |
---|---|
TST (shifted register) | Rd == '11111' |
bits(datasize) operand1 = X[n]; bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount); if invert then operand2 = NOT(operand2); case op of when LogicalOp_AND result = operand1 AND operand2; when LogicalOp_ORR result = operand1 OR operand2; when LogicalOp_EOR result = operand1 EOR operand2; if setflags then PSTATE.<N,Z,C,V> = result<datasize-1>:IsZeroBit(result):'00'; X[d] = result;
If PSTATE.DIT is 1:
Internal version only: isa v30.25v29.05, AdvSIMD v27.01v26.0, pseudocode v85-xml-00bet8_rc3v35.3
; Build timestamp: 2018-09-13T132018-06-16T09:0445
Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.
(old) | htmldiff from- | (new) |