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Move Immediate (vector). This instruction places an immediate constant into every vector element of the destination SIMD&FP register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | Q | op | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | a | b | c | cmode | 0 | 1 | d | e | f | g | h | Rd |
integer rd = UInt(Rd);
integer datasize = if Q == '1' then 128 else 64;
bits(datasize) imm;
bits(64) imm64;
ImmediateOp operation;
case cmode:op of
when '0xx00' operation = ImmediateOp_MOVI;
when '0xx01' operation = ImmediateOp_MVNI;
when '0xx10' operation = ImmediateOp_ORR;
when '0xx11' operation = ImmediateOp_BIC;
when '10x00' operation = ImmediateOp_MOVI;
when '10x01' operation = ImmediateOp_MVNI;
when '10x10' operation = ImmediateOp_ORR;
when '10x11' operation = ImmediateOp_BIC;
when '110x0' operation = ImmediateOp_MOVI;
when '110x1' operation = ImmediateOp_MVNI;
when '1110x' operation = ImmediateOp_MOVI;
when '11110' operation = ImmediateOp_MOVI;
when '11111'
// FMOV Dn,#imm is in main FP instruction set
if Q == '0' then UNDEFINED;
operation = if Q == '0' then UnallocatedEncoding();
operation = ImmediateOp_MOVI;
imm64 = AdvSIMDExpandImm(op, cmode, a:b:c:d:e:f:g:h);
imm = Replicate(imm64, datasize DIV 64);
<Dd> | Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Vd> | Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
<imm> | Is a 64-bit immediate 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh', encoded in "a:b:c:d:e:f:g:h". |
<imm8> | Is an 8-bit immediate encoded in "a:b:c:d:e:f:g:h". |
<amount> |
For the 16-bit shifted immediate variant: is the shift amount
encoded in
cmode<1>:
| ||||||||||
For the 32-bit shifted immediate variant: is the shift amount
encoded in
cmode<2:1>:
| |||||||||||
For the 32-bit shifting ones variant: is the shift amount
encoded in
cmode<0>:
|
CheckFPAdvSIMDEnabled64(); bits(datasize) operand; bits(datasize) result; case operation of when ImmediateOp_MOVI result = imm; when ImmediateOp_MVNI result = NOT(imm); when ImmediateOp_ORR operand = V[rd]; result = operand OR imm; when ImmediateOp_BIC operand = V[rd]; result = operand AND NOT(imm); V[rd] = result;
If PSTATE.DIT is 1:
Internal version only: isa v30.25v29.05, AdvSIMD v27.01v26.0, pseudocode v85-xml-00bet8_rc3v35.3
; Build timestamp: 2018-09-13T132018-06-16T09:0445
Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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