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SHA1SU1

SHA1 schedule update 1.

313029282726252423222120191817161514131211109876543210
0101111000101000000110RnRd

Advanced SIMD

SHA1SU1 <Vd>.4S, <Vn>.4S

integer d = UInt(Rd); integer n = UInt(Rn); if !HaveSHA1Ext() then UNDEFINED;() thenUnallocatedEncoding();

Assembler Symbols

<Vd>

Is the name of the SIMD&FP source and destination register, encoded in the "Rd" field.

<Vn>

Is the name of the second SIMD&FP source register, encoded in the "Rn" field.

Operation

AArch64.CheckFPAdvSIMDEnabled(); bits(128) operand1 = V[d]; bits(128) operand2 = V[n]; bits(128) result; bits(128) T = operand1 EOR LSR(operand2, 32); result<31:0> = ROL(T<31:0>, 1); result<63:32> = ROL(T<63:32>, 1); result<95:64> = ROL(T<95:64>, 1); result<127:96> = ROL(T<127:96>, 1) EOR ROL(T<31:0>, 2); V[d] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v30.25v29.05, AdvSIMD v27.01v26.0, pseudocode v85-xml-00bet8_rc3v35.3 ; Build timestamp: 2018-09-13T132018-06-16T09:0445

Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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