(old) htmldiff from-(new)

Top-level encodings for A64

313029282726252423222120191817161514131211109876543210
op0
Decode fields Instruction details
op0
0000 Reserved
0001 UNALLOCATED
001x UNALLOCATED
100x Data Processing -- Immediate
101x Branches, Exception Generating and System instructions
x1x0 Loads and Stores
x101 Data Processing -- Register
x111 Data Processing -- Scalar Floating-Point and Advanced SIMD

Reserved

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
op00000op1
Decode fields Instruction details
op0op1
000 000000000 UDF
000 != 000000000 UNALLOCATED
!= 000 000000000 UNALLOCATED

Data Processing -- Immediate

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
100op0op1
Decode fields Instruction details
op0op1
00 PC-rel. addressing
01 1x Add/subtract (immediate, with tags)
01 != 1x Add/subtract (immediate)
10 0x Logical (immediate)
10 1x Move wide (immediate)
11 0x Bitfield
11 1x Extract

PC-rel. addressing

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
opimmlo10000immhiRd
Decode fields Instruction Details
op
0ADR
1ADRP

Add/subtract (immediate, with tags)

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopS100011o2uimm6op3uimm4RnRd
Decode fields Instruction Details Architecture Version
sfopS
0UNALLOCATED-
11UNALLOCATED-
100ADDGARMv8.5
110SUBGARMv8.5

Add/subtract (immediate)

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopS10001!= 1ximm12RnRd
shift

The following constraints also apply to this encoding: shift<1> != 1x && shift<1> != 1x

Decode fields Instruction Details
sfopS
000ADD (immediate)32-bit
001ADDS (immediate)32-bit
010SUB (immediate)32-bit
011SUBS (immediate)32-bit
100ADD (immediate)64-bit
101ADDS (immediate)64-bit
110SUB (immediate)64-bit
111SUBS (immediate)64-bit

Logical (immediate)

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopc100100NimmrimmsRnRd
Decode fields Instruction Details
sfopcN
01UNALLOCATED
0000AND (immediate)32-bit
0010ORR (immediate)32-bit
0100EOR (immediate)32-bit
0110ANDS (immediate)32-bit
100AND (immediate)64-bit
101ORR (immediate)64-bit
110EOR (immediate)64-bit
111ANDS (immediate)64-bit

Move wide (immediate)

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopc100101hwimm16Rd
Decode fields Instruction Details
sfopchw
01UNALLOCATED
01xUNALLOCATED
000MOVN32-bit
010MOVZ32-bit
011MOVK32-bit
100MOVN64-bit
110MOVZ64-bit
111MOVK64-bit

Bitfield

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopc100110NimmrimmsRnRd
Decode fields Instruction Details
sfopcN
11UNALLOCATED
01UNALLOCATED
0000SBFM32-bit
0010BFM32-bit
0100UBFM32-bit
10UNALLOCATED
1001SBFM64-bit
1011BFM64-bit
1101UBFM64-bit

Extract

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfop21100111No0RmimmsRnRd
Decode fields Instruction Details
sfop21No0imms
x1UNALLOCATED
001UNALLOCATED
1xUNALLOCATED
01xxxxxUNALLOCATED
01UNALLOCATED
000000xxxxxEXTR32-bit
10UNALLOCATED
10010EXTR64-bit

Branches, Exception Generating and System instructions

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
op0101op1op2
Decode fields Instruction details
op0op1op2
010 0xxxxxxxxxxxxx Conditional branch (immediate)
010 1xxxxxxxxxxxxx UNALLOCATED
110 00xxxxxxxxxxxx Exception generation
110 010000000x001x UNALLOCATED
110 0100000010001x UNALLOCATED
110 01000000110010 11111 Hints
110 01000000110010 != 11111 UNALLOCATED
110 01000000110011 Barriers
110 01000001xx001x UNALLOCATED
110 0100000xxx000x UNALLOCATED
110 0100000xxx0100 PSTATE
110 0100000xxx0101 UNALLOCATED
110 0100000xxx011x UNALLOCATED
110 0100000xxx1xxx UNALLOCATED
110 0100x01xxxxxxx System instructions
110 0100x1xxxxxxxx System register move
110 0101xxxxxxxxxx UNALLOCATED
110 011xxxxxxxxxxx UNALLOCATED
110 1xxxxxxxxxxxxx Unconditional branch (register)
x00 Unconditional branch (immediate)
x01 0xxxxxxxxxxxxx Compare and branch (immediate)
x01 1xxxxxxxxxxxxx Test and branch (immediate)
x11 UNALLOCATED

Conditional branch (immediate)

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
0101010o1imm19o0cond
Decode fields Instruction Details
o1o0
00B.cond
01UNALLOCATED
1UNALLOCATED

Exception generation

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
11010100opcimm16op2LL
Decode fields Instruction Details
opcop2LL
xx1UNALLOCATED
x1xUNALLOCATED
1xxUNALLOCATED
00000001SVC
00000010HVC
00000011SMC
001000x1UNALLOCATED
00100000BRK
0010001xUNALLOCATED
010000x1UNALLOCATED
01000000HLT
0100001xUNALLOCATED
01100001UNALLOCATED
0110001xUNALLOCATED
10100000UNALLOCATED
10100001DCPS1
10100010DCPS2
10100011DCPS3
110000UNALLOCATED
11100001UNALLOCATED
1110001xUNALLOCATED

Hints

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
11010101000000110010CRmop211111
Decode fields Instruction Details Architecture Version
CRmop2
HINT-
0000000NOP-
0000001YIELD-
0000010WFE-
0000011WFI-
0000100SEV-
0000101SEVL-
0000111XPACD, XPACI, XPACLRIARMv8.3
0001000PACIA, PACIA1716, PACIASP, PACIAZ, PACIZAPACIA1716ARMv8.3
0001010PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZBPACIB1716ARMv8.3
0001100AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZAAUTIA1716ARMv8.3
0001110AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZBAUTIB1716ARMv8.3
0010000ESBARMv8.2
0010001PSB CSYNCARMv8.2
0010010TSB CSYNCARMv8.4
0010100CSDB-
0011000PACIA, PACIA1716, PACIASP, PACIAZ, PACIZAPACIAZARMv8.3
0011001PACIA, PACIA1716, PACIASP, PACIAZ, PACIZAPACIASPARMv8.3
0011010PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZBPACIBZARMv8.3
0011011PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZBPACIBSPARMv8.3
0011100AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZAAUTIAZARMv8.3
0011101AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZAAUTIASPARMv8.3
0011110AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZBAUTIBZARMv8.3
0011111AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZBAUTIBSPARMv8.3
0100xx0BTIARMv8.5

Barriers

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
11010101000000110011CRmop2Rt
Decode fields Instruction Details
CRmop2Rt
000UNALLOCATED
001UNALLOCATED
01011111CLREX
10111111DMB
11011111ISB
111!= 11111UNALLOCATED
11111111SB
!= 0x0010011111DSB
000010011111SSBB
0001011UNALLOCATED
001x011UNALLOCATED
01xx011UNALLOCATED
010010011111PSSBB
1xxx011UNALLOCATED

PSTATE

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101010100000op10100CRmop2Rt
Decode fields Instruction Details Architecture Version
op1op2Rt
!= 11111UNALLOCATED-
11111MSR (immediate)-
00000011111CFINVARMv8.4
00000111111XAFlagARMv8.5
00001011111AXFlagARMv8.5

System instructions

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101010100L01op1CRnCRmop2Rt
Decode fields Instruction Details
L
0SYS
1SYSL

System register move

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101010100L1o0op1CRnCRmop2Rt
Decode fields Instruction Details
L
0MSR (register)
1MRS

Unconditional branch (register)

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101011opcop2op3Rnop4
Decode fields Instruction Details Architecture Version
opcop2op3Rnop4
!= 11111UNALLOCATED-
000011111000000!= 00000UNALLOCATED-
00001111100000000000BR-
000011111000001UNALLOCATED-
000011111000010!= 11111UNALLOCATED-
00001111100001011111BRAA, BRAAZ, BRAB, BRABZkey A, zero modifierARMv8.3
000011111000011!= 11111UNALLOCATED-
00001111100001111111BRAA, BRAAZ, BRAB, BRABZkey B, zero modifierARMv8.3
0000111110001xxUNALLOCATED-
000011111001xxxUNALLOCATED-
00001111101xxxxUNALLOCATED-
0000111111xxxxxUNALLOCATED-
000111111000000!= 00000UNALLOCATED-
00011111100000000000BLR-
000111111000001UNALLOCATED-
000111111000010!= 11111UNALLOCATED-
00011111100001011111BLRAA, BLRAAZ, BLRAB, BLRABZkey A, zero modifierARMv8.3
000111111000011!= 11111UNALLOCATED-
00011111100001111111BLRAA, BLRAAZ, BLRAB, BLRABZkey B, zero modifierARMv8.3
0001111110001xxUNALLOCATED-
000111111001xxxUNALLOCATED-
00011111101xxxxUNALLOCATED-
0001111111xxxxxUNALLOCATED-
001011111000000!= 00000UNALLOCATED-
00101111100000000000RET-
001011111000001UNALLOCATED-
001011111000010!= 11111!= 11111UNALLOCATED-
0010111110000101111111111RETAA, RETABRETAAARMv8.3
001011111000011!= 11111!= 11111UNALLOCATED-
0010111110000111111111111RETAA, RETABRETABARMv8.3
0010111110001xxUNALLOCATED-
001011111001xxxUNALLOCATED-
00101111101xxxxUNALLOCATED-
0010111111xxxxxUNALLOCATED-
001111111UNALLOCATED-
010011111000000!= 11111!= 00000UNALLOCATED-
010011111000000!= 1111100000UNALLOCATED-
01001111100000011111!= 00000UNALLOCATED-
0100111110000001111100000ERET-
010011111000001UNALLOCATED-
010011111000010!= 11111!= 11111UNALLOCATED-
010011111000010!= 1111111111UNALLOCATED-
01001111100001011111!= 11111UNALLOCATED-
0100111110000101111111111ERETAA, ERETABERETAAARMv8.3
010011111000011!= 11111!= 11111UNALLOCATED-
010011111000011!= 1111111111UNALLOCATED-
01001111100001111111!= 11111UNALLOCATED-
0100111110000111111111111ERETAA, ERETABERETABARMv8.3
0100111110001xxUNALLOCATED-
010011111001xxxUNALLOCATED-
01001111101xxxxUNALLOCATED-
0100111111xxxxxUNALLOCATED-
010111111!= 000000UNALLOCATED-
010111111000000!= 11111!= 00000UNALLOCATED-
010111111000000!= 1111100000UNALLOCATED-
01011111100000011111!= 00000UNALLOCATED-
0101111110000001111100000DRPS-
011x11111UNALLOCATED-
10001111100000xUNALLOCATED-
100011111000010BRAA, BRAAZ, BRAB, BRABZkey A, register modifierARMv8.3
100011111000011BRAA, BRAAZ, BRAB, BRABZkey B, register modifierARMv8.3
1000111110001xxUNALLOCATED-
100011111001xxxUNALLOCATED-
10001111101xxxxUNALLOCATED-
1000111111xxxxxUNALLOCATED-
10011111100000xUNALLOCATED-
100111111000010BLRAA, BLRAAZ, BLRAB, BLRABZkey A, register modifierARMv8.3
100111111000011BLRAA, BLRAAZ, BLRAB, BLRABZkey B, register modifierARMv8.3
1001111110001xxUNALLOCATED-
100111111001xxxUNALLOCATED-
10011111101xxxxUNALLOCATED-
1001111111xxxxxUNALLOCATED-
101x11111UNALLOCATED-
11xx11111UNALLOCATED-

Unconditional branch (immediate)

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
op00101imm26
Decode fields Instruction Details
op
0B
1BL

Compare and branch (immediate)

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
sf011010opimm19Rt
Decode fields Instruction Details
sfop
00CBZ32-bit
01CBNZ32-bit
10CBZ64-bit
11CBNZ64-bit

Test and branch (immediate)

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
b5011011opb40imm14Rt
Decode fields Instruction Details
op
0TBZ
1TBNZ

Loads and Stores

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
op01op10op2op3op4
Decode fields Instruction details
op0op1op2op3op4
0x00 1 00 000000 Advanced SIMD load/store multiple structures
0x00 1 01 0xxxxx Advanced SIMD load/store multiple structures (post-indexed)
0x00 1 0x 1xxxxx UNALLOCATED
0x00 1 10 x00000 Advanced SIMD load/store single structure
0x00 1 11 Advanced SIMD load/store single structure (post-indexed)
0x00 1 x0 x1xxxx UNALLOCATED
0x00 1 x0 xx1xxx UNALLOCATED
0x00 1 x0 xxx1xx UNALLOCATED
0x00 1 x0 xxxx1x UNALLOCATED
0x00 1 x0 xxxxx1 UNALLOCATED
0x01 0 1x 1xxxxx UNALLOCATED
1001 0 1x 1xxxxx UNALLOCATED
1101 0 1x 1xxxxx Load/store memory tags
1x00 1 UNALLOCATED
xx00 0 0x Load/store exclusive
xx00 0 1x UNALLOCATED
xx01 0x Load register (literal)
xx01 1x 0xxxxx 00 UNALLOCATED
xx10 00 Load/store no-allocate pair (offset)
xx10 01 Load/store register pair (post-indexed)
xx10 10 Load/store register pair (offset)
xx10 11 Load/store register pair (pre-indexed)
xx11 0x 0xxxxx 00 Load/store register (unscaled immediate)
xx11 0x 0xxxxx 01 Load/store register (immediate post-indexed)
xx11 0x 0xxxxx 10 Load/store register (unprivileged)
xx11 0x 0xxxxx 11 Load/store register (immediate pre-indexed)
xx11 0x 1xxxxx 00 Atomic memory operations
xx11 0x 1xxxxx 10 Load/store register (register offset)
xx11 0x 1xxxxx x1 Load/store register (pac)
xx11 1x Load/store register (unsigned immediate)

Advanced SIMD load/store multiple structures

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
0Q0011000L000000opcodesizeRnRt
Decode fields Instruction Details
Lopcode
00000ST4 (multiple structures)
00001UNALLOCATED
00010ST1 (multiple structures)four registers
00011UNALLOCATED
00100ST3 (multiple structures)
00101UNALLOCATED
00110ST1 (multiple structures)three registers
00111ST1 (multiple structures)one register
01000ST2 (multiple structures)
01001UNALLOCATED
01010ST1 (multiple structures)two registers
01011UNALLOCATED
011xxUNALLOCATED
10000LD4 (multiple structures)
10001UNALLOCATED
10010LD1 (multiple structures)four registers
10011UNALLOCATED
10100LD3 (multiple structures)
10101UNALLOCATED
10110LD1 (multiple structures)three registers
10111LD1 (multiple structures)one register
11000LD2 (multiple structures)
11001UNALLOCATED
11010LD1 (multiple structures)two registers
11011UNALLOCATED
111xxUNALLOCATED

Advanced SIMD load/store multiple structures (post-indexed)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
0Q0011001L0RmopcodesizeRnRt
Decode fields Instruction Details
LRmopcode
00001UNALLOCATED
00011UNALLOCATED
00101UNALLOCATED
01001UNALLOCATED
01011UNALLOCATED
011xxUNALLOCATED
0!= 111110000ST4 (multiple structures)register offset
0!= 111110010ST1 (multiple structures)four registers, register offset
0!= 111110100ST3 (multiple structures)register offset
0!= 111110110ST1 (multiple structures)three registers, register offset
0!= 111110111ST1 (multiple structures)one register, register offset
0!= 111111000ST2 (multiple structures)register offset
0!= 111111010ST1 (multiple structures)two registers, register offset
0111110000ST4 (multiple structures)immediate offset
0111110010ST1 (multiple structures)four registers, immediate offset
0111110100ST3 (multiple structures)immediate offset
0111110110ST1 (multiple structures)three registers, immediate offset
0111110111ST1 (multiple structures)one register, immediate offset
0111111000ST2 (multiple structures)immediate offset
0111111010ST1 (multiple structures)two registers, immediate offset
10001UNALLOCATED
10011UNALLOCATED
10101UNALLOCATED
11001UNALLOCATED
11011UNALLOCATED
111xxUNALLOCATED
1!= 111110000LD4 (multiple structures)register offset
1!= 111110010LD1 (multiple structures)four registers, register offset
1!= 111110100LD3 (multiple structures)register offset
1!= 111110110LD1 (multiple structures)three registers, register offset
1!= 111110111LD1 (multiple structures)one register, register offset
1!= 111111000LD2 (multiple structures)register offset
1!= 111111010LD1 (multiple structures)two registers, register offset
1111110000LD4 (multiple structures)immediate offset
1111110010LD1 (multiple structures)four registers, immediate offset
1111110100LD3 (multiple structures)immediate offset
1111110110LD1 (multiple structures)three registers, immediate offset
1111110111LD1 (multiple structures)one register, immediate offset
1111111000LD2 (multiple structures)immediate offset
1111111010LD1 (multiple structures)two registers, immediate offset

Advanced SIMD load/store single structure

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
0Q0011010LR00000opcodeSsizeRnRt
Decode fields Instruction Details
LRopcodeSsize
011xUNALLOCATED
00000ST1 (single structure)8-bit
00001ST3 (single structure)8-bit
00010x0ST1 (single structure)16-bit
00010x1UNALLOCATED
00011x0ST3 (single structure)16-bit
00011x1UNALLOCATED
0010000ST1 (single structure)32-bit
001001xUNALLOCATED
00100001ST1 (single structure)64-bit
00100101UNALLOCATED
0010100ST3 (single structure)32-bit
0010110UNALLOCATED
00101001ST3 (single structure)64-bit
00101011UNALLOCATED
001011x1UNALLOCATED
01000ST2 (single structure)8-bit
01001ST4 (single structure)8-bit
01010x0ST2 (single structure)16-bit
01010x1UNALLOCATED
01011x0ST4 (single structure)16-bit
01011x1UNALLOCATED
0110000ST2 (single structure)32-bit
0110010UNALLOCATED
01100001ST2 (single structure)64-bit
01100011UNALLOCATED
011001x1UNALLOCATED
0110100ST4 (single structure)32-bit
0110110UNALLOCATED
01101001ST4 (single structure)64-bit
01101011UNALLOCATED
011011x1UNALLOCATED
10000LD1 (single structure)8-bit
10001LD3 (single structure)8-bit
10010x0LD1 (single structure)16-bit
10010x1UNALLOCATED
10011x0LD3 (single structure)16-bit
10011x1UNALLOCATED
1010000LD1 (single structure)32-bit
101001xUNALLOCATED
10100001LD1 (single structure)64-bit
10100101UNALLOCATED
1010100LD3 (single structure)32-bit
1010110UNALLOCATED
10101001LD3 (single structure)64-bit
10101011UNALLOCATED
101011x1UNALLOCATED
101100LD1R
101101UNALLOCATED
101110LD3R
101111UNALLOCATED
11000LD2 (single structure)8-bit
11001LD4 (single structure)8-bit
11010x0LD2 (single structure)16-bit
11010x1UNALLOCATED
11011x0LD4 (single structure)16-bit
11011x1UNALLOCATED
1110000LD2 (single structure)32-bit
1110010UNALLOCATED
11100001LD2 (single structure)64-bit
11100011UNALLOCATED
111001x1UNALLOCATED
1110100LD4 (single structure)32-bit
1110110UNALLOCATED
11101001LD4 (single structure)64-bit
11101011UNALLOCATED
111011x1UNALLOCATED
111100LD2R
111101UNALLOCATED
111110LD4R
111111UNALLOCATED

Advanced SIMD load/store single structure (post-indexed)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
0Q0011011LRRmopcodeSsizeRnRt
Decode fields Instruction Details
LRRmopcodeSsize
011xUNALLOCATED
00010x1UNALLOCATED
00011x1UNALLOCATED
001001xUNALLOCATED
00100101UNALLOCATED
0010110UNALLOCATED
00101011UNALLOCATED
001011x1UNALLOCATED
00!= 11111000ST1 (single structure)8-bit, register offset
00!= 11111001ST3 (single structure)8-bit, register offset
00!= 11111010x0ST1 (single structure)16-bit, register offset
00!= 11111011x0ST3 (single structure)16-bit, register offset
00!= 1111110000ST1 (single structure)32-bit, register offset
00!= 11111100001ST1 (single structure)64-bit, register offset
00!= 1111110100ST3 (single structure)32-bit, register offset
00!= 11111101001ST3 (single structure)64-bit, register offset
0011111000ST1 (single structure)8-bit, immediate offset
0011111001ST3 (single structure)8-bit, immediate offset
0011111010x0ST1 (single structure)16-bit, immediate offset
0011111011x0ST3 (single structure)16-bit, immediate offset
001111110000ST1 (single structure)32-bit, immediate offset
0011111100001ST1 (single structure)64-bit, immediate offset
001111110100ST3 (single structure)32-bit, immediate offset
0011111101001ST3 (single structure)64-bit, immediate offset
01010x1UNALLOCATED
01011x1UNALLOCATED
0110010UNALLOCATED
01100011UNALLOCATED
011001x1UNALLOCATED
0110110UNALLOCATED
01101011UNALLOCATED
011011x1UNALLOCATED
01!= 11111000ST2 (single structure)8-bit, register offset
01!= 11111001ST4 (single structure)8-bit, register offset
01!= 11111010x0ST2 (single structure)16-bit, register offset
01!= 11111011x0ST4 (single structure)16-bit, register offset
01!= 1111110000ST2 (single structure)32-bit, register offset
01!= 11111100001ST2 (single structure)64-bit, register offset
01!= 1111110100ST4 (single structure)32-bit, register offset
01!= 11111101001ST4 (single structure)64-bit, register offset
0111111000ST2 (single structure)8-bit, immediate offset
0111111001ST4 (single structure)8-bit, immediate offset
0111111010x0ST2 (single structure)16-bit, immediate offset
0111111011x0ST4 (single structure)16-bit, immediate offset
011111110000ST2 (single structure)32-bit, immediate offset
0111111100001ST2 (single structure)64-bit, immediate offset
011111110100ST4 (single structure)32-bit, immediate offset
0111111101001ST4 (single structure)64-bit, immediate offset
10010x1UNALLOCATED
10011x1UNALLOCATED
101001xUNALLOCATED
10100101UNALLOCATED
1010110UNALLOCATED
10101011UNALLOCATED
101011x1UNALLOCATED
101101UNALLOCATED
101111UNALLOCATED
10!= 11111000LD1 (single structure)8-bit, register offset
10!= 11111001LD3 (single structure)8-bit, register offset
10!= 11111010x0LD1 (single structure)16-bit, register offset
10!= 11111011x0LD3 (single structure)16-bit, register offset
10!= 1111110000LD1 (single structure)32-bit, register offset
10!= 11111100001LD1 (single structure)64-bit, register offset
10!= 1111110100LD3 (single structure)32-bit, register offset
10!= 11111101001LD3 (single structure)64-bit, register offset
10!= 111111100LD1Rregister offset
10!= 111111110LD3Rregister offset
1011111000LD1 (single structure)8-bit, immediate offset
1011111001LD3 (single structure)8-bit, immediate offset
1011111010x0LD1 (single structure)16-bit, immediate offset
1011111011x0LD3 (single structure)16-bit, immediate offset
101111110000LD1 (single structure)32-bit, immediate offset
1011111100001LD1 (single structure)64-bit, immediate offset
101111110100LD3 (single structure)32-bit, immediate offset
1011111101001LD3 (single structure)64-bit, immediate offset
10111111100LD1Rimmediate offset
10111111110LD3Rimmediate offset
11010x1UNALLOCATED
11011x1UNALLOCATED
1110010UNALLOCATED
11100011UNALLOCATED
111001x1UNALLOCATED
1110110UNALLOCATED
11101011UNALLOCATED
111011x1UNALLOCATED
111101UNALLOCATED
111111UNALLOCATED
11!= 11111000LD2 (single structure)8-bit, register offset
11!= 11111001LD4 (single structure)8-bit, register offset
11!= 11111010x0LD2 (single structure)16-bit, register offset
11!= 11111011x0LD4 (single structure)16-bit, register offset
11!= 1111110000LD2 (single structure)32-bit, register offset
11!= 11111100001LD2 (single structure)64-bit, register offset
11!= 1111110100LD4 (single structure)32-bit, register offset
11!= 11111101001LD4 (single structure)64-bit, register offset
11!= 111111100LD2Rregister offset
11!= 111111110LD4Rregister offset
1111111000LD2 (single structure)8-bit, immediate offset
1111111001LD4 (single structure)8-bit, immediate offset
1111111010x0LD2 (single structure)16-bit, immediate offset
1111111011x0LD4 (single structure)16-bit, immediate offset
111111110000LD2 (single structure)32-bit, immediate offset
1111111100001LD2 (single structure)64-bit, immediate offset
111111110100LD4 (single structure)32-bit, immediate offset
1111111101001LD4 (single structure)64-bit, immediate offset
11111111100LD2Rimmediate offset
11111111110LD4Rimmediate offset

Load/store memory tags

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
11011001opc1imm9op2RnRt
Decode fields Instruction Details Architecture Version
opcimm9op2
0000UNALLOCATED-
0001STGpost-indexARMv8.5
0010STGsigned offsetARMv8.5
0011STGpre-indexARMv8.5
0100LDGARMv8.5
0101STZGpost-indexARMv8.5
0110STZGsigned offsetARMv8.5
0111STZGpre-indexARMv8.5
1001ST2Gpost-indexARMv8.5
1010ST2Gsigned offsetARMv8.5
1011ST2Gpre-indexARMv8.5
10!= 00000000000UNALLOCATED-
1000000000000STGVARMv8.5
1101STZ2Gpost-indexARMv8.5
1110STZ2Gsigned offsetARMv8.5
1111STZ2Gpre-indexARMv8.5
11!= 00000000000UNALLOCATED-
1100000000000LDGVARMv8.5

Load/store exclusive

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size001000o2Lo1Rso0Rt2RnRt
Decode fields Instruction Details Architecture Version
sizeo2Lo1o0Rt2
11!= 11111UNALLOCATED-
0x01!= 11111UNALLOCATED-
000000STXRB-
000001STLXRB-
00001011111CASP, CASPA, CASPAL, CASPL32-bit CASPARMv8.1
00001111111CASP, CASPA, CASPAL, CASPL32-bit CASPLARMv8.1
000100LDXRB-
000101LDAXRB-
00011011111CASP, CASPA, CASPAL, CASPL32-bit CASPAARMv8.1
00011111111CASP, CASPA, CASPAL, CASPL32-bit CASPALARMv8.1
001000STLLRBARMv8.1
001001STLRB-
00101011111CASB, CASAB, CASALB, CASLBCASBARMv8.1
00101111111CASB, CASAB, CASALB, CASLBCASLBARMv8.1
001100LDLARBARMv8.1
001101LDARB-
00111011111CASB, CASAB, CASALB, CASLBCASABARMv8.1
00111111111CASB, CASAB, CASALB, CASLBCASALBARMv8.1
010000STXRH-
010001STLXRH-
01001011111CASP, CASPA, CASPAL, CASPL64-bit CASPARMv8.1
01001111111CASP, CASPA, CASPAL, CASPL64-bit CASPLARMv8.1
010100LDXRH-
010101LDAXRH-
01011011111CASP, CASPA, CASPAL, CASPL64-bit CASPAARMv8.1
01011111111CASP, CASPA, CASPAL, CASPL64-bit CASPALARMv8.1
011000STLLRHARMv8.1
011001STLRH-
01101011111CASH, CASAH, CASALH, CASLHCASHARMv8.1
01101111111CASH, CASAH, CASALH, CASLHCASLHARMv8.1
011100LDLARHARMv8.1
011101LDARH-
01111011111CASH, CASAH, CASALH, CASLHCASAHARMv8.1
01111111111CASH, CASAH, CASALH, CASLHCASALHARMv8.1
100000STXR32-bit-
100001STLXR32-bit-
100010STXP32-bit-
100011STLXP32-bit-
100100LDXR32-bit-
100101LDAXR32-bit-
100110LDXP32-bit-
100111LDAXP32-bit-
101000STLLR32-bitARMv8.1
101001STLR32-bit-
10101011111CAS, CASA, CASAL, CASL32-bit CASARMv8.1
10101111111CAS, CASA, CASAL, CASL32-bit CASLARMv8.1
101100LDLAR32-bitARMv8.1
101101LDAR32-bit-
10111011111CAS, CASA, CASAL, CASL32-bit CASAARMv8.1
10111111111CAS, CASA, CASAL, CASL32-bit CASALARMv8.1
110000STXR64-bit-
110001STLXR64-bit-
110010STXP64-bit-
110011STLXP64-bit-
110100LDXR64-bit-
110101LDAXR64-bit-
110110LDXP64-bit-
110111LDAXP64-bit-
111000STLLR64-bitARMv8.1
111001STLR64-bit-
11101011111CAS, CASA, CASAL, CASL64-bit CASARMv8.1
11101111111CAS, CASA, CASAL, CASL64-bit CASLARMv8.1
111100LDLAR64-bitARMv8.1
111101LDAR64-bit-
11111011111CAS, CASA, CASAL, CASL64-bit CASAARMv8.1
11111111111CAS, CASA, CASAL, CASL64-bit CASALARMv8.1

Load register (literal)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
opc011V00imm19Rt
Decode fields Instruction Details
opcV
000LDR (literal)32-bit
001LDR (literal, SIMD&FP)32-bit
010LDR (literal)64-bit
011LDR (literal, SIMD&FP)64-bit
100LDRSW (literal)
101LDR (literal, SIMD&FP)128-bit
110PRFM (literal)
111UNALLOCATED

Load/store no-allocate pair (offset)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
opc101V000Limm7Rt2RnRt
Decode fields Instruction Details
opcVL
0000STNP32-bit
0001LDNP32-bit
0010STNP (SIMD&FP)32-bit
0011LDNP (SIMD&FP)32-bit
010UNALLOCATED
0110STNP (SIMD&FP)64-bit
0111LDNP (SIMD&FP)64-bit
1000STNP64-bit
1001LDNP64-bit
1010STNP (SIMD&FP)128-bit
1011LDNP (SIMD&FP)128-bit
11UNALLOCATED

Load/store register pair (post-indexed)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
opc101V001Limm7Rt2RnRt
Decode fields Instruction Details Architecture Version
opcVL
0000STP32-bit-
0001LDP32-bit-
0010STP (SIMD&FP)32-bit-
0011LDP (SIMD&FP)32-bit-
0100STGPARMv8.5
0101LDPSW-
0110STP (SIMD&FP)64-bit-
0111LDP (SIMD&FP)64-bit-
1000STP64-bit-
1001LDP64-bit-
1010STP (SIMD&FP)128-bit-
1011LDP (SIMD&FP)128-bit-
11UNALLOCATED-

Load/store register pair (offset)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
opc101V010Limm7Rt2RnRt
Decode fields Instruction Details Architecture Version
opcVL
0000STP32-bit-
0001LDP32-bit-
0010STP (SIMD&FP)32-bit-
0011LDP (SIMD&FP)32-bit-
0100STGPARMv8.5
0101LDPSW-
0110STP (SIMD&FP)64-bit-
0111LDP (SIMD&FP)64-bit-
1000STP64-bit-
1001LDP64-bit-
1010STP (SIMD&FP)128-bit-
1011LDP (SIMD&FP)128-bit-
11UNALLOCATED-

Load/store register pair (pre-indexed)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
opc101V011Limm7Rt2RnRt
Decode fields Instruction Details Architecture Version
opcVL
0000STP32-bit-
0001LDP32-bit-
0010STP (SIMD&FP)32-bit-
0011LDP (SIMD&FP)32-bit-
0100STGPARMv8.5
0101LDPSW-
0110STP (SIMD&FP)64-bit-
0111LDP (SIMD&FP)64-bit-
1000STP64-bit-
1001LDP64-bit-
1010STP (SIMD&FP)128-bit-
1011LDP (SIMD&FP)128-bit-
11UNALLOCATED-

Load/store register (unscaled immediate)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111V00opc0imm900RnRt
Decode fields Instruction Details
sizeVopc
x111xUNALLOCATED
00000STURB
00001LDURB
00010LDURSB64-bit
00011LDURSB32-bit
00100STUR (SIMD&FP)8-bit
00101LDUR (SIMD&FP)8-bit
00110STUR (SIMD&FP)128-bit
00111LDUR (SIMD&FP)128-bit
01000STURH
01001LDURH
01010LDURSH64-bit
01011LDURSH32-bit
01100STUR (SIMD&FP)16-bit
01101LDUR (SIMD&FP)16-bit
1x011UNALLOCATED
1x11xUNALLOCATED
10000STUR32-bit
10001LDUR32-bit
10010LDURSW
10100STUR (SIMD&FP)32-bit
10101LDUR (SIMD&FP)32-bit
11000STUR64-bit
11001LDUR64-bit
11010PRFM (unscaled offset)
11100STUR (SIMD&FP)64-bit
11101LDUR (SIMD&FP)64-bit

Load/store register (immediate post-indexed)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111V00opc0imm901RnRt
Decode fields Instruction Details
sizeVopc
x111xUNALLOCATED
00000STRB (immediate)
00001LDRB (immediate)
00010LDRSB (immediate)64-bit
00011LDRSB (immediate)32-bit
00100STR (immediate, SIMD&FP)8-bit
00101LDR (immediate, SIMD&FP)8-bit
00110STR (immediate, SIMD&FP)128-bit
00111LDR (immediate, SIMD&FP)128-bit
01000STRH (immediate)
01001LDRH (immediate)
01010LDRSH (immediate)64-bit
01011LDRSH (immediate)32-bit
01100STR (immediate, SIMD&FP)16-bit
01101LDR (immediate, SIMD&FP)16-bit
1x011UNALLOCATED
1x11xUNALLOCATED
10000STR (immediate)32-bit
10001LDR (immediate)32-bit
10010LDRSW (immediate)
10100STR (immediate, SIMD&FP)32-bit
10101LDR (immediate, SIMD&FP)32-bit
11000STR (immediate)64-bit
11001LDR (immediate)64-bit
11010UNALLOCATED
11100STR (immediate, SIMD&FP)64-bit
11101LDR (immediate, SIMD&FP)64-bit

Load/store register (unprivileged)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111V00opc0imm910RnRt
Decode fields Instruction Details
sizeVopc
1UNALLOCATED
00000STTRB
00001LDTRB
00010LDTRSB64-bit
00011LDTRSB32-bit
01000STTRH
01001LDTRH
01010LDTRSH64-bit
01011LDTRSH32-bit
1x011UNALLOCATED
10000STTR32-bit
10001LDTR32-bit
10010LDTRSW
11000STTR64-bit
11001LDTR64-bit
11010UNALLOCATED

Load/store register (immediate pre-indexed)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111V00opc0imm911RnRt
Decode fields Instruction Details
sizeVopc
x111xUNALLOCATED
00000STRB (immediate)
00001LDRB (immediate)
00010LDRSB (immediate)64-bit
00011LDRSB (immediate)32-bit
00100STR (immediate, SIMD&FP)8-bit
00101LDR (immediate, SIMD&FP)8-bit
00110STR (immediate, SIMD&FP)128-bit
00111LDR (immediate, SIMD&FP)128-bit
01000STRH (immediate)
01001LDRH (immediate)
01010LDRSH (immediate)64-bit
01011LDRSH (immediate)32-bit
01100STR (immediate, SIMD&FP)16-bit
01101LDR (immediate, SIMD&FP)16-bit
1x011UNALLOCATED
1x11xUNALLOCATED
10000STR (immediate)32-bit
10001LDR (immediate)32-bit
10010LDRSW (immediate)
10100STR (immediate, SIMD&FP)32-bit
10101LDR (immediate, SIMD&FP)32-bit
11000STR (immediate)64-bit
11001LDR (immediate)64-bit
11010UNALLOCATED
11100STR (immediate, SIMD&FP)64-bit
11101LDR (immediate, SIMD&FP)64-bit

Atomic memory operations

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111V00AR1Rso3opc00RnRt
Decode fields Instruction Details Architecture Version
sizeVARo3opc
01001UNALLOCATED-
0101xUNALLOCATED-
01101UNALLOCATED-
0111xUNALLOCATED-
001100UNALLOCATED-
0111100UNALLOCATED-
1UNALLOCATED-
000000000LDADDB, LDADDAB, LDADDALB, LDADDLBLDADDBARMv8.1
000000001LDCLRB, LDCLRAB, LDCLRALB, LDCLRLBLDCLRBARMv8.1
000000010LDEORB, LDEORAB, LDEORALB, LDEORLBLDEORBARMv8.1
000000011LDSETB, LDSETAB, LDSETALB, LDSETLBLDSETBARMv8.1
000000100LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLBLDSMAXBARMv8.1
000000101LDSMINB, LDSMINAB, LDSMINALB, LDSMINLBLDSMINBARMv8.1
000000110LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLBLDUMAXBARMv8.1
000000111LDUMINB, LDUMINAB, LDUMINALB, LDUMINLBLDUMINBARMv8.1
000001000SWPB, SWPAB, SWPALB, SWPLBSWPBARMv8.1
000010000LDADDB, LDADDAB, LDADDALB, LDADDLBLDADDLBARMv8.1
000010001LDCLRB, LDCLRAB, LDCLRALB, LDCLRLBLDCLRLBARMv8.1
000010010LDEORB, LDEORAB, LDEORALB, LDEORLBLDEORLBARMv8.1
000010011LDSETB, LDSETAB, LDSETALB, LDSETLBLDSETLBARMv8.1
000010100LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLBLDSMAXLBARMv8.1
000010101LDSMINB, LDSMINAB, LDSMINALB, LDSMINLBLDSMINLBARMv8.1
000010110LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLBLDUMAXLBARMv8.1
000010111LDUMINB, LDUMINAB, LDUMINALB, LDUMINLBLDUMINLBARMv8.1
000011000SWPB, SWPAB, SWPALB, SWPLBSWPLBARMv8.1
000100000LDADDB, LDADDAB, LDADDALB, LDADDLBLDADDABARMv8.1
000100001LDCLRB, LDCLRAB, LDCLRALB, LDCLRLBLDCLRABARMv8.1
000100010LDEORB, LDEORAB, LDEORALB, LDEORLBLDEORABARMv8.1
000100011LDSETB, LDSETAB, LDSETALB, LDSETLBLDSETABARMv8.1
000100100LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLBLDSMAXABARMv8.1
000100101LDSMINB, LDSMINAB, LDSMINALB, LDSMINLBLDSMINABARMv8.1
000100110LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLBLDUMAXABARMv8.1
000100111LDUMINB, LDUMINAB, LDUMINALB, LDUMINLBLDUMINABARMv8.1
000101000SWPB, SWPAB, SWPALB, SWPLBSWPABARMv8.1
000101100LDAPRBARMv8.3
000110000LDADDB, LDADDAB, LDADDALB, LDADDLBLDADDALBARMv8.1
000110001LDCLRB, LDCLRAB, LDCLRALB, LDCLRLBLDCLRALBARMv8.1
000110010LDEORB, LDEORAB, LDEORALB, LDEORLBLDEORALBARMv8.1
000110011LDSETB, LDSETAB, LDSETALB, LDSETLBLDSETALBARMv8.1
000110100LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLBLDSMAXALBARMv8.1
000110101LDSMINB, LDSMINAB, LDSMINALB, LDSMINLBLDSMINALBARMv8.1
000110110LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLBLDUMAXALBARMv8.1
000110111LDUMINB, LDUMINAB, LDUMINALB, LDUMINLBLDUMINALBARMv8.1
000111000SWPB, SWPAB, SWPALB, SWPLBSWPALBARMv8.1
010000000LDADDH, LDADDAH, LDADDALH, LDADDLHLDADDHARMv8.1
010000001LDCLRH, LDCLRAH, LDCLRALH, LDCLRLHLDCLRHARMv8.1
010000010LDEORH, LDEORAH, LDEORALH, LDEORLHLDEORHARMv8.1
010000011LDSETH, LDSETAH, LDSETALH, LDSETLHLDSETHARMv8.1
010000100LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLHLDSMAXHARMv8.1
010000101LDSMINH, LDSMINAH, LDSMINALH, LDSMINLHLDSMINHARMv8.1
010000110LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLHLDUMAXHARMv8.1
010000111LDUMINH, LDUMINAH, LDUMINALH, LDUMINLHLDUMINHARMv8.1
010001000SWPH, SWPAH, SWPALH, SWPLHSWPHARMv8.1
010010000LDADDH, LDADDAH, LDADDALH, LDADDLHLDADDLHARMv8.1
010010001LDCLRH, LDCLRAH, LDCLRALH, LDCLRLHLDCLRLHARMv8.1
010010010LDEORH, LDEORAH, LDEORALH, LDEORLHLDEORLHARMv8.1
010010011LDSETH, LDSETAH, LDSETALH, LDSETLHLDSETLHARMv8.1
010010100LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLHLDSMAXLHARMv8.1
010010101LDSMINH, LDSMINAH, LDSMINALH, LDSMINLHLDSMINLHARMv8.1
010010110LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLHLDUMAXLHARMv8.1
010010111LDUMINH, LDUMINAH, LDUMINALH, LDUMINLHLDUMINLHARMv8.1
010011000SWPH, SWPAH, SWPALH, SWPLHSWPLHARMv8.1
010100000LDADDH, LDADDAH, LDADDALH, LDADDLHLDADDAHARMv8.1
010100001LDCLRH, LDCLRAH, LDCLRALH, LDCLRLHLDCLRAHARMv8.1
010100010LDEORH, LDEORAH, LDEORALH, LDEORLHLDEORAHARMv8.1
010100011LDSETH, LDSETAH, LDSETALH, LDSETLHLDSETAHARMv8.1
010100100LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLHLDSMAXAHARMv8.1
010100101LDSMINH, LDSMINAH, LDSMINALH, LDSMINLHLDSMINAHARMv8.1
010100110LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLHLDUMAXAHARMv8.1
010100111LDUMINH, LDUMINAH, LDUMINALH, LDUMINLHLDUMINAHARMv8.1
010101000SWPH, SWPAH, SWPALH, SWPLHSWPAHARMv8.1
010101100LDAPRHARMv8.3
010110000LDADDH, LDADDAH, LDADDALH, LDADDLHLDADDALHARMv8.1
010110001LDCLRH, LDCLRAH, LDCLRALH, LDCLRLHLDCLRALHARMv8.1
010110010LDEORH, LDEORAH, LDEORALH, LDEORLHLDEORALHARMv8.1
010110011LDSETH, LDSETAH, LDSETALH, LDSETLHLDSETALHARMv8.1
010110100LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLHLDSMAXALHARMv8.1
010110101LDSMINH, LDSMINAH, LDSMINALH, LDSMINLHLDSMINALHARMv8.1
010110110LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLHLDUMAXALHARMv8.1
010110111LDUMINH, LDUMINAH, LDUMINALH, LDUMINLHLDUMINALHARMv8.1
010111000SWPH, SWPAH, SWPALH, SWPLHSWPALHARMv8.1
100000000LDADD, LDADDA, LDADDAL, LDADDL32-bit LDADDARMv8.1
100000001LDCLR, LDCLRA, LDCLRAL, LDCLRL32-bit LDCLRARMv8.1
100000010LDEOR, LDEORA, LDEORAL, LDEORL32-bit LDEORARMv8.1
100000011LDSET, LDSETA, LDSETAL, LDSETL32-bit LDSETARMv8.1
100000100LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL32-bit LDSMAXARMv8.1
100000101LDSMIN, LDSMINA, LDSMINAL, LDSMINL32-bit LDSMINARMv8.1
100000110LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL32-bit LDUMAXARMv8.1
100000111LDUMIN, LDUMINA, LDUMINAL, LDUMINL32-bit LDUMINARMv8.1
100001000SWP, SWPA, SWPAL, SWPL32-bit SWPARMv8.1
100010000LDADD, LDADDA, LDADDAL, LDADDL32-bit LDADDLARMv8.1
100010001LDCLR, LDCLRA, LDCLRAL, LDCLRL32-bit LDCLRLARMv8.1
100010010LDEOR, LDEORA, LDEORAL, LDEORL32-bit LDEORLARMv8.1
100010011LDSET, LDSETA, LDSETAL, LDSETL32-bit LDSETLARMv8.1
100010100LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL32-bit LDSMAXLARMv8.1
100010101LDSMIN, LDSMINA, LDSMINAL, LDSMINL32-bit LDSMINLARMv8.1
100010110LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL32-bit LDUMAXLARMv8.1
100010111LDUMIN, LDUMINA, LDUMINAL, LDUMINL32-bit LDUMINLARMv8.1
100011000SWP, SWPA, SWPAL, SWPL32-bit SWPLARMv8.1
100100000LDADD, LDADDA, LDADDAL, LDADDL32-bit LDADDAARMv8.1
100100001LDCLR, LDCLRA, LDCLRAL, LDCLRL32-bit LDCLRAARMv8.1
100100010LDEOR, LDEORA, LDEORAL, LDEORL32-bit LDEORAARMv8.1
100100011LDSET, LDSETA, LDSETAL, LDSETL32-bit LDSETAARMv8.1
100100100LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL32-bit LDSMAXAARMv8.1
100100101LDSMIN, LDSMINA, LDSMINAL, LDSMINL32-bit LDSMINAARMv8.1
100100110LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL32-bit LDUMAXAARMv8.1
100100111LDUMIN, LDUMINA, LDUMINAL, LDUMINL32-bit LDUMINAARMv8.1
100101000SWP, SWPA, SWPAL, SWPL32-bit SWPAARMv8.1
100101100LDAPR32-bitARMv8.3
100110000LDADD, LDADDA, LDADDAL, LDADDL32-bit LDADDALARMv8.1
100110001LDCLR, LDCLRA, LDCLRAL, LDCLRL32-bit LDCLRALARMv8.1
100110010LDEOR, LDEORA, LDEORAL, LDEORL32-bit LDEORALARMv8.1
100110011LDSET, LDSETA, LDSETAL, LDSETL32-bit LDSETALARMv8.1
100110100LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL32-bit LDSMAXALARMv8.1
100110101LDSMIN, LDSMINA, LDSMINAL, LDSMINL32-bit LDSMINALARMv8.1
100110110LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL32-bit LDUMAXALARMv8.1
100110111LDUMIN, LDUMINA, LDUMINAL, LDUMINL32-bit LDUMINALARMv8.1
100111000SWP, SWPA, SWPAL, SWPL32-bit SWPALARMv8.1
110000000LDADD, LDADDA, LDADDAL, LDADDL64-bit LDADDARMv8.1
110000001LDCLR, LDCLRA, LDCLRAL, LDCLRL64-bit LDCLRARMv8.1
110000010LDEOR, LDEORA, LDEORAL, LDEORL64-bit LDEORARMv8.1
110000011LDSET, LDSETA, LDSETAL, LDSETL64-bit LDSETARMv8.1
110000100LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL64-bit LDSMAXARMv8.1
110000101LDSMIN, LDSMINA, LDSMINAL, LDSMINL64-bit LDSMINARMv8.1
110000110LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL64-bit LDUMAXARMv8.1
110000111LDUMIN, LDUMINA, LDUMINAL, LDUMINL64-bit LDUMINARMv8.1
110001000SWP, SWPA, SWPAL, SWPL64-bit SWPARMv8.1
110010000LDADD, LDADDA, LDADDAL, LDADDL64-bit LDADDLARMv8.1
110010001LDCLR, LDCLRA, LDCLRAL, LDCLRL64-bit LDCLRLARMv8.1
110010010LDEOR, LDEORA, LDEORAL, LDEORL64-bit LDEORLARMv8.1
110010011LDSET, LDSETA, LDSETAL, LDSETL64-bit LDSETLARMv8.1
110010100LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL64-bit LDSMAXLARMv8.1
110010101LDSMIN, LDSMINA, LDSMINAL, LDSMINL64-bit LDSMINLARMv8.1
110010110LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL64-bit LDUMAXLARMv8.1
110010111LDUMIN, LDUMINA, LDUMINAL, LDUMINL64-bit LDUMINLARMv8.1
110011000SWP, SWPA, SWPAL, SWPL64-bit SWPLARMv8.1
110100000LDADD, LDADDA, LDADDAL, LDADDL64-bit LDADDAARMv8.1
110100001LDCLR, LDCLRA, LDCLRAL, LDCLRL64-bit LDCLRAARMv8.1
110100010LDEOR, LDEORA, LDEORAL, LDEORL64-bit LDEORAARMv8.1
110100011LDSET, LDSETA, LDSETAL, LDSETL64-bit LDSETAARMv8.1
110100100LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL64-bit LDSMAXAARMv8.1
110100101LDSMIN, LDSMINA, LDSMINAL, LDSMINL64-bit LDSMINAARMv8.1
110100110LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL64-bit LDUMAXAARMv8.1
110100111LDUMIN, LDUMINA, LDUMINAL, LDUMINL64-bit LDUMINAARMv8.1
110101000SWP, SWPA, SWPAL, SWPL64-bit SWPAARMv8.1
110101100LDAPR64-bitARMv8.3
110110000LDADD, LDADDA, LDADDAL, LDADDL64-bit LDADDALARMv8.1
110110001LDCLR, LDCLRA, LDCLRAL, LDCLRL64-bit LDCLRALARMv8.1
110110010LDEOR, LDEORA, LDEORAL, LDEORL64-bit LDEORALARMv8.1
110110011LDSET, LDSETA, LDSETAL, LDSETL64-bit LDSETALARMv8.1
110110100LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL64-bit LDSMAXALARMv8.1
110110101LDSMIN, LDSMINA, LDSMINAL, LDSMINL64-bit LDSMINALARMv8.1
110110110LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL64-bit LDUMAXALARMv8.1
110110111LDUMIN, LDUMINA, LDUMINAL, LDUMINL64-bit LDUMINALARMv8.1
110111000SWP, SWPA, SWPAL, SWPL64-bit SWPALARMv8.1

Load/store register (register offset)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111V00opc1RmoptionS10RnRt
Decode fields Instruction Details
sizeVopcoption
x0xUNALLOCATED
x111xUNALLOCATED
00000!= 011STRB (register)extended register
00000011STRB (register)shifted register
00001!= 011LDRB (register)extended register
00001011LDRB (register)shifted register
00010!= 011LDRSB (register)64-bit with extended register offset
00010011LDRSB (register)64-bit with shifted register offset
00011!= 011LDRSB (register)32-bit with extended register offset
00011011LDRSB (register)32-bit with shifted register offset
00100!= 011STR (register, SIMD&FP)
00100011STR (register, SIMD&FP)
00101!= 011LDR (register, SIMD&FP)
00101011LDR (register, SIMD&FP)
00110STR (register, SIMD&FP)
00111LDR (register, SIMD&FP)
01000STRH (register)
01001LDRH (register)
01010LDRSH (register)64-bit
01011LDRSH (register)32-bit
01100STR (register, SIMD&FP)
01101LDR (register, SIMD&FP)
1x011UNALLOCATED
1x11xUNALLOCATED
10000STR (register)32-bit
10001LDR (register)32-bit
10010LDRSW (register)
10100STR (register, SIMD&FP)
10101LDR (register, SIMD&FP)
11000STR (register)64-bit
11001LDR (register)64-bit
11010PRFM (register)
11100STR (register, SIMD&FP)
11101LDR (register, SIMD&FP)

Load/store register (pac)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111V00MS1imm9W1RnRt
Decode fields Instruction Details Architecture Version
sizeMW
!= 11UNALLOCATED-
1100LDRAA, LDRABkey A, offsetARMv8.3
1101LDRAA, LDRABkey A, pre-indexedARMv8.3
1110LDRAA, LDRABkey B, offsetARMv8.3
1111LDRAA, LDRABkey B, pre-indexedARMv8.3

Load/store register (unsigned immediate)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111V01opcimm12RnRt
Decode fields Instruction Details
sizeVopc
x111xUNALLOCATED
00000STRB (immediate)
00001LDRB (immediate)
00010LDRSB (immediate)64-bit
00011LDRSB (immediate)32-bit
00100STR (immediate, SIMD&FP)8-bit
00101LDR (immediate, SIMD&FP)8-bit
00110STR (immediate, SIMD&FP)128-bit
00111LDR (immediate, SIMD&FP)128-bit
01000STRH (immediate)
01001LDRH (immediate)
01010LDRSH (immediate)64-bit
01011LDRSH (immediate)32-bit
01100STR (immediate, SIMD&FP)16-bit
01101LDR (immediate, SIMD&FP)16-bit
1x011UNALLOCATED
1x11xUNALLOCATED
10000STR (immediate)32-bit
10001LDR (immediate)32-bit
10010LDRSW (immediate)
10100STR (immediate, SIMD&FP)32-bit
10101LDR (immediate, SIMD&FP)32-bit
11000STR (immediate)64-bit
11001LDR (immediate)64-bit
11010PRFM (immediate)
11100STR (immediate, SIMD&FP)64-bit
11101LDR (immediate, SIMD&FP)64-bit

Data Processing -- Register

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
op0op1101op2op3
Decode fields Instruction details
op0op1op2op3
0 1 0110 Data-processing (2 source)
1 1 0110 Data-processing (1 source)
0 0xxx Logical (shifted register)
0 1xx0 Add/subtract (shifted register)
0 1xx1 Add/subtract (extended register)
1 0000 000000 Add/subtract (with carry)
1 0000 000011 UNALLOCATED
1 0000 0001xx UNALLOCATED
1 0000 001xxx UNALLOCATED
1 0000 01xxxx UNALLOCATED
1 0000 1xxxxx UNALLOCATED
1 0000 x00001 Rotate right into flags
1 0000 xx0010 Evaluate into flags
1 0010 xxxx0x Conditional compare (register)
1 0010 xxxx1x Conditional compare (immediate)
1 0100 Conditional select
1 0xx1 UNALLOCATED
1 1xxx Data-processing (3 source)

Data-processing (2 source)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sf0S11010110RmopcodeRnRd
Decode fields Instruction Details Architecture Version
sfSopcode
000001UNALLOCATED-
011xxxUNALLOCATED-
1xxxxxUNALLOCATED-
0000101UNALLOCATED-
00011xxUNALLOCATED-
100001xUNALLOCATED-
10001xxUNALLOCATED-
1001xxxUNALLOCATED-
101xxxxUNALLOCATED-
0000000UNALLOCATED-
00000010UDIV32-bit-
00000011SDIV32-bit-
00000100UNALLOCATED-
0000011xUNALLOCATED-
00001000LSLV32-bit-
00001001LSRV32-bit-
00001010ASRV32-bit-
00001011RORV32-bit-
00010x11UNALLOCATED-
00010000CRC32B, CRC32H, CRC32W, CRC32XCRC32B-
00010001CRC32B, CRC32H, CRC32W, CRC32XCRC32H-
00010010CRC32B, CRC32H, CRC32W, CRC32XCRC32W-
00010100CRC32CB, CRC32CH, CRC32CW, CRC32CXCRC32CB-
00010101CRC32CB, CRC32CH, CRC32CW, CRC32CXCRC32CH-
00010110CRC32CB, CRC32CH, CRC32CW, CRC32CXCRC32CW-
10000000SUBPARMv8.5
10000010UDIV64-bit-
10000011SDIV64-bit-
10000100IRGARMv8.5
10000101GMIARMv8.5
10001000LSLV64-bit-
10001001LSRV64-bit-
10001010ASRV64-bit-
10001011RORV64-bit-
10001100PACGAARMv8.3
10010xx0UNALLOCATED-
10010x0xUNALLOCATED-
10010011CRC32B, CRC32H, CRC32W, CRC32XCRC32X-
10010111CRC32CB, CRC32CH, CRC32CW, CRC32CXCRC32CX-
11000000SUBPSARMv8.5

Data-processing (1 source)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sf1S11010110opcode2opcodeRnRd
Decode fields Instruction Details Architecture Version
sfSopcode2opcodeRn
xx1xxxUNALLOCATED-
x1xxxxUNALLOCATED-
1xxxxxUNALLOCATED-
xxxx1UNALLOCATED-
xxx1xUNALLOCATED-
xx1xxUNALLOCATED-
x1xxxUNALLOCATED-
1xxxxUNALLOCATED-
00000000011xUNALLOCATED-
1UNALLOCATED-
0000000000000RBIT32-bit-
0000000000001REV1632-bit-
0000000000010REV32-bit-
0000000000011UNALLOCATED-
0000000000100CLZ32-bit-
0000000000101CLS32-bit-
1000000000000RBIT64-bit-
1000000000001REV1664-bit-
1000000000010REV32-
1000000000011REV64-bit-
1000000000100CLZ64-bit-
1000000000101CLS64-bit-
1000001000000PACIA, PACIA1716, PACIASP, PACIAZ, PACIZAPACIAARMv8.3
1000001000001PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZBPACIBARMv8.3
1000001000010PACDA, PACDZAPACDAARMv8.3
1000001000011PACDB, PACDZBPACDBARMv8.3
1000001000100AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZAAUTIAARMv8.3
1000001000101AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZBAUTIBARMv8.3
1000001000110AUTDA, AUTDZAAUTDAARMv8.3
1000001000111AUTDB, AUTDZBAUTDBARMv8.3
100000100100011111PACIA, PACIA1716, PACIASP, PACIAZ, PACIZAPACIZAARMv8.3
100000100100111111PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZBPACIZBARMv8.3
100000100101011111PACDA, PACDZAPACDZAARMv8.3
100000100101111111PACDB, PACDZBPACDZBARMv8.3
100000100110011111AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZAAUTIZAARMv8.3
100000100110111111AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZBAUTIZBARMv8.3
100000100111011111AUTDA, AUTDZAAUTDZAARMv8.3
100000100111111111AUTDB, AUTDZBAUTDZBARMv8.3
100000101000011111XPACD, XPACI, XPACLRIXPACIARMv8.3
100000101000111111XPACD, XPACI, XPACLRIXPACDARMv8.3

Logical (shifted register)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopc01010shiftNRmimm6RnRd
Decode fields Instruction Details
sfopcNimm6
01xxxxxUNALLOCATED
0000AND (shifted register)32-bit
0001BIC (shifted register)32-bit
0010ORR (shifted register)32-bit
0011ORN (shifted register)32-bit
0100EOR (shifted register)32-bit
0101EON (shifted register)32-bit
0110ANDS (shifted register)32-bit
0111BICS (shifted register)32-bit
1000AND (shifted register)64-bit
1001BIC (shifted register)64-bit
1010ORR (shifted register)64-bit
1011ORN (shifted register)64-bit
1100EOR (shifted register)64-bit
1101EON (shifted register)64-bit
1110ANDS (shifted register)64-bit
1111BICS (shifted register)64-bit

Add/subtract (shifted register)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS01011shift0Rmimm6RnRd
Decode fields Instruction Details
sfopSshiftimm6
11UNALLOCATED
01xxxxxUNALLOCATED
000ADD (shifted register)32-bit
001ADDS (shifted register)32-bit
010SUB (shifted register)32-bit
011SUBS (shifted register)32-bit
100ADD (shifted register)64-bit
101ADDS (shifted register)64-bit
110SUB (shifted register)64-bit
111SUBS (shifted register)64-bit

Add/subtract (extended register)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS01011opt1Rmoptionimm3RnRd
Decode fields Instruction Details
sfopSoptimm3
1x1UNALLOCATED
11xUNALLOCATED
x1UNALLOCATED
1xUNALLOCATED
00000ADD (extended register)32-bit
00100ADDS (extended register)32-bit
01000SUB (extended register)32-bit
01100SUBS (extended register)32-bit
10000ADD (extended register)64-bit
10100ADDS (extended register)64-bit
11000SUB (extended register)64-bit
11100SUBS (extended register)64-bit

Add/subtract (with carry)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010000Rm000000RnRd
Decode fields Instruction Details
sfopS
000ADC32-bit
001ADCS32-bit
010SBC32-bit
011SBCS32-bit
100ADC64-bit
101ADCS64-bit
110SBC64-bit
111SBCS64-bit

Rotate right into flags

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010000imm600001Rno2mask
Decode fields Instruction Details Architecture Version
sfopSo2
0UNALLOCATED-
100UNALLOCATED-
1010RMIFARMv8.4
1011UNALLOCATED-
11UNALLOCATED-

Evaluate into flags

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010000opcode2sz0010Rno3mask
Decode fields Instruction Details Architecture Version
sfopSopcode2szo3mask
000UNALLOCATED-
001!= 000000UNALLOCATED-
0010000000!= 1101UNALLOCATED-
0010000001UNALLOCATED-
001000000001101SETF8, SETF16SETF8ARMv8.4
001000000101101SETF8, SETF16SETF16ARMv8.4
01UNALLOCATED-
1UNALLOCATED-

Conditional compare (register)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010010Rmcond0o2Rno3nzcv
Decode fields Instruction Details
sfopSo2o3
1UNALLOCATED
1UNALLOCATED
0UNALLOCATED
00100CCMN (register)32-bit
01100CCMP (register)32-bit
10100CCMN (register)64-bit
11100CCMP (register)64-bit

Conditional compare (immediate)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010010imm5cond1o2Rno3nzcv
Decode fields Instruction Details
sfopSo2o3
1UNALLOCATED
1UNALLOCATED
0UNALLOCATED
00100CCMN (immediate)32-bit
01100CCMP (immediate)32-bit
10100CCMN (immediate)64-bit
11100CCMP (immediate)64-bit

Conditional select

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010100Rmcondop2RnRd
Decode fields Instruction Details
sfopSop2
1xUNALLOCATED
1UNALLOCATED
00000CSEL32-bit
00001CSINC32-bit
01000CSINV32-bit
01001CSNEG32-bit
10000CSEL64-bit
10001CSINC64-bit
11000CSINV64-bit
11001CSNEG64-bit

Data-processing (3 source)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfop5411011op31Rmo0RaRnRd
Decode fields Instruction Details
sfop54op31o0
000101UNALLOCATED
00011UNALLOCATED
00100UNALLOCATED
001101UNALLOCATED
00111UNALLOCATED
01UNALLOCATED
1xUNALLOCATED
0000000MADD32-bit
0000001MSUB32-bit
0000010UNALLOCATED
0000011UNALLOCATED
0000100UNALLOCATED
0001010UNALLOCATED
0001011UNALLOCATED
0001100UNALLOCATED
1000000MADD64-bit
1000001MSUB64-bit
1000010SMADDL
1000011SMSUBL
1000100SMULH
1001010UMADDL
1001011UMSUBL
1001100UMULH

Data Processing -- Scalar Floating-Point and Advanced SIMD

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
op0111op1op2op3
Decode fields Instruction details Architecture version
op0op1op2op3
0000 0x x101 00xxxxx10 UNALLOCATED-
0010 0x x101 00xxxxx10 UNALLOCATED-
0100 0x x101 00xxxxx10 Cryptographic AES-
0101 0x x0xx xxx0xxx00 Cryptographic three-register SHA-
0101 0x x0xx xxx0xxx10 UNALLOCATED-
0101 0x x101 00xxxxx10 Cryptographic two-register SHA-
0110 0x x101 00xxxxx10 UNALLOCATED-
0111 0x x0xx xxx0xxxx0 UNALLOCATED-
0111 0x x101 00xxxxx10 UNALLOCATED-
01x1 00 00xx xxx0xxxx1 Advanced SIMD scalar copy-
01x1 01 00xx xxx0xxxx1 UNALLOCATED-
01x1 0x 0111 00xxxxx10 UNALLOCATED-
01x1 0x 10xx xxx00xxx1 Advanced SIMD scalar three same FP16ARMv8.2
01x1 0x 10xx xxx01xxx1 UNALLOCATED-
01x1 0x 1111 00xxxxx10 Advanced SIMD scalar two-register miscellaneous FP16ARMv8.2
01x1 0x x0xx xxx1xxxx0 UNALLOCATED-
01x1 0x x0xx xxx1xxxx1 Advanced SIMD scalar three same extraARMv8.1
01x1 0x x100 00xxxxx10 Advanced SIMD scalar two-register miscellaneous-
01x1 0x x110 00xxxxx10 Advanced SIMD scalar pairwiseARMv8.2
01x1 0x x1xx 1xxxxxx10 UNALLOCATED-
01x1 0x x1xx x1xxxxx10 UNALLOCATED-
01x1 0x x1xx xxxxxxx00 Advanced SIMD scalar three different-
01x1 0x x1xx xxxxxxxx1 Advanced SIMD scalar three same-
01x1 10 xxxxxxxx1 Advanced SIMD scalar shift by immediate-
01x1 11 xxxxxxxx1 UNALLOCATED-
01x1 1x xxxxxxxx0 Advanced SIMD scalar x indexed elementARMv8.2
0x00 0x x0xx xxx0xxx00 Advanced SIMD table lookup-
0x00 0x x0xx xxx0xxx10 Advanced SIMD permute-
0x10 0x x0xx xxx0xxxx0 Advanced SIMD extract-
0xx0 00 00xx xxx0xxxx1 Advanced SIMD copy-
0xx0 01 00xx xxx0xxxx1 UNALLOCATED-
0xx0 0x 0111 00xxxxx10 UNALLOCATED-
0xx0 0x 10xx xxx00xxx1 Advanced SIMD three same (FP16)ARMv8.2
0xx0 0x 10xx xxx01xxx1 UNALLOCATED-
0xx0 0x 1111 00xxxxx10 Advanced SIMD two-register miscellaneous (FP16)ARMv8.2
0xx0 0x x0xx xxx1xxxx0 UNALLOCATED-
0xx0 0x x0xx xxx1xxxx1 Advanced SIMD three same extraARMv8.2
0xx0 0x x100 00xxxxx10 Advanced SIMD two-register miscellaneousARMv8.5
0xx0 0x x110 00xxxxx10 Advanced SIMD across lanesARMv8.2
0xx0 0x x1xx 1xxxxxx10 UNALLOCATED-
0xx0 0x x1xx x1xxxxx10 UNALLOCATED-
0xx0 0x x1xx xxxxxxx00 Advanced SIMD three different-
0xx0 0x x1xx xxxxxxxx1 Advanced SIMD three sameARMv8.2
0xx0 10 0000 xxxxxxxx1 Advanced SIMD modified immediateARMv8.2
0xx0 10 != 0000 xxxxxxxx1 Advanced SIMD shift by immediate-
0xx0 11 xxxxxxxx1 UNALLOCATED-
0xx0 1x xxxxxxxx0 Advanced SIMD vector x indexed elementARMv8.2
1100 00 10xx xxx10xxxx Cryptographic three-register, imm2ARMv8.2
1100 00 11xx xxx1x00xx Cryptographic three-register SHA 512ARMv8.2
1100 00 xxx0xxxxx Cryptographic four-registerARMv8.2
1100 01 00xx XARARMv8.2
1100 01 1000 0001000xx Cryptographic two-register SHA 512ARMv8.2
11x1 UNALLOCATED-
1xx0 1x UNALLOCATED-
x0x1 0x x0xx Conversion between floating-point and fixed-pointARMv8.2
x0x1 0x x1xx xxx000000 Conversion between floating-point and integerARMv8.3
x0x1 0x x1xx xxx100000 UNALLOCATED-
x0x1 0x x1xx xxxx10000 Floating-point data-processing (1 source)ARMv8.5
x0x1 0x x1xx xxxxx1000 Floating-point compareARMv8.2
x0x1 0x x1xx xxxxxx100 Floating-point immediateARMv8.2
x0x1 0x x1xx xxxxxxx01 Floating-point conditional compareARMv8.2
x0x1 0x x1xx xxxxxxx10 Floating-point data-processing (2 source)ARMv8.2
x0x1 0x x1xx xxxxxxx11 Floating-point conditional selectARMv8.2
x0x1 1x Floating-point data-processing (3 source)ARMv8.2

Cryptographic AES

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01001110size10100opcode10RnRd
Decode fields Instruction Details
sizeopcode
x1xxxUNALLOCATED
000xxUNALLOCATED
1xxxxUNALLOCATED
x1UNALLOCATED
0000100AESE
0000101AESD
0000110AESMC
0000111AESIMC
1xUNALLOCATED

Cryptographic three-register SHA

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01011110size0Rm0opcode00RnRd
Decode fields Instruction Details
sizeopcode
111UNALLOCATED
x1UNALLOCATED
00000SHA1C
00001SHA1P
00010SHA1M
00011SHA1SU0
00100SHA256H
00101SHA256H2
00110SHA256SU1
1xUNALLOCATED

Cryptographic two-register SHA

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01011110size10100opcode10RnRd
Decode fields Instruction Details
sizeopcode
xx1xxUNALLOCATED
x1xxxUNALLOCATED
1xxxxUNALLOCATED
x1UNALLOCATED
0000000SHA1H
0000001SHA1SU1
0000010SHA256SU0
0000011UNALLOCATED
1xUNALLOCATED

Advanced SIMD scalar copy

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01op11110000imm50imm41RnRd
Decode fields Instruction Details
opimm5imm4
0xxx1UNALLOCATED
0xx1xUNALLOCATED
0x1xxUNALLOCATED
00000DUP (element)
01xxxUNALLOCATED
0x00000000UNALLOCATED
1UNALLOCATED

Advanced SIMD scalar three same FP16

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110a10Rm00opcode1RnRd
Decode fields Instruction Details Architecture Version
Uaopcode
110UNALLOCATED-
1011UNALLOCATED-
00011FMULXARMv8.2
00100FCMEQ (register)ARMv8.2
00101UNALLOCATED-
00111FRECPSARMv8.2
01100UNALLOCATED-
01101UNALLOCATED-
01111FRSQRTSARMv8.2
10011UNALLOCATED-
10100FCMGE (register)ARMv8.2
10101FACGEARMv8.2
10111UNALLOCATED-
11010FABDARMv8.2
11100FCMGT (register)ARMv8.2
11101FACGTARMv8.2
11111UNALLOCATED-

Advanced SIMD scalar two-register miscellaneous FP16

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110a111100opcode10RnRd
Decode fields Instruction Details Architecture Version
Uaopcode
00xxxUNALLOCATED-
010xxUNALLOCATED-
10xxxUNALLOCATED-
1100xUNALLOCATED-
11110UNALLOCATED-
0011xxUNALLOCATED-
011111UNALLOCATED-
101111UNALLOCATED-
111100UNALLOCATED-
0011010FCVTNS (vector)ARMv8.2
0011011FCVTMS (vector)ARMv8.2
0011100FCVTAS (vector)ARMv8.2
0011101SCVTF (vector, integer)ARMv8.2
0101100FCMGT (zero)ARMv8.2
0101101FCMEQ (zero)ARMv8.2
0101110FCMLT (zero)ARMv8.2
0111010FCVTPS (vector)ARMv8.2
0111011FCVTZS (vector, integer)ARMv8.2
0111101FRECPEARMv8.2
0111111FRECPXARMv8.2
1011010FCVTNU (vector)ARMv8.2
1011011FCVTMU (vector)ARMv8.2
1011100FCVTAU (vector)ARMv8.2
1011101UCVTF (vector, integer)ARMv8.2
1101100FCMGE (zero)ARMv8.2
1101101FCMLE (zero)ARMv8.2
1101110UNALLOCATED-
1111010FCVTPU (vector)ARMv8.2
1111011FCVTZU (vector, integer)ARMv8.2
1111101FRSQRTEARMv8.2
1111111UNALLOCATED-

Advanced SIMD scalar three same extra

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110size0Rm1opcode1RnRd
Decode fields Instruction Details Architecture Version
Uopcode
001xUNALLOCATED-
01xxUNALLOCATED-
1xxxUNALLOCATED-
00000UNALLOCATED-
00001UNALLOCATED-
10000SQRDMLAH (vector)ARMv8.1
10001SQRDMLSH (vector)ARMv8.1

Advanced SIMD scalar two-register miscellaneous

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110size10000opcode10RnRd
Decode fields Instruction Details
Usizeopcode
0000xUNALLOCATED
00010UNALLOCATED
0010xUNALLOCATED
00110UNALLOCATED
01111UNALLOCATED
1000xUNALLOCATED
10011UNALLOCATED
10101UNALLOCATED
10111UNALLOCATED
1100xUNALLOCATED
11110UNALLOCATED
0x011xxUNALLOCATED
0x11111UNALLOCATED
1x10110UNALLOCATED
1x11100UNALLOCATED
000011SUQADD
000111SQABS
001000CMGT (zero)
001001CMEQ (zero)
001010CMLT (zero)
001011ABS
010010UNALLOCATED
010100SQXTN, SQXTN2
00x10110UNALLOCATED
00x11010FCVTNS (vector)
00x11011FCVTMS (vector)
00x11100FCVTAS (vector)
00x11101SCVTF (vector, integer)
01x01100FCMGT (zero)
01x01101FCMEQ (zero)
01x01110FCMLT (zero)
01x11010FCVTPS (vector)
01x11011FCVTZS (vector, integer)
01x11101FRECPE
01x11111FRECPX
100011USQADD
100111SQNEG
101000CMGE (zero)
101001CMLE (zero)
101010UNALLOCATED
101011NEG (vector)
110010SQXTUN, SQXTUN2
110100UQXTN, UQXTN2
10x10110FCVTXN, FCVTXN2
10x11010FCVTNU (vector)
10x11011FCVTMU (vector)
10x11100FCVTAU (vector)
10x11101UCVTF (vector, integer)
11x01100FCMGE (zero)
11x01101FCMLE (zero)
11x01110UNALLOCATED
11x11010FCVTPU (vector)
11x11011FCVTZU (vector, integer)
11x11101FRSQRTE
11x11111UNALLOCATED

Advanced SIMD scalar pairwise

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110size11000opcode10RnRd
Decode fields Instruction Details Architecture Version
Usizeopcode
00xxxUNALLOCATED-
010xxUNALLOCATED-
01110UNALLOCATED-
10xxxUNALLOCATED-
1100xUNALLOCATED-
11010UNALLOCATED-
111xxUNALLOCATED-
1x01101UNALLOCATED-
011011ADDP (scalar)-
00001100FMAXNMP (scalar)half-precisionARMv8.2
00001101FADDP (scalar)half-precisionARMv8.2
00001111FMAXP (scalar)half-precisionARMv8.2
00101100UNALLOCATED-
00101101UNALLOCATED-
00101111UNALLOCATED-
01001100FMINNMP (scalar)half-precisionARMv8.2
01001111FMINP (scalar)half-precisionARMv8.2
01101100UNALLOCATED-
01101111UNALLOCATED-
111011UNALLOCATED-
10x01100FMAXNMP (scalar)single-precision and double-precision-
10x01101FADDP (scalar)single-precision and double-precision-
10x01111FMAXP (scalar)single-precision and double-precision-
11x01100FMINNMP (scalar)single-precision and double-precision-
11x01111FMINP (scalar)single-precision and double-precision-

Advanced SIMD scalar three different

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110size1Rmopcode00RnRd
Decode fields Instruction Details
Uopcode
00xxUNALLOCATED
01xxUNALLOCATED
1000UNALLOCATED
1010UNALLOCATED
1100UNALLOCATED
111xUNALLOCATED
01001SQDMLAL, SQDMLAL2 (vector)
01011SQDMLSL, SQDMLSL2 (vector)
01101SQDMULL, SQDMULL2 (vector)
11001UNALLOCATED
11011UNALLOCATED
11101UNALLOCATED

Advanced SIMD scalar three same

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110size1Rmopcode1RnRd
Decode fields Instruction Details
Usizeopcode
00000UNALLOCATED
0001xUNALLOCATED
00100UNALLOCATED
011xxUNALLOCATED
1001xUNALLOCATED
1x11011UNALLOCATED
000001SQADD
000101SQSUB
000110CMGT (register)
000111CMGE (register)
001000SSHL
001001SQSHL (register)
001010SRSHL
001011SQRSHL
010000ADD (vector)
010001CMTST
010100UNALLOCATED
010101UNALLOCATED
010110SQDMULH (vector)
010111UNALLOCATED
00x11000UNALLOCATED
00x11001UNALLOCATED
00x11010UNALLOCATED
00x11011FMULX
00x11100FCMEQ (register)
00x11101UNALLOCATED
00x11110UNALLOCATED
00x11111FRECPS
01x11000UNALLOCATED
01x11001UNALLOCATED
01x11010UNALLOCATED
01x11100UNALLOCATED
01x11101UNALLOCATED
01x11110UNALLOCATED
01x11111FRSQRTS
100001UQADD
100101UQSUB
100110CMHI (register)
100111CMHS (register)
101000USHL
101001UQSHL (register)
101010URSHL
101011UQRSHL
110000SUB (vector)
110001CMEQ (register)
110100UNALLOCATED
110101UNALLOCATED
110110SQRDMULH (vector)
110111UNALLOCATED
10x11000UNALLOCATED
10x11001UNALLOCATED
10x11010UNALLOCATED
10x11011UNALLOCATED
10x11100FCMGE (register)
10x11101FACGE
10x11110UNALLOCATED
10x11111UNALLOCATED
11x11000UNALLOCATED
11x11001UNALLOCATED
11x11010FABD
11x11100FCMGT (register)
11x11101FACGT
11x11110UNALLOCATED
11x11111UNALLOCATED

Advanced SIMD scalar shift by immediate

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U111110immhimmbopcode1RnRd
Decode fields Instruction Details
Uimmhopcode
!= 000000001UNALLOCATED
!= 000000011UNALLOCATED
!= 000000101UNALLOCATED
!= 000000111UNALLOCATED
!= 000001001UNALLOCATED
!= 000001011UNALLOCATED
!= 000001101UNALLOCATED
!= 000001111UNALLOCATED
!= 0000101xxUNALLOCATED
!= 0000110xxUNALLOCATED
!= 000011101UNALLOCATED
!= 000011110UNALLOCATED
0000UNALLOCATED
0!= 000000000SSHR
0!= 000000010SSRA
0!= 000000100SRSHR
0!= 000000110SRSRA
0!= 000001000UNALLOCATED
0!= 000001010SHL
0!= 000001100UNALLOCATED
0!= 000001110SQSHL (immediate)
0!= 000010000UNALLOCATED
0!= 000010001UNALLOCATED
0!= 000010010SQSHRN, SQSHRN2
0!= 000010011SQRSHRN, SQRSHRN2
0!= 000011100SCVTF (vector, fixed-point)
0!= 000011111FCVTZS (vector, fixed-point)
1!= 000000000USHR
1!= 000000010USRA
1!= 000000100URSHR
1!= 000000110URSRA
1!= 000001000SRI
1!= 000001010SLI
1!= 000001100SQSHLU
1!= 000001110UQSHL (immediate)
1!= 000010000SQSHRUN, SQSHRUN2
1!= 000010001SQRSHRUN, SQRSHRUN2
1!= 000010010UQSHRN, UQSHRN2
1!= 000010011UQRSHRN, UQRSHRN2
1!= 000011100UCVTF (vector, fixed-point)
1!= 000011111FCVTZU (vector, fixed-point)

Advanced SIMD scalar x indexed element

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11111sizeLMRmopcodeH0RnRd
Decode fields Instruction Details Architecture Version
Usizeopcode
0000UNALLOCATED-
0010UNALLOCATED-
0100UNALLOCATED-
0110UNALLOCATED-
1000UNALLOCATED-
1010UNALLOCATED-
1110UNALLOCATED-
010001UNALLOCATED-
010101UNALLOCATED-
011001UNALLOCATED-
00011SQDMLAL, SQDMLAL2 (by element)-
00111SQDMLSL, SQDMLSL2 (by element)-
01011SQDMULL, SQDMULL2 (by element)-
01100SQDMULH (by element)-
01101SQRDMULH (by element)-
01111UNALLOCATED-
0000001FMLA (by element)half-precisionARMv8.2
0000101FMLS (by element)half-precisionARMv8.2
0001001FMUL (by element)half-precisionARMv8.2
01x0001FMLA (by element)single-precision and double-precision-
01x0101FMLS (by element)single-precision and double-precision-
01x1001FMUL (by element)single-precision and double-precision-
10011UNALLOCATED-
10111UNALLOCATED-
11011UNALLOCATED-
11100UNALLOCATED-
11101SQRDMLAH (by element)ARMv8.1
11111SQRDMLSH (by element)ARMv8.1
1000001UNALLOCATED-
1000101UNALLOCATED-
1001001FMULX (by element)half-precisionARMv8.2
11x0001UNALLOCATED-
11x0101UNALLOCATED-
11x1001FMULX (by element)single-precision and double-precision-

Advanced SIMD table lookup

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0Q001110op20Rm0lenop00RnRd
Decode fields Instruction Details
op2lenop
x1UNALLOCATED
00000TBLsingle register table
00001TBXsingle register table
00010TBLtwo register table
00011TBXtwo register table
00100TBLthree register table
00101TBXthree register table
00110TBLfour register table
00111TBXfour register table
1xUNALLOCATED

Advanced SIMD permute

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0Q001110size0Rm0opcode10RnRd
Decode fields Instruction Details
opcode
000UNALLOCATED
001UZP1
010TRN1
011ZIP1
100UNALLOCATED
101UZP2
110TRN2
111ZIP2

Advanced SIMD extract

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0Q101110op20Rm0imm40RnRd
Decode fields Instruction Details
op2
x1UNALLOCATED
00EXT
1xUNALLOCATED

Advanced SIMD copy

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0Qop01110000imm50imm41RnRd
Decode fields Instruction Details
Qopimm5imm4
x0000UNALLOCATED
00000DUP (element)
00001DUP (general)
00010UNALLOCATED
00100UNALLOCATED
00110UNALLOCATED
01xxxUNALLOCATED
000011UNALLOCATED
000101SMOV
000111UMOV
01UNALLOCATED
100011INS (general)
100101SMOV
10x10000111UMOV
11INS (element)

Advanced SIMD three same (FP16)

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110a10Rm00opcode1RnRd
Decode fields Instruction Details Architecture Version
Uaopcode
00000FMAXNM (vector)ARMv8.2
00001FMLA (vector)ARMv8.2
00010FADD (vector)ARMv8.2
00011FMULXARMv8.2
00100FCMEQ (register)ARMv8.2
00101UNALLOCATED-
00110FMAX (vector)ARMv8.2
00111FRECPSARMv8.2
01000FMINNM (vector)ARMv8.2
01001FMLS (vector)ARMv8.2
01010FSUB (vector)ARMv8.2
01011UNALLOCATED-
01100UNALLOCATED-
01101UNALLOCATED-
01110FMIN (vector)ARMv8.2
01111FRSQRTSARMv8.2
10000FMAXNMP (vector)ARMv8.2
10001UNALLOCATED-
10010FADDP (vector)ARMv8.2
10011FMUL (vector)ARMv8.2
10100FCMGE (register)ARMv8.2
10101FACGEARMv8.2
10110FMAXP (vector)ARMv8.2
10111FDIV (vector)ARMv8.2
11000FMINNMP (vector)ARMv8.2
11001UNALLOCATED-
11010FABDARMv8.2
11011UNALLOCATED-
11100FCMGT (register)ARMv8.2
11101FACGTARMv8.2
11110FMINP (vector)ARMv8.2
11111UNALLOCATED-

Advanced SIMD two-register miscellaneous (FP16)

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110a111100opcode10RnRd
Decode fields Instruction Details Architecture Version
Uaopcode
00xxxUNALLOCATED-
010xxUNALLOCATED-
10xxxUNALLOCATED-
11110UNALLOCATED-
0011xxUNALLOCATED-
011111UNALLOCATED-
111100UNALLOCATED-
0011000FRINTN (vector)ARMv8.2
0011001FRINTM (vector)ARMv8.2
0011010FCVTNS (vector)ARMv8.2
0011011FCVTMS (vector)ARMv8.2
0011100FCVTAS (vector)ARMv8.2
0011101SCVTF (vector, integer)ARMv8.2
0101100FCMGT (zero)ARMv8.2
0101101FCMEQ (zero)ARMv8.2
0101110FCMLT (zero)ARMv8.2
0101111FABS (vector)ARMv8.2
0111000FRINTP (vector)ARMv8.2
0111001FRINTZ (vector)ARMv8.2
0111010FCVTPS (vector)ARMv8.2
0111011FCVTZS (vector, integer)ARMv8.2
0111101FRECPEARMv8.2
0111111UNALLOCATED-
1011000FRINTA (vector)ARMv8.2
1011001FRINTX (vector)ARMv8.2
1011010FCVTNU (vector)ARMv8.2
1011011FCVTMU (vector)ARMv8.2
1011100FCVTAU (vector)ARMv8.2
1011101UCVTF (vector, integer)ARMv8.2
1101100FCMGE (zero)ARMv8.2
1101101FCMLE (zero)ARMv8.2
1101110UNALLOCATED-
1101111FNEG (vector)ARMv8.2
1111000UNALLOCATED-
1111001FRINTI (vector)ARMv8.2
1111010FCVTPU (vector)ARMv8.2
1111011FCVTZU (vector, integer)ARMv8.2
1111101FRSQRTEARMv8.2
1111111FSQRT (vector)ARMv8.2

Advanced SIMD three same extra

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110size0Rm1opcode1RnRd
Decode fields Instruction Details Architecture Version
Uopcode
0011UNALLOCATED-
01xxUNALLOCATED-
00000UNALLOCATED-
00001UNALLOCATED-
00010SDOT (vector)ARMv8.2
01xxxUNALLOCATED-
10000SQRDMLAH (vector)ARMv8.1
10001SQRDMLSH (vector)ARMv8.1
10010UDOT (vector)ARMv8.2
110xxFCMLAARMv8.3
111x0FCADDARMv8.3
111x1UNALLOCATED-

Advanced SIMD two-register miscellaneous

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110size10000opcode10RnRd
Decode fields Instruction Details Architecture Version
Usizeopcode
1000xUNALLOCATED-
10101UNALLOCATED-
0x011xxUNALLOCATED-
1x10110UNALLOCATED-
1x10111UNALLOCATED-
1x11110UNALLOCATED-
000000REV64-
000001REV16 (vector)-
000010SADDLP-
000011SUQADD-
000100CLS (vector)-
000101CNT-
000110SADALP-
000111SQABS-
001000CMGT (zero)-
001001CMEQ (zero)-
001010CMLT (zero)-
001011ABS-
010010XTN, XTN2-
010011UNALLOCATED-
010100SQXTN, SQXTN2-
00x10110FCVTN, FCVTN2-
00x10111FCVTL, FCVTL2-
00x11000FRINTN (vector)-
00x11001FRINTM (vector)-
00x11010FCVTNS (vector)-
00x11011FCVTMS (vector)-
00x11100FCVTAS (vector)-
00x11101SCVTF (vector, integer)-
00x11110FRINT32Z (vector)ARMv8.5
00x11111FRINT64Z (vector)ARMv8.5
01x01100FCMGT (zero)-
01x01101FCMEQ (zero)-
01x01110FCMLT (zero)-
01x01111FABS (vector)-
01x11000FRINTP (vector)-
01x11001FRINTZ (vector)-
01x11010FCVTPS (vector)-
01x11011FCVTZS (vector, integer)-
01x11100URECPE-
01x11101FRECPE-
01x11111UNALLOCATED-
100000REV32 (vector)-
100001UNALLOCATED-
100010UADDLP-
100011USQADD-
100100CLZ (vector)-
100110UADALP-
100111SQNEG-
101000CMGE (zero)-
101001CMLE (zero)-
101010UNALLOCATED-
101011NEG (vector)-
110010SQXTUN, SQXTUN2-
110011SHLL, SHLL2-
110100UQXTN, UQXTN2-
10x10110FCVTXN, FCVTXN2-
10x10111UNALLOCATED-
10x11000FRINTA (vector)-
10x11001FRINTX (vector)-
10x11010FCVTNU (vector)-
10x11011FCVTMU (vector)-
10x11100FCVTAU (vector)-
10x11101UCVTF (vector, integer)-
10x11110FRINT32X (vector)ARMv8.5
10x11111FRINT64X (vector)ARMv8.5
10000101NOT-
10100101RBIT (vector)-
11x00101UNALLOCATED-
11x01100FCMGE (zero)-
11x01101FCMLE (zero)-
11x01110UNALLOCATED-
11x01111FNEG (vector)-
11x11000UNALLOCATED-
11x11001FRINTI (vector)-
11x11010FCVTPU (vector)-
11x11011FCVTZU (vector, integer)-
11x11100URSQRTE-
11x11101FRSQRTE-
11x11111FSQRT (vector)-

Advanced SIMD across lanes

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110size11000opcode10RnRd
Decode fields Instruction Details Architecture Version
Usizeopcode
0000xUNALLOCATED-
00010UNALLOCATED-
001xxUNALLOCATED-
0100xUNALLOCATED-
01011UNALLOCATED-
01101UNALLOCATED-
01110UNALLOCATED-
10xxxUNALLOCATED-
1100xUNALLOCATED-
111xxUNALLOCATED-
000011SADDLV-
001010SMAXV-
011010SMINV-
011011ADDV-
00001100FMAXNMVhalf-precisionARMv8.2
00001111FMAXVhalf-precisionARMv8.2
00101100UNALLOCATED-
00101111UNALLOCATED-
01001100FMINNMVhalf-precisionARMv8.2
01001111FMINVhalf-precisionARMv8.2
01101100UNALLOCATED-
01101111UNALLOCATED-
100011UADDLV-
101010UMAXV-
111010UMINV-
111011UNALLOCATED-
10x01100FMAXNMVsingle-precision and double-precision-
10x01111FMAXVsingle-precision and double-precision-
11x01100FMINNMVsingle-precision and double-precision-
11x01111FMINVsingle-precision and double-precision-

Advanced SIMD three different

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110size1Rmopcode00RnRd
Decode fields Instruction Details
Uopcode
1111UNALLOCATED
00000SADDL, SADDL2
00001SADDW, SADDW2
00010SSUBL, SSUBL2
00011SSUBW, SSUBW2
00100ADDHN, ADDHN2
00101SABAL, SABAL2
00110SUBHN, SUBHN2
00111SABDL, SABDL2
01000SMLAL, SMLAL2 (vector)
01001SQDMLAL, SQDMLAL2 (vector)
01010SMLSL, SMLSL2 (vector)
01011SQDMLSL, SQDMLSL2 (vector)
01100SMULL, SMULL2 (vector)
01101SQDMULL, SQDMULL2 (vector)
01110PMULL, PMULL2
10000UADDL, UADDL2
10001UADDW, UADDW2
10010USUBL, USUBL2
10011USUBW, USUBW2
10100RADDHN, RADDHN2
10101UABAL, UABAL2
10110RSUBHN, RSUBHN2
10111UABDL, UABDL2
11000UMLAL, UMLAL2 (vector)
11001UNALLOCATED
11010UMLSL, UMLSL2 (vector)
11011UNALLOCATED
11100UMULL, UMULL2 (vector)
11101UNALLOCATED
11110UNALLOCATED

Advanced SIMD three same

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110size1Rmopcode1RnRd
Decode fields Instruction Details Architecture Version
Usizeopcode
000000SHADD-
000001SQADD-
000010SRHADD-
000100SHSUB-
000101SQSUB-
000110CMGT (register)-
000111CMGE (register)-
001000SSHL-
001001SQSHL (register)-
001010SRSHL-
001011SQRSHL-
001100SMAX-
001101SMIN-
001110SABD-
001111SABA-
010000ADD (vector)-
010001CMTST-
010010MLA (vector)-
010011MUL (vector)-
010100SMAXP-
010101SMINP-
010110SQDMULH (vector)-
010111ADDP (vector)-
00x11000FMAXNM (vector)-
00x11001FMLA (vector)-
00x11010FADD (vector)-
00x11011FMULX-
00x11100FCMEQ (register)-
00x11110FMAX (vector)-
00x11111FRECPS-
00000011AND (vector)-
00011101FMLAL, FMLAL2 (vector)FMLALARMv8.2
00100011BIC (vector, register)-
00111101UNALLOCATED-
01x11000FMINNM (vector)-
01x11001FMLS (vector)-
01x11010FSUB (vector)-
01x11011UNALLOCATED-
01x11100UNALLOCATED-
01x11110FMIN (vector)-
01x11111FRSQRTS-
01000011ORR (vector, register)-
01011101FMLSL, FMLSL2 (vector)FMLSLARMv8.2
01100011ORN (vector)-
01111101UNALLOCATED-
100000UHADD-
100001UQADD-
100010URHADD-
100100UHSUB-
100101UQSUB-
100110CMHI (register)-
100111CMHS (register)-
101000USHL-
101001UQSHL (register)-
101010URSHL-
101011UQRSHL-
101100UMAX-
101101UMIN-
101110UABD-
101111UABA-
110000SUB (vector)-
110001CMEQ (register)-
110010MLS (vector)-
110011PMUL-
110100UMAXP-
110101UMINP-
110110SQRDMULH (vector)-
110111UNALLOCATED-
10x11000FMAXNMP (vector)-
10x11010FADDP (vector)-
10x11011FMUL (vector)-
10x11100FCMGE (register)-
10x11101FACGE-
10x11110FMAXP (vector)-
10x11111FDIV (vector)-
10000011EOR (vector)-
10011001FMLAL, FMLAL2 (vector)FMLAL2ARMv8.2
10100011BSL-
10111001UNALLOCATED-
11x11000FMINNMP (vector)-
11x11010FABD-
11x11011UNALLOCATED-
11x11100FCMGT (register)-
11x11101FACGT-
11x11110FMINP (vector)-
11x11111UNALLOCATED-
11000011BIT-
11011001FMLSL, FMLSL2 (vector)FMLSL2ARMv8.2
11100011BIF-
11111001UNALLOCATED-

Advanced SIMD modified immediate

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0Qop0111100000abccmodeo21defghRd
Decode fields Instruction Details Architecture Version
Qopcmodeo2
00xxx1UNALLOCATED-
00xx00MOVI32-bit shifted immediate-
00xx10ORR (vector, immediate)32-bit-
010xx1UNALLOCATED-
010x00MOVI16-bit shifted immediate-
010x10ORR (vector, immediate)16-bit-
0110x0MOVI32-bit shifting ones-
0110x1UNALLOCATED-
011100MOVI8-bit-
011101UNALLOCATED-
011110FMOV (vector, immediate)single-precision-
011111FMOV (vector, immediate)half-precisionARMv8.2
11UNALLOCATED-
10xx00MVNI32-bit shifted immediate-
10xx10BIC (vector, immediate)32-bit-
110x00MVNI16-bit shifted immediate-
110x10BIC (vector, immediate)16-bit-
1110x0MVNI32-bit shifting ones-
0111100MOVI64-bit scalar-
0111110UNALLOCATED-
1111100MOVI64-bit vector-
1111110FMOV (vector, immediate)double-precision-

Advanced SIMD shift by immediate

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU011110!= 0000immbopcode1RnRd
immh

The following constraints also apply to this encoding: immh != 0000 && immh != 0000

Decode fields Instruction Details
Uopcode
00001UNALLOCATED
00011UNALLOCATED
00101UNALLOCATED
00111UNALLOCATED
01001UNALLOCATED
01011UNALLOCATED
01101UNALLOCATED
01111UNALLOCATED
10101UNALLOCATED
1011xUNALLOCATED
110xxUNALLOCATED
11101UNALLOCATED
11110UNALLOCATED
000000SSHR
000010SSRA
000100SRSHR
000110SRSRA
001000UNALLOCATED
001010SHL
001100UNALLOCATED
001110SQSHL (immediate)
010000SHRN, SHRN2
010001RSHRN, RSHRN2
010010SQSHRN, SQSHRN2
010011SQRSHRN, SQRSHRN2
010100SSHLL, SSHLL2
011100SCVTF (vector, fixed-point)
011111FCVTZS (vector, fixed-point)
100000USHR
100010USRA
100100URSHR
100110URSRA
101000SRI
101010SLI
101100SQSHLU
101110UQSHL (immediate)
110000SQSHRUN, SQSHRUN2
110001SQRSHRUN, SQRSHRUN2
110010UQSHRN, UQSHRN2
110011UQRSHRN, UQRSHRN2
110100USHLL, USHLL2
111100UCVTF (vector, fixed-point)
111111FCVTZU (vector, fixed-point)

Advanced SIMD vector x indexed element

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01111sizeLMRmopcodeH0RnRd
Decode fields Instruction Details Architecture Version
Usizeopcode
011001UNALLOCATED-
00010SMLAL, SMLAL2 (by element)-
00011SQDMLAL, SQDMLAL2 (by element)-
00110SMLSL, SMLSL2 (by element)-
00111SQDMLSL, SQDMLSL2 (by element)-
01000MUL (by element)-
01010SMULL, SMULL2 (by element)-
01011SQDMULL, SQDMULL2 (by element)-
01100SQDMULH (by element)-
01101SQRDMULH (by element)-
01110SDOT (by element)ARMv8.2
01111UNALLOCATED-
00x0000UNALLOCATED-
00x0100UNALLOCATED-
0000001FMLA (by element)half-precisionARMv8.2
0000101FMLS (by element)half-precisionARMv8.2
0001001FMUL (by element)half-precisionARMv8.2
0010001UNALLOCATED-
0010101UNALLOCATED-
01x0001FMLA (by element)single-precision and double-precision-
01x0101FMLS (by element)single-precision and double-precision-
01x1001FMUL (by element)single-precision and double-precision-
0100000FMLAL, FMLAL2 (by element)FMLALARMv8.2
0100100FMLSL, FMLSL2 (by element)FMLSLARMv8.2
0110000UNALLOCATED-
0110100UNALLOCATED-
10000MLA (by element)-
10010UMLAL, UMLAL2 (by element)-
10100MLS (by element)-
10110UMLSL, UMLSL2 (by element)-
11010UMULL, UMULL2 (by element)-
11011UNALLOCATED-
11101SQRDMLAH (by element)ARMv8.1
11110UDOT (by element)ARMv8.2
11111SQRDMLSH (by element)ARMv8.1
10x1000UNALLOCATED-
10x1100UNALLOCATED-
1000001UNALLOCATED-
1000011UNALLOCATED-
1000101UNALLOCATED-
1000111UNALLOCATED-
1001001FMULX (by element)half-precisionARMv8.2
1010xx1FCMLA (by element)ARMv8.3
11x1001FMULX (by element)single-precision and double-precision-
1100xx1FCMLA (by element)ARMv8.3
1101000FMLAL, FMLAL2 (by element)FMLAL2ARMv8.2
1101100FMLSL, FMLSL2 (by element)FMLSL2ARMv8.2
1110001UNALLOCATED-
1110011UNALLOCATED-
1110101UNALLOCATED-
1110111UNALLOCATED-
1111000UNALLOCATED-
1111100UNALLOCATED-

Cryptographic three-register, imm2

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
11001110010Rm10imm2opcodeRnRd
Decode fields Instruction Details Architecture Version
opcode
00SM3TT1AARMv8.2
01SM3TT1BARMv8.2
10SM3TT2AARMv8.2
11SM3TT2BARMv8.2

Cryptographic three-register SHA 512

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
11001110011Rm1O00opcodeRnRd
Decode fields Instruction Details Architecture Version
Oopcode
000SHA512HARMv8.2
001SHA512H2ARMv8.2
010SHA512SU1ARMv8.2
011RAX1ARMv8.2
100SM3PARTW1ARMv8.2
101SM3PARTW2ARMv8.2
110SM4EKEYARMv8.2
111UNALLOCATED-

Cryptographic four-register

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
110011100Op0Rm0RaRnRd
Decode fields Instruction Details Architecture Version
Op0
00EOR3ARMv8.2
01BCAXARMv8.2
10SM3SS1ARMv8.2
11UNALLOCATED-

Cryptographic two-register SHA 512

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
11001110110000001000opcodeRnRd
Decode fields Instruction Details Architecture Version
opcode
00SHA512SU0ARMv8.2
01SM4EARMv8.2
1xUNALLOCATED-

Conversion between floating-point and fixed-point

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
sf0S11110type0rmodeopcodescaleRnRd
Decode fields Instruction Details Architecture Version
sfStypermodeopcodescale
1xxUNALLOCATED-
x000xUNALLOCATED-
x101xUNALLOCATED-
0x00xUNALLOCATED-
1x01xUNALLOCATED-
10UNALLOCATED-
1UNALLOCATED-
00xxxxxUNALLOCATED-
000000010SCVTF (scalar, fixed-point)32-bit to single-precision-
000000011UCVTF (scalar, fixed-point)32-bit to single-precision-
000011000FCVTZS (scalar, fixed-point)single-precision to 32-bit-
000011001FCVTZU (scalar, fixed-point)single-precision to 32-bit-
000100010SCVTF (scalar, fixed-point)32-bit to double-precision-
000100011UCVTF (scalar, fixed-point)32-bit to double-precision-
000111000FCVTZS (scalar, fixed-point)double-precision to 32-bit-
000111001FCVTZU (scalar, fixed-point)double-precision to 32-bit-
001100010SCVTF (scalar, fixed-point)32-bit to half-precisionARMv8.2
001100011UCVTF (scalar, fixed-point)32-bit to half-precisionARMv8.2
001111000FCVTZS (scalar, fixed-point)half-precision to 32-bitARMv8.2
001111001FCVTZU (scalar, fixed-point)half-precision to 32-bitARMv8.2
100000010SCVTF (scalar, fixed-point)64-bit to single-precision-
100000011UCVTF (scalar, fixed-point)64-bit to single-precision-
100011000FCVTZS (scalar, fixed-point)single-precision to 64-bit-
100011001FCVTZU (scalar, fixed-point)single-precision to 64-bit-
100100010SCVTF (scalar, fixed-point)64-bit to double-precision-
100100011UCVTF (scalar, fixed-point)64-bit to double-precision-
100111000FCVTZS (scalar, fixed-point)double-precision to 64-bit-
100111001FCVTZU (scalar, fixed-point)double-precision to 64-bit-
101100010SCVTF (scalar, fixed-point)64-bit to half-precisionARMv8.2
101100011UCVTF (scalar, fixed-point)64-bit to half-precisionARMv8.2
101111000FCVTZS (scalar, fixed-point)half-precision to 64-bitARMv8.2
101111001FCVTZU (scalar, fixed-point)half-precision to 64-bitARMv8.2

Conversion between floating-point and integer

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
sf0S11110type1rmodeopcode000000RnRd
Decode fields Instruction Details Architecture Version
sfStypermodeopcode
x101xUNALLOCATED-
x110xUNALLOCATED-
1x01xUNALLOCATED-
1x10xUNALLOCATED-
0100xxUNALLOCATED-
01010xUNALLOCATED-
1UNALLOCATED-
0000x111xUNALLOCATED-
000000000FCVTNS (scalar)single-precision to 32-bit-
000000001FCVTNU (scalar)single-precision to 32-bit-
000000010SCVTF (scalar, integer)32-bit to single-precision-
000000011UCVTF (scalar, integer)32-bit to single-precision-
000000100FCVTAS (scalar)single-precision to 32-bit-
000000101FCVTAU (scalar)single-precision to 32-bit-
000000110FMOV (general)single-precision to 32-bit-
000000111FMOV (general)32-bit to single-precision-
000001000FCVTPS (scalar)single-precision to 32-bit-
000001001FCVTPU (scalar)single-precision to 32-bit-
00001x11xUNALLOCATED-
000010000FCVTMS (scalar)single-precision to 32-bit-
000010001FCVTMU (scalar)single-precision to 32-bit-
000011000FCVTZS (scalar, integer)single-precision to 32-bit-
000011001FCVTZU (scalar, integer)single-precision to 32-bit-
00010x11xUNALLOCATED-
000100000FCVTNS (scalar)double-precision to 32-bit-
000100001FCVTNU (scalar)double-precision to 32-bit-
000100010SCVTF (scalar, integer)32-bit to double-precision-
000100011UCVTF (scalar, integer)32-bit to double-precision-
000100100FCVTAS (scalar)double-precision to 32-bit-
000100101FCVTAU (scalar)double-precision to 32-bit-
000101000FCVTPS (scalar)double-precision to 32-bit-
000101001FCVTPU (scalar)double-precision to 32-bit-
000110000FCVTMS (scalar)double-precision to 32-bit-
000110001FCVTMU (scalar)double-precision to 32-bit-
00011011xUNALLOCATED-
000111000FCVTZS (scalar, integer)double-precision to 32-bit-
000111001FCVTZU (scalar, integer)double-precision to 32-bit-
000111110FJCVTZSARMv8.3
000111111UNALLOCATED-
001011xUNALLOCATED-
001100000FCVTNS (scalar)half-precision to 32-bitARMv8.2
001100001FCVTNU (scalar)half-precision to 32-bitARMv8.2
001100010SCVTF (scalar, integer)32-bit to half-precisionARMv8.2
001100011UCVTF (scalar, integer)32-bit to half-precisionARMv8.2
001100100FCVTAS (scalar)half-precision to 32-bitARMv8.2
001100101FCVTAU (scalar)half-precision to 32-bitARMv8.2
001100110FMOV (general)half-precision to 32-bitARMv8.2
001100111FMOV (general)32-bit to half-precisionARMv8.2
001101000FCVTPS (scalar)half-precision to 32-bitARMv8.2
001101001FCVTPU (scalar)half-precision to 32-bitARMv8.2
001110000FCVTMS (scalar)half-precision to 32-bitARMv8.2
001110001FCVTMU (scalar)half-precision to 32-bitARMv8.2
001111000FCVTZS (scalar, integer)half-precision to 32-bitARMv8.2
001111001FCVTZU (scalar, integer)half-precision to 32-bitARMv8.2
100011xUNALLOCATED-
100000000FCVTNS (scalar)single-precision to 64-bit-
100000001FCVTNU (scalar)single-precision to 64-bit-
100000010SCVTF (scalar, integer)64-bit to single-precision-
100000011UCVTF (scalar, integer)64-bit to single-precision-
100000100FCVTAS (scalar)single-precision to 64-bit-
100000101FCVTAU (scalar)single-precision to 64-bit-
100001000FCVTPS (scalar)single-precision to 64-bit-
100001001FCVTPU (scalar)single-precision to 64-bit-
100010000FCVTMS (scalar)single-precision to 64-bit-
100010001FCVTMU (scalar)single-precision to 64-bit-
100011000FCVTZS (scalar, integer)single-precision to 64-bit-
100011001FCVTZU (scalar, integer)single-precision to 64-bit-
1001x111xUNALLOCATED-
100100000FCVTNS (scalar)double-precision to 64-bit-
100100001FCVTNU (scalar)double-precision to 64-bit-
100100010SCVTF (scalar, integer)64-bit to double-precision-
100100011UCVTF (scalar, integer)64-bit to double-precision-
100100100FCVTAS (scalar)double-precision to 64-bit-
100100101FCVTAU (scalar)double-precision to 64-bit-
100100110FMOV (general)double-precision to 64-bit-
100100111FMOV (general)64-bit to double-precision-
100101000FCVTPS (scalar)double-precision to 64-bit-
100101001FCVTPU (scalar)double-precision to 64-bit-
10011x11xUNALLOCATED-
100110000FCVTMS (scalar)double-precision to 64-bit-
100110001FCVTMU (scalar)double-precision to 64-bit-
100111000FCVTZS (scalar, integer)double-precision to 64-bit-
100111001FCVTZU (scalar, integer)double-precision to 64-bit-
1010x011xUNALLOCATED-
101001110FMOV (general)top half of 128-bit to 64-bit-
101001111FMOV (general)64-bit to top half of 128-bit-
10101x11xUNALLOCATED-
101100000FCVTNS (scalar)half-precision to 64-bitARMv8.2
101100001FCVTNU (scalar)half-precision to 64-bitARMv8.2
101100010SCVTF (scalar, integer)64-bit to half-precisionARMv8.2
101100011UCVTF (scalar, integer)64-bit to half-precisionARMv8.2
101100100FCVTAS (scalar)half-precision to 64-bitARMv8.2
101100101FCVTAU (scalar)half-precision to 64-bitARMv8.2
101100110FMOV (general)half-precision to 64-bitARMv8.2
101100111FMOV (general)64-bit to half-precisionARMv8.2
101101000FCVTPS (scalar)half-precision to 64-bitARMv8.2
101101001FCVTPU (scalar)half-precision to 64-bitARMv8.2
101110000FCVTMS (scalar)half-precision to 64-bitARMv8.2
101110001FCVTMU (scalar)half-precision to 64-bitARMv8.2
101111000FCVTZS (scalar, integer)half-precision to 64-bitARMv8.2
101111001FCVTZU (scalar, integer)half-precision to 64-bitARMv8.2

Floating-point data-processing (1 source)

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110type1opcode10000RnRd
Decode fields Instruction Details Architecture Version
MStypeopcode
1xxxxxUNALLOCATED-
1UNALLOCATED-
0000000000FMOV (register)single-precision-
0000000001FABS (scalar)single-precision-
0000000010FNEG (scalar)single-precision-
0000000011FSQRT (scalar)single-precision-
0000000100UNALLOCATED-
0000000101FCVTsingle-precision to double-precision-
0000000110UNALLOCATED-
0000000111FCVTsingle-precision to half-precision-
0000001000FRINTN (scalar)single-precision-
0000001001FRINTP (scalar)single-precision-
0000001010FRINTM (scalar)single-precision-
0000001011FRINTZ (scalar)single-precision-
0000001100FRINTA (scalar)single-precision-
0000001101UNALLOCATED-
0000001110FRINTX (scalar)single-precision-
0000001111FRINTI (scalar)single-precision-
0000010000FRINT32Z (scalar)single-precisionARMv8.5
0000010001FRINT32X (scalar)single-precisionARMv8.5
0000010010FRINT64Z (scalar)single-precisionARMv8.5
0000010011FRINT64X (scalar)single-precisionARMv8.5
00000101xxUNALLOCATED-
0000011xxxUNALLOCATED-
0001000000FMOV (register)double-precision-
0001000001FABS (scalar)double-precision-
0001000010FNEG (scalar)double-precision-
0001000011FSQRT (scalar)double-precision-
0001000100FCVTdouble-precision to single-precision-
0001000101UNALLOCATED-
0001000110UNALLOCATED-
0001000111FCVTdouble-precision to half-precision-
0001001000FRINTN (scalar)double-precision-
0001001001FRINTP (scalar)double-precision-
0001001010FRINTM (scalar)double-precision-
0001001011FRINTZ (scalar)double-precision-
0001001100FRINTA (scalar)double-precision-
0001001101UNALLOCATED-
0001001110FRINTX (scalar)double-precision-
0001001111FRINTI (scalar)double-precision-
0001010000FRINT32Z (scalar)double-precisionARMv8.5
0001010001FRINT32X (scalar)double-precisionARMv8.5
0001010010FRINT64Z (scalar)double-precisionARMv8.5
0001010011FRINT64X (scalar)double-precisionARMv8.5
00010101xxUNALLOCATED-
0001011xxxUNALLOCATED-
00100xxxxxUNALLOCATED-
0011000000FMOV (register)half-precisionARMv8.2
0011000001FABS (scalar)half-precisionARMv8.2
0011000010FNEG (scalar)half-precisionARMv8.2
0011000011FSQRT (scalar)half-precisionARMv8.2
0011000100FCVThalf-precision to single-precision-
0011000101FCVThalf-precision to double-precision-
001100011xUNALLOCATED-
0011001000FRINTN (scalar)half-precisionARMv8.2
0011001001FRINTP (scalar)half-precisionARMv8.2
0011001010FRINTM (scalar)half-precisionARMv8.2
0011001011FRINTZ (scalar)half-precisionARMv8.2
0011001100FRINTA (scalar)half-precisionARMv8.2
0011001101UNALLOCATED-
0011001110FRINTX (scalar)half-precisionARMv8.2
0011001111FRINTI (scalar)half-precisionARMv8.2
001101xxxxUNALLOCATED-
1UNALLOCATED-

Floating-point compare

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110type1Rmop1000Rnopcode2
Decode fields Instruction Details Architecture Version
MStypeopopcode2
xxxx1UNALLOCATED-
xxx1xUNALLOCATED-
xx1xxUNALLOCATED-
x1UNALLOCATED-
1xUNALLOCATED-
10UNALLOCATED-
1UNALLOCATED-
00000000000FCMP-
00000001000FCMP-
00000010000FCMPE-
00000011000FCMPE-
00010000000FCMP-
00010001000FCMP-
00010010000FCMPE-
00010011000FCMPE-
00110000000FCMPARMv8.2
00110001000FCMPARMv8.2
00110010000FCMPEARMv8.2
00110011000FCMPEARMv8.2
1UNALLOCATED-

Floating-point immediate

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110type1imm8100imm5Rd
Decode fields Instruction Details Architecture Version
MStypeimm5
xxxx1UNALLOCATED-
xxx1xUNALLOCATED-
xx1xxUNALLOCATED-
x1xxxUNALLOCATED-
1xxxxUNALLOCATED-
10UNALLOCATED-
1UNALLOCATED-
000000000FMOV (scalar, immediate)single-precision-
000100000FMOV (scalar, immediate)double-precision-
001100000FMOV (scalar, immediate)half-precisionARMv8.2
1UNALLOCATED-

Floating-point conditional compare

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110type1Rmcond01Rnopnzcv
Decode fields Instruction Details Architecture Version
MStypeop
10UNALLOCATED-
1UNALLOCATED-
00000FCCMPsingle-precision-
00001FCCMPEsingle-precision-
00010FCCMPdouble-precision-
00011FCCMPEdouble-precision-
00110FCCMPhalf-precisionARMv8.2
00111FCCMPEhalf-precisionARMv8.2
1UNALLOCATED-

Floating-point data-processing (2 source)

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110type1Rmopcode10RnRd
Decode fields Instruction Details Architecture Version
MStypeopcode
1xx1UNALLOCATED-
1x1xUNALLOCATED-
11xxUNALLOCATED-
10UNALLOCATED-
1UNALLOCATED-
00000000FMUL (scalar)single-precision-
00000001FDIV (scalar)single-precision-
00000010FADD (scalar)single-precision-
00000011FSUB (scalar)single-precision-
00000100FMAX (scalar)single-precision-
00000101FMIN (scalar)single-precision-
00000110FMAXNM (scalar)single-precision-
00000111FMINNM (scalar)single-precision-
00001000FNMUL (scalar)single-precision-
00010000FMUL (scalar)double-precision-
00010001FDIV (scalar)double-precision-
00010010FADD (scalar)double-precision-
00010011FSUB (scalar)double-precision-
00010100FMAX (scalar)double-precision-
00010101FMIN (scalar)double-precision-
00010110FMAXNM (scalar)double-precision-
00010111FMINNM (scalar)double-precision-
00011000FNMUL (scalar)double-precision-
00110000FMUL (scalar)half-precisionARMv8.2
00110001FDIV (scalar)half-precisionARMv8.2
00110010FADD (scalar)half-precisionARMv8.2
00110011FSUB (scalar)half-precisionARMv8.2
00110100FMAX (scalar)half-precisionARMv8.2
00110101FMIN (scalar)half-precisionARMv8.2
00110110FMAXNM (scalar)half-precisionARMv8.2
00110111FMINNM (scalar)half-precisionARMv8.2
00111000FNMUL (scalar)half-precisionARMv8.2
1UNALLOCATED-

Floating-point conditional select

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110type1Rmcond11RnRd
Decode fields Instruction Details Architecture Version
MStype
10UNALLOCATED-
1UNALLOCATED-
0000FCSELsingle-precision-
0001FCSELdouble-precision-
0011FCSELhalf-precisionARMv8.2
1UNALLOCATED-

Floating-point data-processing (3 source)

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11111typeo1Rmo0RaRnRd
Decode fields Instruction Details Architecture Version
MStypeo1o0
10UNALLOCATED-
1UNALLOCATED-
000000FMADDsingle-precision-
000001FMSUBsingle-precision-
000010FNMADDsingle-precision-
000011FNMSUBsingle-precision-
000100FMADDdouble-precision-
000101FMSUBdouble-precision-
000110FNMADDdouble-precision-
000111FNMSUBdouble-precision-
001100FMADDhalf-precisionARMv8.2
001101FMSUBhalf-precisionARMv8.2
001110FNMADDhalf-precisionARMv8.2
001111FNMSUBhalf-precisionARMv8.2
1UNALLOCATED-

Internal version only: isa v30.25, AdvSIMD v27.01, pseudocode v85-xml-00bet8_rc3 ; Build timestamp: 2018-09-13T13:2504

Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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