(old) htmldiff from-(new)

MSR (immediate)

Move immediate value to Special Register moves an immediate value to selected bits of the PSTATE. For more information, see Process state, PSTATE.

The bits that can be written byare thisD, instructionA, areI, F, and SP. This set of bits is expanded in extensions to the architecture as follows:

313029282726252423222120191817161514131211109876543210
1101010100000op10100CRmop211111

System

MSR <pstatefield>, #<imm>

if op1 == '000' && op2 == '000' then SEE "CFINV"; if op1 == '000' && op2 == '001' then SEE "XAFlag"; if op1 == '000' && op2 == '010' then SEE "AXFlag"; AArch64.CheckSystemAccess('00', op1, '0100', CRm, op2, '11111', '0'); bits(4) operand = CRm; PSTATEField field; case op1:op2 of when '000 000' SEE "CFINV"; when '000 011' if !HaveUAOExt() then UNDEFINED; field =() then UnallocatedEncoding(); field = PSTATEField_UAO; when '000 100' if !HavePANExt() then UNDEFINED; field =() then UnallocatedEncoding(); field = PSTATEField_PAN; when '000 101' field = PSTATEField_SP; when '011 010' if !HaveDITExt() then UNDEFINED; field =() then UnallocatedEncoding(); field = PSTATEField_DIT; when '011 110' field = PSTATEField_DAIFSet; when '011 111' field = PSTATEField_DAIFClr; when '011 001' if ! otherwiseHaveSSBSExtUnallocatedEncoding() then UNDEFINED; field = PSTATEField_SSBS; otherwise UNDEFINED; (); // Check that an AArch64 MSR/MRS access to the DAIF flags is permitted if op1 == '011' && PSTATE.EL == EL0 && (IsInHost() || SCTLR_EL1.UMA == '0') then AArch64.SystemRegisterTrap(EL1, '00', op2, op1, '0100', '11111', CRm, '0');

Assembler Symbols

<pstatefield> Is a PSTATE field name, encoded in op1:op2:
op1op2<pstatefield>Architectural Feature
00000x011UAOSEE PSTATE -ARMv8.2-UAO
000010100PANSEE PSTATE -ARMv8.1-PAN
000011101UAOSPSel ARMv8.2-UAO-
000011100010PANDIT ARMv8.1-PANARMv8.4-DIT
000011101110SPSelDAIFSet -
00001111x111RESERVEDDAIFClr -
001xxxRESERVED -
010xxxRESERVED -
011000RESERVED -
011001SSBS ARMv8.0-SpecRest
011010DIT ARMv8.4-DIT
011011RESERVED -
01110xRESERVED -
011110DAIFSet -
011111DAIFClr -
1xxxxxRESERVED -
<imm>

Is a 4-bit unsigned immediate, in the range 0 to 15, encoded in the "CRm" field.

Operation

case field of when PSTATEField_SSBS PSTATE.SSBS = operand<0>; when PSTATEField_SP PSTATE.SP = operand<0>; when PSTATEField_DAIFSet PSTATE.D = PSTATE.D OR operand<3>; PSTATE.A = PSTATE.A OR operand<2>; PSTATE.I = PSTATE.I OR operand<1>; PSTATE.F = PSTATE.F OR operand<0>; when PSTATEField_DAIFClr PSTATE.D = PSTATE.D AND NOT(operand<3>); PSTATE.A = PSTATE.A AND NOT(operand<2>); PSTATE.I = PSTATE.I AND NOT(operand<1>); PSTATE.F = PSTATE.F AND NOT(operand<0>); when PSTATEField_PAN PSTATE.PAN = operand<0>; when PSTATEField_UAO PSTATE.UAO = operand<0>; when PSTATEField_DIT PSTATE.DIT = operand<0>;


Internal version only: isa v30.25v29.05, AdvSIMD v27.01v26.0, pseudocode v85-xml-00bet8_rc3v35.3 ; Build timestamp: 2018-09-13T132018-06-16T09:0445

Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.

(old) htmldiff from-(new)