Swap halfword in memory atomically loads a 16-bit halfword from a memory location, and stores the value held in a register back to the same memory location. The value initially loaded from memory is returned in the destination register.
For more information about memory ordering semantics see Load-Acquire, Store-Release.
For information about memory accesses see Load/Store addressing modes.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | A | R | 1 | Rs | 1 | 0 | 0 | 0 | 0 | 0 | Rn | Rt | ||||||||||||
size |
if !HaveAtomicExt() then UNDEFINED; integer t = UInt(Rt); integer n = UInt(Rn); integer s = UInt(Rs); AccType ldacctype = if A == '1' && Rt != '11111' then AccType_ORDEREDATOMICRW else AccType_ATOMICRW; AccType stacctype = if R == '1' then AccType_ORDEREDATOMICRW else AccType_ATOMICRW;
<Ws> |
Is the 32-bit name of the general-purpose register to be stored, encoded in the "Rs" field. |
<Wt> |
Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field. |
<Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
bits(64) address; bits(16) data; if HaveMTEExt() then SetNotTagCheckedInstruction(n == 31); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n]; // All observers in the shareability domain observe the // following load and store atomically. data = Mem[address, 2, ldacctype]; Mem[address, 2, stacctype] = X[s]; X[t] = ZeroExtend(data, 32);
Internal version only: isa v30.25, AdvSIMD v27.01, pseudocode v85-xml-00bet8_rc3 ; Build timestamp: 2018-09-13T13:25
Copyright © 2010-2018 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.