ESB

Error Synchronization Barrier is a synchronization barrier instruction to barrier between errors. This instruction can be used at all Exception levels and in Debug state. This instruction might update DISR and VDISR.

In Debug state, this instruction behaves as if SError interrupts are masked at all Exception levels. See Error Synchronization Barrier in the ARM(R) Reliability, Availability, and Serviceability (RAS) Specification, ARMv8, for ARMv8-A architecture profile.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1
(ARMv8.2)

313029282726252423222120191817161514131211109876543210
!= 1111001100100000(1)(1)(1)(1)(0)(0)(0)(0)00010000
cond

A1

ESB{<c>}{<q>}

if cond != '1110' then UNPREDICTABLE; // ESB must be encoded with AL condition

CONSTRAINED UNPREDICTABLE behavior

If cond != '1110', then one of the following behaviors must occur:

T1
(ARMv8.2)

15141312111098765432101514131211109876543210
111100111010(1)(1)(1)(1)10(0)0(0)00000010000

T1

ESB{<c>}.W

if InITBlock() then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If InITBlock(), then one of the following behaviors must occur:

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

Operation

if ConditionPassed() then EncodingSpecificOperations(); ErrorSynchronizationBarrier(MBReqDomain_FullSystem, MBReqTypes_All); AArch32.ESBOperation(); if HaveEL(EL2) && !IsSecure() && PSTATE.EL IN {EL0,EL1} then AArch32.vESBOperation(); TakeUnmaskedSErrorInterrupts();


Internal version only: isa v00_66, pseudocode v31.3

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