AArch32 ISA XML for ARMv8.3
(00bet6)
19th December 2017
1. Introduction
This is the 00bet6
release of the AArch32 ISA XML for ARMv8.3.
The Proprietary Notice
gives details of the terms and conditions under which this package
is provided.
If you have comments on the content of this package, please send
them by e-mail to
support-aarchv8@arm.com.
Give:
- The title, "AArch32 ISA XML for ARMv8.3".
- The version, "00bet6".
- A concise explanation of your comments.
2. Contents
3. Release Notes
Change history
The following changes are made to the instruction definitions:
-
The VFMAL and VFMSL instructions are added as an OPTIONAL
extension to ARMv8.2.
-
The VCADD and VCMLA instruction descriptions are corrected to
improve their accuracy.
-
The VCADD and VCMLA instructions are corrected to check the
HaveFCADDExt() function.
-
The placement of the InITBlock() check in new T32 instructions is
corrected.
-
The VSDOT and VUDOT instructions are corrected to check the
HaveDOTPExt() function.
The following changes are made to the Shared Pseudocode:
-
The AddPACGA() function is corrected so that the setting of
TrapEL3 when PSTATE.EL is EL0 checks HaveEL(EL3).
-
The AArch32.SetExclusiveMonitors() and
AArch64.SetExclusiveMonitors() functions were incorrectly setting
the aligned variable to reflect an unaligned address. This is
corrected.
-
The Fault enumeration is extended to include the fault
Fault_HWUpdateAccessFlag, which is introduced by the Hardware
management of the Access Flag feature in ARMv8.1.
-
The IsEL1TransRegimeRegs() function is removed and all uses of
this function are replaced with the use of the
S1TranslationRegime() function.
-
The S2ConvertAttrsHints() function is corrected to include the
s2fs1walk parameter, which can be used when checking for
Non-cacheable accesses.
Known issues
-
The table for the "Advanced SIMD two registers and shift amount"
class within the A32 and T32 encoding index page includes a column
"imm3H:L" with the value "!= 0000" for all rows. This condition
applies to all instructions in this table, and so is removed.
-
The encoding diagram for the "Advanced SIMD and floating-point
32-bit move" class within the A32 and T32 encoding index page
shows bits[3:0] as "1111". This is incorrect, as the next level of
decode shows these bits as "(0)(0)(0)(0)".