ISA_v83A_AArch32_xml_00bet5 (old) | htmldiff from-ISA_v83A_AArch32_xml_00bet5 | (new) ISA_v83A_AArch32_xml_00bet6 |
Vector Complex Multiply Accumulate (by element).
None, one, or both of the two vector elements that are read from each of the numbers in the second source SIMD&FP register can be negated based on the rotation value:
This instruction operatesmultiplies onthe complex numbers thatin arethe representedfirst source vector register by the specified complex number in SIMD&FPthe registerssecond assource pairsvector of elementsregister, withand adds the moreresults significantto elementthe holdingcorresponding complex numbers in the imaginarydestination partvector register. The number of complex numbers that can be stored in the numbersource and the lessdestination significantvector elementregisters holdingis calculated as the realvector partregister ofsize divided by the length of each complex number. Each elementcomplex holdsnumber is represented in a floating-pointSIMD&FP value.register Itas performsa pair of elements with the followingimaginary computationpart onof complexthe numbersnumber frombeing placed in the firstmore sourcesignificant registerelement, and the destinationreal registerpart withof the specifiednumber complexbeing numberplaced fromin the secondless significant element. Both real and imaginary parts of the source register:and the resulting complex number are represented as floating-point values.
The multiplicationindexed andelement additionvariant operationsof arethis performedinstruction asis aavailable fusedfor multiply-addhalf-precision and single-precision number values. For this variant, withoutthe anyindex intermediatevalue rounding.determines the position in the specified element of the second source vector register of the single source value that is multiplied with each of the complex numbers in the first source vector register.
Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Securitysecurity state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | S | D | rot | Vn | Vd | 1 | 0 | 0 | 0 | N | Q | M | 0 | Vm |
if !HaveFCADDExtHaveFJCVTZSExt() then UNDEFINED;
if Q == '1' && (Vd<0> == '1' || Vn<0> == '1') then UNDEFINED;
d = UInt(D:Vd); n = UInt(N:Vn);
m = if S=='1' then UInt(M:Vm) else UInt(Vm);
esize = 16 << UInt(S);
if !HaveFP16Ext() && esize == 16 then UNDEFINED;
elements = 64 DIV esize;
regs = if Q == '0' then 1 else 2;
regs = if Q=='0' then 1 else 2;
index = if S=='1' then 0 else UInt(M);
if InITBlock(M);() then UNPREDICTABLE;
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | S | D | rot | Vn | Vd | 1 | 0 | 0 | 0 | N | Q | M | 0 | Vm |
ifif ! InITBlockHaveFJCVTZSExt() then UNPREDICTABLE;
if !() then UNDEFINED;
if Q == '1' && (Vd<0> == '1' || Vn<0> == '1') then UNDEFINED;
d =HaveFCADDExt() then UNDEFINED;
if Q == '1' && (Vd<0> == '1' || Vn<0> == '1') then UNDEFINED;
d = UInt(D:Vd); n = UInt(N:Vn);
m = if S=='1' then UInt(M:Vm) else UInt(Vm);
esize = 16 << UInt(S);
if !HaveFP16Ext() && esize == 16 then UNDEFINED;
elements = 64 DIV esize;
regs = if Q == '0' then 1 else 2;
regs = if Q=='0' then 1 else 2;
index = if S=='1' then 0 else UInt(M);
if InITBlock(M);() then UNPREDICTABLE;
<q> |
<Qd> | Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2. |
<Qn> | Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2. |
<Dd> | Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
<Dn> | Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field. |
<index> | Is the element index in the range 0 to 1, encoded in the "M" field. |
<rotate> |
Is the rotation to be applied to elements in the second SIMD&FP source register,
encoded in
rot:
|
EncodingSpecificOperations();
CheckAdvSIMDEnabled();
for r = 0 to regs-1
operand1 = operand2 = D[n+r];
operand2 = operand1 = D[m];
operand3 = D[d+r];
for e = 0 to (elements DIV 2)-1
case rot of
when '00'
element1 = Elem[operand2,index*2,esize];
[operand1,index*2,esize];
element2 = Elem[operand1,e*2,esize];
[operand2,e*2,esize];
element3 = Elem[operand2,index*2+1,esize];
[operand1,index*2+1,esize];
element4 = Elem[operand1,e*2,esize];
[operand2,e*2,esize];
when '01'
element1 = FPNeg(Elem[operand2,index*2+1,esize]);
[operand1,index*2+1,esize]);
element2 = Elem[operand1,e*2+1,esize];
[operand2,e*2+1,esize];
element3 = Elem[operand2,index*2,esize];
[operand1,index*2,esize];
element4 = Elem[operand1,e*2+1,esize];
[operand2,e*2+1,esize];
when '10'
element1 = FPNeg(Elem[operand2,index*2,esize]);
[operand1,index*2,esize]);
element2 = Elem[operand1,e*2,esize];
[operand2,e*2,esize];
element3 = FPNeg(Elem[operand2,index*2+1,esize]);
[operand1,index*2+1,esize]);
element4 = Elem[operand1,e*2,esize];
[operand2,e*2,esize];
when '11'
element1 = Elem[operand2,index*2+1,esize];
[operand1,index*2+1,esize];
element2 = Elem[operand1,e*2+1,esize];
[operand2,e*2+1,esize];
element3 = FPNeg(Elem[operand2,index*2,esize]);
[operand1,index*2,esize]);
element4 = Elem[operand1,e*2+1,esize];
[operand2,e*2+1,esize];
result1 = FPMulAdd(Elem[operand3,e*2,esize],element2,element1, StandardFPSCRValue());
result2 = FPMulAdd(Elem[operand3,e*2+1,esize],element4,element3,StandardFPSCRValue());
Elem[D[d+r],e*2,esize] = result1;
Elem[D[d+r],e*2+1,esize] = result2;
Internal version only: isa v00_79v00_76, pseudocode v34.2v33.1
; Build timestamp: 2017-12-19T152017-09-26T15:4210
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.
ISA_v83A_AArch32_xml_00bet5 (old) | htmldiff from-ISA_v83A_AArch32_xml_00bet5 | (new) ISA_v83A_AArch32_xml_00bet6 |