Vector Complex Add.
This instruction adds corresponding complex numbers from the two source vector registers and writes the resulting complex numbers into the destination vector register. The number of complex numbers that can be stored in the source and the destination vector registers is calculated as the vector register size divided by the length of each complex number. Each complex number is represented in a SIMD&FP register as a pair of elements with the imaginary part of the number being placed in the more significant element, and the real part of the number being placed in the less significant element. Both real and imaginary parts of the source and the resulting complex number are represented as floating-point values.
One of the two vector elements that are read from each of the numbers in the second source SIMD&FP register can be optionally negated based on the rotation value:
Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 1 | 0 | rot | 1 | D | 0 | S | Vn | Vd | 1 | 0 | 0 | 0 | N | Q | M | 0 | Vm |
if !HaveFJCVTZSExt() then UNDEFINED; if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED; d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm); esize = 16 << UInt(S); if !HaveFP16Ext() && esize == 16 then UNDEFINED; elements = 64 DIV esize; regs = if Q=='0' then 1 else 2; if CurrentInstrSet() == InstrSet_T32 then if InITBlock() then UNPREDICTABLE;
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 1 | 0 | rot | 1 | D | 0 | S | Vn | Vd | 1 | 0 | 0 | 0 | N | Q | M | 0 | Vm |
if !HaveFJCVTZSExt() then UNDEFINED; if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED; d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm); esize = 16 << UInt(S); if !HaveFP16Ext() && esize == 16 then UNDEFINED; elements = 64 DIV esize; regs = if Q=='0' then 1 else 2; if CurrentInstrSet() == InstrSet_T32 then if InITBlock() then UNPREDICTABLE;
<q> |
<dt> |
Is the data type for the elements of the vectors,
encoded in
S:
|
<Qd> |
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2. |
<Qn> |
Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2. |
<Qm> |
Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2. |
<Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
<Dn> |
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field. |
<Dm> |
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field. |
<rotate> |
Is the rotation to be applied to elements in the second SIMD&FP source register,
encoded in
rot:
|
EncodingSpecificOperations(); CheckAdvSIMDEnabled(); for r = 0 to regs-1 operand2 = D[n+r]; operand1 = D[m+r]; operand3 = D[d+r]; for e = 0 to (elements DIV 2)-1 case rot of when '0' element1 = FPNeg(Elem[operand1,e*2+1,esize]); element3 = Elem[operand1,e*2,esize]; when '1' element1 = Elem[operand1,e*2+1,esize]; element3 = FPNeg(Elem[operand1,e*2,esize]); result1 = FPAdd(Elem[operand2,e*2,esize],element1,StandardFPSCRValue()); result2 = FPAdd(Elem[operand2,e*2+1,esize],element3,StandardFPSCRValue()); Elem[D[d+r],e*2,esize] = result1; Elem[D[d+r],e*2+1,esize] = result2;
Internal version only: isa v00_76, pseudocode v33.1 ; Build timestamp: 2017-09-26T15:10
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