ISA_v83A_AArch32_xml_00bet5 (old) | htmldiff from-ISA_v83A_AArch32_xml_00bet5 | (new) ISA_v83A_AArch32_xml_00bet6 |
Dot Product vector form with unsigned integers. This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of the corresponding 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.
From ARMv8.2, this is an optional instruction.
ID_ISAR6.DP indicates whether this instruction is supported in the T32 and A32 instruction sets.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | D | 1 | 0 | Vn | Vd | 1 | 1 | 0 | 1 | N | Q | M | 1 | Vm | |||||||||
U |
if !if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
boolean signed = U=='0';
integer d =HaveDOTPExtUInt() then UNDEFINED;
if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
boolean signed = U=='0';
integer d =(D:Vd);
integer n = UInt(D:Vd);
integer n =(N:Vn);
integer m = UInt(N:Vn);
integer m =(M:Vm);
integer esize = 32;
integer regs = if Q=='1' then 2 else 1;
if UIntInITBlock(M:Vm);
integer esize = 32;
integer regs = if Q == '1' then 2 else 1;() then UNPREDICTABLE;
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | D | 1 | 0 | Vn | Vd | 1 | 1 | 0 | 1 | N | Q | M | 1 | Vm | |||||||||
U |
ifif Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
boolean signed = U=='0';
integer d = InITBlockUInt() then UNPREDICTABLE;
if !(D:Vd);
integer n =HaveDOTPExt() then UNDEFINED;
if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
boolean signed = U=='0';
integer d = UInt(D:Vd);
integer n =(N:Vn);
integer m = UInt(N:Vn);
integer m =(M:Vm);
integer esize = 32;
integer regs = if Q=='1' then 2 else 1;
if UIntInITBlock(M:Vm);
integer esize = 32;
integer regs = if Q == '1' then 2 else 1;() then UNPREDICTABLE;
<q> |
<Qd> | Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2. |
<Qn> | Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2. |
<Qm> | Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2. |
<Dd> | Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
<Dn> | Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field. |
<Dm> | Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field. |
bits(64) operand1; bits(64) operand2; bits(64) result; CheckAdvSIMDEnabled(); for r = 0 to regs-1 operand1 = D[n+r]; operand2 = D[m+r]; result = D[d+r]; integer element1, element2; for e = 0 to 1 integer res = 0; for i = 0 to 3 if signed then element1 = SInt(Elem[operand1, 4 * e + i, esize DIV 4]); element2 = SInt(Elem[operand2, 4 * e + i, esize DIV 4]); else element1 = UInt(Elem[operand1, 4 * e + i, esize DIV 4]); element2 = UInt(Elem[operand2, 4 * e + i, esize DIV 4]); res = res + element1 * element2; Elem[result, e, esize] = Elem[result, e, esize] + res; D[d+r] = result;
Internal version only: isa v00_79v00_76, pseudocode v34.2v33.1
; Build timestamp: 2017-12-19T152017-09-26T15:4210
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.
ISA_v83A_AArch32_xml_00bet5 (old) | htmldiff from-ISA_v83A_AArch32_xml_00bet5 | (new) ISA_v83A_AArch32_xml_00bet6 |