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Add to SP (immediate) adds an immediate value to the SP value, and writes the result to the destination register.
If the destination register is not the PC, the ADDS variant of the instruction updates the condition flags based on the result.
The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. However, when the destination register is the PC:
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 , T2 , T3 and T4 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | S | 1 | 1 | 0 | 1 | Rd | imm12 | |||||||||||||||||
cond |
d = UInt(Rd); setflags = (S == '1'); imm32 = A32ExpandImm(imm12);
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 0 | 1 | 0 | 1 | Rd | imm8 |
d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm8:'00', 32);
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | imm7 |
d = 13; setflags = FALSE; imm32 = ZeroExtend(imm7:'00', 32);
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 0 | i | 0 | 1 | 0 | 0 | 0 | S | 1 | 1 | 0 | 1 | 0 | imm3 | Rd | imm8 |
if Rd == '1111' && S == '1' then SEE "CMN (immediate)"; d = UInt(Rd); setflags = (S == '1'); imm32 = T32ExpandImm(i:imm3:imm8); if d == 15 && !setflags then UNPREDICTABLE;
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 0 | i | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | imm3 | Rd | imm8 |
ADD{<c>}{<q>} {<Rd>,} SP, #<imm12> // (<imm12> cannot be represented in T1, T2, or T3)
ADDW{<c>}{<q>} {<Rd>,} SP, #<imm12> // (<imm12> can be represented in T1, T2, or T3)
d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(i:imm3:imm8, 32); if d == 15 then UNPREDICTABLE;
For more information about the constrained unpredictable behavior, see Architectural Constraints on UNPREDICTABLE behaviors.
<c> |
<q> |
SP, | Is the stack |
<imm7 |
Is |
| |
|
<Rd | For
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For encoding T1: is the general-purpose destination register, encoded in the "Rd" field. | |
For encoding T3 and T4: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the SP. |
<imm8 | Is an |
<imm12 | Is |
|
<const> | For encoding A1: an immediate value. See Modified immediate constants in A32 instructions for the range of values. |
For encoding T3: an immediate value. See Modified immediate constants in T32 instructions for the range of values. |
if ConditionPassed() then EncodingSpecificOperations(); (result, nzcv) = AddWithCarry(SP, imm32, '0'); if d == 15 then // Can only occur for A32 encoding if setflags then ALUExceptionReturn(result); else ALUWritePC(result); else R[d] = result; if setflags then PSTATE.<N,Z,C,V> = nzcv;
Internal version only: isa v00_88v00_87, pseudocode v85-xml-00bet9_rc1_1v85-xml-00bet8_rc3
; Build timestamp: 2018-12-12T122018-09-13T14:3300
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This document is Non-Confidential.
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