ID_AA64MMFR1_EL1, AArch64 Memory Model Feature Register 1

The ID_AA64MMFR1_EL1 characteristics are:

Purpose

Provides information about the implemented memory model and memory management support in AArch64 state.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.

This register is part of the Identification registers functional group.

Configuration

There are no configuration notes.

Attributes

ID_AA64MMFR1_EL1 is a 64-bit register.

Field descriptions

The ID_AA64MMFR1_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
00000000000000000000000000000000
XNXSpecSEIPANLOHPDSVHVMIDBitsHAFDBS
313029282726252423222120191817161514131211109876543210

Bits [63:32]

Reserved, RES0.

XNX, bits [31:28]
In ARMv8.2:

Indicates support for Execute Never control distinction at stage 2 bit. Defined values are:

XNXMeaning
0000

Distinction between EL0 and EL1 execute permission at stage 2 not supported.

0001

Distinction between EL0 and EL1 execute permission at stage 2 supported.

All other values are reserved.

In ARMv8.0 and ARMv8.1, the only permitted value is 0000.

From ARMv8.2, the only permitted value is 0001. This feature is identified by the name ARMv8.2-TTS2UXN.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

SpecSEI, bits [27:24]

Describes whether the PE can generate SError interrupt exceptions from speculative reads of memory, including speculative instruction fetches. The defined values of this field are:

SpecSEIMeaning
0000

The PE never generates an SError interrupt due to an external abort on a speculative read.

0001

The PE might generate an SError interrupt due to an external abort on a speculative read.

All other values are reserved.

When the RAS Extension is not implemented, this field is RAZ.

PAN, bits [23:20]
In ARMv8.2 and ARMv8.1:

Privileged Access Never. Indicates support for the PAN bit in PSTATE, SPSR_EL1, SPSR_EL2, SPSR_EL3, and DSPSR_EL0. Defined values are:

PANMeaning
0000

PAN not supported.

0001

PAN supported.

0010

PAN supported and AT S1E1RP and AT S1E1WP instructions supported.

All other values are reserved.

In ARMv8.0 the only permitted value is 0000.

In ARMv8.1 the only permitted value is 0001. This feature is identified by the name ARMv8.1-PAN.

From ARMv8.2, the only permitted value is 0010. This feature is identified by the name ARMv8.2-ATS1E1.


In ARMv8.0:

Reserved, RES0.

LO, bits [19:16]
In ARMv8.2 and ARMv8.1:

LORegions. Indicates support for LORegions. Defined values are:

LOMeaning
0000

LORegions not supported.

0001

LORegions supported.

All other values are reserved.

In ARMv8.0 the only permitted value is 0000.

From ARMv8.1, the only permitted value is 0001. This feature is identified by the name ARMv8.1-LOR.


In ARMv8.0:

Reserved, RES0.

HPDS, bits [15:12]
In ARMv8.2 and ARMv8.1:

Hierarchical permission disables bits in translation tables. Defined values are:

HPDSMeaning
0000

Disabling of hierarchical controls not supported.

0001

Disabling of hierarchical controls supported using TCR_EL1.HPD0, TCR_EL1.HPD1, TCR_EL2.HPD, and TCR_EL3.HPD bits.

0010

Disabling of hierarchical controls supported using the TCR_EL1.HPD0, TCR_EL1.HPD1, TCR_EL2.HPD, and TCR_EL3.HPD bits, and hardware allocation of bits[62:59] of the last level page table descriptor for IMPLEMENTATION DEFINED use.

All other values are reserved.

In ARMv8.0 the only permitted value is 0000.

In ARMv8.1 the only permitted value is 0001. This feature is identified by the name ARMv8.1-HPD.

From ARMv8.2, the permitted values are 0001 and 0010. This feature is identified by the name ARMv8.2-TTPBHA.


In ARMv8.0:

Reserved, RES0.

VH, bits [11:8]
In ARMv8.2 and ARMv8.1:

Virtualization Host Extensions. Defined values are:

VHMeaning
0000

Virtualization Host Extensions not supported.

0001

Virtualization Host Extensions supported.

All other values are reserved.

In ARMv8.0 the only permitted value is 0000.

From ARMv8.1, the only permitted value is 0001. This feature is identified by the name ARMv8.1-VHE.


In ARMv8.0:

Reserved, RES0.

VMIDBits, bits [7:4]
In ARMv8.2 and ARMv8.1:

Number of VMID bits. Defined values are:

VMIDBitsMeaning
0000

8 bits

0010

16 bits

All other values are reserved.

In ARMv8.0 the only permitted value is 0000.

From ARMv8.1, the permitted values are 0000 and 0010.


In ARMv8.0:

Reserved, RES0.

HAFDBS, bits [3:0]
In ARMv8.2 and ARMv8.1:

Hardware updates to Access flag and Dirty state in translation tables. Defined values are:

HAFDBSMeaning
0000

No hardware update of the Access flag and dirty state is supported in hardware.

0001

Hardware update of the Access flag is supported in hardware.

0010

Hardware update of both the Access flag and dirty state is supported in hardware.

All other values are reserved.

From ARMv8.1, the permitted values are 0000, 0001, and 0010. This feature is identified by the name ARMv8.1-VHE.


In ARMv8.0:

Reserved, RES0.

Accessing the ID_AA64MMFR1_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
ID_AA64MMFR1_EL11100000000111001

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RO n/a RO
x01 - RORORO
x11 - n/a RORO

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :




18/04/2017 17:00

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