The PMDEVARCH characteristics are:
Identifies the programmers' model architecture of the Performance Monitor component.
This register is part of the Performance Monitors registers functional group.
This register is accessible as follows:
SLK | Default |
---|---|
RO | RO |
PMDEVARCH is in the Debug power domain.
PMDEVARCH is a 32-bit register.
The PMDEVARCH bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ARCHITECT | PRESENT | REVISION | ARCHID |
Defines the architecture of the component. For Performance Monitors, this is ARM Limited.
Bits [31:28] are the JEP106 continuation code, 0x4.
Bits [27:21] are the JEP106 ID code, 0x3B.
When set to 1, indicates that the DEVARCH is present.
This field is 1 in ARMv8.
Defines the architecture revision. For architectures defined by ARM this is the minor revision.
For Performance Monitors, the revision defined by ARMv8 is 0x0.
All other values are reserved.
Defines this part to be an ARMv8 debug component. For architectures defined by ARM this is further subdivided.
For Performance Monitors:
This corresponds to Performance Monitors architecture version PMUv3.
The PMUv3 memory-mapped programmers' model can be used by devices other than ARMv8 processors. Software must determine whether the PMU is attached to an ARMv8 processor by using the PMDEVAFF0 and PMDEVAFF1 registers to discover the affinity of the PMU to any ARMv8 processors.
PMDEVARCH can be accessed through the external debug interface:
Component | Offset |
---|---|
PMU | 0xFBC |
18/04/2017 17:00
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