PMCNTENSET, Performance Monitors Count Enable Set register

The PMCNTENSET characteristics are:

Purpose

Enables the Cycle Count Register, PMCCNTR, and any implemented event counters PMEVCNTR<n>. Reading this register shows which counters are enabled.

PMCNTENSET is used in conjunction with the PMCNTENCLR register.

This register is part of the Performance Monitors registers functional group.

Configuration

There is one instance of this register that is used in both Secure and Non-secure states.

AArch32 System register PMCNTENSET is architecturally mapped to AArch64 System register PMCNTENSET_EL0.

AArch32 System register PMCNTENSET is architecturally mapped to External register PMCNTENSET_EL0.

This register is in the Warm reset domain. On a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.

Attributes

PMCNTENSET is a 32-bit register.

Field descriptions

The PMCNTENSET bit assignments are:

313029282726252423222120191817161514131211109876543210
CP<n>, bit [n]

C, bit [31]

PMCCNTR enable bit. Enables the cycle counter register. Possible values are:

CMeaning
0

When read, means the cycle counter is disabled. When written, has no effect.

1

When read, means the cycle counter is enabled. When written, enables the cycle counter.

P<n>, bit [n], for n = 0 to 30

Event counter enable bit for PMEVCNTR<n>.

Bits [30:N] are RAZ/WI. When EL2 is implemented, in Non-secure EL1 and EL0, N is the value in MDCR_EL2.HPMN, if EL2 is using AArch64 or in HDCR.HPMN if EL2 is using AArch32. Otherwise, N is the value in PMCR.N.

Possible values of each bit are:

P<n>Meaning
0

When read, means that PMEVCNTR<n> is disabled. When written, has no effect.

1

When read, means that PMEVCNTR<n> event counter is enabled. When written, enables PMEVCNTR<n>.

Accessing the PMCNTENSET

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 0, <Rt>, c9, c12, 1000001100111111100

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0RWRW n/a RW
x01RWRWRWRW
x11RW n/a RWRW

This table applies to all instructions that can access this register.

If EL2 is implemented, in Non-secure EL1 and EL0 modes, the value of HDCR.HPMN can change the behavior of accesses to PMCNTENSET. See the description of the P<n> bit.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :

When EL3 is implemented and is using AArch64 :




18/04/2017 17:00

Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Confidential.