The TLBI ASIDE1IS characteristics are:
Invalidate cached copies of translation table entries from TLBs that meet all the following requirements:
The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this instructions.
This System instruction is part of the TLB maintenance instructions functional group.
There are no configuration notes.
TLBI ASIDE1IS is a 64-bit System instruction.
The TLBI ASIDE1IS input value bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
ASID | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||||||||||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ASID value to match. Any appropriate TLB entries that match the ASID values will be affected by this operation.
If the implementation supports 16 bits of ASID, but only 8 bits are being used in the context being invalidated, the upper bits are RES0 and must be written to 0 by software performing the TLB maintenance.
Reserved, RES0.
This instruction is executed using TLBI with the following syntax:
TLBI <tlbi_op>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<tlbi_op> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
ASIDE1IS | 01 | 000 | 1000 | 0011 | 010 |
The instruction is executable as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | WO | n/a | WO |
0 | 0 | 1 | - | WO | WO | WO |
0 | 1 | 1 | - | n/a | WO | WO |
1 | 0 | 1 | - | WO | WO | WO |
1 | 1 | 1 | - | n/a | WO | WO |
This table applies to all syntax that can be used to execute this instruction.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when executing this System instruction.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TTLB==1, Non-secure execution of this instruction at EL1 is trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TTLB==1, Non-secure execution of this instruction at EL1 is trapped to EL2.
18/04/2017 17:00
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