ICC_BPR0_EL1, Interrupt Controller Binary Point Register 0

The ICC_BPR0_EL1 characteristics are:

Purpose

Defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field. The group priority field determines Group 0 interrupt preemption.

This register is part of:

Configuration

AArch64 System register ICC_BPR0_EL1 is architecturally mapped to AArch32 System register ICC_BPR0.

Virtual accesses to this register update ICH_VMCR_EL2.VBPR0.

Attributes

ICC_BPR0_EL1 is a 32-bit register.

Field descriptions

The ICC_BPR0_EL1 bit assignments are:

313029282726252423222120191817161514131211109876543210
00000000000000000000000000000BinaryPoint

Bits [31:3]

Reserved, RES0.

BinaryPoint, bits [2:0]

The value of this field controls how the 8-bit interrupt priority field is split into a group priority field, that determines interrupt preemption, and a subpriority field. This is done as follows:

Binary point value Group priority field Subpriority field Field with binary point
0 [7:1] [0] ggggggg.s
1 [7:2] [1:0] gggggg.ss
2 [7:3] [2:0] ggggg.sss
3 [7:4] [3:0] gggg.ssss
4 [7:5] [4:0] ggg.sssss
5 [7:6] [5:0] gg.ssssss
6 [7] [6:0] g.sssssss
7 No preemption [7:0] .ssssssss

Accessing the ICC_BPR0_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op1CRnCRmop2
ICC_BPR0_EL100011001000011

When HCR_EL2.FMO is set to 1, execution of this encoding at Non-secure EL1 results in an access to ICV_BPR0_EL1.

Accessibility

The register is accessible as follows:

Control Accessibility
FMOIMOTGENSEL0EL1EL2EL3
xxx0 - RW n/a RW
xx11 - n/a RWRW
0x01 - RWRWRW
1x01 - ICV_BPR0_EL1 RWRW

This table applies to all instructions that can access this register.

ICC_BPR0_EL1 is only accessible at Non-secure EL1 when HCR_EL2.FMO is set to 0.

Note

When HCR_EL2.FMO is set to 1, at Non-secure EL1, the instruction encoding used to access ICC_BPR0_EL1 results in an access to ICV_BPR0_EL1.

The minimum binary point value is derived from the number of implemented priority bits. The number of priority bits is IMPLEMENTATION DEFINED, and reported by ICC_CTLR_EL1.PRIbits and ICC_CTLR_EL3.PRIbits.

An attempt to program the binary point field to a value less than the minimum value sets the field to the minimum value. On a reset, the binary point field is UNKNOWN.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When SCR_EL3.NS==1 :

When EL3 is implemented and is using AArch64 and SCR_EL3.NS==0 :

When EL3 is implemented and is using AArch64 :

When EL3 is implemented and is using AArch64 and SCR_EL3.NS==1 :




18/04/2017 17:00

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