MDRAR_EL1, Monitor Debug ROM Address Register

The MDRAR_EL1 characteristics are:

Purpose

Defines the base physical address of a 4KB-aligned memory-mapped debug component, usually a ROM table that locates and describes the memory-mapped debug components in the system. ARMv8 deprecates any use of this register.

This register is part of the Debug registers functional group.

Configuration

AArch64 System register MDRAR_EL1 is architecturally mapped to AArch32 System register DBGDRAR.

Attributes

MDRAR_EL1 is a 64-bit register.

Field descriptions

The MDRAR_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
000000000000ROMADDR[51:48]ROMADDR[47:12]
ROMADDR[47:12]0000000000Valid
313029282726252423222120191817161514131211109876543210

Bits [63:52]

Reserved, RES0.

ROMADDR[51:48], bits [51:48]
In ARMv8.2:

Extension to ROMADDR[47:12]. See ROMADDR[47:12] for more details.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

ROMADDR[47:12], bits [47:12]

Bits[47:12] of the ROM table physical address.

When ARMv8.2-LPA is implemented, and 52-bit addresses and a 64KB translation granule are in use, ROMADDR[52:49] forms the upper part of the address value. Otherwise, ROMADDR[52:49] is RES0.

If the physical address size in bits (PAsize) is less than 52 then the register bits corresponding to ROMADDR [51:PAsize] are RES0.

Bits [11:0] of the ROM table physical address are zero.

ARM strongly recommends that bits ROMADDR[(PAsize-1):32] are zero in any system that supports AArch32 at the highest implemented Exception level.

In an implementation that includes EL3, ROMADDR is an address in Non-secure memory. It is IMPLEMENTATION DEFINED whether the ROM table is also accessible in Secure memory.

Bits [11:2]

Reserved, RES0.

Valid, bits [1:0]

This field indicates whether the ROM Table address is valid. The permitted values of this field are:

ValidMeaning
00

ROM Table address is not valid. Software must ignore ROMADDR.

11

ROM Table address is valid.

Other values are reserved.

Accessing the MDRAR_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
MDRAR_EL11000000010000000

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RO n/a RO
x01 - RORORO
x11 - n/a RORO

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :

When EL3 is implemented and is using AArch64 :




18/04/2017 17:00

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