The DC IVAC characteristics are:
Invalidate data cache by address to Point of Coherency.
This System instruction is part of the Cache maintenance instructions functional group.
AArch64 System instruction DC IVAC performs the same function as AArch32 System instruction DCIMVAC.
DC IVAC is a 64-bit System instruction.
The DC IVAC input value bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
Virtual address to use | |||||||||||||||||||||||||||||||
Virtual address to use | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Virtual address to use.
This instruction is executed using DC with the following syntax:
DC <dc_op>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<dc_op> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
IVAC | 01 | 000 | 0111 | 0110 | 001 |
When the instruction is executed, it can generate a watchpoint, which is prioritized in the same way as other watchpoints. If a watchpoint is generated, the CM bit in the ESR_ELx.ISS field is set to 1.
The instruction is executable as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | WO | n/a | WO |
x | 0 | 1 | - | WO | WO | WO |
x | 1 | 1 | - | n/a | WO | WO |
This table applies to all syntax that can be used to execute this instruction.
This instruction requires write access permission to the VA, otherwise it causes a Permission Fault.
At EL1, this instruction performs a cache clean and invalidate, meaning it performs the same invalidation as a DC CIVAC instruction, if all of the following apply:
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when executing this System instruction.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TPC==1, Non-secure execution of this instruction at EL1 is trapped to EL2.
18/04/2017 17:00
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