The ID_MMFR3 characteristics are:
Provides information about the implemented memory model and memory management support in AArch32 state.
Must be interpreted with ID_MMFR0, ID_MMFR1, ID_MMFR2, and ID_MMFR4.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section G4.14.6.
This register is part of the Identification registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register ID_MMFR3 is architecturally mapped to AArch64 System register ID_MMFR3_EL1.
ID_MMFR3 is a 32-bit register.
The ID_MMFR3 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Supersec | CMemSz | CohWalk | PAN | MaintBcst | BPMaint | CMaintSW | CMaintVA |
Supersections. On a VMSA implementation, indicates whether Supersections are supported. Defined values are:
Supersec | Meaning |
---|---|
0000 |
Supersections supported. |
1111 |
Supersections not supported. |
All other values are reserved.
In ARMv8-A the permitted values are 0000 and 1111.
Cached Memory Size. Indicates the physical memory size supported by the caches. Defined values are:
CMemSz | Meaning |
---|---|
0000 |
4GB, corresponding to a 32-bit physical address range. |
0001 |
64GB, corresponding to a 36-bit physical address range. |
0010 |
1TB or more, corresponding to a 40-bit or larger physical address range. |
All other values are reserved.
In ARMv8-A the permitted values are 0000, 0001, and 0010.
Coherent Walk. Indicates whether Translation table updates require a clean to the point of unification. Defined values are:
CohWalk | Meaning |
---|---|
0000 |
Updates to the translation tables require a clean to the point of unification to ensure visibility by subsequent translation table walks. |
0001 |
Updates to the translation tables do not require a clean to the point of unification to ensure visibility by subsequent translation table walks. |
All other values are reserved.
In ARMv8-A the only permitted value is 0001.
Privileged Access Never. Indicates support for the PAN bit in CPSR, SPSR, and DSPSR in AArch32. Defined values are:
PAN | Meaning |
---|---|
0000 |
PAN not supported. |
0001 |
PAN supported. |
0010 |
PAN supported and ATS1CPRP and ATS1CPWP instructions supported. |
All other values are reserved.
In ARMv8.0 the only permitted value is 0000.
In ARMv8.1 the only permitted value is 0001. This feature is identified by the name ARMv8.1-PAN.
From ARMv8.2, the only permitted value is 0010. This feature is identified by the name ARMv8.2-ATS1E1.
Reserved, RES0.
Maintenance Broadcast. Indicates whether Cache, TLB, and branch predictor operations are broadcast. Defined values are:
MaintBcst | Meaning |
---|---|
0000 |
Cache, TLB, and branch predictor operations only affect local structures. |
0001 |
Cache and branch predictor operations affect structures according to shareability and defined behavior of instructions. TLB operations only affect local structures. |
0010 |
Cache, TLB, and branch predictor operations affect structures according to shareability and defined behavior of instructions. |
All other values are reserved.
In ARMv8-A the only permitted value is 0010.
Branch Predictor Maintenance. Indicates the supported branch predictor maintenance operations in an implementation with hierarchical cache maintenance operations. Defined values are:
BPMaint | Meaning |
---|---|
0000 |
None supported. |
0001 |
Supported branch predictor maintenance operations are:
|
0010 |
As for 0001, and adds:
|
All other values are reserved.
In ARMv8-A the only permitted value is 0010.
Cache Maintenance by Set/Way. Indicates the supported cache maintenance operations by set/way, in an implementation with hierarchical caches. Defined values are:
CMaintSW | Meaning |
---|---|
0000 |
None supported. |
0001 |
Supported hierarchical cache maintenance instructions by set/way are:
|
All other values are reserved.
In ARMv8-A the only permitted value is 0001.
In a unified cache implementation, the data cache maintenance operations apply to the unified caches.
Cache Maintenance by Virtual Address. Indicates the supported cache maintenance operations by VA, in an implementation with hierarchical caches. Defined values are:
CMaintVA | Meaning |
---|---|
0000 |
None supported. |
0001 |
Supported hierarchical cache maintenance operations by VA are:
|
All other values are reserved.
In ARMv8-A the only permitted value is 0001.
In a unified cache implementation, data cache maintenance operations apply to the unified caches, and the instruction cache maintenance instructions are not implemented.
This register can be read using MRC with the following syntax:
MRC <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c0, c1, 7 | 000 | 111 | 0000 | 1111 | 0001 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HSTR_EL2.T0==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HSTR_EL2.T0==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
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