The PMUSERENR characteristics are:
Enables or disables User mode access to the Performance Monitors.
This register is part of the Performance Monitors registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register PMUSERENR is architecturally mapped to AArch64 System register PMUSERENR_EL0.
This register is in the Warm reset domain. Some or all RW fields of this register have defined reset values. On a Warm or Cold reset these apply only if the PE resets into an Exception level that is using AArch32. Otherwise, on a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.
PMUSERENR is a 32-bit register.
The PMUSERENR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ER | CR | SW | EN |
Reserved, RES0.
Event counter read trap control:
ER | Meaning |
---|---|
0 |
EL0 reads of the PMXEVCNTR and PMEVCNTR<n>, and EL0 read/write access to the PMSELR, are trapped to Undefined mode if PMUSERENR.EN is also 0. |
1 |
This control does not cause any instructions to be trapped. |
When this register has an architecturally-defined reset value, this field resets to 0.
Cycle counter read trap control:
CR | Meaning |
---|---|
0 |
EL0 reads of the PMCCNTR are trapped to Undefined mode if PMUSERENR.EN is also 0. |
1 |
This control does not cause any instructions to be trapped. |
When this register has an architecturally-defined reset value, this field resets to 0.
Software increment write trap control:
SW | Meaning |
---|---|
0 |
EL0 writes to the PMSWINC are trapped to Undefined mode if PMUSERENR.EN is also 0. |
1 |
This control does not cause any instructions to be trapped. |
When this register has an architecturally-defined reset value, this field resets to 0.
Traps EL0 accesses to the Performance Monitors registers to Undefined mode:
EN | Meaning |
---|---|
0 |
EL0 accesses to the Performance Monitors registers are trapped to Undefined mode, unless enabled by one of PMUSERENR.{ER, CR, SW}. |
1 |
This control does not cause any instructions to be trapped. Software can access all PMU registers at EL0. |
When this register has an architecturally-defined reset value, this field resets to 0.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c9, c14, 0 | 000 | 000 | 1001 | 1111 | 1110 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | RO | RW | n/a | RW |
x | 0 | 1 | RO | RW | RW | RW |
x | 1 | 1 | RO | n/a | RW | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HSTR_EL2.T9==1, Non-secure accesses to this register from EL0 and EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TPM==1, Non-secure accesses to this register from EL0 and EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T9==1, Non-secure write accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HDCR.TPM==1, Non-secure accesses to this register from EL0 and EL1 are trapped to Hyp mode.
If HSTR.T9==1, Non-secure accesses to this register from EL0 and EL1 are trapped to Hyp mode.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TPM==1, accesses to this register from EL0, EL1, and EL2 are trapped to EL3.
18/04/2017 17:00
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