The CP15DSB characteristics are:
Performs a Data Synchronization Barrier.
ARM deprecates any use of this operation, and strongly recommends that software use the DSB instruction instead.
This System instruction is part of the Legacy feature registers functional group.
There are no configuration notes.
CP15DSB is a 32-bit System instruction.
CP15DSB ignores the value in the register specified by the instruction encoding. Software does not have to write a value to the register before issuing this instruction.
This instruction is executed using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c7, c10, 4 | 000 | 100 | 0111 | 1111 | 1010 |
The instruction is executable as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | WO | WO | n/a | WO |
x | 0 | 1 | WO | WO | WO | WO |
x | 1 | 1 | WO | n/a | WO | WO |
This table applies to all syntax that can be used to execute this instruction.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when executing this System instruction.
In both Security states, and not dependent on other configuration bits:
If SCTLR.CP15BEN==0, execution of this instruction at PL0 and PL1 is UNDEFINED.
If SCTLR_EL1.CP15BEN==0, execution of this instruction at PL0 is UNDEFINED.
If HSCTLR.CP15BEN==0, execution of this instruction at PL2 is UNDEFINED.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HSTR_EL2.T7==1, Non-secure execution of this instruction at EL0 and EL1 is trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T7==1, Non-secure execution of this instruction at EL0 and EL1 is trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HSTR.T7==1, Non-secure execution of this instruction at EL0 and EL1 is trapped to Hyp mode.
18/04/2017 17:00
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