The GICR_VPROPBASER characteristics are:
Specifies the base address of the memory that holds the virtual LPI Configuration table for the currently scheduled virtual machine.
This register is part of the GIC Redistributor registers functional group.
This register is accessible as follows:
Security disabled | Secure | Non-secure |
---|---|---|
RW | RW | RW |
RW fields in this register reset to architecturally UNKNOWN values.
This register is provided in GICv4 implementations only.
GICR_VPROPBASER is a 64-bit register.
The GICR_VPROPBASER bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | OuterCache | 0 | 0 | 0 | 0 | Physical_Address | |||||||||||||||||||||
Physical_Address | Shareability | InnerCache | 0 | 0 | IDbits | ||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Indicates the Outer Cacheability attributes of accesses to the LPI Configuration table. The possible values of this field are:
OuterCache | Meaning |
---|---|
000 |
Memory type defined in InnerCache field. For Normal memory, Outer Cacheability is the same as Inner Cacheability. |
001 |
Normal Outer Non-cacheable. |
010 |
Normal Outer Cacheable Read-allocate, Write-through. |
011 |
Normal Outer Cacheable Read-allocate, Write-back. |
100 |
Normal Outer Cacheable Write-allocate, Write-through. |
101 |
Normal Outer Cacheable Write-allocate, Write-back. |
110 |
Normal Outer Cacheable Read-allocate, Write-allocate, Write-through. |
111 |
Normal Outer Cacheable Read-allocate, Write-allocate, Write-back. |
It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to a value that is architecturally UNKNOWN.
Reserved, RES0.
Bits [51:12] of the physical address containing the virtual LPI Configuration table.
In implementations supporting fewer than 52 bits of physical address, unimplemented upper bits are RES0.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Indicates the Shareability attributes of accesses to the LPI Configuration table. The possible values of this field are:
Shareability | Meaning |
---|---|
00 |
Non-shareable. |
01 |
Inner Shareable. |
10 |
Outer Shareable. |
11 |
Reserved. Treated as 00. |
It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to a value that is architecturally UNKNOWN.
Indicates the Inner Cacheability attributes of accesses to the LPI Configuration table. The possible values of this field are:
InnerCache | Meaning |
---|---|
000 |
Device-nGnRnE. |
001 |
Normal Inner Non-cacheable. |
010 |
Normal Inner Cacheable Read-allocate, Write-through. |
011 |
Normal Inner Cacheable Read-allocate, Write-back. |
100 |
Normal Inner Cacheable Write-allocate, Write-through. |
101 |
Normal Inner Cacheable Write-allocate, Write-back. |
110 |
Normal Inner Cacheable Read-allocate, Write-allocate, Write-through. |
111 |
Normal Inner Cacheable Read-allocate, Write-allocate, Write-back. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Reserved, RES0.
The number of bits of virtual LPI INTID supported, minus one.
If the value of this field is less than 0b1101, indicating that the largest INTID is less than 8192 (the smallest LPI interrupt ID), the GIC will behave as if all virtual LPIs are out of range.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
GICR_VPROPBASER can be accessed through its memory-mapped interface:
Component | Frame | Offset |
---|---|---|
GIC Redistributor | VLPI_base | 0x0070-0x0074 |
18/04/2017 17:00
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