The ID_ISAR1_EL1 characteristics are:
Provides information about the instruction sets implemented by the PE in AArch32 state.
Must be interpreted with ID_ISAR0_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1, ID_ISAR4_EL1, and ID_ISAR5_EL1.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.
This register is part of the Identification registers functional group.
AArch64 System register ID_ISAR1_EL1 is architecturally mapped to AArch32 System register ID_ISAR1.
In an implementation that supports only AArch64 state, this register is UNKNOWN.
ID_ISAR1_EL1 is a 32-bit register.
The ID_ISAR1_EL1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Jazelle | Interwork | Immediate | IfThen | Extend | Except_AR | Except | Endian |
Indicates the implemented Jazelle extension instructions. Defined values are:
Jazelle | Meaning |
---|---|
0000 |
No support for Jazelle. |
0001 |
Adds the BXJ instruction, and the J bit in the PSR. This setting might indicate a trivial implementation of the Jazelle extension. |
All other values are reserved.
In ARMv8-A the only permitted value is 0001.
Indicates the implemented Interworking instructions. Defined values are:
Interwork | Meaning |
---|---|
0000 |
None implemented. |
0001 |
Adds the BX instruction, and the T bit in the PSR. |
0010 |
As for 0001, and adds the BLX instruction. PC loads have BX-like behavior. |
0011 |
As for 0010, and guarantees that data-processing instructions in the A32 instruction set with the PC as the destination and the S bit clear have BX-like behavior. |
All other values are reserved.
In ARMv8-A the only permitted value is 0011.
Indicates the implemented data-processing instructions with long immediates. Defined values are:
Immediate | Meaning |
---|---|
0000 |
None implemented. |
0001 |
Adds:
|
All other values are reserved.
In ARMv8-A the only permitted value is 0001.
Indicates the implemented If-Then instructions in the T32 instruction set. Defined values are:
IfThen | Meaning |
---|---|
0000 |
None implemented. |
0001 |
Adds the IT instructions, and the IT bits in the PSRs. |
All other values are reserved.
In ARMv8-A the only permitted value is 0001.
Indicates the implemented Extend instructions. Defined values are:
Extend | Meaning |
---|---|
0000 |
No scalar sign-extend or zero-extend instructions are implemented, where scalar instructions means non-Advanced SIMD instructions. |
0001 |
Adds the SXTB, SXTH, UXTB, and UXTH instructions. |
0010 |
As for 0001, and adds the SXTB16, SXTAB, SXTAB16, SXTAH, UXTB16, UXTAB, UXTAB16, and UXTAH instructions. |
All other values are reserved.
In ARMv8-A the only permitted value is 0010.
Indicates the implemented A and R profile exception-handling instructions. Defined values are:
Except_AR | Meaning |
---|---|
0000 |
None implemented. |
0001 |
Adds the SRS and RFE instructions, and the A and R profile forms of the CPS instruction. |
All other values are reserved.
In ARMv8-A the only permitted value is 0001.
Indicates the implemented exception-handling instructions in the ARM instruction set. Defined values are:
Except | Meaning |
---|---|
0000 |
Not implemented. This indicates that the User bank and Exception return forms of the LDM and STM instructions are not implemented. |
0001 |
Adds the LDM (exception return), LDM (user registers), and STM (user registers) instruction versions. |
All other values are reserved.
In ARMv8-A the only permitted value is 0001.
Indicates the implemented Endian instructions. Defined values are:
Endian | Meaning |
---|---|
0000 |
None implemented. |
0001 |
Adds the SETEND instruction, and the E bit in the PSRs. |
All other values are reserved.
In ARMv8-A the permitted values are 0000 and 0001.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
ID_ISAR1_EL1 | 11 | 000 | 0000 | 0010 | 001 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
18/04/2017 17:00
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Confidential.