AFSR1_EL2, Auxiliary Fault Status Register 1 (EL2)

The AFSR1_EL2 characteristics are:

Purpose

Provides additional IMPLEMENTATION DEFINED fault status information for exceptions taken to EL2.

This register is part of:

Configuration

AArch64 System register AFSR1_EL2 is architecturally mapped to AArch32 System register HAIFSR.

If EL2 is not implemented, this register is RES0 from EL3.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

AFSR1_EL2 is a 32-bit register.

Field descriptions

The AFSR1_EL2 bit assignments are:

313029282726252423222120191817161514131211109876543210
IMPLEMENTATION DEFINED

IMPLEMENTATION DEFINED, bits [31:0]

IMPLEMENTATION DEFINED.

Accessing the AFSR1_EL2

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
AFSR1_EL21110001010001001
AFSR1_EL11100001010001001

Accessibility

The register is accessible as follows:

<systemreg> Control Accessibility
E2HTGENSEL0EL1EL2EL3
AFSR1_EL2xx0 - - n/a RW
AFSR1_EL2001 - - RWRW
AFSR1_EL2011 - n/a RWRW
AFSR1_EL2101 - - RWRW
AFSR1_EL2111 - n/a RWRW
AFSR1_EL1xx0 - AFSR1_EL1 n/a AFSR1_EL1
AFSR1_EL1001 - AFSR1_EL1 AFSR1_EL1 AFSR1_EL1
AFSR1_EL1011 - n/a AFSR1_EL1 AFSR1_EL1
AFSR1_EL1101 - AFSR1_EL1 RW AFSR1_EL1
AFSR1_EL1111 - n/a RW AFSR1_EL1

When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic AFSR1_EL2 or AFSR1_EL1 are not guaranteed to be ordered with respect to accesses using the other mnemonic.




18/04/2017 17:00

Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Confidential.