The CTIDEVAFF1 characteristics are:
Copy of the high half of the PE MPIDR_EL1 register that allows a debugger to determine which PE in a multiprocessor system the CTI component relates to.
This register is part of the Cross-Trigger Interface registers functional group.
This register is accessible as follows:
SLK | Default |
---|---|
RO | RO |
CTIDEVAFF1 is in the Debug power domain.
Implementation of this register is OPTIONAL.
CTIDEVAFF1 is a 32-bit register.
The CTIDEVAFF1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MPIDR_EL1 high half |
MPIDR_EL1 high half. Read-only copy of the high half of MPIDR_EL1, as seen from the highest implemented Exception level.
CTIDEVAFF1 can be accessed through the external debug interface:
Component | Offset |
---|---|
CTI | 0xFAC |
18/04/2017 17:00
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