The ID_MMFR2_EL1 characteristics are:
Provides information about the implemented memory model and memory management support in AArch32 state.
Must be interpreted with ID_MMFR0_EL1, ID_MMFR1_EL1, ID_MMFR3_EL1, and ID_MMFR4_EL1.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.
This register is part of the Identification registers functional group.
AArch64 System register ID_MMFR2_EL1 is architecturally mapped to AArch32 System register ID_MMFR2.
In an implementation that supports only AArch64 state, this register is UNKNOWN.
ID_MMFR2_EL1 is a 32-bit register.
The ID_MMFR2_EL1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HWAccFlg | WFIStall | MemBarr | UniTLB | HvdTLB | L1HvdRng | L1HvdBG | L1HvdFG |
Hardware Access Flag. In earlier versions of the ARM Architecture, this field indicates support for a Hardware Access flag, as part of the VMSAv7 implementation. Defined values are:
HWAccFlg | Meaning |
---|---|
0000 |
Not supported. |
0001 |
Support for VMSAv7 Access flag, updated in hardware. |
All other values are reserved.
In ARMv8 the only permitted value is 0000.
Wait For Interrupt Stall. Indicates the support for Wait For Interrupt (WFI) stalling. Defined values are:
WFIStall | Meaning |
---|---|
0000 |
Not supported. |
0001 |
Support for WFI stalling. |
All other values are reserved.
In ARMv8 the permitted values are 0000 and 0001.
Memory Barrier. Indicates the supported memory barrier System instructions in the (coproc==1111) encoding space:
MemBarr | Meaning |
---|---|
0000 |
None supported. |
0001 |
Supported memory barrier System instructions are:
|
0010 |
As for 0001, and adds:
|
All other values are reserved.
In ARMv8 the only permitted value is 0010.
ARM deprecates the use of these operations. ID_ISAR4.Barrier_instrs indicates the level of support for the preferred barrier instructions.
Unified TLB. Indicates the supported TLB maintenance operations, for a unified TLB implementation. Defined values are:
UniTLB | Meaning |
---|---|
0000 |
Not supported. |
0001 |
Supported unified TLB maintenance operations are:
|
0010 |
As for 0001, and adds:
|
0011 |
As for 0010, and adds:
|
0100 |
As for 0011, and adds:
|
0101 |
As for 0100, and adds the following operations: TLBIMVALIS, TLBIMVAALIS, TLBIMVALHIS, TLBIMVAL, TLBIMVAAL, TLBIMVALH. |
0110 |
As for 0101, and adds the following operations: TLBIIPAS2IS, TLBIIPAS2LIS, TLBIIPAS2, TLBIIPAS2L. |
All other values are reserved.
In ARMv8-A the only permitted value is 0110.
If the Unified TLB field (UniTLB, bits [19:16]) is not 0000, then the meaning of this field is IMPLEMENTATION DEFINED. ARM deprecates the use of this field by software.
Level 1 Harvard cache Range. Indicates the supported Level 1 cache maintenance range operations, for a Harvard cache implementation. Defined values are:
L1HvdRng | Meaning |
---|---|
0000 |
Not supported. |
0001 |
Supported Level 1 Harvard cache maintenance range operations are:
|
All other values are reserved.
In ARMv8 the only permitted value is 0000.
Level 1 Harvard cache Background fetch. Indicates the supported Level 1 cache background fetch operations, for a Harvard cache implementation. When supported, background fetch operations are non-blocking operations. Defined values are:
L1HvdBG | Meaning |
---|---|
0000 |
Not supported. |
0001 |
Supported Level 1 Harvard cache background fetch operations are:
|
All other values are reserved.
In ARMv8 the only permitted value is 0000.
Level 1 Harvard cache Foreground fetch. Indicates the supported Level 1 cache foreground fetch operations, for a Harvard cache implementation. When supported, foreground fetch operations are blocking operations. Defined values are:
L1HvdFG | Meaning |
---|---|
0000 |
Not supported. |
0001 |
Supported Level 1 Harvard cache foreground fetch operations are:
|
All other values are reserved.
In ARMv8 the only permitted value is 0000.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
ID_MMFR2_EL1 | 11 | 000 | 0000 | 0001 | 110 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
18/04/2017 17:00
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