The ICC_AP0R<n>_EL1 characteristics are:
Provides information about Group 0 active priorities.
This register is part of:
AArch64 System register ICC_AP0R<n>_EL1 is architecturally mapped to AArch32 System register ICC_AP0R<n>.
ICC_AP0R<n>_EL1 is a 32-bit register.
The ICC_AP0R<n>_EL1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED |
IMPLEMENTATION DEFINED.
When this register has an architecturally-defined reset value, this field resets to 0.
The contents of these registers are IMPLEMENTATION DEFINED with the one architectural requirement that the value 0x00000000 is consistent with no interrupts being active.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op1 | CRn | CRm | op2 |
---|---|---|---|---|
ICC_AP0R<n>_EL1 | 000 | 1100 | 1000 | 1:n<1:0> |
When HCR_EL2.FMO is set to 1, execution of this encoding at Non-secure EL1 results in an access to ICV_AP0R<n>_EL1.
The register is accessible as follows:
Control | Accessibility | ||||||
---|---|---|---|---|---|---|---|
FMO | IMO | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | x | 0 | - | RW | n/a | RW |
x | x | 1 | 1 | - | n/a | RW | RW |
0 | x | 0 | 1 | - | RW | RW | RW |
1 | x | 0 | 1 | - | ICV_AP0R<n>_EL1 | RW | RW |
This table applies to all instructions that can access this register.
The ICC_AP0R<n>_EL1 registers are only accessible at Non-secure EL1 when HCR_EL2.FMO is set to 0.
When HCR_EL2.FMO is set to 1, at Non-secure EL1, the instruction encoding used to access ICC_AP0R<n>_EL1 results in an access to ICV_AP0R<n>_EL1.
Writing to these registers with any value other than the last read value of the register (or 0x00000000 when there are no Group 0 active priorities) might result in UNPREDICTABLE behavior of the interrupt prioritization system, causing:
ICC_AP0R1_EL1 is only implemented in implementations that support 6 or more bits of priority. ICC_AP0R2_EL1 and ICC_AP0R3_EL1 are only implemented in implementations that support 7 bits of priority. Unimplemented registers are UNDEFINED.
Writing to the active priority registers in any order other than the following order will result in UNPREDICTABLE behavior:
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_SRE_EL1.SRE==0, accesses to this register from EL1 are trapped to EL1.
If ICC_SRE_EL2.SRE==0, accesses to this register from EL2 are trapped to EL2.
If ICC_SRE_EL3.SRE==0, accesses to this register from EL3 are trapped to EL3.
When SCR_EL3.NS==1 :
If ICH_HCR_EL2.TALL0==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL3 is implemented and is using AArch64 and SCR_EL3.NS==0 :
If SCR_EL3.FIQ==1, Secure accesses to this register from EL1 are trapped to EL3.
When EL3 is implemented and is using AArch64 :
If SCR_EL3.FIQ==1, accesses to this register from EL2 are trapped to EL3.
When EL3 is implemented and is using AArch64 and SCR_EL3.NS==1 :
18/04/2017 17:00
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Confidential.