The ESR_EL3 characteristics are:
Holds syndrome information for an exception taken to EL3.
This register is part of the Exception and fault handling registers functional group.
RW fields in this register reset to architecturally UNKNOWN values.
ESR_EL3 is a 32-bit register.
See ESR_ELx.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
ESR_EL3 | 11 | 110 | 0101 | 0010 | 000 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | - | n/a | RW |
0 | 0 | 1 | - | - | - | RW |
0 | 1 | 1 | - | n/a | - | RW |
1 | 0 | 1 | - | - | - | RW |
1 | 1 | 1 | - | n/a | - | RW |
This table applies to all instructions that can access this register.
18/04/2017 17:00
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Confidential.