The GITS_CBASER characteristics are:
Specifies the base address and size of the ITS command queue.
This register is part of the GIC ITS registers functional group.
This register is accessible as follows:
Security disabled | Secure | Non-secure |
---|---|---|
RW | RW | RW |
When GITS_CTLR.Enabled == 1 or GITS_CTLR.Quiescent == 0, writing this register is UNPREDICTABLE.
Some or all RW fields of this register have defined reset values.
Bits [63:32] and bits [31:0] are accessible separately.
GITS_CBASER is a 64-bit register.
The GITS_CBASER bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
Valid | 0 | InnerCache | 0 | 0 | 0 | OuterCache | 0 | Physical_Address | |||||||||||||||||||||||
Physical_Address | Shareability | 0 | 0 | Size | |||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Indicates whether software has allocated memory for the command queue:
Valid | Meaning |
---|---|
0 |
No memory is allocated for the command queue. |
1 |
Memory is allocated to the command queue. |
When this register has an architecturally-defined reset value, this field resets to 0.
Reserved, RES0.
Indicates the Inner Cacheability attributes of accesses to the command queue. The possible values of this field are:
InnerCache | Meaning |
---|---|
000 |
Device-nGnRnE. |
001 |
Normal Inner Non-cacheable. |
010 |
Normal Inner Cacheable Read-allocate, Write-through. |
011 |
Normal Inner Cacheable Read-allocate, Write-back. |
100 |
Normal Inner Cacheable Write-allocate, Write-through. |
101 |
Normal Inner Cacheable Write-allocate, Write-back. |
110 |
Normal Inner Cacheable Read-allocate, Write-allocate, Write-through. |
111 |
Normal Inner Cacheable Read-allocate, Write-allocate, Write-back. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Reserved, RES0.
Indicates the Outer Cacheability attributes of accesses to the command queue. The possible values of this field are:
OuterCache | Meaning |
---|---|
000 |
Memory type defined in InnerCache field. For Normal memory, Outer Cacheability is the same as Inner Cacheability. |
001 |
Normal Outer Non-cacheable. |
010 |
Normal Outer Cacheable Read-allocate, Write-through. |
011 |
Normal Outer Cacheable Read-allocate, Write-back. |
100 |
Normal Outer Cacheable Write-allocate, Write-through. |
101 |
Normal Outer Cacheable Write-allocate, Write-back. |
110 |
Normal Outer Cacheable Read-allocate, Write-allocate, Write-through. |
111 |
Normal Outer Cacheable Read-allocate, Write-allocate, Write-back. |
It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to a value that is architecturally UNKNOWN.
Reserved, RES0.
Bits [51:12] of the base physical address of the command queue. Bits [11:0] of the base address are 0.
In implementations supporting fewer than 52 bits of physical address, unimplemented upper bits are RES0.
If bits [15:12] are not all zeros, behavior is a CONSTRAINED UNPREDICTABLE choice:
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Indicates the Shareability attributes of accesses to the command queue. The possible values of this field are:
Shareability | Meaning |
---|---|
00 |
Non-shareable. |
01 |
Inner Shareable. |
10 |
Outer Shareable. |
11 |
Reserved. Treated as 00. |
It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to a value that is architecturally UNKNOWN.
Reserved, RES0.
The number of 4KB pages of physical memory allocated to the command queue, minus one.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
The command queue is a circular buffer and wraps at Physical Address [47:0] + (4096 * (Size + 1)).
When this register is successfully written, the value of GITS_CREADR is set to zero.
GITS_CBASER can be accessed through its memory-mapped interface:
Component | Offset |
---|---|
GIC ITS control | 0x0080-0x0084 |
18/04/2017 17:00
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Confidential.