GICV_HPPIR, Virtual Machine Highest Priority Pending Interrupt Register

The GICV_HPPIR characteristics are:

Purpose

Provides the INTID of the highest priority pending Group 0 virtual interrupt in the List registers.

This register corresponds to the physical CPU interface register GICC_HPPIR.

This register is part of the GIC virtual CPU interface registers functional group.

Usage constraints

This register is accessible as follows:

Security disabledSecureNon-secure
RORORO

This register is used only when System register access is not enabled. When System register access is enabled:

This register is used for Group 0 interrupts only. GICV_AHPPIR provides equivalent functionality for Group 1 interrupts.

When affinity routing is enabled, it is a programming error to use memory-mapped registers to access the GIC.

Configuration

This register is available when the GIC implementation supports interrupt virtualization.

Attributes

GICV_HPPIR is a 32-bit register.

Field descriptions

The GICV_HPPIR bit assignments are:

313029282726252423222120191817161514131211109876543210
0000000INTID

Bits [31:25]

Reserved, RES0.

INTID, bits [24:0]

The INTID of the signaled interrupt.

Note

INTIDs 1020-1023 are reserved and convey additional information such as spurious interrupts.

When affinity routing is not enabled:

Reads of the GICC_HPPIR that do not return a valid INTID return a spurious INTID, 1022 or 1023. See Special INTIDs.

Highest priority pending interrupt Group GICV_HPPIR read GICV_CTLR.AckCtl Returned INTID
1 Non-secure x ID of Group 1 interrupt
1 Secure 0 1022
1 Secure 1 ID of Group 1 interrupt
0 Non-secure x 1023
0 Secure x ID of Group 0 interrupt
No pending interrupts x x 1023

If the CPU interface supports only a single Security state, the entries that apply to Secure reads describe the behavior.

Accessing the GICV_HPPIR

GICV_HPPIR can be accessed through its memory-mapped interface:

ComponentOffset
GIC Virtual CPU interface 0x0018



18/04/2017 17:00

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