The DBGOSLSR characteristics are:
Provides status information for the OS lock.
This register is part of the Debug registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register DBGOSLSR is architecturally mapped to AArch64 System register OSLSR_EL1.
The OS lock status is also visible in the external debug interface through EDPRSR.
This register is in the Cold reset domain. Some or all RW fields of this register have defined reset values. On a Cold reset these apply only if the PE resets into an Exception level that is using AArch32. Otherwise, on a Cold reset RW fields in this register reset to architecturally UNKNOWN values. The register is not affected by a Warm reset.
DBGOSLSR is a 32-bit register.
The DBGOSLSR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | OSLM[1] | nTT | OSLK | OSLM[0] |
Reserved, RES0.
See below for description of the OSLM field.
Not 32-bit access. This bit is always RAZ. It indicates that a 32-bit access is needed to write the key to the OS Lock Access Register.
OS Lock Status. The possible values are:
OSLK | Meaning |
---|---|
0 |
OS lock unlocked. |
1 |
OS lock locked. |
The OS lock is locked and unlocked by writing to the OS Lock Access Register.
When this register has an architecturally-defined reset value, this field resets to 1.
OS lock model implemented. Identifies the form of OS save and restore mechanism implemented. In ARMv8 these bits are as follows:
OSLM | Meaning |
---|---|
10 |
OS lock implemented. DBGOSSRR not implemented. |
All other values are reserved.
This register can be read using MRC with the following syntax:
MRC <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p14, 0, <Rt>, c1, c1, 4 | 000 | 100 | 0001 | 1110 | 0001 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TDOSA==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HDCR.TDOSA==1, Non-secure read accesses to this register from EL1 are trapped to Hyp mode.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TDOSA==1, read accesses to this register from EL1 and EL2 are trapped to EL3.
18/04/2017 17:00
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