GICD_SETSPI_NSR, Set Non-secure SPI Pending Register

The GICD_SETSPI_NSR characteristics are:

Purpose

Adds the pending state to a valid SPI if permitted by the Security state of the access and the GICD_NSACR<n> value for that SPI.

A write to this register changes the state of an inactive SPI to pending, and the state of an active SPI to active and pending.

This register is part of the GIC Distributor registers functional group.

Usage constraints

This register is accessible as follows:

Security disabledSecureNon-secure
WOWOWO

Writes to this register have no effect if:

16-bit accesses to bits [15:0] of this register must be supported.

Note

A Secure access to this register can set the pending state of any valid SPI.

Configuration

If GICD_TYPER.MBIS == 0, this register is reserved.

When GICD_CTLR.DS==1, this register provides functionality for all SPIs.

Attributes

GICD_SETSPI_NSR is a 32-bit register.

Field descriptions

The GICD_SETSPI_NSR bit assignments are:

313029282726252423222120191817161514131211109876543210
0000000000000000000000INTID

Bits [31:10]

Reserved, RES0.

INTID, bits [9:0]

The INTID of the SPI.

The function of this register depends on whether the targeted SPI is configured to be an edge-triggered or level-sensitive interrupt:

Accessing the GICD_SETSPI_NSR

GICD_SETSPI_NSR can be accessed through its memory-mapped interface:

ComponentOffset
GIC Distributor 0x0040



18/04/2017 17:00

Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Confidential.