DBGBVR<n>_EL1, Debug Breakpoint Value Registers, n = 0 - 15

The DBGBVR<n>_EL1 characteristics are:

Purpose

Holds a virtual address, or a VMID and/or a context ID, for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR<n>_EL1.

This register is part of the Debug registers functional group.

Usage constraints

This register is accessible as follows:

OffDLKOSLKEDADSLKDefault
ErrorErrorErrorErrorRORW

Configuration

External register DBGBVR<n>_EL1 is architecturally mapped to AArch64 System register DBGBVR<n>_EL1.

External register DBGBVR<n>_EL1 bits [31:0] are architecturally mapped to AArch32 System register DBGBVR<n>.

External register DBGBVR<n>_EL1 bits [63:32] are architecturally mapped to AArch32 System register DBGBXVR<n>.

DBGBVR<n>_EL1 is in the Core power domain. RW fields in this register reset to architecturally UNKNOWN values. These apply only on a Cold reset. The register is not affected by a Warm reset and is not affected by an External debug reset.

If breakpoint n is not implemented then this register is unallocated.

Attributes

How this register is interpreted depends on the value of DBGBCR<n>_EL1.BT.

For other values of DBGBCR<n>_EL1.BT, this register is RES0.

Field descriptions

The DBGBVR<n>_EL1 bit assignments are:

When DBGBCR<n>_EL1.BT==0b0x0x:

6362616059585756555453525150494847464544434241403938373635343332
RESS[14:4]VA[52:49]VA[48:2]
VA[48:2]00
313029282726252423222120191817161514131211109876543210

RESS[14:4], bits [63:53]

Reserved, Sign extended. Software must treat this field as RES0 if the most significant bit of VA is 0 or RES0, and as RES1 if the most significant bit of VA is 1.

Hardware always ignores the value of these bits and it is IMPLEMENTATION DEFINED whether:

VA[52:49], bits [52:49]
In ARMv8.2:

Extension to VA[48:2]. See VA[48:2] for more details.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.


In ARMv8.1 and ARMv8.0:

Extension to RESS[14:4]. See RESS[14:4] for more details.

VA[48:2], bits [48:2]

If the address is being matched in an AArch64 stage 1 translation regime:

If the address is being matched in an AArch32 stage 1 translation regime, the first 20 bits of this field are RES0, and the rest of the field contains bits[31:2] of the address for comparison.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bits [1:0]

Reserved, RES0.

When DBGBCR<n>_EL1.BT==0b001x:

6362616059585756555453525150494847464544434241403938373635343332
00000000000000000000000000000000
ContextID
313029282726252423222120191817161514131211109876543210

Bits [63:32]

Reserved, RES0.

ContextID, bits [31:0]

Context ID value for comparison.

The value is compared against CONTEXTIDR and CONTEXTIDR_EL1 in the following cases:

When ARMv8.1-VHE is implemented, HCR_EL2.E2H is 1, the value is compared against CONTEXTIDR_EL2 in the following cases:

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

When DBGBCR<n>_EL1.BT==0b011x:

6362616059585756555453525150494847464544434241403938373635343332
00000000000000000000000000000000
ContextID
313029282726252423222120191817161514131211109876543210

Bits [63:32]

Reserved, RES0.

ContextID, bits [31:0]

Context ID value for comparison against CONTEXTIDR_EL1.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

When DBGBCR<n>_EL1.BT==0b100x and EL2 implemented:

6362616059585756555453525150494847464544434241403938373635343332
0000000000000000VMID[15:8]VMID[7:0]
00000000000000000000000000000000
313029282726252423222120191817161514131211109876543210

Bits [63:48]

Reserved, RES0.

VMID[15:8], bits [47:40]
In ARMv8.2 and ARMv8.1:

Extension to VMID[7:0]. See VMID[7:0] for more details.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.


In ARMv8.0:

Reserved, RES0.

VMID[7:0], bits [39:32]

VMID value for comparison.

The VMID is 8 bits in the following cases.

When ARMv8.1-VMID16 is implemented and EL2 is using AArch64, it is IMPLEMENTATION DEFINED whether the VMID is 8 bits or 16 bits.

VMID[15:8] is RES0 if any of the following applies:

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bits [31:0]

Reserved, RES0.

When DBGBCR<n>_EL1.BT==0b101x and EL2 implemented:

6362616059585756555453525150494847464544434241403938373635343332
0000000000000000VMID[15:8]VMID[7:0]
ContextID
313029282726252423222120191817161514131211109876543210

Bits [63:48]

Reserved, RES0.

VMID[15:8], bits [47:40]
In ARMv8.2 and ARMv8.1:

Extension to VMID[7:0]. See VMID[7:0] for more details.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.


In ARMv8.0:

Reserved, RES0.

VMID[7:0], bits [39:32]

VMID value for comparison.

The VMID is 8 bits in the following cases.

When ARMv8.1-VMID16 is implemented and EL2 is using AArch64, it is IMPLEMENTATION DEFINED whether the VMID is 8 bits or 16 bits.

VMID[15:8] is RES0 if any of the following applies:

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

ContextID, bits [31:0]

Context ID value for comparison against CONTEXTIDR_EL1.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

When DBGBCR<n>_EL1.BT==0b110x and EL2 implemented:

6362616059585756555453525150494847464544434241403938373635343332
ContextID2
00000000000000000000000000000000
313029282726252423222120191817161514131211109876543210

ContextID2, bits [63:32]

Context ID value for comparison against CONTEXTIDR_EL2.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bits [31:0]

Reserved, RES0.

When DBGBCR<n>_EL1.BT==0b111x and EL2 implemented:

6362616059585756555453525150494847464544434241403938373635343332
ContextID2
ContextID
313029282726252423222120191817161514131211109876543210

ContextID2, bits [63:32]

Context ID value for comparison against CONTEXTIDR_EL2.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

ContextID, bits [31:0]

Context ID value for comparison against CONTEXTIDR_EL1.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Accessing the DBGBVR<n>_EL1

DBGBVR<n>_EL1[31:0] can be accessed through the external debug interface:

ComponentOffset
Debug0x400 + 16n

DBGBVR<n>_EL1[63:32] can be accessed through the external debug interface:

ComponentOffset
Debug0x404 + 16n



18/04/2017 17:00

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