CNTP_CVAL, Counter-timer Physical Timer CompareValue

The CNTP_CVAL characteristics are:

Purpose

Holds the 64-bit compare value for the EL1 physical timer.

This register is part of the Generic Timer registers functional group.

Usage constraints

This register is accessible as follows:

Default
RW

CNTP_CVAL can be implemented in any implemented CNTBaseN frame, and in the corresponding CNTEL0BaseN frame.

'CNTCTLBase status and control fields for the CNTBaseN and CNTEL0BaseN frames' in Chapter I1 of the ARMv8 ARM describes the status fields that identify whether a CNTBaseN frame is implemented, and for an implemented frame:

For an implemented CNTBaseN frame:

For an implemented CNTEL0BaseN frame:

If the implementation supports 64-bit atomic accesses, then the CNTP_CVAL register must be accessible as an atomic 64-bit value.

Configuration

The power domain of CNTP_CVAL is IMPLEMENTATION DEFINED.

On a reset of the reset domain in which an RW instance of this register is implemented, RW fields in the register reset to UNKNOWN values. The register is not affected by a reset of any other reset domain. For more information see 'Power and reset domains for the system level implementation of the Generic Timer' in Chapter I1 of the ARMv8 ARM.

Attributes

CNTP_CVAL is a 64-bit register.

Field descriptions

The CNTP_CVAL bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
CompareValue
CompareValue
313029282726252423222120191817161514131211109876543210

CompareValue, bits [63:0]

Holds the EL1 physical timer CompareValue.

When CNTP_CTL.ENABLE is 1, the timer condition is met when (CNTPCT - CompareValue) is greater than zero. This means that CompareValue acts like a 64-bit upcounter timer. When the timer condition is met:

When CNTP_CTL.ENABLE is 0, the timer condition is not met, but CNTPCT continues to count.

Accessing the CNTP_CVAL

CNTP_CVAL[31:0] can be accessed through its memory-mapped interface:

ComponentFrameOffset
TimerCNTBaseN 0x020
TimerCNTEL0BaseN 0x020

CNTP_CVAL[63:32] can be accessed through its memory-mapped interface:

ComponentFrameOffset
TimerCNTBaseN 0x024
TimerCNTEL0BaseN 0x024



18/04/2017 17:00

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