The ID_PFR1_EL1 characteristics are:
Gives information about the AArch32 programmers' model.
Must be interpreted with ID_PFR0_EL1.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.
This register is part of the Identification registers functional group.
AArch64 System register ID_PFR1_EL1 is architecturally mapped to AArch32 System register ID_PFR1.
In an implementation that supports only AArch64 state, this register is UNKNOWN.
ID_PFR1_EL1 is a 32-bit register.
The ID_PFR1_EL1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GIC | Virt_frac | Sec_frac | GenTimer | Virtualization | MProgMod | Security | ProgMod |
System register GIC CPU interface. Defined values are:
GIC | Meaning |
---|---|
0000 |
No System register interface to the GIC CPU interface is supported. |
0001 |
System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported. |
All other values are reserved.
Virtualization fractional field. When the Virtualization field is 0000, determines the support for features from the ARMv7 Virtualization Extensions. Defined values are:
Virt_frac | Meaning |
---|---|
0000 |
No features from the ARMv7 Virtualization Extensions are implemented. |
0001 |
The following features of the ARMv7 Virtualization Extensions are implemented: |
All other values are reserved.
In ARMv8-A the permitted values are:
This field is only valid when the value of ID_PFR1_EL1.Virtualization is 0, otherwise it holds the value 0000.
The ID_ISAR registers do not identify whether the instructions added by the ARMv7 Virtualization Extensions are implemented.
Security fractional field. When the Security field is 0000, determines the support for features from the ARMv7 Security Extensions. Defined values are:
Sec_frac | Meaning |
---|---|
0000 |
No features from the ARMv7 Security Extensions are implemented. |
0001 |
The following features from the ARMv7 Security Extensions are implemented: |
0010 |
As for 0001, plus the ability to access Secure or Non-secure physical memory is supported. |
All other values are reserved.
In ARMv8-A the permitted values are:
This field is only valid when the value of ID_PFR1_EL1.Security is 0, otherwise it holds the value 0000.
Generic Timer support. Defined values are:
GenTimer | Meaning |
---|---|
0000 |
Not implemented. |
0001 |
Generic Timer implemented. |
All other values are reserved.
In ARMv8-A the only permitted value is 0001.
Virtualization support. Defined values are:
Virtualization | Meaning |
---|---|
0000 |
EL2, Hyp mode, and the HVC instruction not implemented. |
0001 |
EL2, Hyp mode, the HVC instruction, and all the features described by Virt_frac == 0001 implemented. |
All other values are reserved.
In ARMv8-A the permitted values are:
In an implementation that includes EL2, if EL2 cannot use AArch32 but EL1 can use AArch32 then this field has the value 0001.
If EL1 cannot use AArch32 then this field has the value 0000.
The ID_ISARs do not identify whether the HVC instruction is implemented.
M profile programmers' model support. Defined values are:
MProgMod | Meaning |
---|---|
0000 |
Not supported. |
0010 |
Support for two-stack programmers' model. |
All other values are reserved.
In ARMv8-A the only permitted value is 0000.
Security support. Defined values are:
Security | Meaning |
---|---|
0000 |
EL3, Monitor mode, and the SMC instruction not implemented. |
0001 |
EL3, Monitor mode, the SMC instruction, and all the features described by Sec_frac == 0001 implemented. |
0010 |
As for 0001, and adds the ability to set the NSACR.RFR bit. Not permitted in ARMv8 as the NSACR.RFR bit is RES0. |
All other values are reserved.
In ARMv8-A the permitted values are:
In an implementation that includes EL3, if EL3 cannot use AArch32 but EL1 can use AArch32 then this field has the value 0001.
If EL1 cannot use AArch32 then this field has the value 0000.
Support for the standard programmers' model for ARMv4 and later. Model must support User, FIQ, IRQ, Supervisor, Abort, Undefined, and System modes. Defined values are:
ProgMod | Meaning |
---|---|
0000 |
Not supported. |
0001 |
Supported. |
All other values are reserved.
In ARMv8-A the permitted values are 0001 and 0000.
If EL1 cannot use AArch32 then this field has the value 0000.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
ID_PFR1_EL1 | 11 | 000 | 0000 | 0001 | 001 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
18/04/2017 17:00
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