EDCIDSR, External Debug Context ID Sample Register

The EDCIDSR characteristics are:

Purpose

Contains the sampled value of the Context ID, captured on reading EDPCSR[31:0].

This register is part of the Debug registers functional group.

Usage constraints

This register is accessible as follows:

OffDLKOSLKDefault
ErrorErrorErrorRO

Configuration

EDCIDSR is in the Core power domain.

Fields in this register reset to architecturally UNKNOWN values. These apply only on a Cold reset. The register is not affected by a Warm reset and is not affected by an External debug reset.

Implemented only if the OPTIONAL PC Sample-based Profiling Extension is implemented but not with ARMv8.2-PCSample. If ARMv8.2-PCSample is implemented, this register is RES0 and the architecture defines the functionality in PMCID1SR and PMCID2SR.

Attributes

EDCIDSR is a 32-bit register.

Field descriptions

The EDCIDSR bit assignments are:

When ARMv8.2-PCSample is not implemented:

313029282726252423222120191817161514131211109876543210
CONTEXTIDR

CONTEXTIDR, bits [31:0]

Context ID. The value of CONTEXTIDR that is associated with the most recent EDPCSR sample.

Because the value written to EDCIDSR is an indirect read of CONTEXTIDR, therefore it is CONSTRAINED UNPREDICTABLE whether EDCIDSR is set to the original or new value if a read of EDPCSRlo samples:

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

When ARMv8.2-PCSample is implemented:

313029282726252423222120191817161514131211109876543210
00000000000000000000000000000000

Bits [31:0]

Reserved, RES0.

Accessing the EDCIDSR

EDCIDSR can be accessed through the external debug interface:

ComponentOffset
Debug 0x0A4



18/04/2017 17:00

Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Confidential.