DAIF, Interrupt Mask Bits

The DAIF characteristics are:

Purpose

Allows access to the interrupt mask bits.

This register is part of the Process state registers functional group.

Configuration

Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.

Attributes

DAIF is a 32-bit register.

Field descriptions

The DAIF bit assignments are:

313029282726252423222120191817161514131211109876543210
0000000000000000000000DAIF000000

Bits [31:10]

Reserved, RES0.

D, bit [9]

Process state D mask. The possible values of this bit are:

DMeaning
0

Watchpoint, Breakpoint, and Software Step exceptions targeted at the current Exception level are not masked.

1

Watchpoint, Breakpoint, and Software Step exceptions targeted at the current Exception level are masked.

When the target Exception level of the debug exception is higher than the current Exception level, the exception is not masked by this bit.

When this register has an architecturally-defined reset value, this field resets to 1.

A, bit [8]

SError interrupt mask bit. The possible values of this bit are:

AMeaning
0

Exception not masked.

1

Exception masked.

When this register has an architecturally-defined reset value, this field resets to 1.

I, bit [7]

IRQ mask bit. The possible values of this bit are:

IMeaning
0

Exception not masked.

1

Exception masked.

When this register has an architecturally-defined reset value, this field resets to 1.

F, bit [6]

FIQ mask bit. The possible values of this bit are:

FMeaning
0

Exception not masked.

1

Exception masked.

When this register has an architecturally-defined reset value, this field resets to 1.

Bits [5:0]

Reserved, RES0.

Accessing the DAIF

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
DAIF1101101000010001

This register can be modified using MSR (immediate) with the following syntax:

MSR <pstatefield>, <imm>

This syntax uses the following encoding in the System instruction encoding space:

<pstatefield> op0op1CRnop2
DAIFSet000110100110
DAIFClr000110100111

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0RWRW n/a RW
x01RWRWRWRW
x11RW n/a RWRW

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:




18/04/2017 17:00

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