ID_MMFR4_EL1, AArch32 Memory Model Feature Register 4

The ID_MMFR4_EL1 characteristics are:

Purpose

Provides information about the implemented memory model and memory management support in AArch32 state.

Must be interpreted with ID_MMFR0_EL1, ID_MMFR1_EL1, ID_MMFR2_EL1, and ID_MMFR3_EL1.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.

This register is part of the Identification registers functional group.

Configuration

AArch64 System register ID_MMFR4_EL1 is architecturally mapped to AArch32 System register ID_MMFR4.

In an implementation that supports only AArch64 state, this register is UNKNOWN.

Attributes

ID_MMFR4_EL1 is a 32-bit register.

Field descriptions

The ID_MMFR4_EL1 bit assignments are:

313029282726252423222120191817161514131211109876543210
00000000LSMHPDSCnPXNXAC2SpecSEI

Bits [31:24]

Reserved, RAZ.

LSM, bits [23:20]
In ARMv8.2:

Indicates support for LSMAOE and nTLSMD bits in HSCTLR and SCTLR. Defined values are:

LSMMeaning
0000

LSMAOE and nTLSMD bits not supported.

0001

LSMAOE and nTLSMD bits supported.

All other values are reserved.

In ARMv8.0 and ARMv8.1 the only permitted value is 0000.

From ARMv8.2, the permitted values are 0000 and 0001. This feature is identified by the name ARMv8.2-LSMAOC.


In ARMv8.1 and ARMv8.0:

Reserved, RAZ.

HPDS, bits [19:16]
In ARMv8.2:

Hierarchical permission disables bits in translation tables. Defined values are:

HPDSMeaning
0000

Disabling of hierarchical controls not supported.

0001

Supports disabling of hierarchical controls using the TTBCR2.HPD0, TTBCR2.HPD1, and HTCR.HPD bits.

0010

Supports disabling of hierarchical controls using the TTBCR2.HPD0, TTBCR2.HPD1, and HTCR.HPD bits, and hardware allocation of bits[62:59] of the last level page table descriptor for IMPLEMENTATION DEFINED use.

All other values are reserved.

In ARMv8.0 and ARMv8.1 the only permitted value is 0000.

From ARMv8.2, the permitted values are 0000, 0001 and 0010. This feature is identified by the name ARMv8.2-AA32HPD.

Note

The encoding 0000 implies that the encoding for TTBCR2 is unallocated.


In ARMv8.1 and ARMv8.0:

Reserved, RAZ.

CnP, bits [15:12]
In ARMv8.2:

Common not Private translations. Defined values are:

CnPMeaning
0000

Common not Private translations not supported.

0001

Common not Private translations supported.

All other values are reserved.

In ARMv8.0 and ARMv8.1 the only permitted value is 0000.

From ARMv8.2, the only permitted value is 0001. This feature is identified by the name ARMv8.2-TTCNP.


In ARMv8.1 and ARMv8.0:

Reserved, RAZ.

XNX, bits [11:8]
In ARMv8.2:

Support for execute never control distinction at stage 2 bit. Defined values are:

XNXMeaning
0000

Distinction between EL0 and EL1 execute permission at stage 2 not supported.

0001

Distinction between EL0 and EL1 execute permission at stage 2 supported.

All other values are reserved.

In ARMv8.0 and ARMv8.1 the only permitted value is 0000.

From ARMv8.2, the only permitted value is 0001. This feature is identified by the name ARMv8.2-TTS2UXN.


In ARMv8.1 and ARMv8.0:

Reserved, RAZ.

AC2, bits [7:4]

Indicates the extension of the ACTLR and HACTLR registers using ACTLR2 and HACTLR2. Defined values are:

AC2Meaning
0000

ACTLR2 and HACTLR2 are not implemented.

0001

ACTLR2 and HACTLR2 are implemented.

All other values are reserved.

In ARMv8.0 and ARMv8.1 the permitted values are 0000 and 0001.

From ARMv8.2, the only permitted value is 0001.

SpecSEI, bits [3:0]

Describes whether the PE can generate SError interrupt exceptions from speculative reads of memory, including speculative instruction fetches. The defined values of this field are:

SpecSEIMeaning
0000

The PE never generates an SError interrupt due to an external abort on a speculative read.

0001

The PE might generate an SError interrupt due to an external abort on a speculative read.

All other values are reserved.

When the RAS Extension is not implemented, this field is RAZ.

Accessing the ID_MMFR4_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
ID_MMFR4_EL11100000000010110

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RO n/a RO
x01 - RORORO
x11 - n/a RORO

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :




18/04/2017 17:00

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