ICV_IGRPEN1, Interrupt Controller Virtual Interrupt Group 1 Enable register

The ICV_IGRPEN1 characteristics are:

Purpose

Controls whether virtual Group 1 interrupts are enabled for the current Security state.

This register is part of:

Configuration

AArch32 System register ICV_IGRPEN1 is architecturally mapped to AArch64 System register ICV_IGRPEN1_EL1.

Attributes

ICV_IGRPEN1 is a 32-bit register.

Field descriptions

The ICV_IGRPEN1 bit assignments are:

313029282726252423222120191817161514131211109876543210
0000000000000000000000000000000Enable

Bits [31:1]

Reserved, RES0.

Enable, bit [0]

Enables virtual Group 1 interrupts.

EnableMeaning
0

Virtual Group 1 interrupts are disabled.

1

Virtual Group 1 interrupts are enabled.

When this register has an architecturally-defined reset value, this field resets to 0.

Accessing the ICV_IGRPEN1

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 0, <Rt>, c12, c12, 7000111110011111100
p15, 0, <Rt>, c12, c12, 7000111110011111100

When HCR.IMO is set to 0, execution of this encoding at Non-secure EL1 results in an access to ICC_IGRPEN1.

Accessibility

The register is accessible as follows:

<syntax> Control Accessibility
FMOIMOTGENSEL0EL1EL2EL3
p15, 0, <Rt>, c12, c12, 7xxx0 - ICC_IGRPEN1 n/a ICC_IGRPEN1
p15, 0, <Rt>, c12, c12, 7xx11 - n/a ICC_IGRPEN1 ICC_IGRPEN1
p15, 0, <Rt>, c12, c12, 7x001 - ICC_IGRPEN1 ICC_IGRPEN1 ICC_IGRPEN1
p15, 0, <Rt>, c12, c12, 7x101 - RW ICC_IGRPEN1 ICC_IGRPEN1

ICV_IGRPEN1 is only accessible at Non-secure EL1 when HCR.IMO is set to 1.

Note

When HCR.IMO is set to 0, at Non-secure EL1, the instruction encoding used to access ICV_IGRPEN1 results in an access to ICC_IGRPEN1.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :

When SCR_EL3.NS==1 :




18/04/2017 17:00

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