TLBI IPAS2LE1IS, TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Inner Shareable

The TLBI IPAS2LE1IS characteristics are:

Purpose

If EL2 is implemented, invalidate cached copies of translation table entries from TLBs that meet all the following requirements:

The invalidation is not required to apply to caching structures that combine stage 1 and stage 2 translation table entries.

The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this instructions.

For more information about the architectural requirements for this instruction see 'Invalidation of TLB entries from stage 2 translations' in the ARMv8 ARM.

This System instruction is part of:

Configuration

There are no configuration notes.

Attributes

TLBI IPAS2LE1IS is a 64-bit System instruction.

Field descriptions

The TLBI IPAS2LE1IS input value bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
000000000000000000000000IPA[51:48]IPA[47:12]
IPA[47:12]
313029282726252423222120191817161514131211109876543210

Bits [63:40]

Reserved, RES0.

IPA[51:48], bits [39:36]
In ARMv8.2:

Extension to IPA[47:12]. See IPA[47:12] for more details.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

IPA[47:12], bits [35:0]

Bits[47:12] of the intermediate physical address to match.

When ARMv8.2-LPA is implemented, and 52-bit addresses and a 64KB translation granule are in use, IPA[51:48] form the upper part of the address value. Otherwise, IPA[51:48] are RES0.

Executing the TLBI IPAS2LE1IS instruction

This instruction is executed using TLBI with the following syntax:

TLBI <tlbi_op>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<tlbi_op> op0op1CRnCRmop2
IPAS2LE1IS0110010000000101

Accessibility

The instruction is executable as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - - n/a WO
x01 - - WOWO
x11 - n/a WOWO

This table applies to all syntax that can be used to execute this instruction.

If EL2 is not implemented, or SCR_EL3.NS is 0, this instruction is a NOP.




18/04/2017 17:00

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