The GICH_EISR characteristics are:
Indicates which List registers have outstanding EOI maintenance interrupts.
This register is part of the GIC virtualised guest interface control registers functional group.
This register is accessible as follows:
Security disabled | Secure | Non-secure |
---|---|---|
RO | RO | RO |
This register is used only when System register access is not enabled. When System register access is enabled:
Bits corresponding to unimplemented List registers are RAZ.
RW fields in this register reset to architecturally UNKNOWN values.
This register is available when the GIC implementation supports interrupt virtualization.
GICH_EISR is a 32-bit register.
The GICH_EISR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Status<n>, bit [n], for n = 0 to 15 |
Reserved, RES0.
EOI maintenance interrupt status for List register <n>:
Status<n> | Meaning |
---|---|
0 |
GICH_LR<n> does not have an EOI maintenance interrupt. |
1 |
GICH_LR<n> has an EOI maintenance interrupt that has not been handled. |
For any GICH_LR<n> register, the corresponding status bit is set to 1 if all of the following are true:
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
GICH_EISR can be accessed through its memory-mapped interface:
Component | Offset |
---|---|
GIC Virtual interface control | 0x0020 |
18/04/2017 17:00
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