The GICD_NSACR<n> characteristics are:
Enables Secure software to permit Non-secure software on a particular PE to create and control Group 0 interrupts.
This register is part of the GIC Distributor registers functional group.
This register is accessible as follows:
Security disabled | Secure | Non-secure |
---|---|---|
RAZ/WI | RW | RAZ/WI |
When GICD_CTLR.DS==1, this register is RAZ/WI.
These registers are Secure, and are RAZ/WI to Non-secure accesses.
These registers are always used when affinity routing is not enabled. When affinity routing is enabled for the Secure state, GICD_NSACR0 is RES0 and GICR_NSACR provides equivalent functionality for SGIs.
These registers do not support PPIs, therefore GICD_NSACR1 is RAZ/WI.
Some or all RW fields of this register have defined reset values.
The concept of selective enabling of Non-secure access to Group 0 and Secure Group 1 interrupts applies to SGIs and SPIs.
GICD_NSACR0 is a Banked register used for SGIs. A copy is provided for every PE that has a CPU interface and that supports this feature.
GICD_NSACR<n> is a 32-bit register.
The GICD_NSACR<n> bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NS_access<x>, bits [2x+1:2x], for x = 0 to 15 |
Controls Non-secure access of the interrupt with ID 16n + x.
If the corresponding interrupt does not support configurable Non-secure access, the field is RAZ/WI.
Otherwise, the field is RW and determines the level of Non-secure control permitted if the interrupt is a Secure interrupt. If the interrupt is a Non-secure interrupt, this field is ignored.
The possible values of each 2-bit field are:
NS_access<x> | Meaning |
---|---|
00 |
No Non-secure access is permitted to fields associated with the corresponding interrupt. |
01 |
Non-secure read and write access is permitted to set-pending bits in GICD_ISPENDR<n> associated with the corresponding interrupt. A Non-secure write access to GICD_SETSPI_NSR is permitted to set the pending state of the corresponding interrupt. A Non-secure write access to GICD_SGIR is permitted to generate a Secure SGI for the corresponding interrupt. An implementation might also provide read access to clear-pending bits in GICD_ICPENDR<n> associated with the corresponding interrupt. |
10 |
As 01, but adds Non-secure read and write access permission to fields associated with the corresponding interrupt in the GICD_ICPENDR<n> registers. A Non-secure write access to GICD_CLRSPI_NSR is permitted to clear the pending state of the corresponding interrupt. Also adds Non-secure read access permission to fields associated with the corresponding interrupt in the GICD_ISACTIVER<n> and GICD_ICACTIVER<n> registers. |
11 |
For GICD_NSACR0 this encoding is reserved and treated as 10. For all other GICD_NSACR<n> registers this encoding is treated as 10, but adds Non-secure read and write access permission to GICD_ITARGETSR<n> and GICD_IROUTER<n> fields associated with the corresponding interrupt. |
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.
For interrupt ID m, when DIV and MOD are the integer division and modulo operations:
Because each field in this register comprises two bits, GICD_NSACR0 controls access rights to SGI registers, GICD_NSACR1 controls access to PPI registers (and is always RAZ/WI), and all other GICD_NSACR<n> registers control access to SPI registers.
For compatibility with GICv2, writes to GICD_NSACR0 for a particular PE must be coordinated within the Distributor and must update GICR_NSACR for the Redistributor associated with that PE.
GICD_NSACR<n> can be accessed through its memory-mapped interface:
Component | Offset |
---|---|
GIC Distributor | 0x0E00 + 4n |
18/04/2017 17:00
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