CNTFRQ_EL0, Counter-timer Frequency register

The CNTFRQ_EL0 characteristics are:

Purpose

This register is provided so that software can discover the frequency of the system counter. It must be programmed with this value as part of system initialization. The value of the register is not interpreted by hardware.

This register is part of the Generic Timer registers functional group.

Configuration

AArch64 System register CNTFRQ_EL0 is architecturally mapped to AArch32 System register CNTFRQ.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

CNTFRQ_EL0 is a 32-bit register.

Field descriptions

The CNTFRQ_EL0 bit assignments are:

313029282726252423222120191817161514131211109876543210
Clock frequency

Bits [31:0]

Clock frequency. Indicates the system counter clock frequency, in Hz.

Accessing the CNTFRQ_EL0

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
CNTFRQ_EL01101111100000000

Accessibility

The register is accessible as follows:

Configuration Control Accessibility
E2HTGENSEL0EL1EL2EL3
EL1 is the highest implemented Exception levelxxxRORW n/a n/a
EL2 is the highest implemented Exception levelx01RORORW n/a
EL2 is the highest implemented Exception levelx11RO n/a RW n/a
EL3 is the highest implemented Exception levelxx0RORORORW
EL3 is the highest implemented Exception levelx01RORORORW
EL3 is the highest implemented Exception levelx11RO n/a RORW

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==1 :




18/04/2017 17:00

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