The TPIDRPRW characteristics are:
Provides a location where software executing at EL1 or higher can store thread identifying information that is not visible to software executing at EL0, for OS management purposes.
The PE makes no use of this register.
This register is part of the Thread and process ID registers functional group.
AArch32 System register TPIDRPRW is architecturally mapped to AArch64 System register TPIDR_EL1[31:0] .
The PE never updates this register. This means the register is always UNKNOWN on reset.
TPIDRPRW is a 32-bit register.
The TPIDRPRW bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Thread ID |
Thread ID. Thread identifying information stored by software running at this Exception level.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c13, c0, 4 | 000 | 100 | 1101 | 1111 | 0000 |
The register is accessible as follows:
Configuration | Control | Accessibility | Instance | |||||
---|---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | ||
EL3 using AArch32 | x | x | 0 | - | n/a | n/a | RW | TPIDRPRW_s |
EL3 not implemented | x | x | 0 | - | RW | n/a | n/a | TPIDRPRW |
EL3 not implemented | x | 0 | 1 | - | RW | RW | n/a | TPIDRPRW |
EL3 not implemented | x | 1 | 1 | - | n/a | RW | n/a | TPIDRPRW |
EL3 using AArch64 | x | x | 0 | - | RW | n/a | n/a | TPIDRPRW |
EL3 using AArch64 | x | 0 | 1 | - | RW | RW | n/a | TPIDRPRW |
EL3 using AArch64 | x | 1 | 1 | - | n/a | RW | n/a | TPIDRPRW |
EL3 using AArch32 | x | 0 | 1 | - | RW | RW | RW | TPIDRPRW_ns |
EL3 using AArch32 | x | 1 | 1 | - | n/a | RW | RW | TPIDRPRW_ns |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HSTR_EL2.T13==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T13==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HSTR.T13==1, Non-secure accesses to this register from EL1 are trapped to Hyp mode.
18/04/2017 17:00
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