ICV_PMR_EL1, Interrupt Controller Virtual Interrupt Priority Mask Register

The ICV_PMR_EL1 characteristics are:

Purpose

Provides a virtual interrupt priority filter. Only virtual interrupts with a higher priority than the value in this register are signaled to the PE.

This register is part of:

Configuration

AArch64 System register ICV_PMR_EL1 is architecturally mapped to AArch32 System register ICV_PMR.

To allow software to ensure appropriate observability of actions initiated by GIC register accesses, the PE and CPU interface logic must ensure that writes to this register are self-synchronising. This ensures that no interrupts below the written PMR value will be taken after a write to this register is architecturally executed. See Observability of the effects of accesses to the GIC registers, for more information.

Attributes

ICV_PMR_EL1 is a 32-bit register.

Field descriptions

The ICV_PMR_EL1 bit assignments are:

313029282726252423222120191817161514131211109876543210
000000000000000000000000Priority

Bits [31:8]

Reserved, RES0.

Priority, bits [7:0]

The priority mask level for the virtual CPU interface. If the priority of a virtual interrupt is higher than the value indicated by this field, the interface signals the virtual interrupt to the PE.

The possible priority field values are as follows:

Implemented priority bits Possible priority field values Number of priority levels
[7:0] 0x00-0xFF (0-255), all values 256
[7:1] 0x00-0xFE (0-254), even values only 128
[7:2] 0x00-0xFC (0-252), in steps of 4 64
[7:3] 0x00-0xF8 (0-248), in steps of 8 32
[7:4] 0x00-0xF0 (0-240), in steps of 16 16

Unimplemented priority bits are RAZ/WI.

When this register has an architecturally-defined reset value, this field resets to 0.

Accessing the ICV_PMR_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op1CRnCRmop2
ICC_PMR_EL100001000110000

When HCR_EL2.{FMO, IMO} == {0, 0}, execution of this encoding at Non-secure EL1 results in an access to ICC_PMR_EL1.

Accessibility

The register is accessible as follows:

Control Accessibility
FMOIMOTGENSEL0EL1EL2EL3
xxx0 - ICC_PMR_EL1 n/a ICC_PMR_EL1
xx11 - n/a ICC_PMR_EL1 ICC_PMR_EL1
x101 - RW ICC_PMR_EL1 ICC_PMR_EL1
1x01 - RW ICC_PMR_EL1 ICC_PMR_EL1
0001 - ICC_PMR_EL1 ICC_PMR_EL1 ICC_PMR_EL1

This table applies to all instructions that can access this register.

ICV_PMR_EL1 is only accessible at Non-secure EL1 when HCR_EL2.{FMO, IMO} != {0, 0}.

Note

When HCR_EL2.{FMO, IMO} == {0, 0}, at Non-secure EL1, the instruction encoding used to access ICV_PMR_EL1 results in an access to ICC_PMR_EL1.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When SCR_EL3.NS==1 :




18/04/2017 17:00

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