GITS_CBASER, ITS Command Queue Descriptor

The GITS_CBASER characteristics are:

Purpose

Specifies the base address and size of the ITS command queue.

This register is part of the GIC ITS registers functional group.

Usage constraints

This register is accessible as follows:

Security disabledSecureNon-secure
RWRWRW

When GITS_CTLR.Enabled == 1 or GITS_CTLR.Quiescent == 0, writing this register is UNPREDICTABLE.

Configuration

Some or all RW fields of this register have defined reset values.

Bits [63:32] and bits [31:0] are accessible separately.

Attributes

GITS_CBASER is a 64-bit register.

Field descriptions

The GITS_CBASER bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
Valid0InnerCache000OuterCache0Physical_Address
Physical_AddressShareability00Size
313029282726252423222120191817161514131211109876543210

Valid, bit [63]

Indicates whether software has allocated memory for the command queue:

ValidMeaning
0

No memory is allocated for the command queue.

1

Memory is allocated to the command queue.

When this register has an architecturally-defined reset value, this field resets to 0.

Bit [62]

Reserved, RES0.

InnerCache, bits [61:59]

Indicates the Inner Cacheability attributes of accesses to the command queue. The possible values of this field are:

InnerCacheMeaning
000

Device-nGnRnE.

001

Normal Inner Non-cacheable.

010

Normal Inner Cacheable Read-allocate, Write-through.

011

Normal Inner Cacheable Read-allocate, Write-back.

100

Normal Inner Cacheable Write-allocate, Write-through.

101

Normal Inner Cacheable Write-allocate, Write-back.

110

Normal Inner Cacheable Read-allocate, Write-allocate, Write-through.

111

Normal Inner Cacheable Read-allocate, Write-allocate, Write-back.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bits [58:56]

Reserved, RES0.

OuterCache, bits [55:53]

Indicates the Outer Cacheability attributes of accesses to the command queue. The possible values of this field are:

OuterCacheMeaning
000

Memory type defined in InnerCache field. For Normal memory, Outer Cacheability is the same as Inner Cacheability.

001

Normal Outer Non-cacheable.

010

Normal Outer Cacheable Read-allocate, Write-through.

011

Normal Outer Cacheable Read-allocate, Write-back.

100

Normal Outer Cacheable Write-allocate, Write-through.

101

Normal Outer Cacheable Write-allocate, Write-back.

110

Normal Outer Cacheable Read-allocate, Write-allocate, Write-through.

111

Normal Outer Cacheable Read-allocate, Write-allocate, Write-back.

It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.

When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to a value that is architecturally UNKNOWN.

Bit [52]

Reserved, RES0.

Physical_Address, bits [51:12]

Bits [51:12] of the base physical address of the command queue. Bits [11:0] of the base address are 0.

In implementations supporting fewer than 52 bits of physical address, unimplemented upper bits are RES0.

If bits [15:12] are not all zeros, behavior is a CONSTRAINED UNPREDICTABLE choice:

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Shareability, bits [11:10]

Indicates the Shareability attributes of accesses to the command queue. The possible values of this field are:

ShareabilityMeaning
00

Non-shareable.

01

Inner Shareable.

10

Outer Shareable.

11

Reserved. Treated as 00.

It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.

When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to a value that is architecturally UNKNOWN.

Bits [9:8]

Reserved, RES0.

Size, bits [7:0]

The number of 4KB pages of physical memory allocated to the command queue, minus one.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

The command queue is a circular buffer and wraps at Physical Address [47:0] + (4096 * (Size + 1)).

Note

When this register is successfully written, the value of GITS_CREADR is set to zero.

Accessing the GITS_CBASER

GITS_CBASER can be accessed through its memory-mapped interface:

ComponentOffset
GIC ITS control0x0080-0x0084



18/04/2017 17:00

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