The ID_PFR0_EL1 characteristics are:
Gives top-level information about the instruction sets supported by the PE in AArch32 state.
Must be interpreted with ID_PFR1_EL1.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.
This register is part of the Identification registers functional group.
AArch64 System register ID_PFR0_EL1 is architecturally mapped to AArch32 System register ID_PFR0.
In an implementation that supports only AArch64 state, this register is UNKNOWN.
ID_PFR0_EL1 is a 32-bit register.
The ID_PFR0_EL1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAS | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | State3 | State2 | State1 | State0 |
RAS Extension version. The defined values of this field are:
RAS | Meaning |
---|---|
0000 |
No RAS Extension. |
0001 |
Version 1 of the RAS Extension present. |
All other values are reserved.
Reserved, RES0.
T32EE instruction set support. Defined values are:
State3 | Meaning |
---|---|
0000 |
Not implemented. |
0001 |
T32EE instruction set implemented. |
All other values are reserved.
In ARMv8-A the only permitted value is 0000.
Jazelle extension support. Defined values are:
State2 | Meaning |
---|---|
0000 |
Not implemented. |
0001 |
Jazelle extension implemented, without clearing of JOSCR.CV on exception entry. |
0010 |
Jazelle extension implemented, with clearing of JOSCR.CV on exception entry. |
All other values are reserved.
In ARMv8-A the only permitted value is 0001.
T32 instruction set support. Defined values are:
State1 | Meaning |
---|---|
0000 |
T32 instruction set not implemented. |
0001 |
T32 encodings before the introduction of Thumb-2 technology implemented:
|
0011 |
T32 encodings after the introduction of Thumb-2 technology implemented, for all 16-bit and 32-bit T32 basic instructions. |
All other values are reserved.
In ARMv8-A the only permitted value is 0011.
A32 instruction set support. Defined values are:
State0 | Meaning |
---|---|
0000 |
A32 instruction set not implemented. |
0001 |
A32 instruction set implemented. |
All other values are reserved.
In ARMv8-A the only permitted value is 0001.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
ID_PFR0_EL1 | 11 | 000 | 0000 | 0001 | 000 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
18/04/2017 17:00
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