DACR, Domain Access Control Register

The DACR characteristics are:

Purpose

Defines the access permission for each of the sixteen memory domains.

This register is part of the Virtual memory control registers functional group.

Configuration

AArch32 System register DACR is architecturally mapped to AArch64 System register DACR32_EL2.

When EL3 is using AArch32, write access to DACR(S) is disabled when the CP15SDISABLE signal is asserted HIGH.

This register has no function when TTBCR.EAE is set to 1, to select the Long-descriptor translation table format.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

DACR is a 32-bit register.

Field descriptions

The DACR bit assignments are:

313029282726252423222120191817161514131211109876543210
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

D<n>, bits [2n+1:2n], for n = 0 to 15

Domain n access permission, where n = 0 to 15. Permitted values are:

D<n>Meaning
00

No access. Any access to the domain generates a Domain fault.

01

Client. Accesses are checked against the permission bits in the translation tables.

11

Manager. Accesses are not checked against the permission bits in the translation tables.

The value 10 is reserved.

Accessing the DACR

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 0, <Rt>, c3, c0, 0000000001111110000

Accessibility

The register is accessible as follows:

Configuration Control Accessibility Instance
E2HTGENSEL0EL1EL2EL3
EL3 not implemented xx0 - RW n/a n/a DACR
EL3 not implemented x01 - RWRW n/a DACR
EL3 not implemented x11 - n/a RW n/a DACR
EL3 using AArch64xx0 - RW n/a n/a DACR
EL3 using AArch64x01 - RWRW n/a DACR
EL3 using AArch64x11 - n/a RW n/a DACR
EL3 using AArch32xx0 - n/a n/a RWDACR_s
EL3 using AArch32x01 - RWRWRWDACR_ns
EL3 using AArch32x11 - n/a RWRWDACR_ns

This table applies to all instructions that can access this register.

When EL3 is using AArch32, write access to DACR_s is UNDEFINED when the CP15SDISABLE signal is asserted HIGH.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :




18/04/2017 17:00

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