The DLR characteristics are:
In Debug state, holds the address to restart from.
This register is part of:
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register DLR is architecturally mapped to AArch64 System register DLR_EL0[31:0] .
DLR is a 32-bit register.
The DLR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Restart address |
Restart address.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 3, <Rt>, c4, c5, 1 | 011 | 001 | 0100 | 1111 | 0101 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | RW | RW | n/a | RW |
x | 0 | 1 | RW | RW | RW | RW |
x | 1 | 1 | RW | n/a | RW | RW |
This table applies to all instructions that can access this register.
Access to this register is from Debug state only. During normal execution this register is unallocated.
18/04/2017 17:00
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