The PMITCTRL characteristics are:
Enables the Performance Monitors to switch from default mode into integration mode, where test software can control directly the inputs and outputs of the PE, for integration testing or topology detection.
This register is part of the Performance Monitors registers functional group.
This register is accessible as follows:
Off | DLK | OSLK | Default |
---|---|---|---|
IMP DEF | IMP DEF | IMP DEF | RW |
It is IMPLEMENTATION DEFINED whether PMITCTRL is implemented in the Core power domain or in the Debug power domain. Some or all RW fields of this register have defined reset values, and:
Implementation of this register is OPTIONAL.
PMITCTRL is a 32-bit register.
The PMITCTRL bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | IME |
Reserved, RES0.
Integration mode enable. When IME == 1, the device reverts to an integration mode to enable integration testing or topology detection. The integration mode behavior is IMPLEMENTATION DEFINED.
IME | Meaning |
---|---|
0 |
Normal operation. |
1 |
Integration mode enabled. |
When this register has an architecturally-defined reset value, this field resets to 0.
PMITCTRL can be accessed through the external debug interface:
Component | Offset |
---|---|
PMU | 0xF00 |
18/04/2017 17:00
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