ICC_BPR1, Interrupt Controller Binary Point Register 1

The ICC_BPR1 characteristics are:

Purpose

Defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field. The group priority field determines Group 1 interrupt preemption.

This register is part of:

Configuration

AArch32 System register ICC_BPR1 (S) is architecturally mapped to AArch64 System register ICC_BPR1_EL1 (S) .

AArch32 System register ICC_BPR1 (NS) is architecturally mapped to AArch64 System register ICC_BPR1_EL1 (NS) .

In GIC implementations supporting two Security states, this register is Banked.

Attributes

ICC_BPR1 is a 32-bit register.

Field descriptions

The ICC_BPR1 bit assignments are:

313029282726252423222120191817161514131211109876543210
00000000000000000000000000000BinaryPoint

Bits [31:3]

Reserved, RES0.

BinaryPoint, bits [2:0]

If the GIC is configured to use separate binary point fields for Group 0 and Group 1 interrupts, the value of this field controls how the 8-bit interrupt priority field is split into a group priority field, that determines interrupt preemption, and a subpriority field. For more information about priorities, see Priority grouping.

Writing 0 to this field will set this field to its reset value, which is IMPLEMENTATION DEFINED and non-zero.

If EL3 is implemented and ICC_MCTLR.CBPR_EL1S is 1:

If EL3 is implemented and ICC_MCTLR.CBPR_EL1NS is 1, Non-secure accesses to this register at EL1 or EL2 behave as follows, depending on the values of HCR.IMO and SCR.IRQ:

HCR.IMO SCR.IRQ Behavior
0 0 Non-secure EL1 and EL2 reads return ICC_BPR0 + 1 saturated to 0b111. Non-secure EL1 and EL2 writes are ignored.
0 1 Non-secure EL1 and EL2 accesses trap to EL3.
1 0 Non-secure EL1 accesses affect virtual interrupts. Non-secure EL2 reads return ICC_BPR0 + 1 saturated to 0b111. Non-secure EL2 writes are ignored.
1 1 Non-secure EL1 accesses affect virtual interrupts. Non-secure EL2 accesses trap to EL3.

If EL3 is not implemented and ICC_CTLR.CBPR is 1, Non-secure accesses to this register at EL1 or EL2 behave as follows, depending on the values of HCR.IMO:

HCR.IMO Behavior
0 Non-secure EL1 and EL2 reads return ICC_BPR0 + 1 saturated to 0b111. Non-secure EL1 and EL2 writes are ignored.
1 Non-secure EL1 accesses affect virtual interrupts. Non-secure EL2 reads return ICC_BPR0 + 1 saturated to 0b111. Non-secure EL2 writes are ignored.

Accessing the ICC_BPR1

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 0, <Rt>, c12, c12, 3000011110011111100

When HCR.IMO is set to 1, execution of this encoding at Non-secure EL1 results in an access to ICV_BPR1.

Accessibility

The register is accessible as follows:

Configuration Control Accessibility Instance
FMOIMOTGENSEL0EL1EL2EL3
EL3 not implemented xxx0 - RW n/a n/a ICC_BPR1
EL3 not implemented xx11 - n/a RW n/a ICC_BPR1
EL3 not implemented x001 - RWRW n/a ICC_BPR1
EL3 not implemented x101 - ICV_BPR1 RW n/a ICC_BPR1
EL3 using AArch64xx11 - n/a RW n/a ICC_BPR1_ns
EL3 using AArch64x001 - RWRW n/a ICC_BPR1_ns
EL3 using AArch64x101 - ICV_BPR1 RW n/a ICC_BPR1_ns
EL3 using AArch32xx11 - n/a RWRWICC_BPR1_ns
EL3 using AArch32x001 - RWRWRWICC_BPR1_ns
EL3 using AArch32x101 - ICV_BPR1 RWRWICC_BPR1_ns
EL3 using AArch64xxx0 - RW n/a n/a ICC_BPR1_s
EL3 using AArch32xxx0 - - - RWICC_BPR1_s

This table applies to all instructions that can access this register.

ICC_BPR1 is only accessible at Non-secure EL1 when HCR.IMO is set to 0.

Note

When HCR.IMO is set to 1, at Non-secure EL1, the instruction encoding used to access ICC_BPR1 results in an access to ICV_BPR1.

When the PE resets into an Exception level that is using AArch32, the reset value is equal to:

Where the minimum value of ICC_BPR0 is IMPLEMENTATION DEFINED.

If EL3 is not implemented:

An attempt to program the binary point field to a value less than the reset value sets the field to the reset value.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :

When SCR_EL3.NS==1 :

When EL3 is implemented and is using AArch32 :

When EL3 is implemented and is using AArch32 and SCR_EL3.NS==1 :

When EL3 is implemented and is using AArch64 and SCR_EL3.NS==0 :

When EL3 is implemented and is using AArch64 :

When EL3 is implemented and is using AArch64 and SCR_EL3.NS==1 :




18/04/2017 17:00

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