ICC_IGRPEN0, Interrupt Controller Interrupt Group 0 Enable register

The ICC_IGRPEN0 characteristics are:

Purpose

Controls whether Group 0 interrupts are enabled or not.

This register is part of:

Configuration

There is one instance of this register that is used in both Secure and Non-secure states.

AArch32 System register ICC_IGRPEN0 is architecturally mapped to AArch64 System register ICC_IGRPEN0_EL1.

Attributes

ICC_IGRPEN0 is a 32-bit register.

Field descriptions

The ICC_IGRPEN0 bit assignments are:

313029282726252423222120191817161514131211109876543210
0000000000000000000000000000000Enable

Bits [31:1]

Reserved, RES0.

Enable, bit [0]

Enables Group 0 interrupts.

EnableMeaning
0

Group 0 interrupts are disabled.

1

Group 0 interrupts are enabled.

Virtual accesses to this register update ICH_VMCR.VENG0.

When this register has an architecturally-defined reset value, this field resets to 0.

Accessing the ICC_IGRPEN0

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 0, <Rt>, c12, c12, 6000110110011111100
p15, 0, <Rt>, c12, c12, 6000110110011111100

When HCR.FMO is set to 1, execution of this encoding at Non-secure EL1 results in an access to ICV_IGRPEN0.

Accessibility

The register is accessible as follows:

<syntax> Control Accessibility
FMOIMOTGENSEL0EL1EL2EL3
p15, 0, <Rt>, c12, c12, 6xxx0 - RW n/a RW
p15, 0, <Rt>, c12, c12, 6xx11 - n/a RWRW
p15, 0, <Rt>, c12, c12, 60x01 - RWRWRW
p15, 0, <Rt>, c12, c12, 61x01 - ICV_IGRPEN0 RWRW

ICC_IGRPEN0 is only accessible at Non-secure EL1 when HCR.FMO is set to 0.

Note

When HCR.FMO is set to 1, at Non-secure EL1, the instruction encoding used to access ICC_IGRPEN0 results in an access to ICV_IGRPEN0.

The lowest Exception level at which this register can be accessed is governed by the Exception level to which FIQ is routed. This routing depends on SCR.FIQ, SCR.NS and HCR.FMO.

If an interrupt is pending within the CPU interface when Enable becomes 0, the interrupt must be released to allow the Distributor to forward the interrupt to a different PE.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :

When SCR_EL3.NS==1 :

When EL3 is implemented and is using AArch32 :

When EL3 is implemented and is using AArch32 and SCR_EL3.NS==1 :

When EL3 is implemented and is using AArch64 and SCR_EL3.NS==0 :

When EL3 is implemented and is using AArch64 :

When EL3 is implemented and is using AArch64 and SCR_EL3.NS==1 :




18/04/2017 17:00

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