ICC_CTLR, Interrupt Controller Control Register

The ICC_CTLR characteristics are:

Purpose

Controls aspects of the behavior of the GIC CPU interface and provides information about the features implemented.

This register is part of:

Configuration

AArch32 System register ICC_CTLR (S) is architecturally mapped to AArch64 System register ICC_CTLR_EL1 (S) .

AArch32 System register ICC_CTLR (NS) is architecturally mapped to AArch64 System register ICC_CTLR_EL1 (NS) .

Attributes

ICC_CTLR is a 32-bit register.

Field descriptions

The ICC_CTLR bit assignments are:

313029282726252423222120191817161514131211109876543210
0000000000000000A3VSEISIDbitsPRIbits0PMHE0000EOImodeCBPR

Bits [31:16]

Reserved, RES0.

A3V, bit [15]

Affinity 3 Valid. Read-only and writes are ignored. Possible values are:

A3VMeaning
0

The CPU interface logic only supports zero values of Affinity 3 in SGI generation System registers.

1

The CPU interface logic supports non-zero values of Affinity 3 in SGI generation System registers.

If EL3 is implemented and using AArch32, this bit is an alias of ICC_MCTLR.A3V.

If EL3 is implemented and using AArch64, this bit is an alias of ICC_CTLR_EL3.A3V.

SEIS, bit [14]

SEI Support. Read-only and writes are ignored. Indicates whether the CPU interface supports local generation of SEIs:

SEISMeaning
0

The CPU interface logic does not support local generation of SEIs.

1

The CPU interface logic supports local generation of SEIs.

If EL3 is implemented and using AArch32, this bit is an alias of ICC_MCTLR.SEIS.

If EL3 is implemented and using AArch64, this bit is an alias of ICC_CTLR_EL3.SEIS.

IDbits, bits [13:11]

Identifier bits. Read-only and writes are ignored. The number of physical interrupt identifier bits supported:

IDbitsMeaning
000

16 bits.

001

24 bits.

All other values are reserved.

If EL3 is implemented and using AArch32, this field is an alias of ICC_MCTLR.IDbits.

If EL3 is implemented and using AArch64, this field is an alias of ICC_CTLR_EL3.IDbits.

PRIbits, bits [10:8]

Priority bits. Read-only and writes are ignored. The number of priority bits implemented, minus one.

An implementation that supports two Security states must implement at least 32 levels of physical priority (5 priority bits).

An implementation that supports only a single Security state must implement at least 16 levels of physical priority (4 priority bits).

Note

This field always returns the number of priority bits implemented, regardless of the Security state of the access or the value of GICD_CTLR.DS.

The division between group priority and subpriority is defined in the binary point registers ICC_BPR0 and ICC_BPR1.

If EL3 is implemented and using AArch32, physical accesses return the value from ICC_MCTLR.PRIbits.

If EL3 is implemented and using AArch64, physical accesses return the value from ICC_CTLR_EL3.PRIbits.

If EL3 is not implemented, physical accesses return the value from this field.

Bit [7]

Reserved, RES0.

PMHE, bit [6]

Priority Mask Hint Enable. Controls whether the priority mask register is used as a hint for interrupt distribution:

PMHEMeaning
0

Disables use of ICC_PMR as a hint for interrupt distribution.

1

Enables use of ICC_PMR as a hint for interrupt distribution.

If EL3 is implemented:

If EL3 is not implemented, it is IMPLEMENTATION DEFINED whether this bit is read-only or read-write:

Bits [5:2]

Reserved, RES0.

EOImode, bit [1]

EOI mode for the current Security state. Controls whether a write to an End of Interrupt register also deactivates the interrupt:

EOImodeMeaning
0

ICC_EOIR0 and ICC_EOIR1 provide both priority drop and interrupt deactivation functionality. Accesses to ICC_DIR are UNPREDICTABLE.

1

ICC_EOIR0 and ICC_EOIR1 provide priority drop functionality only. ICC_DIR provides interrupt deactivation functionality.

If EL3 is implemented:

If EL3 is not implemented, it is IMPLEMENTATION DEFINED whether this bit is read-only or read-write:

When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to a value that is architecturally UNKNOWN.

CBPR, bit [0]

Common Binary Point Register. Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 interrupts:

CBPRMeaning
0

ICC_BPR0 determines the preemption group for Group 0 interrupts only.

ICC_BPR1 determines the preemption group for Group 1 interrupts.

1

ICC_BPR0 determines the preemption group for both Group 0 and Group 1 interrupts.

If EL3 is implemented:

If EL3 is not implemented, it is IMPLEMENTATION DEFINED whether this bit is read-only or read-write:

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Accessing the ICC_CTLR

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 0, <Rt>, c12, c12, 4000100110011111100

When HCR.{FMO, IMO} != {0, 0}, execution of this encoding at Non-secure EL1 results in an access to ICV_CTLR.

Accessibility

The register is accessible as follows:

Configuration Control Accessibility Instance
FMOIMOTGENSEL0EL1EL2EL3
EL3 not implemented xxx0 - RW n/a n/a ICC_CTLR
EL3 not implemented xx11 - n/a RW n/a ICC_CTLR
EL3 not implemented x101 - ICV_CTLR RW n/a ICC_CTLR
EL3 not implemented 1x01 - ICV_CTLR RW n/a ICC_CTLR
EL3 not implemented 0001 - RWRW n/a ICC_CTLR
EL3 using AArch64xxx0 - RW n/a n/a ICC_CTLR_s
EL3 using AArch32xxx0 - - - RWICC_CTLR_s
EL3 using AArch64xx11 - n/a RW n/a ICC_CTLR_ns
EL3 using AArch64x101 - ICV_CTLR RW n/a ICC_CTLR_ns
EL3 using AArch641x01 - ICV_CTLR RW n/a ICC_CTLR_ns
EL3 using AArch640001 - RWRW n/a ICC_CTLR_ns
EL3 using AArch32xx11 - n/a RWRWICC_CTLR_ns
EL3 using AArch32x101 - ICV_CTLR RWRWICC_CTLR_ns
EL3 using AArch321x01 - ICV_CTLR RWRWICC_CTLR_ns
EL3 using AArch320001 - RWRWRWICC_CTLR_ns

This table applies to all instructions that can access this register.

ICC_CTLR is only accessible at Non-secure EL1 when HCR.{FMO, IMO} == {0, 0}.

Note

When HCR.{FMO, IMO} != {0, 0}, at Non-secure EL1, the instruction encoding used to access ICC_CTLR results in an access to ICV_CTLR.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :

When SCR_EL3.NS==1 :

When EL3 is implemented and is using AArch32 :

When EL3 is implemented and is using AArch32 and SCR_EL3.NS==1 :

When EL3 is implemented and is using AArch64 and SCR_EL3.NS==0 :

When EL3 is implemented and is using AArch64 :

When EL3 is implemented and is using AArch64 and SCR_EL3.NS==1 :




18/04/2017 17:00

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