ISR_EL1, Interrupt Status Register

The ISR_EL1 characteristics are:

Purpose

Shows whether any IRQ, FIQ, or SError interrupt is pending. In an implementation that includes EL2, when the register is accessed from Non-secure EL1, a pending interrupt or external abort might be physical or virtual, and the architecture does not provide any mechanism that software executing at Non-secure EL1 can use to determine whether a pending interrupt or external abort is physical or virtual. For all other accesses, any indicated interrupt or external abort must be physical.

This register is part of the Exception and fault handling registers functional group.

Configuration

AArch64 System register ISR_EL1 is architecturally mapped to AArch32 System register ISR.

Attributes

ISR_EL1 is a 32-bit register.

Field descriptions

The ISR_EL1 bit assignments are:

313029282726252423222120191817161514131211109876543210
00000000000000000000000AIF000000

Bits [31:9]

Reserved, RES0.

A, bit [8]

SError interrupt pending bit:

AMeaning
0

No pending SError.

1

An SError interrupt is pending.

I, bit [7]

IRQ pending bit. Indicates whether an IRQ interrupt is pending:

IMeaning
0

No pending IRQ.

1

An IRQ interrupt is pending.

F, bit [6]

FIQ pending bit. Indicates whether an FIQ interrupt is pending.

FMeaning
0

No pending FIQ.

1

An FIQ interrupt is pending.

Bits [5:0]

Reserved, RES0.

Accessing the ISR_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
ISR_EL11100011000001000

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RO n/a RO
x01 - RORORO
x11 - n/a RORO

This table applies to all instructions that can access this register.




18/04/2017 17:00

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