The CNTFRQ characteristics are:
This register is provided so that software can discover the frequency of the system counter. It must be programmed with this value as part of system initialization. The value of the register is not interpreted by hardware.
This register is part of the Generic Timer registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register CNTFRQ is architecturally mapped to AArch64 System register CNTFRQ_EL0.
RW fields in this register reset to architecturally UNKNOWN values.
CNTFRQ is a 32-bit register.
The CNTFRQ bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Clock frequency |
Clock frequency. Indicates the system counter clock frequency, in Hz.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c14, c0, 0 | 000 | 000 | 1110 | 1111 | 0000 |
The register is accessible as follows:
Configuration | Control | Accessibility | |||||
---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | |
EL1 is the highest implemented Exception level | x | x | x | RO | RW | n/a | n/a |
EL2 is the highest implemented Exception level | x | 0 | 1 | RO | RO | RW | n/a |
EL2 is the highest implemented Exception level | x | 1 | 1 | RO | n/a | RW | n/a |
EL3 is the highest implemented Exception level | x | x | 0 | RO | RO | RO | RW |
EL3 is the highest implemented Exception level | x | 0 | 1 | RO | RO | RO | RW |
EL3 is the highest implemented Exception level | x | 1 | 1 | RO | n/a | RO | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When HCR_EL2.E2H==0 :
If CNTKCTL_EL1.EL0PCTEN==0, and CNTKCTL_EL1.EL0VCTEN==0, read accesses to this register from EL0 are trapped to EL1.
If CNTKCTL.PL0PCTEN==0, and CNTKCTL.PL0VCTEN==0, read accesses to this register from EL0 are trapped to Undefined mode.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If CNTKCTL_EL1.EL0PCTEN==0, and CNTKCTL_EL1.EL0VCTEN==0, Non-secure read accesses to this register from EL0 are trapped to EL1.
If CNTKCTL.PL0PCTEN==0, and CNTKCTL.PL0VCTEN==0, Non-secure read accesses to this register from EL0 are trapped to Undefined mode.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==1 :
If CNTHCTL_EL2.EL0PCTEN==0, and CNTHCTL_EL2.EL0VCTEN==0, Non-secure read accesses to this register from EL0 are trapped to EL2.
18/04/2017 17:00
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