PMCEID0_EL0, Performance Monitors Common Event Identification register 0

The PMCEID0_EL0 characteristics are:

Purpose

Defines which common architectural and common microarchitectural feature events in the ranges 0x0000 to 0x001F and 0x4000 to 0x401F are implemented. If a particular bit is set to 1, then the event for that bit is implemented.

This register is part of the Performance Monitors registers functional group.

Configuration

AArch64 System register PMCEID0_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMCEID0.

AArch64 System register PMCEID0_EL0 bits [63:32] are architecturally mapped to AArch32 System register PMCEID2.

AArch64 System register PMCEID0_EL0 bits [31:0] are architecturally mapped to External register PMCEID0.

AArch64 System register PMCEID0_EL0 bits [63:32] are architecturally mapped to External register PMCEID2.

Attributes

PMCEID0_EL0 is a 64-bit register.

Field descriptions

The PMCEID0_EL0 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
ID[16415:16384]
ID[31:0]
313029282726252423222120191817161514131211109876543210

ID[16415:16384], bits [63:32]
In ARMv8.2 and ARMv8.1:

PMCEID0_EL0[63:32] maps to common events 0x4000 to 0x401F. For a list of event numbers and descriptions, see 'Event numbers and mnemonics' in the ARM ARM, section D5.10.

For each bit:

ID[16415:16384]Meaning
0

The common event is not implemented.

1

The common event is implemented.

Bits that map to reserved event numbers are reserved to identify events that might be defined in future revisions to the architecture.

Events that do not require additional features in the PMU can be defined retrospectively, meaning that they can be implemented as part of a PMUv3 implementation.


In ARMv8.0:

Reserved, RES0.

ID[31:0], bits [31:0]

PMCEID0_EL0[31:0] maps to common events 0x0000 to 0x001F. For a list of event numbers and descriptions, see 'Event numbers and mnemonics' in the ARM ARM, section D5.10.

For each bit:

ID[31:0]Meaning
0

The common event is not implemented.

1

The common event is implemented.

Bits that map to reserved event numbers are reserved to identify events that might be defined in future revisions to the architecture.

Events that do not require additional features in the PMU can be defined retrospectively, meaning that they can be implemented as part of a PMUv3 implementation.

Accessing the PMCEID0_EL0

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
PMCEID0_EL01101110011100110

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0RORO n/a RO
x01RORORORO
x11RO n/a RORO

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :

When EL3 is implemented and is using AArch64 :




18/04/2017 17:00

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