The TTBCR2 characteristics are:
The second control register for stage 1 of the PL1&0 translation regime.
If ARMv8.2-AA32HPD is not implemented and ARMv8.2-TTPBHA is not implemented then this register is not implemented and its encoding is unallocated. Otherwise:
This register is part of the Virtual memory control registers functional group.
AArch32 System register TTBCR2 is architecturally mapped to AArch64 System register TCR_EL1[63:32] .
When EL3 is using AArch32, write access to TTBCR2(S) is disabled when the CP15SDISABLE signal is asserted HIGH.
RW fields in this register reset to architecturally UNKNOWN values.
This register is introduced in ARMv8.2.
TTBCR2 is a 32-bit register.
The TTBCR2 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | HWU162 | HWU161 | HWU160 | HWU159 | HWU062 | HWU061 | HWU060 | HWU059 | HPD1 | HPD0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Reserved, RES0.
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[62] of the stage 1 translation table block or level 3 entry for pages pointed to by TTBR1 if TTBCR2.HPD1==1 and TTBCR.T2E==1.
Defined values are:
HWU162 | Meaning |
---|---|
0 |
The stage 1 translation table entry block or level 3 bit cannot be interpreted by hardware for an IMPLEMENTATION DEFINED purpose. |
1 |
The stage 1 translation table entry block or level 3 bit can be interpreted by hardware for an IMPLEMENTATION DEFINED purpose if the TTBCR2.HPD1 value is 1. |
This bit is RES0 if ARMv8.2-TTPBHA is not implemented.
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[61] of the stage 1 translation table block or level 3 entry for pages pointed to by TTBR1 if TTBCR2.HPD1==1 and TTBCR.T2E==1.
Defined values are:
HWU161 | Meaning |
---|---|
0 |
The stage 1 translation table entry block or level 3 bit cannot be interpreted by hardware for an IMPLEMENTATION DEFINED purpose. |
1 |
The stage 1 translation table entry block or level 3 bit can be interpreted by hardware for an IMPLEMENTATION DEFINED purpose if the TTBCR2.HPD1 value is 1. |
This bit is RES0 if ARMv8.2-TTPBHA is not implemented.
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[60] of the stage 1 translation table block or level 3 entry for pages pointed to by TTBR1 if TTBCR2.HPD1==1 and TTBCR.T2E==1.
Defined values are:
HWU160 | Meaning |
---|---|
0 |
The stage 1 translation table entry block or level 3 bit cannot be interpreted by hardware for an IMPLEMENTATION DEFINED purpose. |
1 |
The stage 1 translation table entry block or level 3 bit can be interpreted by hardware for an IMPLEMENTATION DEFINED purpose if the TTBCR2.HPD1 value is 1. |
This bit is RES0 if ARMv8.2-TTPBHA is not implemented.
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[59] of the stage 1 translation table block or level 3 entry for pages pointed to by TTBR1 if TTBCR2.HPD1==1 and TTBCR.T2E==1.
Defined values are:
HWU159 | Meaning |
---|---|
0 |
The stage 1 translation table entry block or level 3 bit cannot be interpreted by hardware for an IMPLEMENTATION DEFINED purpose. |
1 |
The stage 1 translation table entry block or level 3 bit can be interpreted by hardware for an IMPLEMENTATION DEFINED purpose if the TTBCR2.HPD1 value is 1. |
This bit is RES0 if ARMv8.2-TTPBHA is not implemented.
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[62] of the stage 1 translation table block or level 3 entry for pages pointed to by TTBR0 if TTBCR2.HPD0==1 and TTBCR.T2E==1.
Defined values are:
HWU062 | Meaning |
---|---|
0 |
The stage 1 translation table entry block or level 3 bit cannot be interpreted by hardware for an IMPLEMENTATION DEFINED purpose. |
1 |
The stage 1 translation table entry block or level 3 bit can be interpreted by hardware for an IMPLEMENTATION DEFINED purpose if the TTBCR2.HPD0 value is 1. |
This bit is RES0 if ARMv8.2-TTPBHA is not implemented.
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[61] of the stage 1 translation table block or level 3 entry for pages pointed to by TTBR0 if TTBCR2.HPD0==1 and TTBCR.T2E==1.
Defined values are:
HWU061 | Meaning |
---|---|
0 |
The stage 1 translation table entry block or level 3 bit cannot be interpreted by hardware for an IMPLEMENTATION DEFINED purpose. |
1 |
The stage 1 translation table entry block or level 3 bit can be interpreted by hardware for an IMPLEMENTATION DEFINED purpose if the TTBCR2.HPD0 value is 1. |
This bit is RES0 if ARMv8.2-TTPBHA is not implemented.
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[60] of the stage 1 translation table block or level 3 entry for pages pointed to by TTBR0 if TTBCR2.HPD0==1 and TTBCR.T2E==1.
Defined values are:
HWU060 | Meaning |
---|---|
0 |
The stage 1 translation table entry block or level 3 bit cannot be interpreted by hardware for an IMPLEMENTATION DEFINED purpose. |
1 |
The stage 1 translation table entry block or level 3 bit can be interpreted by hardware for an IMPLEMENTATION DEFINED purpose if the TTBCR2.HPD0 value is 1. |
This bit is RES0 if ARMv8.2-TTPBHA is not implemented.
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[59] of the stage 1 translation table block or level 3 entry for pages pointed to by TTBR0 if TTBCR2.HPD0==1 and TTBCR.T2E==1.
Defined values are:
HWU059 | Meaning |
---|---|
0 |
The stage 1 translation table entry block or level 3 bit cannot be interpreted by hardware for an IMPLEMENTATION DEFINED purpose. |
1 |
The stage 1 translation table entry block or level 3 bit can be interpreted by hardware for an IMPLEMENTATION DEFINED purpose if the TTBCR2.HPD0 value is 1. |
This bit is RES0 if ARMv8.2-TTPBHA is not implemented.
Hierarchical Permission Disables. This affects the hierarchical control bits, APTable, XNTable, and PXNTable, in the translation tables pointed to by TTBR1.
Defined values are:
HPD1 | Meaning |
---|---|
0 |
Hierarchical permissions are enabled. |
1 |
Hierarchical permissions are disabled if TTBCR.T2E == 1. |
When disabled, the permissions are treated as if the bits are 0.
If TTBCR.T2E == 0, the hierarchical permissions are enabled.
This bit is RES0 if ARMv8.2-AA32HPD is not implemented.
Hierarchical Permission Disables. This affects the hierarchical control bits, APTable, XNTable, and PXNTable, in the translation tables pointed to by TTBR0.
Defined values are:
HPD0 | Meaning |
---|---|
0 |
Hierarchical permissions are enabled. |
1 |
Hierarchical permissions are disabled if TTBCR.T2E ==1. |
When disabled, the permissions are treated is as if the bits are 0.
If TTBCR.T2E == 0, the hierarchical permissions are enabled.
This bit is RES0 if ARMv8.2-AA32HPD is not implemented.
Reserved, RES0.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c2, c0, 3 | 000 | 011 | 0010 | 1111 | 0000 |
The register is accessible as follows:
Configuration | Control | Accessibility | Instance | |||||
---|---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | ||
EL3 using AArch32 | x | 0 | 1 | - | RW | RW | RW | TTBCR2_ns |
EL3 using AArch32 | x | 1 | 1 | - | n/a | RW | RW | TTBCR2_ns |
EL3 not implemented | x | x | 0 | - | RW | n/a | n/a | TTBCR2 |
EL3 not implemented | x | 0 | 1 | - | RW | RW | n/a | TTBCR2 |
EL3 not implemented | x | 1 | 1 | - | n/a | RW | n/a | TTBCR2 |
EL3 using AArch64 | x | x | 0 | - | RW | n/a | n/a | TTBCR2 |
EL3 using AArch64 | x | 0 | 1 | - | RW | RW | n/a | TTBCR2 |
EL3 using AArch64 | x | 1 | 1 | - | n/a | RW | n/a | TTBCR2 |
EL3 using AArch32 | x | x | 0 | - | n/a | n/a | RW | TTBCR2_s |
This table applies to all instructions that can access this register.
When EL3 is using AArch32, write access to TTBCR2_s is UNDEFINED when the CP15SDISABLE signal is asserted HIGH.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TVM==1, Non-secure write accesses to this register from EL1 are trapped to EL2.
If HCR_EL2.TRVM==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HSTR_EL2.T2==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TVM==1, Non-secure write accesses to this register from EL1 are trapped to EL2.
If HCR_EL2.TRVM==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HSTR_EL2.T2==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
18/04/2017 17:00
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