EDECCR, External Debug Exception Catch Control Register

The EDECCR characteristics are:

Purpose

Controls Exception Catch debug events.

This register is part of the Debug registers functional group.

Usage constraints

This register is accessible as follows:

OffDLKOSLKSLKDefault
ErrorErrorErrorRORW

Configuration

External register EDECCR is architecturally mapped to AArch64 System register OSECCR_EL1.

External register EDECCR is architecturally mapped to AArch32 System register DBGOSECCR.

EDECCR is in the Core power domain. Some or all RW fields of this register have defined reset values. These apply only on a Cold reset. The register is not affected by a Warm reset and is not affected by an External debug reset.

Attributes

EDECCR is a 32-bit register.

Field descriptions

The EDECCR bit assignments are:

313029282726252423222120191817161514131211109876543210
0000000000000000NSR<n>SR<n>NSE<n>SE<n>

Bits [31:16]

Reserved, RES0.

NSR<n>, bits [15:12]
In ARMv8.2:

Controls Non-secure exception catch on exception return to EL<n> in conjunction with NSE<n>. If EL3 and EL2 are not implemented and the PE behaves as if SCR_EL3.NS is set to 0, this field is reserved, RES0. Otherwise, possible values for this field are:

NSR<n>Meaning
0

If the corresponding NSE<n> bit is 0, then Exception Catch debug events are disabled for Non-secure Exception level <n>.

If the corresponding NSE<n> bit is 1, then Exception Catch debug events are enabled for exception entry, reset entry and exception return to Non-secure Exception level <n>.

1

If the corresponding NSE<n> bit is 0, then Exception Catch debug events are enabled for exception returns to Non-secure Exception level <n>.

If the corresponding NSE<n> bit is 1, then Exception Catch debug events are enabled for exception entry and reset entry to Non-secure Exception level <n>.

Note

It is IMPLEMENTATION DEFINED whether a reset entry to an Exception level is permitted to generate an Exception Catch debug event.

NSR[3] is RES0.

If EL2 is not implemented, NSR[2] is RES0.

A value that enables an Exception Catch debug event for an Exception level that is not implemented is reserved. If this field is programmed with a reserved value then:

When this register has an architecturally-defined reset value, this field resets to 0.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

SR<n>, bits [11:8]
In ARMv8.2:

Controls Secure exception catch on exception return to EL<n> in conjunction with SE<n>. If EL3 is not implemented and the PE behaves as if SCR_EL3.NS is set to 1, this field is reserved, RES0. Otherwise, possible values for this field are:

SR<n>Meaning
0

If the corresponding SE<n> bit is 0, then Exception Catch debug events are disabled for Secure Exception level <n>.

If the corresponding SE<n> bit is 1, then Exception Catch debug events are enabled for exception entry, reset entry and exception return to Secure Exception level <n>.

1

If the corresponding SE<n> bit is 0, then Exception Catch debug events are enabled for exception returns to Secure Exception level <n>.

If the corresponding SE<n> bit is 1, then Exception Catch debug events are enabled for exception entry and reset entry to Secure Exception level <n>.

Note

It is IMPLEMENTATION DEFINED whether a reset entry to an Exception level is permitted to generate an Exception Catch debug event.

SR[2] is RES0.

If EL3 is not implemented, SR[3] is RES0.

A value that enables an Exception Catch debug event for an Exception level that is not implemented is reserved. If this field is programmed with a reserved value then:

If ExternalSecureInvasiveDebugEnabled() == FALSE, then this field is ignored.

When this register has an architecturally-defined reset value, this field resets to 0.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

NSE<n>, bits [7:4]
In ARMv8.2:

Coarse-grained Non-secure exception catch for EL<n>. This controls whether Exception Catch debug events are enabled for Non-secure EL<n>. This also controls:

If EL3 and EL2 are not implemented and the PE behaves as if SCR_EL3.NS is set to 0, this field is reserved, RES0. Otherwise, possible values for this field are:

NSE<n>Meaning
0

Exception Catch debug events are disabled for Non-secure Exception level <n>.

1

Exception Catch debug events are enabled for Non-secure Exception level <n>.

NSE[3,0] are RES0.

A value that enables an Exception Catch debug event for an Exception level that is not implemented is reserved. If this field is programmed with a reserved value then:

When this register has an architecturally-defined reset value, this field resets to 0.


In ARMv8.1 and ARMv8.0:

Coarse-grained Non-secure exception catch. If EL3 and EL2 are not implemented and the PE behaves as if SCR_EL3.NS is set to 0, this field is reserved, RES0. Otherwise, possible values for this field are:

NSEMeaning
0000

Exception Catch debug event disabled for Non-secure Exception levels.

0010

Exception Catch debug event enabled for Non-secure EL1.

0100

Exception Catch debug event enabled for Non-secure EL2.

0110

Exception Catch debug event enabled for Non-secure EL1 and EL2.

All other values are reserved. A value that enables an Exception Catch debug event for an Exception level that is not implemented is reserved. If this field is programmed with a reserved value then:

SE<n>, bits [3:0]
In ARMv8.2:

Coarse-grained Secure exception catch for EL<n>. This field controls whether Exception Catch debug events are enabled for Secure EL<n>.

If EL3 is not implemented and the PE behaves as if SCR_EL3.NS is set to 1, this field is reserved, RES0. Otherwise, possible values for this field are:

SE<n>Meaning
0

Exception Catch debug events are disabled for Secure Exception level <n>.

1

Exception Catch debug events are enabled for Secure Exception level <n>.

SE[2,0] are RES0.

If EL3 is not implemented, SE[3] is RES0.

A value that enables an Exception Catch debug event for an Exception level that is not implemented is reserved. If this field is programmed with a reserved value then:

If ExternalSecureInvasiveDebugEnabled() == FALSE, then this field is ignored.

When this register has an architecturally-defined reset value, this field resets to 0.


In ARMv8.1 and ARMv8.0:

Coarse-grained Secure exception catch. If EL3 is not implemented and the PE behaves as if SCR_EL3.NS is set to 1, this field is reserved, RES0. Otherwise, possible values for this field are:

SEMeaning
0000

Exception Catch debug event disabled for Secure Exception levels.

0010

Exception Catch debug event enabled for Secure EL1.

1000

Exception Catch debug event enabled for Secure EL3.

1010

Exception Catch debug event enabled for Secure EL1 and EL3.

All other values are reserved. A value that enables an Exception Catch debug event for an Exception level that is not implemented is reserved. If this field is programmed with a reserved value then:

The NSR<n>, SR<n>, NSE<n>, and SE<n> fields combine to control Exception Catch as follows:

(N)SR<n> (N)SE<n> Behavior on exception return to ELn Behavior on exception taken to ELn
0 0 No action No action
0 1 Halt if allowed Halt if allowed
1 0 Halt if allowed No action
1 1 No action Halt if allowed

Accessing the EDECCR

EDECCR can be accessed through the external debug interface:

ComponentOffset
Debug 0x098



18/04/2017 17:00

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