The S1_<op1>_<Cn>_<Cm>_<op2> characteristics are:
This area of the System instruction encoding space is reserved for IMPLEMENTATION DEFINED System instructions.
This System instruction is part of the IMPLEMENTATION DEFINED functional group.
There are no configuration notes.
S1_<op1>_<Cn>_<Cm>_<op2> is a 64-bit System instruction.
The S1_<op1>_<Cn>_<Cm>_<op2> input value bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED.
This instruction is executed using SYS with the following syntax:
SYS <op1>, C<Cn>, C<Cm>, <op2>
This instruction is executed using SYSL with the following syntax:
SYSL <op1>, C<Cn>, C<Cm>, <op2>
This syntax uses the following encoding in the System instruction encoding space:
CRn | op1 | op2 | CRm |
---|---|---|---|
Cn<3:0> | op1<2:0> | op2<2:0> | Cm<3:0> |
The value of <Cn> must be either 11 or 15. Other values may refer to architecturally-defined system instructions.
The accessibility of system instructions with these encodings is IMPLEMENTATION DEFINED.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when executing this System instruction.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TIDCP==1, Non-secure execution of this instruction at EL1 is trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TIDCP==1, Non-secure execution of this instruction at EL1 is trapped to EL2.
18/04/2017 17:00
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