EDPIDR1, External Debug Peripheral Identification Register 1

The EDPIDR1 characteristics are:

Purpose

Provides information to identify an external debug component.

For more information see 'About the Peripheral identification scheme' in the ARMv8 ARM, section H8 (About the External Debug Registers).

This register is part of the Debug registers functional group.

Usage constraints

This register is accessible as follows:

Default
RO

Configuration

EDPIDR1 is in the Debug power domain.

Implementation of this register is OPTIONAL.

This register is required for CoreSight compliance.

Attributes

EDPIDR1 is a 32-bit register.

Field descriptions

The EDPIDR1 bit assignments are:

313029282726252423222120191817161514131211109876543210
000000000000000000000000DES_0PART_1

Bits [31:8]

Reserved, RES0.

DES_0, bits [7:4]

Designer, least significant nibble of JEP106 ID code. For ARM Limited, this field is 0b1011.

PART_1, bits [3:0]

Part number, most significant nibble.

Accessing the EDPIDR1

EDPIDR1 can be accessed through the external debug interface:

ComponentOffset
Debug 0xFE4



18/04/2017 17:00

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