The PMCEID3 characteristics are:
Defines which common architectural and common microarchitectural feature events in the range 0x4020 to 0x403F are implemented. If a particular bit is set to 1, then the event for that bit is implemented.
This register is part of the Performance Monitors registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register PMCEID3 is architecturally mapped to AArch64 System register PMCEID1_EL0[63:32] .
AArch32 System register PMCEID3 is architecturally mapped to External register PMCEID3[63:32] .
This register is introduced in ARMv8.1.
PMCEID3 is a 32-bit register.
The PMCEID3 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ID[16447:16416] |
PMCEID3[31:0] maps to common events 0x4020 to 0x403F. For a list of event numbers and descriptions, see 'Event numbers and mnemonics' in the ARM ARM, section D5.10.
For each bit:
ID[16447:16416] | Meaning |
---|---|
0 |
The common event is not implemented. |
1 |
The common event is implemented. |
Bits that map to reserved event numbers are reserved to identify events that might be defined in future revisions to the architecture.
Events that do not require additional features in the PMU can be defined retrospectively, meaning that they can be implemented as part of a PMUv3 implementation.
This register can be read using MRC with the following syntax:
MRC <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c9, c14, 5 | 000 | 101 | 1001 | 1111 | 1110 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | RO | RO | n/a | RO |
x | 0 | 1 | RO | RO | RO | RO |
x | 1 | 1 | RO | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If PMUSERENR.EN==0, read accesses to this register from EL0 are trapped to Undefined mode.
If PMUSERENR_EL0.EN==0, read accesses to this register from EL0 are trapped to EL1.
18/04/2017 17:00
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