The ICH_AP0R<n>_EL2 characteristics are:
Provides information about Group 0 virtual active priorities for EL2.
This register is part of:
AArch64 System register ICH_AP0R<n>_EL2 is architecturally mapped to AArch32 System register ICH_AP0R<n>.
If EL2 is not implemented, this register is RES0 from EL3.
ICH_AP0R<n>_EL2 is a 32-bit register.
The ICH_AP0R<n>_EL2 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
P31 | P30 | P29 | P28 | P27 | P26 | P25 | P24 | P23 | P22 | P21 | P20 | P19 | P18 | P17 | P16 | P15 | P14 | P13 | P12 | P11 | P10 | P9 | P8 | P7 | P6 | P5 | P4 | P3 | P2 | P1 | P0 |
Provides the access to the virtual active priorities for Group 0 interrupts. Possible values of each bit are:
P<x> | Meaning |
---|---|
0 |
There is no Group 0 interrupt active with this priority level, or all active Group 0 interrupts with this priority level have undergone priority-drop. |
1 |
There is a Group 0 interrupt active with this priority level which has not undergone priority drop. |
The correspondence between priority levels and bits depends on the number of bits of priority that are implemented.
If 5 bits of priority are implemented (bits [7:3] of priority), then there are 32 priority levels, and the active state of these priority levels are held in ICH_AP0R0_EL2 in the bits corresponding to Priority[7:3].
If 6 bits of priority are implemented (bits [7:2] of priority), then there are 64 priority levels, and:
If 7 bits of priority are implemented (bits [7:1] of priority), then there are 128 priority levels, and:
Having the bit corresponding to a priority set to 1 in both ICH_AP0R<n>_EL2 and ICH_AP1R<n>_EL2 might result in UNPREDICTABLE behavior of the interrupt prioritization system for virtual interrupts.
When this register has an architecturally-defined reset value, this field resets to 0.
Software must ensure that ICH_AP0R<n>_EL2 is 0 for legacy VMs otherwise behaviour is UNPREDICTABLE. For more information about support for legacy VMs, see Support for legacy operation of VMs.
The active priorities for Group 0 and Group 1 interrupts for legacy VMs are held in ICH_AP1R<n>_EL2 and reads and writes to GICV_APR access ICH_AP1R<n>_EL2. This means that ICH_AP0R<n>_EL2 is inaccessible to legacy VMs.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op1 | CRn | CRm | op2 |
---|---|---|---|---|
ICH_AP0R<n>_EL2 | 100 | 1100 | 1000 | 0:n<1:0> |
The register is accessible as follows:
Control | Accessibility | ||||||
---|---|---|---|---|---|---|---|
FMO | IMO | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | x | 0 | - | - | n/a | RW |
x | x | 0 | 1 | - | - | RW | RW |
x | x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
ICH_AP0R1_EL2 is only implemented in implementations that support 6 or more bits of priority. ICH_AP0R2_EL2 and ICH_AP0R3_EL2 are only implemented in implementations that support 7 bits of priority. Unimplemented registers are UNDEFINED.
Writing to these registers with any value other than the last read value of the register (or 0x00000000 for a newly set up virtual machine) can result in UNPREDICTABLE behavior of the virtual interrupt prioritization system allowing either:
Writing to the active priority registers in any order other than the following order will result in UNPREDICTABLE behavior:
Having the bit corresponding to a priority set in both ICH_AP0R<n>_EL2 and ICH_AP1R<n>_EL2 can result in UNPREDICTABLE behavior of the interrupt prioritization system for virtual interrupts.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_SRE_EL2.SRE==0, accesses to this register from EL2 are trapped to EL2.
If ICC_SRE_EL3.SRE==0, accesses to this register from EL3 are trapped to EL3.
18/04/2017 17:00
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