GICR_IGROUPR0, Interrupt Group Register 0

The GICR_IGROUPR0 characteristics are:

Purpose

Controls whether the corresponding SGI or PPI is in Group 0 or Group 1.

This register is part of the GIC Redistributor registers functional group.

Usage constraints

This register is accessible as follows:

Security disabledSecureNon-secure
RWRWRW

When affinity routing is not enabled for the Security state of an interrupt in GICR_IGROUPR0, the corresponding bit is RES0 and equivalent functionality is provided by GICD_IGROUPR<n> with n=0.

When GICD_CTLR.DS == 0, the register is RAZ/WI to Non-secure accesses.

Bits corresponding to unimplemented interrupts are RAZ/WI.

Note

Implementations must ensure that an interrupt that is pending at the time of the write uses either the old value or the new value and must ensure that the interrupt is neither lost nor handled more than once. The effect of the change must be visible in finite time.

Configuration

RW fields in this register reset to architecturally UNKNOWN values.

This register is available in all GIC configurations. If the GIC implementation supports two Security states, this register is Secure.

A copy of this register is provided for each Redistributor.

Attributes

GICR_IGROUPR0 is a 32-bit register.

Field descriptions

The GICR_IGROUPR0 bit assignments are:

313029282726252423222120191817161514131211109876543210
Redistributor_group_status_bit<x>, bit [x], for x = 0 to 31

Redistributor_group_status_bit<x>, bit [x], for x = 0 to 31

Group status bit. In this register:

Redistributor_group_status_bit<x>Meaning
0

When GICD_CTLR.DS==1, the corresponding interrupt is Group 0.

When GICD_CTLR.DS==0, the corresponding interrupt is Secure.

1

When GICD_CTLR.DS==1, the corresponding interrupt is Group 1.

When GICD_CTLR.DS==0, the corresponding interrupt is Non-secure Group 1.

When GICD_CTLR.DS == 0, the bit that corresponds to the interrupt is concatenated with the equivalent bit in GICR_IGRPMODR0 to form a 2-bit field that defines an interrupt group. The encoding of this field is at GICR_IGRPMODR0.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

The considerations for the reset value of this register are the same as those for GICD_IGROUPR<n> with n=0.

Accessing the GICR_IGROUPR0

GICR_IGROUPR0 can be accessed through its memory-mapped interface:

ComponentFrameOffset
GIC RedistributorSGI_base 0x0080



18/04/2017 17:00

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