The PMCCFILTR_EL0 characteristics are:
Determines the modes in which the Cycle Counter, PMCCNTR_EL0, increments.
This register is part of the Performance Monitors registers functional group.
This register is accessible as follows:
Off | DLK | OSLK | EPMAD | SLK | Default |
---|---|---|---|---|---|
Error | Error | Error | Error | RO | RW |
External register PMCCFILTR_EL0 is architecturally mapped to AArch64 System register PMCCFILTR_EL0.
External register PMCCFILTR_EL0 is architecturally mapped to AArch32 System register PMCCFILTR.
PMCCFILTR_EL0 is in the Core power domain.
On a Warm or Cold reset RW fields in this register reset:
The register is not affected by an External debug reset.
PMCCFILTR_EL0 is a 32-bit register.
The PMCCFILTR_EL0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
P | U | NSK | NSU | NSH | M | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Privileged filtering bit. Controls counting in EL1. If EL3 is implemented, then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are:
P | Meaning |
---|---|
0 |
Count cycles in EL1. |
1 |
Do not count cycles in EL1. |
User filtering bit. Controls counting in EL0. If EL3 is implemented, then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are:
U | Meaning |
---|---|
0 |
Count cycles in EL0. |
1 |
Do not count cycles in EL0. |
Non-secure EL1 (kernel) modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented, this bit is RES0.
If the value of this bit is equal to the value of P, cycles in Non-secure EL1 are counted.
Otherwise, cycles in Non-secure EL1 are not counted.
Non-secure EL0 (Unprivileged) filtering. Controls counting in Non-secure EL0. If EL3 is not implemented, this bit is RES0.
If the value of this bit is equal to the value of U, cycles in Non-secure EL0 are counted.
Otherwise, cycles in Non-secure EL0 are not counted.
Non-secure EL2 (Hypervisor) filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented, this bit is RES0.
NSH | Meaning |
---|---|
0 |
Do not count cycles in EL2. |
1 |
Count cycles in EL2. |
Secure EL3 filtering bit. If EL3 is not implemented, this bit is RES0.
If the value of this bit is equal to the value of P, cycles in Secure EL3 are counted.
Otherwise, cycles in Secure EL3 are not counted.
Most applications can ignore this field and set its value to 0.
This field is not visible in the AArch32 PMCCFILTR System register.
Reserved, RES0.
PMCCFILTR_EL0 can be accessed through the external debug interface:
Component | Offset |
---|---|
PMU | 0x47C |
18/04/2017 17:00
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