The SPSR_fiq characteristics are:
Holds the saved process state when an exception is taken to FIQ mode.
This register is part of the Special-purpose registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register SPSR_fiq is architecturally mapped to AArch64 System register SPSR_fiq.
SPSR_fiq is a 32-bit register.
The SPSR_fiq bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
N | Z | C | V | Q | IT[1:0] | J | 0 | PAN | 0 | IL | GE | IT[7:2] | E | A | I | F | T | M[4] | M[3:0] |
Set to the value of CPSR.N on taking an exception to FIQ mode, and copied to CPSR.N on executing an exception return operation in FIQ mode.
Set to the value of CPSR.Z on taking an exception to FIQ mode, and copied to CPSR.Z on executing an exception return operation in FIQ mode.
Set to the value of CPSR.C on taking an exception to FIQ mode, and copied to CPSR.C on executing an exception return operation in FIQ mode.
Set to the value of CPSR.V on taking an exception to FIQ mode, and copied to CPSR.V on executing an exception return operation in FIQ mode.
Set to the value of CPSR.Q on taking an exception to FIQ mode, and copied to CPSR.Q on executing an exception return operation in FIQ mode.
IT block state bits for the T32 IT (If-Then) instruction. See IT[7:2] for explanation of this field.
RES0.
In previous versions of the architecture, the {J, T} bits determined the AArch32 Instruction set state. ARMv8 does not support either Jazelle state or T32EE state, and the T bit determines the Instruction set state.
Reserved, RES0.
When ARMv8.1-PAN is implemented, set to the value of CPSR.PAN on taking an exception to FIQ mode, and copied to CPSR.PAN on executing an exception return operation in FIQ mode.
When ARMv8.1-PAN is not implemented, this bit is RES0.
Reserved, RES0.
Reserved, RES0.
Illegal Execution state bit. Shows the value of PSTATE.IL immediately before the exception was taken.
Greater than or Equal flags, for parallel addition and subtraction.
IT block state bits for the T32 IT (If-Then) instruction. This field must be interpreted in two parts.
The IT field is 0b00000000 when no IT block is active.
Endianness state bit. Controls the load and store endianness for data accesses:
E | Meaning |
---|---|
0 |
Little-endian operation |
1 |
Big-endian operation. |
Instruction fetches ignore this bit.
When the reset value of the SCTLR.EE bit is defined by a configuration input signal, that value also applies to the CPSR.E bit on reset, and therefore applies to software execution from reset.
If an implementation does not provide Big-endian support, this bit is RES0. If it does not provide Little-endian support, this bit is RES1.
If an implementation provides Big-endian support but only at EL0, this bit is RES0 for an exception return to any Exception level other than EL0.
Likewise, if it provides Little-endian support only at EL0, this bit is RES1 for an exception return to any Exception level other than EL0.
SError interrupt mask bit. The possible values of this bit are:
A | Meaning |
---|---|
0 |
Exception not masked. |
1 |
Exception masked. |
IRQ mask bit. The possible values of this bit are:
I | Meaning |
---|---|
0 |
Exception not masked. |
1 |
Exception masked. |
FIQ mask bit. The possible values of this bit are:
F | Meaning |
---|---|
0 |
Exception not masked. |
1 |
Exception masked. |
T32 Instruction set state bit. Determines the AArch32 instruction set state that the exception was taken from. Possible values of this bit are:
T | Meaning |
---|---|
0 |
Taken from A32 state. |
1 |
Taken from T32 state. |
Execution state that the exception was taken from. Possible values of this bit are:
M[4] | Meaning |
---|---|
1 |
Exception taken from AArch32. |
AArch32 mode that an exception was taken from. The possible values are:
M[3:0] | Mode |
---|---|
0b0000 | User |
0b0001 | FIQ |
0b0010 | IRQ |
0b0011 | Supervisor |
0b0110 | Monitor (only valid in Secure state, if EL3 is implemented and can use AArch32) |
0b0111 | Abort |
0b1011 | Undefined |
0b1111 | System |
Other values are reserved. The effect of programming this field to a Reserved value is that behavior is CONSTRAINED UNPREDICTABLE, as described in 'Unallocated values in fields of AArch32 System registers and translation table entries' in the ARM ARM, section K1.1.11.
This register can be read using MRS (banked register) with the following syntax:
MRS <Rd>, <banked_reg>
This register can be written using MSR (banked register) with the following syntax:
MSR <banked_reg>, <Rd>
This syntax uses the following encoding in the System instruction encoding space:
<banked_reg> | R | M | M1 |
---|---|---|---|
SPSR_fiq | 1 | 0 | 1110 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RW | n/a | RW |
x | 0 | 1 | - | RW | RW | RW |
x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
Using MRS (banked register) and MSR (banked register) instructions, at PL1 this register is only accessible from PE modes other than FIQ mode. In FIQ mode, it is accessible as the current SPSR.
18/04/2017 17:00
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