GICD_CPENDSGIR<n>, SGI Clear-Pending Registers, n = 0 - 3

The GICD_CPENDSGIR<n> characteristics are:

Purpose

Removes the pending state from an SGI.

A write to this register changes the state of a pending SGI to inactive, and the state of an active and pending SGI to active.

This register is part of the GIC Distributor registers functional group.

Usage constraints

This register is accessible as follows:

Security disabledSecureNon-secure
RWRWRW

These registers are used only when affinity routing is not enabled. When affinity routing is enabled, this register is RES0. An implementation is permitted to make the register RAZ/WI in this case.

A register bit that corresponds to an unimplemented SGI is RAZ/WI.

These registers are byte-accessible.

If the GIC implementation supports two Security states:

Configuration

Some or all RW fields of this register have defined reset values.

Four SGI clear-pending registers are implemented. Each register contains eight clear-pending bits for each of four SGIs, for a total of 16 possible SGIs.

In multiprocessor implementations, each PE has a copy of these registers.

Attributes

GICD_CPENDSGIR<n> is a 32-bit register.

Field descriptions

The GICD_CPENDSGIR<n> bit assignments are:

313029282726252423222120191817161514131211109876543210
SGI_clear_pending_bits<x>, bits [8x+7:8x], for x = 0 to 3

SGI_clear_pending_bits<x>, bits [8x+7:8x], for x = 0 to 3

Removes the pending state from SGI number 4n + x for the PE corresponding to the bit number written to.

Reads and writes have the following behavior:

SGI_clear_pending_bits<x>Meaning
0

If read, indicates that the SGI from the corresponding PE is not pending and is not active and pending.

If written, has no effect.

1

If read, indicates that the SGI from the corresponding PE is pending or is active and pending.

If written, removes the pending state from the SGI for the corresponding PE.

When this register has an architecturally-defined reset value, this field resets to 0.

For SGI ID m, generated by processing element C writing to the corresponding GICD_SGIR field, where DIV and MOD are the integer division and modulo operations:

Accessing the GICD_CPENDSGIR<n>

GICD_CPENDSGIR<n> can be accessed through its memory-mapped interface:

ComponentOffset
GIC Distributor0x0F10 + 4n



18/04/2017 17:00

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