The GICR_IGRPMODR0 characteristics are:
When GICD_CTLR.DS==0, this register together with the GICD_IGROUPR<n> registers, controls whether the corresponding interrupt is in:
This register is part of the GIC Redistributor registers functional group.
This register is accessible as follows:
Security disabled | Secure | Non-secure |
---|---|---|
RES0 | RW | RW |
When affinity routing is not enabled for the Security state of an interrupt in GICR_IGRPMODR0, the corresponding bit is RES0 and equivalent functionality is provided by GICD_IGRPMODR<n> with n=0.
This register only applies to SGIs (bits [15:0]) and PPIs (bits [31:16]). For SPIs, this functionality is provided by GICD_IGRPMODR<n>.
When GICD_CTLR.ARE_S == 0 or GICD_CTLR.DS == 1, GICR_IGRPMODR0 is RES0. An implementation can make this register RAZ/WI in this case.
When GICD_CTLR.DS==0, the register is RAZ/WI to Non-secure accesses.
Implementations must ensure that an interrupt that is pending at the time of the write uses either the old value or the new value and must ensure that the interrupt is neither lost nor handled more than once. The effect of the change must be visible in finite time.
RW fields in this register reset to architecturally UNKNOWN values.
When GICD_CLTR.DS==0, this register is Secure.
A copy of this register is provided for each Redistributor.
GICR_IGRPMODR0 is a 32-bit register.
The GICR_IGRPMODR0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Group_modifier_bit<x>, bit [x], for x = 0 to 31 |
Group modifier bit. In implementations where affinity routing is enabled for the Security state of an interrupt, the bit that corresponds to the interrupt is concatenated with the equivalent bit in GICR_IGROUPR0 to form a 2-bit field that defines an interrupt group:
Group modifier bit | Group status bit | Definition | Short name |
---|---|---|---|
0 | 0 | Secure Group 0 | G0S |
0 | 1 | Non-secure Group 1 | G1NS |
1 | 0 | Secure Group 1 | G1S |
1 | 1 | Reserved, treated as Non-secure Group 1 | - |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
GICR_IGRPMODR0 can be accessed through its memory-mapped interface:
Component | Frame | Offset |
---|---|---|
GIC Redistributor | SGI_base | 0x0D00 |
18/04/2017 17:00
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