The ID_AA64MMFR2_EL1 characteristics are:
Provides information about the implemented memory model and memory management support in AArch64 state.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.
This register is part of the Identification registers functional group.
This register is introduced in ARMv8.2.
ID_AA64MMFR2_EL1 is a 64-bit register.
The ID_AA64MMFR2_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | VARange | IESB | LSM | UAO | CnP | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Indicates support for a larger virtual address. Defined values are:
VARange | Meaning |
---|---|
0000 |
48 bits of VA for each translation table page register are supported. |
0001 |
52 bits of VA for each translation table page register are supported. |
All other values are reserved.
From ARMv8.2, the permitted values are 0000 and 0001. This feature is identified by the name ARMv8.2-LVA.
Indicates whether the implicit Error Synchronization Barrier operations are implemented. Defined values are:
IESB | Meaning |
---|---|
0000 |
SCTLR_ELx.IESB implicit ErrorSynchronizationBarrier control not implemented. |
0001 |
SCTLR_ELx.IESB implicit ErrorSynchronizationBarrier control implemented. |
All other values are reserved.
Indicates support for LSMAOE and nTLSMD bits in SCTLR_EL1 and SCTLR_EL2. Defined values are:
LSM | Meaning |
---|---|
0000 |
LSMAOE and nTLSMD bits not supported. |
0001 |
LSMAOE and nTLSMD bits supported. |
All other values are reserved.
From ARMv8.2, the permitted values are 0000 and 0001. This feature is identified by the name ARMv8.2-LSMAOC.
User Access Override. Defined values are:
UAO | Meaning |
---|---|
0000 |
UAO not supported. |
0001 |
UAO supported. |
All other values are reserved.
From ARMv8.2, the only permitted value is 0001. This feature is identified by the name ARMv8.2-UAO.
Common not Private translations. Defined values are:
CnP | Meaning |
---|---|
0000 |
Common not Private translations not supported. |
0001 |
Common not Private translations supported. |
All other values are reserved.
From ARMv8.2, the only permitted value is 0001. This feature is identified by the name ARMv8.2-TTCNP.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
ID_AA64MMFR2_EL1 | 11 | 000 | 0000 | 0111 | 010 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
18/04/2017 17:00
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