The CNTACR<n> characteristics are:
Provides top-level access controls for the elements of a timer frame. CNTACR<n> provides the controls for frame CNTBaseN.
In addition to the CNTACR<n> control:
This register is part of the Generic Timer registers functional group.
This register is accessible as follows:
Default |
---|
RW |
In a system that recognizes two Security states:
The power domain of CNTACR<n> is IMPLEMENTATION DEFINED.
On a reset of the reset domain in which it is implemented, RW fields in this register reset to UNKNOWN values. The register is not affected by a reset of any other reset domain. For more information see 'Power and reset domains for the system level implementation of the Generic Timer' in Chapter I1 of the ARMv8 ARM.
Implemented only if the value of CNTTIDR.Frame<n> is 1.
An implementation of the counters might not provide configurable access to some or all of the features. In this case, the associated field in the CNTACR<n> register is:
CNTACR<n> is a 32-bit register.
The CNTACR<n> bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | RWPT | RWVT | RVOFF | RFRQ | RVCT | RPCT |
Reserved, RES0.
Read/write access to the EL1 Physical Timer registers CNTP_CVAL, CNTP_TVAL, and CNTP_CTL, in frame <n>. The possible values of this bit are:
RWPT | Meaning |
---|---|
0 |
No access to the EL1 Physical Timer registers in frame <n>. The registers are RES0. |
1 |
Read/write access to the EL1 Physical Timer registers in frame <n>. |
Read/write access to the Virtual Timer register CNTV_CVAL, CNTV_TVAL, and CNTV_CTL, in frame <n>. The possible values of this bit are:
RWVT | Meaning |
---|---|
0 |
No access to the Virtual Timer registers in frame <n>. The registers are RES0. |
1 |
Read/write access to the Virtual Timer registers in frame <n>. |
Read-only access to CNTVOFF, in frame <n>. The possible values of this bit are:
RVOFF | Meaning |
---|---|
0 |
No access to CNTVOFF in frame <n>. The register is RES0. |
1 |
Read-only access to CNTVOFF in frame <n>. |
Read-only access to CNTFRQ, in frame <n>. The possible values of this bit are:
RFRQ | Meaning |
---|---|
0 |
No access to CNTFRQ in frame <n>. The register is RES0. |
1 |
Read-only access to CNTFRQ in frame <n>. |
Read-only access to CNTVCT, in frame <n>. The possible values of this bit are:
RVCT | Meaning |
---|---|
0 |
No access to CNTVCT in frame <n>. The register is RES0. |
1 |
Read-only access to CNTVCT in frame <n>. |
Read-only access to CNTPCT, in frame <n>. The possible values of this bit are:
RPCT | Meaning |
---|---|
0 |
No access to CNTPCT in frame <n>. The register is RES0. |
1 |
Read-only access to CNTPCT in frame <n>. |
CNTACR<n> can be accessed through its memory-mapped interface:
Component | Frame | Offset |
---|---|---|
Timer | CNTCTLBase | 0x040 + 4n |
18/04/2017 17:00
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