The PMSWINC_EL0 characteristics are:
Increments a counter that is configured to count the Software increment event, event 0x00. For more information, see 'SW_INCR' in the ARMv8 ARM, section D5.
This register is part of the Performance Monitors registers functional group.
This register is accessible as follows:
Off | DLK | OSLK | EPMAD | SLK | Default |
---|---|---|---|---|---|
Error | Error | Error | Error | WI | WO |
External register PMSWINC_EL0 is architecturally mapped to AArch64 System register PMSWINC_EL0.
External register PMSWINC_EL0 is architecturally mapped to AArch32 System register PMSWINC.
PMSWINC_EL0 is in the Core power domain.
Implementation of this register is OPTIONAL.
If this register is implemented, use of it is deprecated.
If 1 is written to bit [n] from the external debug interface, it is CONSTRAINED UNPREDICTABLE whether or not a SW_INCR event is created for counter n. This is consistent with not implementing the register in the external debug interface.
PMSWINC_EL0 is a 32-bit register.
The PMSWINC_EL0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | P<n>, bit [n] |
Reserved, RES0.
Event counter software increment bit for PMEVCNTR<n>_EL0.
P<n> is WI if n >= PMCR_EL0.N, the number of implemented counters.
Otherwise, the effects of writing to this bit are:
P<n> | Meaning |
---|---|
0 |
No action. The write to this bit is ignored. |
1 |
It is CONSTRAINED UNPREDICTABLE whether a SW_INCR event is generated for event counter n. |
PMSWINC_EL0 can be accessed through the external debug interface:
Component | Offset |
---|---|
PMU | 0xCA0 |
18/04/2017 17:00
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