DC IVAC, Data or unified Cache line Invalidate by VA to PoC

The DC IVAC characteristics are:

Purpose

Invalidate data cache by address to Point of Coherency.

This System instruction is part of the Cache maintenance instructions functional group.

Configuration

AArch64 System instruction DC IVAC performs the same function as AArch32 System instruction DCIMVAC.

Attributes

DC IVAC is a 64-bit System instruction.

Field descriptions

The DC IVAC input value bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
Virtual address to use
Virtual address to use
313029282726252423222120191817161514131211109876543210

Bits [63:0]

Virtual address to use.

Executing the DC IVAC instruction

This instruction is executed using DC with the following syntax:

DC <dc_op>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<dc_op> op0op1CRnCRmop2
IVAC0100001110110001

When the instruction is executed, it can generate a watchpoint, which is prioritized in the same way as other watchpoints. If a watchpoint is generated, the CM bit in the ESR_ELx.ISS field is set to 1.

Accessibility

The instruction is executable as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - WO n/a WO
x01 - WOWOWO
x11 - n/a WOWO

This table applies to all syntax that can be used to execute this instruction.

This instruction requires write access permission to the VA, otherwise it causes a Permission Fault.

At EL1, this instruction performs a cache clean and invalidate, meaning it performs the same invalidation as a DC CIVAC instruction, if all of the following apply:

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when executing this System instruction.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :




18/04/2017 17:00

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