VBAR, Vector Base Address Register

The VBAR characteristics are:

Purpose

When high exception vectors are not selected, holds the vector base address for exceptions that are not taken to Monitor mode or to Hyp mode.

Software must program VBAR(NS) with the required initial value as part of the PE boot sequence.

This register is part of the Exception and fault handling registers functional group.

Configuration

AArch32 System register VBAR is architecturally mapped to AArch64 System register VBAR_EL1[31:0] .

When EL3 is using AArch32, write access to VBAR(S) is disabled when the CP15SDISABLE signal is asserted HIGH.

Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch32. If the PE resets into EL3 using AArch32 they apply only to the Secure instance of the register. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.

Attributes

VBAR is a 32-bit register.

Field descriptions

The VBAR bit assignments are:

313029282726252423222120191817161514131211109876543210
Vector Base Address00000

Bits [31:5]

Vector Base Address. Bits[31:5] of the base address of the exception vectors for exceptions taken to this Exception level. Bits[4:0] of an exception vector are the exception offset.

When this register has an architecturally-defined reset value, this field resets to an IMPLEMENTATION DEFINED value.

Bits [4:0]

Reserved, RES0.

Accessing the VBAR

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 0, <Rt>, c12, c0, 0000000110011110000

Accessibility

The register is accessible as follows:

Configuration Control Accessibility Instance
E2HTGENSEL0EL1EL2EL3
EL3 using AArch32xx0 - n/a n/a RWVBAR_s
EL3 using AArch32x01 - RWRWRWVBAR_ns
EL3 using AArch32x11 - n/a RWRWVBAR_ns
EL3 not implemented xx0 - RW n/a n/a VBAR
EL3 not implemented x01 - RWRW n/a VBAR
EL3 not implemented x11 - n/a RW n/a VBAR
EL3 using AArch64xx0 - RW n/a n/a VBAR
EL3 using AArch64x01 - RWRW n/a VBAR
EL3 using AArch64x11 - n/a RW n/a VBAR

This table applies to all instructions that can access this register.

When EL3 is using AArch32, write access to VBAR_s is UNDEFINED when the CP15SDISABLE signal is asserted HIGH.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :




18/04/2017 17:00

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