ICV_HPPIR0_EL1, Interrupt Controller Virtual Highest Priority Pending Interrupt Register 0

The ICV_HPPIR0_EL1 characteristics are:

Purpose

Indicates the highest priority pending virtual Group 0 interrupt on the virtual CPU interface.

This register is part of:

Configuration

AArch64 System register ICV_HPPIR0_EL1 performs the same function as AArch32 System register ICV_HPPIR0.

Attributes

ICV_HPPIR0_EL1 is a 32-bit register.

Field descriptions

The ICV_HPPIR0_EL1 bit assignments are:

313029282726252423222120191817161514131211109876543210
00000000INTID

Bits [31:24]

Reserved, RES0.

INTID, bits [23:0]

The INTID of the highest priority pending virtual interrupt.

If the highest priority pending interrupt is not observable, this field contains a special INTID to indicate the reason. This special INTID can take the value 1023 only. See Special INTIDs, for more information.

This field has either 16 or 24 bits implemented. The number of implemented bits can be found in ICV_CTLR_EL1.IDbits. If only 16 bits are implemented, bits [23:16] of this register are RES0.

Accessing the ICV_HPPIR0_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op1CRnCRmop2
ICC_HPPIR0_EL100011001000010

When HCR_EL2.FMO is set to 0, execution of this encoding at Non-secure EL1 results in an access to ICC_HPPIR0_EL1.

Accessibility

The register is accessible as follows:

Control Accessibility
FMOIMOTGENSEL0EL1EL2EL3
xxx0 - ICC_HPPIR0_EL1 n/a ICC_HPPIR0_EL1
xx11 - n/a ICC_HPPIR0_EL1 ICC_HPPIR0_EL1
0x01 - ICC_HPPIR0_EL1 ICC_HPPIR0_EL1 ICC_HPPIR0_EL1
1x01 - RO ICC_HPPIR0_EL1 ICC_HPPIR0_EL1

This table applies to all instructions that can access this register.

ICV_HPPIR0_EL1 is only accessible at Non-secure EL1 when HCR_EL2.FMO is set to 1.

Note

When HCR_EL2.FMO is set to 0, at Non-secure EL1, the instruction encoding used to access ICV_HPPIR0_EL1 results in an access to ICC_HPPIR0_EL1.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When SCR_EL3.NS==1 :




18/04/2017 17:00

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