The IC IALLUIS characteristics are:
Invalidate all instruction caches in Inner Shareable domain to Point of Unification.
This System instruction is part of the Cache maintenance instructions functional group.
AArch64 System instruction IC IALLUIS performs the same function as AArch32 System instruction ICIALLUIS.
IC IALLUIS is a 64-bit System instruction.
IC IALLUIS ignores the value in the register specified by the instruction encoding. Software does not have to write a value to the register before issuing this instruction.
This instruction is executed using IC with the following syntax:
IC <ic_op>
This syntax uses the following encoding in the System instruction encoding space:
<ic_op> | op0 | op1 | CRn | CRm | op2 | Rt |
---|---|---|---|---|---|---|
IALLUIS | 01 | 000 | 0111 | 0001 | 000 | 11111 |
The instruction is executable as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | WO | n/a | WO |
x | 0 | 1 | - | WO | WO | WO |
x | 1 | 1 | - | n/a | WO | WO |
This table applies to all syntax that can be used to execute this instruction.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when executing this System instruction.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TPU==1, Non-secure execution of this instruction at EL1 is trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TPU==1, Non-secure execution of this instruction at EL1 is trapped to EL2.
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