The ID_AA64MMFR0_EL1 characteristics are:
Provides information about the implemented memory model and memory management support in AArch64 state.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.
This register is part of the Identification registers functional group.
There are no configuration notes.
ID_AA64MMFR0_EL1 is a 64-bit register.
The ID_AA64MMFR0_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
TGran4 | TGran64 | TGran16 | BigEndEL0 | SNSMem | BigEnd | ASIDBits | PARange | ||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Support for 4KB memory translation granule size. Defined values are:
TGran4 | Meaning |
---|---|
0000 |
4KB granule supported. |
1111 |
4KB granule not supported. |
All other values are reserved.
Support for 64KB memory translation granule size. Defined values are:
TGran64 | Meaning |
---|---|
0000 |
64KB granule supported. |
1111 |
64KB granule not supported. |
All other values are reserved.
Support for 16KB memory translation granule size. Defined values are:
TGran16 | Meaning |
---|---|
0000 |
16KB granule not supported. |
0001 |
16KB granule supported. |
All other values are reserved.
Mixed-endian support at EL0 only. Defined values are:
BigEndEL0 | Meaning |
---|---|
0000 |
No mixed-endian support at EL0. The SCTLR_EL1.E0E bit has a fixed value. |
0001 |
Mixed-endian support at EL0. The SCTLR_EL1.E0E bit can be configured. |
All other values are reserved.
This field is invalid and is RES0 if the BigEnd field, bits [11:8], is not 0000.
Secure versus Non-secure Memory distinction. Defined values are:
SNSMem | Meaning |
---|---|
0000 |
Does not support a distinction between Secure and Non-secure Memory. |
0001 |
Does support a distinction between Secure and Non-secure Memory. |
All other values are reserved.
Mixed-endian configuration support. Defined values are:
BigEnd | Meaning |
---|---|
0000 |
No mixed-endian support. The SCTLR_ELx.EE bits have a fixed value. See the BigEndEL0 field, bits[19:16], for whether EL0 supports mixed-endian. |
0001 |
Mixed-endian support. The SCTLR_ELx.EE and SCTLR_EL1.E0E bits can be configured. |
All other values are reserved.
Number of ASID bits. Defined values are:
ASIDBits | Meaning |
---|---|
0000 |
8 bits. |
0010 |
16 bits. |
All other values are reserved.
Physical Address range supported. Defined values are:
PARange | Meaning |
---|---|
0000 |
32 bits, 4GB. |
0001 |
36 bits, 64GB. |
0010 |
40 bits, 1TB. |
0011 |
42 bits, 4TB. |
0100 |
44 bits, 16TB. |
0101 |
48 bits, 256TB. |
0110 |
52 bits, 4PB. |
All other values are reserved.
In all ARMv8 implementations the values 0000, 0001, 0010, 0011, 0100 and 0101 are permitted.
From ARMv8.1 the value 0110 is permitted and indicates that ARMv8.2-LPA is implemented.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
ID_AA64MMFR0_EL1 | 11 | 000 | 0000 | 0111 | 000 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
18/04/2017 17:00
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