TLBI VMALLE1IS, TLB Invalidate by VMID, All at stage 1, EL1, Inner Shareable

The TLBI VMALLE1IS characteristics are:

Purpose

Invalidate cached copies of translation table entries from TLBs that meet all the following requirements:

The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this instructions.

Note

For the EL1&0 translation regime, the invalidation applies to both:

This System instruction is part of the TLB maintenance instructions functional group.

Configuration

There are no configuration notes.

Attributes

TLBI VMALLE1IS is a 64-bit System instruction.

Field descriptions

TLBI VMALLE1IS ignores the value in the register specified by the instruction encoding. Software does not have to write a value to the register before issuing this instruction.

Executing the TLBI VMALLE1IS instruction

This instruction is executed using TLBI with the following syntax:

TLBI <tlbi_op>

This syntax uses the following encoding in the System instruction encoding space:

<tlbi_op> op0op1CRnCRmop2Rt
VMALLE1IS010001000001100011111

Accessibility

The instruction is executable as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - WO n/a WO
001 - WOWOWO
011 - n/a WOWO
101 - WOWOWO
111 - n/a WOWO

This table applies to all syntax that can be used to execute this instruction.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when executing this System instruction.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :




18/04/2017 17:00

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