ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4

The ID_ISAR4_EL1 characteristics are:

Purpose

Provides information about the instruction sets implemented by the PE in AArch32 state.

Must be interpreted with ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1, and ID_ISAR5_EL1.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.

This register is part of the Identification registers functional group.

Configuration

AArch64 System register ID_ISAR4_EL1 is architecturally mapped to AArch32 System register ID_ISAR4.

In an implementation that supports only AArch64 state, this register is UNKNOWN.

Attributes

ID_ISAR4_EL1 is a 32-bit register.

Field descriptions

The ID_ISAR4_EL1 bit assignments are:

313029282726252423222120191817161514131211109876543210
SWP_fracPSR_MSynchPrim_fracBarrierSMCWritebackWithShiftsUnpriv

SWP_frac, bits [31:28]

Indicates support for the memory system locking the bus for SWP or SWPB instructions. Defined values are:

SWP_fracMeaning
0000

SWP or SWPB instructions not implemented.

0001

SWP or SWPB implemented but only in a uniprocessor context. SWP and SWPB do not guarantee whether memory accesses from other masters can come between the load memory access and the store memory access of the SWP or SWPB.

All other values are reserved. This field is valid only if the ID_ISAR0.Swap_instrs field is 0000.

In ARMv8-A the only permitted value is 0000.

PSR_M, bits [27:24]

Indicates the implemented M profile instructions to modify the PSRs. Defined values are:

PSR_MMeaning
0000

None implemented.

0001

Adds the M profile forms of the CPS, MRS, and MSR instructions.

All other values are reserved.

In ARMv8-A the only permitted value is 0000.

SynchPrim_frac, bits [23:20]

Used in conjunction with ID_ISAR3.SynchPrim to indicate the implemented Synchronization Primitive instructions. Possible values are:

SynchPrim_fracMeaning
0000

If SynchPrim == 0000, no Synchronization Primitives implemented. If SynchPrim == 0001, adds the LDREX and STREX instructions. If SynchPrim == 0010, also adds the CLREX, LDREXB, LDREXH, STREXB, STREXH, LDREXD, and STREXD instructions.

0011

If SynchPrim == 0001, adds the LDREX, STREX, CLREX, LDREXB, LDREXH, STREXB, and STREXH instructions.

All other combinations of SynchPrim and SynchPrim_frac are reserved.

In ARMv8-A the only permitted value is 0000.

Barrier, bits [19:16]

Indicates the implemented Barrier instructions in the A32 and T32 instruction sets. Defined values are:

BarrierMeaning
0000

None implemented. Barrier operations are provided only as System instructions in the (coproc==1111) encoding space.

0001

Adds the DMB, DSB, and ISB barrier instructions.

All other values are reserved.

In ARMv8-A the only permitted value is 0001.

SMC, bits [15:12]

Indicates the implemented SMC instructions. Defined values are:

SMCMeaning
0000

None implemented.

0001

Adds the SMC instruction.

All other values are reserved.

In ARMv8-A the permitted values are 0001 and 0000.

If EL1 cannot use AArch32 then this field has the value 0000.

Writeback, bits [11:8]

Indicates the support for Writeback addressing modes. Defined values are:

WritebackMeaning
0000

Basic support. Only the LDM, STM, PUSH, POP, SRS, and RFE instructions support writeback addressing modes. These instructions support all of their writeback addressing modes.

0001

Adds support for all of the writeback addressing modes.

All other values are reserved.

In ARMv8-A the only permitted value is 0001.

WithShifts, bits [7:4]

Indicates the support for instructions with shifts. Defined values are:

WithShiftsMeaning
0000

Nonzero shifts supported only in MOV and shift instructions.

0001

Adds support for shifts of loads and stores over the range LSL 0-3.

0011

As for 0001, and adds support for other constant shift options, both on load/store and other instructions.

0100

As for 0011, and adds support for register-controlled shift options.

All other values are reserved.

In ARMv8-A the only permitted value is 0100.

Unpriv, bits [3:0]

Indicates the implemented unprivileged instructions. Defined values are:

UnprivMeaning
0000

None implemented. No T variant instructions are implemented.

0001

Adds the LDRBT, LDRT, STRBT, and STRT instructions.

0010

As for 0001, and adds the LDRHT, LDRSBT, LDRSHT, and STRHT instructions.

All other values are reserved.

In ARMv8-A the only permitted value is 0010.

Accessing the ID_ISAR4_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
ID_ISAR4_EL11100000000010100

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RO n/a RO
x01 - RORORO
x11 - n/a RORO

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :




18/04/2017 17:00

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