ICC_SRE_EL3, Interrupt Controller System Register Enable register (EL3)

The ICC_SRE_EL3 characteristics are:

Purpose

Controls whether the System register interface or the memory-mapped interface to the GIC CPU interface is used for EL3.

This register is part of:

Configuration

AArch64 System register ICC_SRE_EL3 can be mapped to AArch32 System register ICC_MSRE, but this is not architecturally mandated.

Attributes

ICC_SRE_EL3 is a 32-bit register.

Field descriptions

The ICC_SRE_EL3 bit assignments are:

313029282726252423222120191817161514131211109876543210
0000000000000000000000000000EnableDIBDFBSRE

Bits [31:4]

Reserved, RES0.

Enable, bit [3]

Enable. Enables lower Exception level access to ICC_SRE_EL1 and ICC_SRE_EL2.

EnableMeaning
0

Secure EL1 accesses to Secure ICC_SRE_EL1 trap to EL3.

EL2 accesses to Non-secure ICC_SRE_EL1 and ICC_SRE_EL2 trap to EL3.

Non-secure EL1 accesses to ICC_SRE_EL1 trap to EL3, unless these accesses are trapped to EL2 as a result of ICC_SRE_EL3.Enable == 0.

1

Secure EL1 accesses to Secure ICC_SRE_EL1 do not trap to EL3.

EL2 accesses to Non-secure ICC_SRE_EL1 and ICC_SRE_EL2 do not trap to EL3.

Non-secure EL1 accesses to ICC_SRE_EL1 do not trap to EL3.

If ICC_SRE_EL3.SRE is RAO/WI, an implementation is permitted to make the Enable bit RAO/WI.

If ICC_SRE_EL3.SRE is 0, the Enable bit behaves as 1 for all purposes other than reading the value of the bit.

DIB, bit [2]

Disable IRQ bypass.

DIBMeaning
0

IRQ bypass enabled.

1

IRQ bypass disabled.

In systems that do not support IRQ bypass, this bit is RAO/WI.

When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.

DFB, bit [1]

Disable FIQ bypass.

DFBMeaning
0

FIQ bypass enabled.

1

FIQ bypass disabled.

In systems that do not support FIQ bypass, this bit is RAO/WI.

When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.

SRE, bit [0]

System Register Enable.

SREMeaning
0

The memory-mapped interface must be used. Access at EL3 to any ICH_* or ICC_* register other than ICC_SRE_EL1, ICC_SRE_EL2, or ICC_SRE_EL3 is trapped to EL3

1

The System register interface to the ICH_* registers and the EL1, EL2, and EL3 ICC_* registers is enabled for EL3.

If software changes this bit from 1 to 0, the results are UNPREDICTABLE.

GICv3 implementations that do not require GICv2 compatibility might choose to make this bit RAO/WI.

When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.

Accessing the ICC_SRE_EL3

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op1CRnCRmop2
ICC_SRE_EL311011001100101

Accessibility

The register is accessible as follows:

Control Accessibility
TGENSEL0EL1EL2EL3
x0 - - n/a RW
01 - - - RW
11 - n/a - RW

This table applies to all instructions that can access this register.

This register is always System register accessible.




18/04/2017 17:00

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