The PMCFGR characteristics are:
Contains PMU-specific configuration data.
This register is part of the Performance Monitors registers functional group.
This register is accessible as follows:
Off | DLK | OSLK | EPMAD | SLK | Default |
---|---|---|---|---|---|
Error | Error | Error | Error | RO | RO |
PMCFGR is in the Core power domain.
PMCFGR is a 32-bit register.
The PMCFGR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NCG | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | UEN | WT | NA | EX | CCD | CC | SIZE | N |
This feature is not supported, so this field is RAZ.
Reserved, RES0.
User-mode Enable Register supported. PMUSERENR_EL0 is not visible in the external debug interface, so this bit is RAZ.
This feature is not supported, so this bit is RAZ.
This feature is not supported, so this bit is RAZ.
Export supported. Value is IMPLEMENTATION DEFINED.
EX | Meaning |
---|---|
0 |
PMCR_EL0.X is RES0. |
1 |
PMCR_EL0.X is read/write. |
Cycle counter has prescale. This is RES1 if AArch32 is supported at any EL, and RAZ otherwise.
CCD | Meaning |
---|---|
0 |
PMCR_EL0.D is RES0. |
1 |
PMCR_EL0.D is read/write. |
Dedicated cycle counter (counter 31) supported. This bit is RAO.
Size of counters. This field determines the spacing of counters in the memory-map.
In ARMv8 the counters are at doubleword-aligned addresses, and the largest counter is 64-bits, so this field is 0b111111.
Number of counters implemented in addition to the cycle counter, PMCCNTR_EL0. The maximum number of event counters is 31.
N | Meaning |
---|---|
00000000 |
Only PMCCNTR_EL0 implemented. |
00000001 |
PMCCNTR_EL0 plus one event counter implemented. |
and so on up to 0b00011111, which indicates PMCCNTR_EL0 and 31 event counters implemented.
PMCFGR can be accessed through the external debug interface:
Component | Offset |
---|---|
PMU | 0xE00 |
18/04/2017 17:00
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