The DBGDSCRext characteristics are:
Main control register for the debug implementation.
This register is part of the Debug registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register DBGDSCRext is architecturally mapped to AArch64 System register MDSCR_EL1.
This register is required in all implementations.
This register is in the Warm reset domain. Some or all RW fields of this register have defined reset values. On a Warm or Cold reset these apply only if the PE resets into an Exception level that is using AArch32. Otherwise, on a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.
DBGDSCRext is a 32-bit register.
The DBGDSCRext bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | RXfull | TXfull | 0 | RXO | TXU | 0 | 0 | INTdis | TDA | 0 | SC2 | NS | SPNIDdis | SPIDdis | MDBGen | HDE | 0 | UDCCdis | 0 | 0 | 0 | 0 | 0 | ERR | MOE | 0 | 0 |
Reserved, RES0.
DTRRX full. Used for save/restore of EDSCR.RXfull.
When DBGOSLSR.OSLK == 0 (the OS lock is unlocked), this bit is RO, and software must treat it as UNK/SBZP.
When DBGOSLSR.OSLK == 1 (the OS lock is locked), this bit is RW and holds the value of EDSCR.RXfull.
ARM deprecates use of this bit other than for save/restore. Use DBGDSCRint to access the DTRRX full status.
Reads and writes of this bit are indirect accesses to EDSCR.RXfull.
The architected behavior of this field determines the value it returns after a reset.
DTRTX full. Used for save/restore of EDSCR.TXfull.
When DBGOSLSR.OSLK == 0 (the OS lock is unlocked), this bit is RO, and software must treat it as UNK/SBZP.
When DBGOSLSR.OSLK == 1 (the OS lock is locked), this bit is RW and holds the value of EDSCR.TXfull.
ARM deprecates use of this bit other than for save/restore. Use DBGDSCRint to access the DTRTX full status.
Reads and writes of this bit are indirect accesses to EDSCR.TXfull.
The architected behavior of this field determines the value it returns after a reset.
Reserved, RES0.
Used for save/restore of EDSCR.RXO.
When DBGOSLSR.OSLK == 0 (the OS lock is unlocked), this bit is RO, and software must treat it as UNK/SBZP.
When DBGOSLSR.OSLK == 1 (the OS lock is locked), this bit is RW and holds the value of EDSCR.RXO.
Reads and writes of this bit are indirect accesses to EDSCR.RXO.
The architected behavior of this field determines the value it returns after a reset.
Used for save/restore of EDSCR.TXU.
When DBGOSLSR.OSLK == 0 (the OS lock is unlocked), this bit is RO, and software must treat it as UNK/SBZP.
When DBGOSLSR.OSLK == 1 (the OS lock is locked), this bit is RW and holds the value of EDSCR.TXU.
Reads and writes of this bit are indirect accesses to EDSCR.TXU.
The architected behavior of this field determines the value it returns after a reset.
Reserved, RES0.
Used for save/restore of EDSCR.INTdis.
When DBGOSLSR.OSLK == 0 (the OS lock is unlocked), this field is RO, and software must treat it as UNK/SBZP.
When DBGOSLSR.OSLK == 1 (the OS lock is locked), this field is RW and holds the value of EDSCR.INTdis.
Reads and writes of this field are indirect accesses to EDSCR.INTdis.
The architected behavior of this field determines the value it returns after a reset.
Used for save/restore of EDSCR.TDA.
When DBGOSLSR.OSLK == 0 (the OS lock is unlocked), this bit is RO, and software must treat it as UNK/SBZP.
When DBGOSLSR.OSLK == 1 (the OS lock is locked), this bit is RW and holds the value of EDSCR.TDA.
Reads and writes of this bit are indirect accesses to EDSCR.TDA.
The architected behavior of this field determines the value it returns after a reset.
Reserved, RES0.
Reserved, RES0.
Used for save/restore of EDSCR.SC2.
When DBGOSLSR.OSLK == 0 (the OS lock is unlocked), this bit is RO, and software must treat it as UNK/SBZP.
When DBGOSLSR.OSLK == 1 (the OS lock is locked), this bit is RW and holds the value of EDSCR.SC2.
Reads and writes of this bit are indirect accesses to EDSCR.SC2.
If the PC Sample-based Profiling Extension is not implemented, then this field is RES0.
Non-secure status. Returns the inverse of IsSecure(). This bit is RO.
ARM deprecates use of this field.
Secure privileged profiling disabled status bit. This bit is RO. Permitted values are:
SPNIDdis | Meaning |
---|---|
0 |
If EL3 is implemented, profiling allowed in Secure privileged modes. |
1 |
If EL3 is implemented, profiling prohibited in Secure privileged modes. |
This field is RES0 if EL3 is not implemented.
ARM deprecates use of this field.
Secure privileged AArch32 invasive self-hosted debug disabled status bit. This bit is RO and depends on the value of SDCR.SPD and the pseudocode function AArch32.SelfHostedSecurePrivilegedInvasiveDebugEnabled(). Permitted values are:
SPIDdis | Meaning |
---|---|
0 |
Self-hosted debug enabled in Secure privileged AArch32 modes. |
1 |
Self-hosted debug disabled in Secure privileged AArch32 modes. |
This bit reads as 1 if any of the following is true and reads as 0 otherwise:
ARM deprecates use of this field.
Monitor debug events enable. Enable Breakpoint, Watchpoint, and Vector Catch exceptions.
MDBGen | Meaning |
---|---|
0 |
Breakpoint, Watchpoint, and Vector Catch exceptions disabled. |
1 |
Breakpoint, Watchpoint, and Vector Catch exceptions enabled. |
When this register has an architecturally-defined reset value, this field resets to 0.
Used for save/restore of EDSCR.HDE.
When DBGOSLSR.OSLK == 0 (the OS lock is unlocked), this bit is RO, and software must treat it as UNK/SBZP.
When DBGOSLSR.OSLK == 1 (the OS lock is locked), this bit is RW and holds the value of EDSCR.HDE.
Reads and writes of this bit are indirect accesses to EDSCR.HDE.
The architected behavior of this field determines the value it returns after a reset.
Reserved, RES0.
Traps EL0 accesses to the DCC registers to Undefined mode.
UDCCdis | Meaning |
---|---|
0 |
This control does not cause any instructions to be trapped. |
1 |
EL0 accesses to the DBGDSCRint, DBGDTRRXint, DBGDTRTXint, DBGDIDR, DBGDSAR, and DBGDRAR are trapped to Undefined mode. |
All accesses to these registers are trapped, including LDC and STC accesses to DBGDTRTXint and DBGDTRRXint, and MRRC accesses to DBGDSAR and DBGDRAR.
Traps of EL0 accesses to the DBGDTRRXint and DBGDTRTXint are ignored in Debug state.
When this register has an architecturally-defined reset value, this field resets to 0.
Reserved, RES0.
Used for save/restore of EDSCR.ERR.
When DBGOSLSR.OSLK == 0 (the OS lock is unlocked), this bit is RO, and software must treat it as UNK/SBZP.
When DBGOSLSR.OSLK == 1 (the OS lock is locked), this bit is RW and holds the value of EDSCR.ERR.
Reads and writes of this bit are indirect accesses to EDSCR.ERR.
The architected behavior of this field determines the value it returns after a reset.
Method of Entry for debug exception. When a debug exception is taken to an Exception level using AArch32, this field is set to indicate the event that caused the exception:
MOE | Meaning |
---|---|
0001 |
Breakpoint |
0011 |
Software breakpoint (BKPT) instruction |
0101 |
Vector catch |
1010 |
Watchpoint |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Reserved, RES0.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p14, 0, <Rt>, c0, c2, 2 | 000 | 010 | 0000 | 1110 | 0010 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RW | n/a | RW |
x | 0 | 1 | - | RW | RW | RW |
x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
Individual fields within this register might have restricted accessibility when DBGOSLSR.OSLK == 0 (the OS lock is unlocked.) See the field descriptions for more detail.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TDA==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HDCR.TDA==1, Non-secure accesses to this register from EL1 are trapped to Hyp mode.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TDA==1, accesses to this register from EL1 and EL2 are trapped to EL3.
18/04/2017 17:00
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