The CONTEXTIDR_EL1 characteristics are:
Identifies the current Process Identifier.
The value of the whole of this register is called the Context ID and is used by:
The significance of this register is for debug and trace use only.
This register is used:
When ARMv8.1-VHE is implemented and HCR_EL2.E2H is set to 1, CONTEXTIDR_EL2 is used.
This register is part of the Virtual memory control registers functional group.
AArch64 System register CONTEXTIDR_EL1 is architecturally mapped to AArch32 System register CONTEXTIDR.
RW fields in this register reset to architecturally UNKNOWN values.
CONTEXTIDR_EL1 is a 32-bit register.
The CONTEXTIDR_EL1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PROCID |
Process Identifier. This field must be programmed with a unique value that identifies the current process.
In AArch32 state, when TTBCR.EAE is set to 0, CONTEXTIDR.ASID holds the ASID.
In AArch64 state, CONTEXTIDR_EL1 is independent of the ASID, and for the EL1&0 translation regime either TTBR0_EL1 or TTBR1_EL1 holds the ASID.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
CONTEXTIDR_EL1 | 11 | 000 | 1101 | 0000 | 001 |
CONTEXTIDR_EL12 | 11 | 101 | 1101 | 0000 | 001 |
The register is accessible as follows:
<systemreg> | Control | Accessibility | |||||
---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | |
CONTEXTIDR_EL1 | x | x | 0 | - | RW | n/a | RW |
CONTEXTIDR_EL1 | 0 | 0 | 1 | - | RW | RW | RW |
CONTEXTIDR_EL1 | 0 | 1 | 1 | - | n/a | RW | RW |
CONTEXTIDR_EL1 | 1 | 0 | 1 | - | RW | CONTEXTIDR_EL2 | RW |
CONTEXTIDR_EL1 | 1 | 1 | 1 | - | n/a | CONTEXTIDR_EL2 | RW |
CONTEXTIDR_EL12 | x | x | 0 | - | - | n/a | - |
CONTEXTIDR_EL12 | 0 | 0 | 1 | - | - | - | - |
CONTEXTIDR_EL12 | 0 | 1 | 1 | - | n/a | - | - |
CONTEXTIDR_EL12 | 1 | 0 | 1 | - | - | RW | RW |
CONTEXTIDR_EL12 | 1 | 1 | 1 | - | n/a | RW | RW |
When HCR_EL2.E2H is 1, without explicit synchronization, access from EL3 using the mnemonic CONTEXTIDR_EL1 or CONTEXTIDR_EL12 are not guaranteed to be ordered with respect to accesses using the other mnemonic.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TRVM==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HCR_EL2.TVM==1, Non-secure write accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
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