CNTVOFF<n>, Counter-timer Virtual Offsets, n = 0 - 7

The CNTVOFF<n> characteristics are:

Purpose

Holds the 64-bit virtual offset for frame CNTBase<n>.

This register is part of the Generic Timer registers functional group.

Usage constraints

This register is accessible as follows:

Default
RW

In the CNTCTLBase frame a CNTVOFF<n> register must be implemented, as a RW register, for each CNTBaseN frame that has virtual timer capability.

Note

The value of <n> in an instance of CNTVOFF<n> specifies the value of N for the associated CNTBaseN frame.

In a system that recognizes two Security states, for any CNTVOFF<n> register in the CNTCTLBase frame:

The register location of any unimplemented CNTVOFF<n> register in the CNTCTLBase frame is RAZ/WI.

The CNTVOFF<n> register is accessible in the CNTBaseN frame using CNTVOFF.

In an implementation that supports 64-bit atomic accesses, then the CNTVOFF<n> registers must be accessible as atomic 64-bit values.

Configuration

The power domain of CNTVOFF<n> is IMPLEMENTATION DEFINED.

On a reset of the reset domain in which an RW instance of this register is implemented, RW fields in the register reset to UNKNOWN values. The register is not affected by a reset of any other reset domain. For more information see 'Power and reset domains for the system level implementation of the Generic Timer' in Chapter I1 of the ARMv8 ARM.

Attributes

CNTVOFF<n> is a 64-bit register.

Field descriptions

The CNTVOFF<n> bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
Virtual offset
Virtual offset
313029282726252423222120191817161514131211109876543210

Bits [63:0]

Virtual offset.

Accessing the CNTVOFF<n>

CNTVOFF<n>[31:0] can be accessed through its memory-mapped interface:

ComponentFrameOffset
TimerCNTCTLBase0x080 + 8n

CNTVOFF<n>[63:32] can be accessed through its memory-mapped interface:

ComponentFrameOffset
TimerCNTCTLBase0x084 + 8n



18/04/2017 17:00

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