PAR, Physical Address Register

The PAR characteristics are:

Purpose

Returns the output address (OA) from an Address translation instruction that executed successfully, or fault information if the instruction did not execute successfully.

This register is part of the Address translation instructions functional group.

Configuration

AArch32 System register PAR is architecturally mapped to AArch64 System register PAR_EL1.

The PAR returns a 32-bit value:

In these cases, PAR[63:32] is RES0.

Otherwise, the PAR returns a 64-bit value. This means it returns a 64-bit value in the following cases:

For PL1&0 stage 1 translations, TTBCR.EAE selects the translation table format.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

PAR is a 64-bit register that can also be accessed as a 32-bit value. If it is accessed as a 32-bit register, accesses read and write bits[31:0] and do not modify bits[63:32].

The Configurations section specifies the cases where each PAR format is used.

Field descriptions

The PAR bit assignments are:

For all register layouts:

F, bit [0]

Indicates whether the instruction performed a successful address translation.

FMeaning
0

Address translation completed successfully.

1

Address translation aborted.

When accessing PAR as a 32-bit register, PAR.F==0:

313029282726252423222120191817161514131211109876543210
PALPAENOSNSIMP DEFSHInner[2:0]Outer[1:0]SSF

This section describes the register value returned by the successful execution of an Address translation instruction. Software might subsequently write a different value to the register, and that write does not affect the operation of the PE.

On a successful conversion, the PAR can return a value that indicates the resulting attributes, rather than the values that appear in the translation table descriptors. More precisely:

PA, bits [31:12]

Output address. The output address (OA) corresponding to the supplied input address. This field returns address bits[31:12].

LPAE, bit [11]

When updating the PAR with the result of the translation operation, this bit is set as follows:

LPAEMeaning
0

Short-descriptor translation table format used. This means the PAR returned a 32-bit value.

NOS, bit [10]

Not Outer Shareable. When the returned value of PAR.SH is 1, indicates the Shareability attribute for the physical memory region:

NOSMeaning
0

Memory region is Outer Shareable.

1

Memory region is Inner Shareable.

When the returned value of PAR.SH is 0 the value returned to this field is UNKNOWN.

The value returned in this field can be the resulting attribute, as determined by any permitted implementation choices and any applicable configuration bits, instead of the value that appears in the translation table descriptor.

NS, bit [9]

Non-secure. The NS attribute for a translation table entry from a Secure translation regime.

For a result from a Secure translation regime, this bit reflects the Security state of the physical address space of the translation. This means it reflects the effect of the NSTable bits of earlier levels of the translation table walk if those NSTable bits have an effect on the translation.

For a result from a Non-secure translation regime, this bit is UNKNOWN.

IMP DEF, bit [8]

IMPLEMENTATION DEFINED.

SH, bit [7]

Shareability. Indicates whether the physical memory region is Non-shareable:

SHMeaning
0

Memory is Non-shareable.

1

Memory is shareable, and PAR.NOS indicates whether the region is Outer Shareable or Inner Shareable.

The value returned in this field can be the resulting attribute, as determined by any permitted implementation choices and any applicable configuration bits, instead of the value that appears in the translation table descriptor.

Inner[2:0], bits [6:4]

Inner cacheability attribute for the region. Permitted values are:

InnerMeaning
000

Non-cacheable.

001

Device-nGnRnE.

011

Device-nGnRE.

101

Write-Back, Write-Allocate.

110

Write-Through.

111

Write-Back, no Write-Allocate.

The values 010 and 100 are reserved.

The value returned in this field can be the resulting attribute, as determined by any permitted implementation choices and any applicable configuration bits, instead of the value that appears in the translation table descriptor.

Outer[1:0], bits [3:2]

Outer cacheability attribute for the region. Permitted values are:

OuterMeaning
00

Non-cacheable.

01

Write-Back, Write-Allocate.

10

Write-Through, no Write-Allocate.

11

Write-Back, no Write-Allocate.

The value returned in this field can be the resulting attribute, as determined by any permitted implementation choices and any applicable configuration bits, instead of the value that appears in the translation table descriptor.

SS, bit [1]

Supersection. Used to indicate if the result is a Supersection:

SSMeaning
0

Result is not a Supersection. PAR[31:12] contains OA[31:12].

1

Result is a Supersection, and:

  • PAR[31:24] contains OA[31:24].
  • PAR[23:16] contains OA[39:32].
  • PAR[15:12] contains 0b0000.

If an implementation supports less than 40 bits of physical address, the bits in the PAR field that correspond to physical address bits that are not implemented are UNKNOWN.

F, bit [0]

Indicates whether the instruction performed a successful address translation.

FMeaning
0

Address translation completed successfully.

When accessing PAR as a 32-bit register, PAR.F==1:

313029282726252423222120191817161514131211109876543210
IMP DEF0000LPAE0000FSF

This section describes the register value returned by a fault on the execution of an Address translation instruction. Software might subsequently write a different value to the register, and that write does not affect the operation of the PE.

IMP DEF, bits [31:16]

IMPLEMENTATION DEFINED.

Bits [15:12]

Reserved, RES0.

LPAE, bit [11]

When updating the PAR with the result of the translation operation, this bit is set as follows:

LPAEMeaning
0

Short-descriptor translation table format used. This means the PAR returned a 32-bit value.

Bits [10:7]

Reserved, RES0.

FS, bits [6:1]

Fault status bits. Bits [12,10,3:0] from the DFSR, indicating the source of the abort.

F, bit [0]

Indicates whether the instruction performed a successful address translation.

FMeaning
1

Address translation aborted.

When accessing PAR as a 64-bit register, PAR.F==0:

6362616059585756555453525150494847464544434241403938373635343332
ATTR0000000000000000PA
PALPAEIMP DEFNSSH000000F
313029282726252423222120191817161514131211109876543210

This section describes the register value returned by the successful execution of an Address translation instruction. Software might subsequently write a different value to the register, and that write does not affect the operation of the PE.

On a successful conversion, the PAR can return a value that indicates the resulting attributes, rather than the values that appear in the translation table descriptors. More precisely:

ATTR, bits [63:56]

Memory attributes for the returned output address. This field uses the same encoding as the Attr<n> fields in MAIR0 and MAIR1.

The value returned in this field can be the resulting attribute, as determined by any permitted implementation choices and any applicable configuration bits, instead of the value that appears in the translation table descriptor.

Bits [55:40]

Reserved, RES0.

PA, bits [39:12]

Output address. The output address (OA) corresponding to the supplied input address. This field returns address bits[39:12].

LPAE, bit [11]

When updating the PAR with the result of the translation operation, this bit is set as follows:

LPAEMeaning
1

Long-descriptor translation table format used. This means the PAR returned a 64-bit value.

IMP DEF, bit [10]

IMPLEMENTATION DEFINED.

NS, bit [9]

Non-secure. The NS attribute for a translation table entry from a Secure translation regime.

For a result from a Secure translation regime, this bit reflects the Security state of the physical address space of the translation. This means it reflects the effect of the NSTable bits of earlier levels of the translation table walk if those NSTable bits have an effect on the translation.

For a result from a Non-secure translation regime, this bit is UNKNOWN.

SH, bits [8:7]

Shareability attribute, for the returned output address. Permitted values are:

SHMeaning
00

Non-shareable.

10

Outer Shareable.

11

Inner Shareable.

The value 01 is reserved.

Note

This field returns the value 10 for:

The value returned in this field can be the resulting attribute, as determined by any permitted implementation choices and any applicable configuration bits, instead of the value that appears in the translation table descriptor.

Bits [6:1]

Reserved, RES0.

F, bit [0]

Indicates whether the instruction performed a successful address translation.

FMeaning
0

Address translation completed successfully.

When accessing PAR as a 64-bit register, PAR.F==1:

6362616059585756555453525150494847464544434241403938373635343332
IMP DEFIMP DEFIMP DEF0000000000000000
00000000000000000000LPAE0FSTAGES2WLK0FSTF
313029282726252423222120191817161514131211109876543210

This section describes the register value returned by a fault on the execution of an Address translation instruction. Software might subsequently write a different value to the register, and that write does not affect the operation of the PE.

IMP DEF, bits [63:56]

IMPLEMENTATION DEFINED.

IMP DEF, bits [55:52]

IMPLEMENTATION DEFINED.

IMP DEF, bits [51:48]

IMPLEMENTATION DEFINED.

Bits [47:12]

Reserved, RES0.

LPAE, bit [11]

When updating the PAR with the result of the translation operation, this bit is set as follows:

LPAEMeaning
1

Long-descriptor translation table format used. This means the PAR returned a 64-bit value.

Bit [10]

Reserved, RES0.

FSTAGE, bit [9]

Indicates the translation stage at which the translation aborted:

FSTAGEMeaning
0

Translation aborted because of a fault in the stage 1 translation.

1

Translation aborted because of a fault in the stage 2 translation.

S2WLK, bit [8]

If this bit is set to 1, it indicates the translation aborted because of a stage 2 fault during a stage 1 translation table walk.

Bit [7]

Reserved, RES0.

FST, bits [6:1]

Fault status field. Values are as in the DFSR.STATUS and IFSR.STATUS fields when using the Long-descriptor translation table format.

F, bit [0]

Indicates whether the instruction performed a successful address translation.

FMeaning
1

Address translation aborted.

Accessing the PAR

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 0, <Rt>, c7, c4, 0000000011111110100

This register can be read using MRRC with the following syntax:

MRRC <syntax>

This register can be written using MCRR with the following syntax:

MCRR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1coprocCRm
p15, 0, <Rt>, <Rt2>, c7000011110111

Accessibility

The register is accessible as follows:

Configuration Control Accessibility Instance
E2HTGENSEL0EL1EL2EL3
EL3 not implemented xx0 - RW n/a n/a PAR
EL3 not implemented x01 - RWRW n/a PAR
EL3 not implemented x11 - n/a RW n/a PAR
EL3 using AArch64xx0 - RW n/a n/a PAR
EL3 using AArch64x01 - RWRW n/a PAR
EL3 using AArch64x11 - n/a RW n/a PAR
EL3 using AArch32x01 - RWRWRWPAR_ns
EL3 using AArch32x11 - n/a RWRWPAR_ns
EL3 using AArch32xx0 - n/a n/a RWPAR_s

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :




18/04/2017 17:00

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