The MVFR1 characteristics are:
Describes the features provided by the AArch32 Advanced SIMD and Floating-point implementation.
Must be interpreted with MVFR0 and MVFR2.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section G4.14.6.
This register is part of:
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register MVFR1 is architecturally mapped to AArch64 System register MVFR1_EL1.
Implemented only if the implementation includes Advanced SIMD and floating-point instructions.
MVFR1 is a 32-bit register.
The MVFR1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SIMDFMAC | FPHP | SIMDHP | SIMDSP | SIMDInt | SIMDLS | FPDNaN | FPFtZ |
Advanced SIMD Fused Multiply-Accumulate. Indicates whether the Advanced SIMD implementation provides fused multiply accumulate instructions. Defined values are:
SIMDFMAC | Meaning |
---|---|
0000 |
Not implemented. |
0001 |
Implemented. |
All other values are reserved.
In ARMv8-A the permitted values are 0000 and 0001.
The Advanced SIMD and floating-point implementations must provide the same level of support for these instructions.
Floating Point Half Precision. Indicates the level of half-precision floating-point support. Defined values are:
FPHP | Meaning |
---|---|
0000 |
Not supported. |
0001 |
Floating-point half-precision conversion instructions are supported for conversion between single-precision and half-precision. |
0010 |
Floating-point half-precision conversion instructions are supported for conversion between single-precision and half-precision and between double-precision and half-precision. |
0011 |
As for 0010, and also includes support for half-precision floating-point arithmetic. |
All other values are reserved.
The permitted values are:
Advanced SIMD Half Precision. Indicates the level of half-precision floating-point support. Defined values are:
SIMDHP | Meaning |
---|---|
0000 |
Not supported. |
0001 |
SIMD half-precision conversion instructions are supported for conversion between single-precision and half-precision. |
0010 |
As for 0010, and also includes support for half-precision floating-point arithmetic. |
All other values are reserved.
The permitted values are:
Advanced SIMD Single Precision. Indicates whether the Advanced SIMD and floating-point implementation provides single-precision floating-point instructions. Defined values are:
SIMDSP | Meaning |
---|---|
0000 |
Not implemented. |
0001 |
Implemented. This value is permitted only if the SIMDInt field is 0001. |
All other values are reserved.
In ARMv8-A the permitted values are 0000 and 0001.
Advanced SIMD Integer. Indicates whether the Advanced SIMD and floating-point implementation provides integer instructions. Defined values are:
SIMDInt | Meaning |
---|---|
0000 |
Not implemented. |
0001 |
Implemented. |
All other values are reserved.
In ARMv8-A the permitted values are 0000 and 0001.
Advanced SIMD Load/Store. Indicates whether the Advanced SIMD and floating-point implementation provides load/store instructions. Defined values are:
SIMDLS | Meaning |
---|---|
0000 |
Not implemented. |
0001 |
Implemented. |
All other values are reserved.
In ARMv8-A the permitted values are 0000 and 0001.
Default NaN mode. Indicates whether the floating-point implementation provides support only for the Default NaN mode. Defined values are:
FPDNaN | Meaning |
---|---|
0000 |
Not implemented, or hardware supports only the Default NaN mode. |
0001 |
Hardware supports propagation of NaN values. |
All other values are reserved.
In ARMv8-A the permitted values are 0000 and 0001.
Flush to Zero mode. Indicates whether the floating-point implementation provides support only for the Flush-to-Zero mode of operation. Defined values are:
FPFtZ | Meaning |
---|---|
0000 |
Not implemented, or hardware supports only the Flush-to-Zero mode of operation. |
0001 |
Hardware supports full denormalized number arithmetic. |
All other values are reserved.
In ARMv8-A the permitted values are 0000 and 0001.
This register can be read using VMRS with the following syntax:
VMRS <Rt>, <spec_reg>
This syntax uses the following encoding in the System instruction encoding space:
<spec_reg> | reg |
---|---|
MVFR1 | 0110 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When HCR_EL2.E2H==0 :
If CPACR.cp10==00, read accesses to this register from PL1 are UNDEFINED.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If CPTR_EL2.TFP==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If CPTR_EL2.FPEN==00, Non-secure read accesses to this register from EL1 are trapped to EL2.
If CPTR_EL2.FPEN==10, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HCPTR.TCP10==1, Non-secure read accesses to this register from EL1 are trapped to Hyp mode.
If HCPTR.TCP10==1, Non-secure read accesses to this register from EL2 are UNDEFINED.
If HCR.TID3==1, Non-secure read accesses to this register from EL1 are trapped to Hyp mode.
When EL3 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If NSACR.cp10==0, Non-secure read accesses to this register from EL1 and EL2 are UNDEFINED.
When EL3 is implemented and is using AArch64 :
If CPTR_EL3.TFP==1, read accesses to this register from EL1 and EL2 are trapped to EL3.
18/04/2017 17:00
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