ID_AA64DFR0_EL1, AArch64 Debug Feature Register 0

The ID_AA64DFR0_EL1 characteristics are:

Purpose

Provides top level information about the debug system in AArch64 state.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.

This register is part of the Identification registers functional group.

Configuration

The external register EDDFR gives information from this register.

Attributes

ID_AA64DFR0_EL1 is a 64-bit register.

Field descriptions

The ID_AA64DFR0_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
0000000000000000000000000000PMSVer
CTX_CMPs0000WRPs0000BRPsPMUVerTraceVerDebugVer
313029282726252423222120191817161514131211109876543210

Bits [63:36]

Reserved, RES0.

PMSVer, bits [35:32]
In ARMv8.2:

Statistical Profiling Extension version. When the Statistical Profiling Extension is implemented, the defined values of this field are:

PMSVerMeaning
0000

No Statistical Profiling extension.

0001

Version 1 of the Statistical Profiling extension present.

All other values are reserved.

When the Statistical Profiling Extension is not implemented this field is reserved, RES0.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

CTX_CMPs, bits [31:28]

Number of breakpoints that are context-aware, minus 1. These are the highest numbered breakpoints.

Bits [27:24]

Reserved, RES0.

WRPs, bits [23:20]

Number of watchpoints, minus 1. The value of 0b0000 is reserved.

Bits [19:16]

Reserved, RES0.

BRPs, bits [15:12]

Number of breakpoints, minus 1. The value of 0b0000 is reserved.

PMUVer, bits [11:8]

Performance Monitors Extension version. Indicates whether System register interface to Performance Monitors extension is implemented. Defined values are:

PMUVerMeaning
0000

Performance Monitors Extension System registers not implemented.

0001

Performance Monitors Extension System registers implemented, PMUv3.

0100

Performance Monitors Extension System registers implemented, PMUv3, with a 16-bit evtCount field, and if EL2 is implemented, the addition of the MDCR_EL2.HPMD bit.

1111

IMPLEMENTATION DEFINED form of performance monitors supported, PMUv3 not supported.

All other values are reserved.

In ARMv8.0 the permitted values are 0b0000, 0b0001 and 0b1111.

From ARMv8.1 the permitted values are 0b0000, 0b0100 and 0b1111.

TraceVer, bits [7:4]

Trace support. Indicates whether System register interface to a trace macrocell is implemented. Defined values are:

TraceVerMeaning
0000

Trace macrocell System registers not implemented.

0001

Trace macrocell System registers implemented.

All other values are reserved.

A value of 0b0000 only indicates that no System register interface to a trace macrocell is implemented. A trace macrocell might nevertheless be implemented without a System register interface.

DebugVer, bits [3:0]

Debug architecture version. Indicates presence of ARMv8 debug architecture.

DebugVerMeaning
0110

ARMv8 debug architecture.

0111

ARMv8 debug architecture with Virtualization Host Extensions.

1000

ARMv8.2 debug architecture

All other values are reserved.

In an ARMv8.0 implementation, the only permitted value is 0b0110.

In an ARMv8.1 implementation that includes ARMv8.1-VHE, the only permitted value is 0b0111.

In an ARMv8.1 implementation that does not include ARMv8.1-VHE, the permitted values are 0b0110 and 0b0111.

In an ARMv8.2 implementation, the only permitted value is 0b1000.

Accessing the ID_AA64DFR0_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
ID_AA64DFR0_EL11100000000101000

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RO n/a RO
x01 - RORORO
x11 - n/a RORO

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :




18/04/2017 17:00

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