The AFSR1_EL3 characteristics are:
Provides additional IMPLEMENTATION DEFINED fault status information for exceptions taken to EL3.
This register is part of:
RW fields in this register reset to architecturally UNKNOWN values.
AFSR1_EL3 is a 32-bit register.
The AFSR1_EL3 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED |
IMPLEMENTATION DEFINED.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
AFSR1_EL3 | 11 | 110 | 0101 | 0001 | 001 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | - | n/a | RW |
x | 0 | 1 | - | - | - | RW |
x | 1 | 1 | - | n/a | - | RW |
This table applies to all instructions that can access this register.
18/04/2017 17:00
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