AMAIR_EL2, Auxiliary Memory Attribute Indirection Register (EL2)

The AMAIR_EL2 characteristics are:

Purpose

Provides IMPLEMENTATION DEFINED memory attributes for the memory regions specified by MAIR_EL2.

This register is part of:

Configuration

AArch64 System register AMAIR_EL2 bits [31:0] are architecturally mapped to AArch32 System register HAMAIR0.

AArch64 System register AMAIR_EL2 bits [63:32] are architecturally mapped to AArch32 System register HAMAIR1.

If EL2 is not implemented, this register is RES0 from EL3.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

AMAIR_EL2 is a 64-bit register.

Field descriptions

The AMAIR_EL2 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
IMPLEMENTATION DEFINED
IMPLEMENTATION DEFINED
313029282726252423222120191817161514131211109876543210

AMAIR_EL2 is permitted to be cached in a TLB.

IMPLEMENTATION DEFINED, bits [63:0]

IMPLEMENTATION DEFINED.

Accessing the AMAIR_EL2

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
AMAIR_EL21110010100011000
AMAIR_EL11100010100011000

Accessibility

The register is accessible as follows:

<systemreg> Control Accessibility
E2HTGENSEL0EL1EL2EL3
AMAIR_EL2xx0 - - n/a RW
AMAIR_EL2001 - - RWRW
AMAIR_EL2011 - n/a RWRW
AMAIR_EL2101 - - RWRW
AMAIR_EL2111 - n/a RWRW
AMAIR_EL1xx0 - AMAIR_EL1 n/a AMAIR_EL1
AMAIR_EL1001 - AMAIR_EL1 AMAIR_EL1 AMAIR_EL1
AMAIR_EL1011 - n/a AMAIR_EL1 AMAIR_EL1
AMAIR_EL1101 - AMAIR_EL1 RW AMAIR_EL1
AMAIR_EL1111 - n/a RW AMAIR_EL1

When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic AMAIR_EL2 or AMAIR_EL1 are not guaranteed to be ordered with respect to accesses using the other mnemonic.




18/04/2017 17:00

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