The SPSel characteristics are:
Allows the Stack Pointer to be selected between SP_EL0 and SP_ELx.
This register is part of the Process state registers functional group.
Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.
SPSel is a 32-bit register.
The SPSel bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SP |
Reserved, RES0.
Stack pointer to use. Possible values of this bit are:
SP | Meaning |
---|---|
0 |
Use SP_EL0 at all Exception levels. |
1 |
Use SP_ELx for Exception level ELx. |
When this register has an architecturally-defined reset value, this field resets to 1.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
SPSel | 11 | 000 | 0100 | 0010 | 000 |
This register can be modified using MSR (immediate) with the following syntax:
MSR <pstatefield>, <imm>
This syntax uses the following encoding in the System instruction encoding space:
<pstatefield> | op0 | op1 | CRn | op2 |
---|---|---|---|---|
SPSel | 00 | 000 | 0100 | 101 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RW | n/a | RW |
x | 0 | 1 | - | RW | RW | RW |
x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
18/04/2017 17:00
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