The CNTPS_CVAL_EL1 characteristics are:
Holds the compare value for the secure physical timer, usually accessible at EL3 but configurably accessible at EL1 in Secure state.
This register is part of the Generic Timer registers functional group.
RW fields in this register reset to architecturally UNKNOWN values.
CNTPS_CVAL_EL1 is a 64-bit register.
The CNTPS_CVAL_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
CompareValue | |||||||||||||||||||||||||||||||
CompareValue | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Holds the secure physical timer CompareValue.
When CNTPS_CTL_EL1.ENABLE is 1, the timer condition is met when (CNTPCT_EL0 - CompareValue) is greater than zero. This means that CompareValue acts like a 64-bit upcounter timer. When the timer condition is met:
When CNTPS_CTL_EL1.ENABLE is 0, the timer condition is not met, but CNTPCT_EL0 continues to count.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
CNTPS_CVAL_EL1 | 11 | 111 | 1110 | 0010 | 010 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RW | n/a | RW |
0 | 0 | 1 | - | - | - | RW |
0 | 1 | 1 | - | n/a | - | RW |
1 | 0 | 1 | - | - | - | RW |
1 | 1 | 1 | - | n/a | - | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL3 is implemented and is using AArch64 and SCR_EL3.NS==0 :
If SCR_EL3.ST==0, Secure accesses to this register from EL1 are trapped to EL3.
18/04/2017 17:00
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