The DAIF characteristics are:
Allows access to the interrupt mask bits.
This register is part of the Process state registers functional group.
Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.
DAIF is a 32-bit register.
The DAIF bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | D | A | I | F | 0 | 0 | 0 | 0 | 0 | 0 |
Reserved, RES0.
Process state D mask. The possible values of this bit are:
D | Meaning |
---|---|
0 |
Watchpoint, Breakpoint, and Software Step exceptions targeted at the current Exception level are not masked. |
1 |
Watchpoint, Breakpoint, and Software Step exceptions targeted at the current Exception level are masked. |
When the target Exception level of the debug exception is higher than the current Exception level, the exception is not masked by this bit.
When this register has an architecturally-defined reset value, this field resets to 1.
SError interrupt mask bit. The possible values of this bit are:
A | Meaning |
---|---|
0 |
Exception not masked. |
1 |
Exception masked. |
When this register has an architecturally-defined reset value, this field resets to 1.
IRQ mask bit. The possible values of this bit are:
I | Meaning |
---|---|
0 |
Exception not masked. |
1 |
Exception masked. |
When this register has an architecturally-defined reset value, this field resets to 1.
FIQ mask bit. The possible values of this bit are:
F | Meaning |
---|---|
0 |
Exception not masked. |
1 |
Exception masked. |
When this register has an architecturally-defined reset value, this field resets to 1.
Reserved, RES0.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
DAIF | 11 | 011 | 0100 | 0010 | 001 |
This register can be modified using MSR (immediate) with the following syntax:
MSR <pstatefield>, <imm>
This syntax uses the following encoding in the System instruction encoding space:
<pstatefield> | op0 | op1 | CRn | op2 |
---|---|---|---|---|
DAIFSet | 00 | 011 | 0100 | 110 |
DAIFClr | 00 | 011 | 0100 | 111 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | RW | RW | n/a | RW |
x | 0 | 1 | RW | RW | RW | RW |
x | 1 | 1 | RW | n/a | RW | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If SCTLR_EL1.UMA==0, accesses to this register from EL0 are trapped to EL1.
18/04/2017 17:00
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