The GITS_TRANSLATER characteristics are:
Written by a requesting a Device to signal an interrupt for translation by the ITS.
This register is part of the GIC ITS registers functional group.
This register is accessible as follows:
Security disabled | Secure | Non-secure |
---|---|---|
WO | WO | WO |
16-bit access to bits [15:0] of this register must be supported. When this register is written by a 16-bit transaction, bits [31:16] are written as zero.
Implementations must ensure that:
Writes to this register are ignored if any of the following are true:
Translation requests that result from writes to this register are subject to certain ordering rules. See Ordering of translations following writes to GITS_TRANSLATER for more information.
This register is at the same offset as GICD_SETSPI_NSR in the Distributor, and is at the same offset as GICR_SETLPIR in the Redistributor.
GITS_TRANSLATER is a 32-bit register.
The GITS_TRANSLATER bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EventID |
An identifier corresponding to the interrupt to be translated.
The size of the EventID is DeviceID specific, and set when the DeviceID is mapped to an ITT (using MAPD).
The number of EventID bits implemented is reported by GITS_TYPER.ID_bits. If a write specifies non-zero identifiers bits outside this range behavior is a CONSTRAINED UNPREDICTABLE choice between:
The DeviceID presented to an ITS is used to index a device table. The device table maps the DeviceID to an interrupt translation table for that device.
GITS_TRANSLATER can be accessed through its memory-mapped interface:
Component | Offset |
---|---|
GIC ITS translation | 0x0040 |
18/04/2017 17:00
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