The PAN characteristics are:
When ARMv8.1-PAN is implemented, allows access to the Privileged Access Never bit.
When ARMv8.1-PAN is not implemented, this register is not implemented.
This register is part of the Process state registers functional group.
This register is introduced in ARMv8.1.
PAN is a 32-bit register.
The PAN bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | PAN | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Reserved, RES0.
Privileged Access Never. Defined values are:
PAN | Meaning |
---|---|
0 |
The translation system is the same as ARMv8.0. |
1 |
Disables privileged read and write accesses to addresses accessible at EL0. |
The value of this bit is usually preserved on taking an exception, except in the following situations:
Reserved, RES0.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
PAN | 11 | 000 | 0100 | 0010 | 011 |
This register can be modified using MSR (immediate) with the following syntax:
MSR <pstatefield>, <imm>
This syntax uses the following encoding in the System instruction encoding space:
<pstatefield> | op0 | op1 | CRn | op2 |
---|---|---|---|---|
PAN | 00 | 000 | 0100 | 100 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RW | n/a | RW |
x | 0 | 1 | - | RW | RW | RW |
x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
18/04/2017 17:00
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