The ICC_MCTLR characteristics are:
Controls aspects of the behavior of the GIC CPU interface and provides information about the features implemented.
This register is part of:
This register is only accessible in Secure state.
AArch32 System register ICC_MCTLR can be mapped to AArch64 System register ICC_CTLR_EL3, but this is not architecturally mandated.
ICC_MCTLR is a 32-bit register.
The ICC_MCTLR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | nDS | 0 | A3V | SEIS | IDbits | PRIbits | 0 | PMHE | RM | EOImode_EL1NS | EOImode_EL1S | EOImode_EL3 | CBPR_EL1NS | CBPR_EL1S |
Reserved, RES0.
Disable Security not supported. Read-only and writes are ignored. Possible values are:
nDS | Meaning |
---|---|
0 |
The CPU interface logic supports disabling of security. |
1 |
The CPU interface logic does not support disabling of security, and requires that security is not disabled. |
Reserved, RES0.
Affinity 3 Valid. Read-only and writes are ignored. Possible values are:
A3V | Meaning |
---|---|
0 |
The CPU interface logic does not support non-zero values of the Aff3 field in SGI generation System registers. |
1 |
The CPU interface logic supports non-zero values of the Aff3 field in SGI generation System registers. |
If EL3 is present, ICC_CTLR.AV3 is an alias of ICC_MCTLR.A3V
SEI Support. Read-only and writes are ignored. Indicates whether the CPU interface supports generation of SEIs:
SEIS | Meaning |
---|---|
0 |
The CPU interface logic does not support generation of SEIs. |
1 |
The CPU interface logic supports generation of SEIs. |
If EL3 is present, ICC_CTLR.SEIS is an alias of ICC_MCTLR.SEIS
Identifier bits. Read-only and writes are ignored. The number of physical interrupt identifier bits supported:
IDbits | Meaning |
---|---|
000 |
16 bits. |
001 |
24 bits. |
All other values are reserved.
If EL3 is present, ICC_CTLR.IDbits is an alias of ICC_MCTLR.IDbits
Priority bits. Read-only and writes are ignored. The number of priority bits implemented, minus one.
An implementation that supports two Security states must implement at least 32 levels of physical priority (5 priority bits).
An implementation that supports only a single Security state must implement at least 16 levels of physical priority (4 priority bits).
This field always returns the number of priority bits implemented, regardless of the value of SCR.NS or the value of GICD_CTLR.DS.
The division between group priority and subpriority is defined in the binary point registers ICC_BPR0 and ICC_BPR1.
This field determines the minimum value of ICC_BPR0.
Reserved, RES0.
Priority Mask Hint Enable.
PMHE | Meaning |
---|---|
0 |
Disables use of the priority mask register as a hint for interrupt distribution. |
1 |
Enables use of the priority mask register as a hint for interrupt distribution. |
Software must write ICC_PMR to 0xFF before clearing this field to 0.
An implementation might choose to make this field RAO/WI.
If EL3 is present, ICC_CTLR.PMHE is an alias of ICC_MCTLR.PMHE.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.
SBZ.
The equivalent bit in AArch64 is the Routing Modifier bit. This feature is not supported when EL3 is using AArch32.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
EOI mode for interrupts handled at Non-secure EL1 and EL2. Controls whether a write to an End of Interrupt register also deactivates the interrupt:
EOImode_EL1NS | Meaning |
---|---|
0 |
ICC_EOIR0 and ICC_EOIR1 provide both priority drop and interrupt deactivation functionality. Accesses to ICC_DIR are UNPREDICTABLE. |
1 |
ICC_EOIR0 and ICC_EOIR1 provide priority drop functionality only. ICC_DIR provides interrupt deactivation functionality. |
If EL3 is present, ICC_CTLR(NS).EOImode is an alias of ICC_MCTLR.EOImode_EL1NS.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
EOI mode for interrupts handled at Secure EL1. Controls whether a write to an End of Interrupt register also deactivates the interrupt:
EOImode_EL1S | Meaning |
---|---|
0 |
ICC_EOIR0 and ICC_EOIR1 provide both priority drop and interrupt deactivation functionality. Accesses to ICC_DIR are UNPREDICTABLE. |
1 |
ICC_EOIR0 and ICC_EOIR1 provide priority drop functionality only. ICC_DIR provides interrupt deactivation functionality. |
If EL3 is present, ICC_CTLR(S).EOImode is an alias of ICC_MCTLR.EOImode_EL1S.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
EOI mode for interrupts handled at EL3. Controls whether a write to an End of Interrupt register also deactivates the interrupt:
EOImode_EL3 | Meaning |
---|---|
0 |
ICC_EOIR0 and ICC_EOIR1 provide both priority drop and interrupt deactivation functionality. Accesses to ICC_DIR are UNPREDICTABLE. |
1 |
ICC_EOIR0 and ICC_EOIR1 provide priority drop functionality only. ICC_DIR provides interrupt deactivation functionality. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Common Binary Point Register, EL1 Non-secure. Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1 and EL2:
CBPR_EL1NS | Meaning |
---|---|
0 |
ICC_BPR0 determines the preemption group for Group 0 interrupts only. ICC_BPR1 determines the preemption group for Non-secure Group 1 interrupts. |
1 |
ICC_BPR0 determines the preemption group for Group 0 interrupts and Non-secure Group 1 interrupts. Non-secure accesses to GICC_BPR and ICC_BPR1 access the state of ICC_BPR0. |
If EL3 is present, ICC_CTLR(NS).CBPR is an alias of ICC_MCTLR.CBPR_EL1NS.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Common Binary Point Register, EL1 Secure. Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes:
CBPR_EL1S | Meaning |
---|---|
0 |
ICC_BPR0 determines the preemption group for Group 0 interrupts only. ICC_BPR1 determines the preemption group for Secure Group 1 interrupts. |
1 |
ICC_BPR0 determines the preemption group for Group 0 interrupts and Secure Group 1 interrupts. Secure EL1 accesses, or EL3 accesses when not in Monitor mode, to ICC_BPR1 access the state of ICC_BPR0. |
If EL3 is present, ICC_CTLR(S).CBPR is an alias of ICC_MCTLR.CBPR_EL1S.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 6, <Rt>, c12, c12, 4 | 110 | 100 | 1100 | 1111 | 1100 |
The register is accessible as follows:
Control | Accessibility | ||||
---|---|---|---|---|---|
TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | 0 | - | - | n/a | RW |
0 | 1 | - | - | - | RW |
1 | 1 | - | n/a | - | RW |
This table applies to all instructions that can access this register.
This register is only accessible when executing in Monitor mode.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_MSRE.SRE==0, accesses to this register from EL3 are UNDEFINED.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==0 :
If HSTR_EL2.T12==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T12==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HSTR.T12==1, Non-secure accesses to this register from EL1 are trapped to Hyp mode.
18/04/2017 17:00
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