The TLBI IPAS2E1IS characteristics are:
If EL2 is implemented, invalidate cached copies of translation table entries from TLBs that meet all the following requirements:
The invalidation is not required to apply to caching structures that combine stage 1 and stage 2 translation table entries.
The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this instructions.
For more information about the architectural requirements for this instruction see 'Invalidation of TLB entries from stage 2 translations' in the ARMv8 ARM.
This System instruction is part of:
There are no configuration notes.
TLBI IPAS2E1IS is a 64-bit System instruction.
The TLBI IPAS2E1IS input value bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | IPA[51:48] | IPA[47:12] | ||||||
IPA[47:12] | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Extension to IPA[47:12]. See IPA[47:12] for more details.
Reserved, RES0.
Bits[47:12] of the intermediate physical address to match.
When ARMv8.2-LPA is implemented, and 52-bit addresses and a 64KB translation granule are in use, IPA[51:48] form the upper part of the address value. Otherwise, IPA[51:48] are RES0.
This instruction is executed using TLBI with the following syntax:
TLBI <tlbi_op>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<tlbi_op> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
IPAS2E1IS | 01 | 100 | 1000 | 0000 | 001 |
The instruction is executable as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | - | n/a | WO |
x | 0 | 1 | - | - | WO | WO |
x | 1 | 1 | - | n/a | WO | WO |
This table applies to all syntax that can be used to execute this instruction.
If EL2 is not implemented, or SCR_EL3.NS is 0, this instruction is a NOP.
18/04/2017 17:00
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