The TCR_EL3 characteristics are:
The control register for stage 1 of the EL3 translation regime.
This register is part of the Virtual memory control registers functional group.
RW fields in this register reset to architecturally UNKNOWN values.
TCR_EL3 is a 32-bit register.
The TCR_EL3 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 0 | 0 | HWU62 | HWU61 | HWU60 | HWU59 | HPD | 1 | HD | HA | TBI | 0 | PS | TG0 | SH0 | ORGN0 | IRGN0 | 0 | 0 | T0SZ |
Any of the bits in TCR_EL3 are permitted to be cached in a TLB.
Reserved, RES1.
Reserved, RES0.
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[62] of the stage 1 translation table block or level 3 entry if the TCR_EL3.HPD value is 1.
Defined values are:
HWU62 | Meaning |
---|---|
0 |
The stage 1 translation table entry block or level 3 bit cannot be interpreted by hardware for an IMPLEMENTATION DEFINED purpose. |
1 |
The stage 1 translation table entry block or level 3 bit can be interpreted by hardware for an IMPLEMENTATION DEFINED purpose if the TCR_EL3.HPD value is 1. |
This bit is RES0 if ARMv8.2-TTPBHA is not implemented.
Reserved, RES0.
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[61] of the stage 1 translation table block or level 3 entry if the TCR_EL3.HPD value is 1.
Defined values are:
HWU61 | Meaning |
---|---|
0 |
The stage 1 translation table entry block or level 3 bit cannot be interpreted by hardware for an IMPLEMENTATION DEFINED purpose. |
1 |
The stage 1 translation table entry block or level 3 bit can be interpreted by hardware for an IMPLEMENTATION DEFINED purpose if the TCR_EL3.HPD bit value is 1. |
This bit is RES0 if ARMv8.2-TTPBHA is not implemented.
Reserved, RES0.
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[60] of the stage 1 translation table block or level 3 entry if the TCR_EL3.HPD value is 1.
Defined values are:
HWU60 | Meaning |
---|---|
0 |
The stage 1 translation table entry block or level 3 bit cannot be interpreted by hardware for an IMPLEMENTATION DEFINED purpose. |
1 |
The stage 1 translation table entry block or level 3 bit can be interpreted by hardware for an IMPLEMENTATION DEFINED purpose if the TCR_EL3.HPD bit value is 1. |
This bit is RES0 if ARMv8.2-TTPBHA is not implemented.
Reserved, RES0.
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[59] of the stage 1 translation table block or level 3 entry if the TCR_EL3.HPD value is 1.
Defined values are:
HWU59 | Meaning |
---|---|
0 |
The stage 1 translation table entry block or level 3 bit cannot be interpreted by hardware for an IMPLEMENTATION DEFINED purpose. |
1 |
The stage 1 translation table entry block or level 3 bit can be interpreted by hardware for an IMPLEMENTATION DEFINED purpose if the TCR_EL3.HPD bit value is 1. |
This bit is RES0 if ARMv8.2-TTPBHA is not implemented.
Reserved, RES0.
Hierarchical Permission Disables. This affects the hierarchical control bits, APTable, PXNTable, and UXNTable, except NSTable, in the translation tables pointed to by TTBR0_EL3.
Defined values are:
HPD | Meaning |
---|---|
0 |
Hierarchical permissions are enabled. |
1 |
Hierarchical permissions are disabled. Note
In this case bit[61] (APTable[0]) and bit[59] (PXNTable) of the next level descriptor attributes are required to be ignored by the PE, and are no longer reserved, allowing them to be used by software. |
When disabled, the permissions are treated as if the bits are zero.
This bit is RES0 if ARMv8.1-HPD is not implemented.
Reserved, RES0.
Reserved, RES1.
Hardware management of dirty state in stage 1 translations from EL3.
Defined values are:
HD | Meaning |
---|---|
0 |
Stage 1 hardware management of dirty state disabled. |
1 |
Stage 1 hardware management of dirty state enabled, only if the HA bit is also set to 1. |
This bit is RES0 if ARMv8.1-TTHM is not implemented.
Reserved, RES0.
Hardware Access flag update in stage 1 translations from EL3.
Defined values are:
HA | Meaning |
---|---|
0 |
Stage 1 Access flag update disabled. |
1 |
Stage 1 Access flag update enabled. |
This bit is RES0 if ARMv8.1-TTHM is not implemented.
Reserved, RES0.
Top Byte ignored - indicates whether the top byte of an address is used for address match for the TTBR0_EL3 region, or ignored and used for tagged addresses.
TBI | Meaning |
---|---|
0 |
Top Byte used in the address calculation. |
1 |
Top Byte ignored in the address calculation. |
This affects addresses generated in EL3 using AArch64 where the address would be translated by tables pointed to by TTBR0_EL3. It has an effect whether the EL3 translation regime is enabled or not.
Additionally, this affects changes to the program counter, when TBI is 1, caused by:
In these cases bits [63:56] of the address are set to 0 before it is stored in the PC.
Reserved, RES0.
Physical Address Size.
PS | Meaning |
---|---|
000 |
32 bits, 4GB. |
001 |
36 bits, 64GB. |
010 |
40 bits, 1TB. |
011 |
42 bits, 4TB. |
100 |
44 bits, 16TB. |
101 |
48 bits, 256TB. |
110 |
52 bits, 4PB |
Other values are reserved.
The reserved values behave in the same way as the 101 encoding, but software must not rely on this property as the behavior of the reserved values might change in a future revision of the architecture.
The value 110 is permitted only if ARMv8.2-LPA is implemented and the translation granule size is 64KB.
In an implementation that supports 52-bit PAs, if the value of this field is not 110, then bits[51:48] of every translation table base address for the stage of translation controlled by TCR_EL3 are 0000.
Granule size for the TTBR0_EL3.
TG0 | Meaning |
---|---|
00 |
4KB |
01 |
64KB |
10 |
16KB |
Other values are reserved.
If the value is programmed to either a reserved value, or a size that has not been implemented, then the hardware will treat the field as if it has been programmed to an IMPLEMENTATION DEFINED choice of the sizes that has been implemented for all purposes other than the value read back from this register.
It is IMPLEMENTATION DEFINED whether the value read back is the value programmed or the value that corresponds to the size chosen.
Shareability attribute for memory associated with translation table walks using TTBR0_EL3.
SH0 | Meaning |
---|---|
00 |
Non-shareable |
10 |
Outer Shareable |
11 |
Inner Shareable |
Other values are reserved. The effect of programming this field to a Reserved value is that behavior is CONSTRAINED UNPREDICTABLE, as described in 'Reserved values in AArch64 System registers and translation table entries' in the ARM ARM, section K1.2.2.
Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL3.
ORGN0 | Meaning |
---|---|
00 |
Normal memory, Outer Non-cacheable |
01 |
Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable |
10 |
Normal memory, Outer Write-Through Read-Allocate No Write-Allocate Cacheable |
11 |
Normal memory, Outer Write-Back Read-Allocate No Write-Allocate Cacheable |
Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3.
IRGN0 | Meaning |
---|---|
00 |
Normal memory, Inner Non-cacheable |
01 |
Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable |
10 |
Normal memory, Inner Write-Through Read-Allocate No Write-Allocate Cacheable |
11 |
Normal memory, Inner Write-Back Read-Allocate No Write-Allocate Cacheable |
Reserved, RES0.
The size offset of the memory region addressed by TTBR0_EL3. The region size is 2(64-T0SZ) bytes.
The maximum and minimum possible values for T0SZ depend on the level of translation table and the memory translation granule size, as described in the AArch64 Virtual Memory System Architecture chapter.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
TCR_EL3 | 11 | 110 | 0010 | 0000 | 010 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | - | n/a | RW |
0 | 0 | 1 | - | - | - | RW |
0 | 1 | 1 | - | n/a | - | RW |
1 | 0 | 1 | - | - | - | RW |
1 | 1 | 1 | - | n/a | - | RW |
This table applies to all instructions that can access this register.
18/04/2017 17:00
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