The PMCCFILTR characteristics are:
Determines the modes in which the Cycle Counter, PMCCNTR, increments.
This register is part of the Performance Monitors registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register PMCCFILTR is architecturally mapped to AArch64 System register PMCCFILTR_EL0.
AArch32 System register PMCCFILTR is architecturally mapped to External register PMCCFILTR_EL0.
This register is in the Warm reset domain. Some or all RW fields of this register have defined reset values. On a Warm or Cold reset these apply only if the PE resets into an Exception level that is using AArch32. Otherwise, on a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.
PMCCFILTR is a 32-bit register.
The PMCCFILTR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
P | U | NSK | NSU | NSH | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Privileged filtering bit. Controls counting in EL1. If EL3 is implemented, then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are:
P | Meaning |
---|---|
0 |
Count cycles in EL1. |
1 |
Do not count cycles in EL1. |
When this register has an architecturally-defined reset value, this field resets to 0.
User filtering bit. Controls counting in EL0. If EL3 is implemented, then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are:
U | Meaning |
---|---|
0 |
Count cycles in EL0. |
1 |
Do not count cycles in EL0. |
When this register has an architecturally-defined reset value, this field resets to 0.
Non-secure EL1 (kernel) modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented, this bit is RES0.
If the value of this bit is equal to the value of P, cycles in Non-secure EL1 are counted.
Otherwise, cycles in Non-secure EL1 are not counted.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.
Non-secure EL0 (Unprivileged) filtering. Controls counting in Non-secure EL0. If EL3 is not implemented, this bit is RES0.
If the value of this bit is equal to the value of U, cycles in Non-secure EL0 are counted.
Otherwise, cycles in Non-secure EL0 are not counted.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.
Non-secure EL2 (Hyp mode) filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented, this bit is RES0.
NSH | Meaning |
---|---|
0 |
Do not count cycles in EL2. |
1 |
Count cycles in EL2. |
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.
Reserved, RES0.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c14, c15, 7 | 000 | 111 | 1110 | 1111 | 1111 |
PMCCFILTR can also be accessed by using PMXEVTYPER with PMSELR.SEL set to 0b11111.
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | RW | RW | n/a | RW |
x | 0 | 1 | RW | RW | RW | RW |
x | 1 | 1 | RW | n/a | RW | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If PMUSERENR.EN==0, accesses to this register from EL0 are trapped to Undefined mode.
If PMUSERENR_EL0.EN==0, accesses to this register from EL0 are trapped to EL1.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TPM==1, Non-secure accesses to this register from EL0 and EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HDCR.TPM==1, Non-secure accesses to this register from EL0 and EL1 are trapped to Hyp mode.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TPM==1, accesses to this register from EL0, EL1, and EL2 are trapped to EL3.
18/04/2017 17:00
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Confidential.