The ICC_IGRPEN1_EL3 characteristics are:
Controls whether Group 1 interrupts are enabled or not.
This register is part of:
AArch64 System register ICC_IGRPEN1_EL3 can be mapped to AArch32 System register ICC_MGRPEN1, but this is not architecturally mandated.
ICC_IGRPEN1_EL3 is a 32-bit register.
The ICC_IGRPEN1_EL3 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | EnableGrp1S | EnableGrp1NS |
Reserved, RES0.
Enables Group 1 interrupts for the Secure state.
EnableGrp1S | Meaning |
---|---|
0 |
Secure Group 1 interrupts are disabled. |
1 |
Secure Group 1 interrupts are enabled. |
The Secure ICC_IGRPEN1_EL1.Enable bit is a read/write alias of the ICC_IGRPEN1_EL3.EnableGrp1S bit.
If the highest priority pending interrupt for that PE is a Group 1 interrupt using 1 of N model, then the interrupt will target another PE as a result of the Enable bit changing from 1 to 0.
When this register has an architecturally-defined reset value, this field resets to 0.
Enables Group 1 interrupts for the Non-secure state.
EnableGrp1NS | Meaning |
---|---|
0 |
Non-secure Group 1 interrupts are disabled. |
1 |
Non-secure Group 1 interrupts are enabled. |
The Non-secure ICC_IGRPEN1_EL1.Enable bit is a read/write alias of the ICC_IGRPEN1_EL3.EnableGrp1NS bit.
If the highest priority pending interrupt for that PE is a Group 1 interrupt using 1 of N model, then the interrupt will target another PE as a result of the Enable bit changing from 1 to 0.
When this register has an architecturally-defined reset value, this field resets to 0.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op1 | CRn | CRm | op2 |
---|---|---|---|---|
ICC_IGRPEN1_EL3 | 110 | 1100 | 1100 | 111 |
The register is accessible as follows:
Control | Accessibility | ||||||
---|---|---|---|---|---|---|---|
FMO | IMO | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | x | 0 | - | - | n/a | RW |
x | x | 0 | 1 | - | - | - | RW |
x | x | 1 | 1 | - | n/a | - | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_SRE_EL3.SRE==0, accesses to this register from EL3 are trapped to EL3.
18/04/2017 17:00
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