The ICV_HPPIR0 characteristics are:
Indicates the highest priority pending virtual Group 0 interrupt on the virtual CPU interface.
This register is part of:
AArch32 System register ICV_HPPIR0 performs the same function as AArch64 System register ICV_HPPIR0_EL1.
ICV_HPPIR0 is a 32-bit register.
The ICV_HPPIR0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | INTID |
Reserved, RES0.
The INTID of the highest priority pending virtual interrupt.
If the highest priority pending interrupt is not observable, this field contains a special INTID to indicate the reason. This special INTID can take the value 1023 only. See Special INTIDs, for more information.
This field has either 16 or 24 bits implemented. The number of implemented bits can be found in ICV_CTLR.IDbits. If only 16 bits are implemented, bits [23:16] of this register are RES0.
This register can be read using MRC with the following syntax:
MRC <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c12, c8, 2 | 000 | 010 | 1100 | 1111 | 1000 |
When HCR.FMO is set to 0, execution of this encoding at Non-secure EL1 results in an access to ICC_HPPIR0.
The register is accessible as follows:
Control | Accessibility | ||||||
---|---|---|---|---|---|---|---|
FMO | IMO | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | x | 0 | - | ICC_HPPIR0 | n/a | ICC_HPPIR0 |
x | x | 1 | 1 | - | n/a | ICC_HPPIR0 | ICC_HPPIR0 |
0 | x | 0 | 1 | - | ICC_HPPIR0 | ICC_HPPIR0 | ICC_HPPIR0 |
1 | x | 0 | 1 | - | RO | ICC_HPPIR0 | ICC_HPPIR0 |
This table applies to all instructions that can access this register.
ICV_HPPIR0 is only accessible at Non-secure EL1 when HCR.FMO is set to 1.
When HCR.FMO is set to 0, at Non-secure EL1, the instruction encoding used to access ICV_HPPIR0 results in an access to ICC_HPPIR0.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_SRE.SRE==0, Non-secure read accesses to this register from EL1 are UNDEFINED.
If ICC_SRE_EL1.SRE==0, Non-secure read accesses to this register from EL1 are trapped to EL1.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==0 :
If HSTR_EL2.T12==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T12==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HSTR.T12==1, Non-secure read accesses to this register from EL1 are trapped to Hyp mode.
When SCR_EL3.NS==1 :
If ICH_HCR.TALL0==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If ICH_HCR_EL2.TALL0==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
18/04/2017 17:00
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