The ICV_RPR characteristics are:
Indicates the Running priority of the virtual CPU interface.
This register is part of:
AArch32 System register ICV_RPR performs the same function as AArch64 System register ICV_RPR_EL1.
ICV_RPR is a 32-bit register.
The ICV_RPR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Priority |
Reserved, RES0.
The current running priority on the virtual CPU interface. This is the group priority of the current active virtual interrupt.
The priority returned is the group priority as if the BPR for the current Exception level and Security state was set to the minimum value of BPR for the number of implemented priority bits.
If 8 bits of priority are implemented the group priority is bits[7:1] of the priority.
This register can be read using MRC with the following syntax:
MRC <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c12, c11, 3 | 000 | 011 | 1100 | 1111 | 1011 |
When HCR.{FMO, IMO} == {0, 0}, execution of this encoding at Non-secure EL1 results in an access to ICC_RPR.
The register is accessible as follows:
Control | Accessibility | ||||||
---|---|---|---|---|---|---|---|
FMO | IMO | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | x | 0 | - | ICC_RPR | n/a | ICC_RPR |
x | x | 1 | 1 | - | n/a | ICC_RPR | ICC_RPR |
x | 1 | 0 | 1 | - | RO | ICC_RPR | ICC_RPR |
1 | x | 0 | 1 | - | RO | ICC_RPR | ICC_RPR |
0 | 0 | 0 | 1 | - | ICC_RPR | ICC_RPR | ICC_RPR |
This table applies to all instructions that can access this register.
ICV_RPR is only accessible at Non-secure EL1 when HCR.{FMO, IMO} != {0, 0}.
When HCR.{FMO, IMO} == {0, 0}, at Non-secure EL1, the instruction encoding used to access ICV_RPR results in an access to ICC_RPR.
If there are no active interrupts on the virtual CPU interface, or all active interrupts have undergone a priority drop, the value returned is the Idle priority.
Software cannot determine the number of implemented priority bits from a read of this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_SRE.SRE==0, Non-secure read accesses to this register from EL1 are UNDEFINED.
If ICC_SRE_EL1.SRE==0, Non-secure read accesses to this register from EL1 are trapped to EL1.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==0 :
If HSTR_EL2.T12==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T12==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HSTR.T12==1, Non-secure read accesses to this register from EL1 are trapped to Hyp mode.
When SCR_EL3.NS==1 :
If ICH_HCR.TC==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If ICH_HCR_EL2.TC==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
18/04/2017 17:00
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