The ICC_HSRE characteristics are:
Controls whether the System register interface or the memory-mapped interface to the GIC CPU interface is used for EL2.
This register is part of:
AArch32 System register ICC_HSRE is architecturally mapped to AArch64 System register ICC_SRE_EL2.
ICC_HSRE is a 32-bit register.
The ICC_HSRE bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Enable | DIB | DFB | SRE |
Reserved, RES0.
Enable. Enables lower Exception level access to ICC_SRE.
Enable | Meaning |
---|---|
0 |
Non-secure EL1 accesses to ICC_SRE trap to EL2. |
1 |
Non-secure EL1 accesses to ICC_SRE do not trap to EL2. |
If ICC_HSRE.SRE is RAO/WI, an implementation is permitted to make the Enable bit RAO/WI.
If ICC_HSRE.SRE is 0, the Enable bit behaves as 1 for all purposes other than reading the value of the bit.
Disable IRQ bypass.
DIB | Meaning |
---|---|
0 |
IRQ bypass enabled. |
1 |
IRQ bypass disabled. |
If EL3 is implemented and GICD_CTLR.DS is 0, this field is a read-only alias of ICC_MSRE.DIB.
If EL3 is implemented and GICD_CTLR.DS is 1, this field is a read-write alias of ICC_MSRE.DIB.
In systems that do not support IRQ bypass, this bit is RAO/WI.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.
Disable FIQ bypass.
DFB | Meaning |
---|---|
0 |
FIQ bypass enabled. |
1 |
FIQ bypass disabled. |
If EL3 is implemented and GICD_CTLR.DS is 0, this field is a read-only alias of ICC_MSRE.DFB.
If EL3 is implemented and GICD_CTLR.DS is 1, this field is a read-write alias of ICC_MSRE.DFB.
In systems that do not support FIQ bypass, this bit is RAO/WI.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.
System Register Enable.
SRE | Meaning |
---|---|
0 |
The memory-mapped interface must be used. Accesses at EL2 or below to any ICH_* System register, or any EL1 or EL2 ICC_* register other than ICC_SRE or ICC_HSRE, are UNDEFINED. |
1 |
The System register interface to the ICH_* registers and the EL1 and EL2 ICC_* registers is enabled for EL2. |
If software changes this bit from 1 to 0, the results are UNPREDICTABLE.
If an implementation supports only a System register interface to the GIC CPU interface, this bit is RAO/WI.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 4, <Rt>, c12, c9, 5 | 100 | 101 | 1100 | 1111 | 1001 |
The register is accessible as follows:
Control | Accessibility | ||||
---|---|---|---|---|---|
TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | 0 | - | - | n/a | - |
0 | 1 | - | - | RW | RW |
1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
The GIC architecture permits, but does not require, that registers can be shared between memory-mapped registers and the equivalent System registers. This means that if the memory-mapped registers have been accessed while ICC_HSRE.SRE==0, then the System registers might be modified. Therefore, software must only rely on the reset values of the System registers if there has been no use of the GIC functionality while the memory-mapped registers are in use. Otherwise, the System register values must be treated as UNKNOWN.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_MSRE.Enable==0, accesses to this register from EL2 are UNDEFINED.
If ICC_SRE_EL3.Enable==0, accesses to this register from EL2 are trapped to EL3.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==0 :
If HSTR_EL2.T12==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T12==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HSTR.T12==1, Non-secure accesses to this register from EL1 are trapped to Hyp mode.
18/04/2017 17:00
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