The GICH_HCR characteristics are:
Controls the virtual CPU interface.
This register is part of the GIC virtualised guest interface control registers functional group.
This register is accessible as follows:
Security disabled | Secure | Non-secure |
---|---|---|
RW | RW | RW |
This register is used only when System register access is not enabled. When System register access is enabled:
GICH_HCR.En must be set to 1 for any virtual or maintenance interrupt to be asserted.
RW fields in this register reset to architecturally UNKNOWN values.
This register is available when the GIC implementation supports interrupt virtualization.
GICH_HCR is a 32-bit register.
The GICH_HCR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EOICount | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | VGrp1DIE | VGrp1EIE | VGrp0DIE | VGrp0EIE | NPIE | LRENPIE | UIE | En |
Counts the number of EOIs received that do not have a corresponding entry in the List registers. The virtual CPU interface increments this field automatically when a matching EOI is received. EOIs that do not clear a bit in GICH_APR<n> do not cause an increment. If an EOI occurs when the value of this field is 31, then the field wraps to 0.
The maintenance interrupt is asserted whenever this field is nonzero and GICH_HCR.LRENPIE == 1.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Reserved, RES0.
VM Group 1 Disabled Interrupt Enable.
Enables the signaling of a maintenance interrupt while signaling of Group 1 interrupts from the virtual CPU interface to the connected virtual machine is disabled:
VGrp1DIE | Meaning |
---|---|
0 |
Maintenance interrupt disabled. |
1 |
Maintenance interrupt signaled when GICV_CTLR.EnableGrp1 == 0. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
VM Group 1 Enabled Interrupt Enable.
Enables the signaling of a maintenance interrupt while signaling of Group 1 interrupts from the virtual CPU interface to the connected virtual machine is enabled:
VGrp1EIE | Meaning |
---|---|
0 |
Maintenance interrupt disabled. |
1 |
Maintenance interrupt signaled when GICV_CTLR.EnableGrp1 == 1. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
VM Group 0 Disabled Interrupt Enable.
Enables the signaling of a maintenance interrupt while signaling of Group 0 interrupts from the virtual CPU interface to the connected virtual machine is disabled:
VGrp0DIE | Meaning |
---|---|
0 |
Maintenance interrupt disabled. |
1 |
Maintenance interrupt signaled when GICV_CTLR.EnableGrp0 == 0. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
VM Group 0 Enabled Interrupt Enable.
Enables the signaling of a maintenance interrupt while signaling of Group 0 interrupts from the virtual CPU interface to the connected virtual machine is enabled:
VGrp0EIE | Meaning |
---|---|
0 |
Maintenance interrupt disabled. |
1 |
Maintenance interrupt signaled when GICV_CTLR.EnableGrp0 == 1. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
No Pending Interrupt Enable.
Enables the signaling of a maintenance interrupt while no pending interrupts are present in the List registers:
NPIE | Meaning |
---|---|
0 |
Maintenance interrupt disabled. |
1 |
Maintenance interrupt signaled while the List registers contain no interrupts in the pending state. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
List Register Entry Not Present Interrupt Enable.
Enables the signaling of a maintenance interrupt while the virtual CPU interface does not have a corresponding valid List register for an EOI request:
LRENPIE | Meaning |
---|---|
0 |
Maintenance interrupt disabled. |
1 |
Maintenance interrupt signaled while GICH_HCR.EOICount is not 0. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Underflow Interrupt Enable.
Enables the signaling of a maintenance interrupt when the List registers are either empty or hold only one valid entry.
UIE | Meaning |
---|---|
0 |
Maintenance interrupt disabled. |
1 |
A maintenance interrupt is signaled if zero or one of the List register entries are marked as a valid interrupt. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Enable.
Global enable bit for the virtual CPU interface.
En | Meaning |
---|---|
0 |
Virtual CPU interface operation is disabled. |
1 |
Virtual CPU interface operation is enabled. |
When this field is 0:
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
The VGrp1DIE, VGrp1EIE, VGrp0DIE, and VGrp0EIE fields permit the hypervisor to track the virtual CPU interfaces that are enabled. The hypervisor can then route interrupts that have multiple targets correctly and efficiently, without having to read the virtual CPU interface status.
See Maintenance interrupts and GICH_MISR for more information.
GICH_HCR can be accessed through its memory-mapped interface:
Component | Offset |
---|---|
GIC Virtual interface control | 0x0000 |
18/04/2017 17:00
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