ICV_DIR, Interrupt Controller Deactivate Virtual Interrupt Register

The ICV_DIR characteristics are:

Purpose

When interrupt priority drop is separated from interrupt deactivation, a write to this register deactivates the specified virtual interrupt.

This register is part of:

Configuration

AArch32 System register ICV_DIR performs the same function as AArch64 System register ICV_DIR_EL1.

Attributes

ICV_DIR is a 32-bit register.

Field descriptions

The ICV_DIR bit assignments are:

313029282726252423222120191817161514131211109876543210
00000000INTID

Bits [31:24]

Reserved, RES0.

INTID, bits [23:0]

The INTID of the virtual interrupt to be deactivated.

This field has either 16 or 24 bits implemented. The number of implemented bits can be found in ICV_CTLR.IDbits. If only 16 bits are implemented, bits [23:16] of this register are RES0.

Accessing the ICV_DIR

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 0, <Rt>, c12, c11, 1000001110011111011

This encoding results in an access to ICV_DIR at Non-secure EL1 in the following cases:

This encoding results in an access to ICC_DIR at Non-secure EL1 in the following cases:

Accessibility

The register is accessible as follows:

Control Accessibility
FMOIMOTGENSEL0EL1EL2EL3
xxx0 - ICC_DIR n/a ICC_DIR
xx11 - n/a ICC_DIR ICC_DIR
x101 - WO ICC_DIR ICC_DIR
1x01 - WO ICC_DIR ICC_DIR
0001 - ICC_DIR ICC_DIR ICC_DIR

This table applies to all instructions that can access this register.

The ICV_DIR register is only accessible at Non-secure EL1 in the following cases:

Note

At Non-secure EL1, the instruction encoding used to access ICV_DIR results in an access to ICC_DIR when HCR.{FMO, IMO} == {0, 0}.

When EOImode == 0, writes are ignored In systems supporting system error generation, an implementation might generate an SEI.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :

When SCR_EL3.NS==1 :




18/04/2017 17:00

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