The GICC_PMR characteristics are:
This register provides an interrupt priority filter. Only interrupts with a higher priority than the value in this register are signaled to the PE.
Higher interrupt priority corresponds to a lower value of the Priority field.
This register is part of the GIC physical CPU interface registers functional group.
This register is accessible as follows:
Security disabled | Secure | Non-secure |
---|---|---|
RW | RW | RW |
If the GIC implementation supports two Security states:
See 'Priority control of Secure and Non-secure interrupts' in the GICv3 Architecture Specification for more information.
RW fields in this register reset to architecturally UNKNOWN values.
This register is available in all configurations of the GIC. If the GIC implementation supports two Security states this register is Common.
GICC_PMR is a 32-bit register.
The GICC_PMR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Priority |
Reserved, RES0.
The priority mask level for the CPU interface. If the priority of the interrupt is higher than the value indicated by this field, the interface signals the interrupt to the PE.
If the GIC implementation supports fewer than 256 priority levels some bits might be RAZ/WI, as follows:
See Interrupt prioritization for more information.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
GICC_PMR can be accessed through its memory-mapped interface:
Component | Offset |
---|---|
GIC CPU interface | 0x0004 |
18/04/2017 17:00
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