The ICC_IGRPEN1_EL1 characteristics are:
Controls whether Group 1 interrupts are enabled for the current Security state.
This register is part of:
AArch64 System register ICC_IGRPEN1_EL1 (S) is architecturally mapped to AArch32 System register ICC_IGRPEN1 (S) .
AArch64 System register ICC_IGRPEN1_EL1 (NS) is architecturally mapped to AArch32 System register ICC_IGRPEN1 (NS) .
ICC_IGRPEN1_EL1 is a 32-bit register.
The ICC_IGRPEN1_EL1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Enable |
Reserved, RES0.
Enables Group 1 interrupts for the current Security state.
Enable | Meaning |
---|---|
0 |
Group 1 interrupts are disabled for the current Security state. |
1 |
Group 1 interrupts are enabled for the current Security state. |
Virtual accesses to this register update ICH_VMCR_EL2.VENG1.
If EL3 is present:
If the highest priority pending interrupt for that PE is a Group 1 interrupt using 1 of N model, then the interrupt will target another PE as a result of the Enable bit changing from 1 to 0.
When this register has an architecturally-defined reset value, this field resets to 0.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op1 | CRn | CRm | op2 |
---|---|---|---|---|
ICC_IGRPEN1_EL1 | 000 | 1100 | 1100 | 111 |
When HCR_EL2.IMO is set to 1, execution of this encoding at Non-secure EL1 results in an access to ICV_IGRPEN1_EL1.
The register is accessible as follows:
Control | Accessibility | Instance | ||||||
---|---|---|---|---|---|---|---|---|
FMO | IMO | TGE | NS | EL0 | EL1 | EL2 | EL3 | |
x | x | x | 0 | - | RW | n/a | RW | ICC_IGRPEN1_EL1_s |
x | x | 1 | 1 | - | n/a | RW | RW | ICC_IGRPEN1_EL1_ns |
x | 0 | 0 | 1 | - | RW | RW | RW | ICC_IGRPEN1_EL1_ns |
x | 1 | 0 | 1 | - | ICV_IGRPEN1_EL1 | RW | RW | ICC_IGRPEN1_EL1_ns |
This table applies to all instructions that can access this register.
ICC_IGRPEN1_EL1 is only accessible at Non-secure EL1 when HCR_EL2.IMO is set to 0.
When HCR_EL2.IMO is set to 1, at Non-secure EL1, the instruction encoding used to access ICC_IGRPEN1_EL1 results in an access to ICV_IGRPEN1_EL1.
If EL3 is present and this register is accessed at EL3, the copy of this register appropriate to the current setting of SCR_EL3.NS is accessed.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_SRE_EL1.SRE==0, accesses to this register from EL1 are trapped to EL1.
If ICC_SRE_EL2.SRE==0, accesses to this register from EL2 are trapped to EL2.
If ICC_SRE_EL3.SRE==0, accesses to this register from EL3 are trapped to EL3.
When SCR_EL3.NS==1 :
If ICH_HCR_EL2.TALL1==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL3 is implemented and is using AArch64 and SCR_EL3.NS==0 :
If SCR_EL3.IRQ==1, Secure accesses to this register from EL1 are trapped to EL3.
When EL3 is implemented and is using AArch64 :
If SCR_EL3.IRQ==1, accesses to this register from EL2 are trapped to EL3.
When EL3 is implemented and is using AArch64 and SCR_EL3.NS==1 :
18/04/2017 17:00
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Confidential.