The ID_PFR0 characteristics are:
Gives top-level information about the instruction sets supported by the PE in AArch32 state.
Must be interpreted with ID_PFR1.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section G4.14.6.
This register is part of the Identification registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register ID_PFR0 is architecturally mapped to AArch64 System register ID_PFR0_EL1.
ID_PFR0 is a 32-bit register.
The ID_PFR0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAS | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | State3 | State2 | State1 | State0 |
RAS Extension version. The defined values of this field are:
RAS | Meaning |
---|---|
0000 |
No RAS Extension. |
0001 |
Version 1 of the RAS Extension present. |
All other values are reserved.
Reserved, RES0.
T32EE instruction set support. Defined values are:
State3 | Meaning |
---|---|
0000 |
Not implemented. |
0001 |
T32EE instruction set implemented. |
All other values are reserved.
In ARMv8-A the only permitted value is 0000.
Jazelle extension support. Defined values are:
State2 | Meaning |
---|---|
0000 |
Not implemented. |
0001 |
Jazelle extension implemented, without clearing of JOSCR.CV on exception entry. |
0010 |
Jazelle extension implemented, with clearing of JOSCR.CV on exception entry. |
All other values are reserved.
In ARMv8-A the only permitted value is 0001.
T32 instruction set support. Defined values are:
State1 | Meaning |
---|---|
0000 |
T32 instruction set not implemented. |
0001 |
T32 encodings before the introduction of Thumb-2 technology implemented:
|
0011 |
T32 encodings after the introduction of Thumb-2 technology implemented, for all 16-bit and 32-bit T32 basic instructions. |
All other values are reserved.
In ARMv8-A the only permitted value is 0011.
A32 instruction set support. Defined values are:
State0 | Meaning |
---|---|
0000 |
A32 instruction set not implemented. |
0001 |
A32 instruction set implemented. |
All other values are reserved.
In ARMv8-A the only permitted value is 0001.
This register can be read using MRC with the following syntax:
MRC <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c0, c1, 0 | 000 | 000 | 0000 | 1111 | 0001 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HSTR_EL2.T0==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HSTR_EL2.T0==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
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