DC CIVAC, Data or unified Cache line Clean and Invalidate by VA to PoC

The DC CIVAC characteristics are:

Purpose

Clean and Invalidate data cache by address to Point of Coherency.

This System instruction is part of the Cache maintenance instructions functional group.

Configuration

AArch64 System instruction DC CIVAC performs the same function as AArch32 System instruction DCCIMVAC.

Attributes

DC CIVAC is a 64-bit System instruction.

Field descriptions

The DC CIVAC input value bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
Virtual address to use
Virtual address to use
313029282726252423222120191817161514131211109876543210

Bits [63:0]

Virtual address to use.

Executing the DC CIVAC instruction

This instruction is executed using DC with the following syntax:

DC <dc_op>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<dc_op> op0op1CRnCRmop2
CIVAC0101101111110001

Accessibility

The instruction is executable as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0WOWO n/a WO
x01WOWOWOWO
x11WO n/a WOWO

This table applies to all syntax that can be used to execute this instruction.

If EL0 access is enabled, when executing at EL0, this instruction requires read access permission to the VA, otherwise it causes a Permission Fault.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when executing this System instruction.

In both Security states, and not dependent on other configuration bits:

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :




18/04/2017 17:00

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