PMOVSSET_EL0, Performance Monitors Overflow Flag Status Set register

The PMOVSSET_EL0 characteristics are:

Purpose

Sets the state of the overflow bit for the Cycle Count Register, PMCCNTR_EL0, and each of the implemented event counters PMEVCNTR<n>.

This register is part of the Performance Monitors registers functional group.

Usage constraints

This register is accessible as follows:

OffDLKOSLKEPMADSLKDefault
ErrorErrorErrorErrorRORW

Configuration

External register PMOVSSET_EL0 is architecturally mapped to AArch64 System register PMOVSSET_EL0.

External register PMOVSSET_EL0 is architecturally mapped to AArch32 System register PMOVSSET.

PMOVSSET_EL0 is in the Core power domain. RW fields in this register reset to architecturally UNKNOWN values. These apply on a Warm or Cold reset. The register is not affected by an External debug reset.

Attributes

PMOVSSET_EL0 is a 32-bit register.

Field descriptions

The PMOVSSET_EL0 bit assignments are:

313029282726252423222120191817161514131211109876543210
CP<n>, bit [n]

C, bit [31]

PMCCNTR_EL0 overflow bit. Possible values are:

CMeaning
0

When read, means the cycle counter has not overflowed. When written, has no effect.

1

When read, means the cycle counter has overflowed. When written, sets the overflow bit to 1.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

P<n>, bit [n], for n = 0 to 30

Event counter overflow set bit for PMEVCNTR<n>_EL0.

Bits [30:N] are RAZ/WI. N is the value in PMCFGR.N.

Possible values are:

P<n>Meaning
0

When read, means that PMEVCNTR<n>_EL0 has not overflowed. When written, has no effect.

1

When read, means that PMEVCNTR<n>_EL0 has overflowed. When written, sets the PMEVCNTR<n>_EL0 overflow bit to 1.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Accessing the PMOVSSET_EL0

PMOVSSET_EL0 can be accessed through the external debug interface:

ComponentOffset
PMU 0xCC0



18/04/2017 17:00

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