The MIDR_EL1 characteristics are:
Provides identification information for the PE, including an implementer code for the device and a device ID number.
This register is part of the Identification registers functional group.
AArch64 System register MIDR_EL1 is architecturally mapped to AArch32 System register MIDR.
AArch64 System register MIDR_EL1 is architecturally mapped to External register MIDR_EL1.
MIDR_EL1 is a 32-bit register.
The MIDR_EL1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Implementer | Variant | Architecture | PartNum | Revision |
The Implementer code. This field must hold an implementer code that has been assigned by ARM. Assigned codes include the following:
Hex representation | ASCII representation | Implementer |
---|---|---|
0x41 | A | ARM Limited |
0x42 | B | Broadcom Corporation |
0x43 | C | Cavium Inc. |
0x44 | D | Digital Equipment Corporation |
0x49 | I | Infineon Technologies AG |
0x4D | M | Motorola or Freescale Semiconductor Inc. |
0x4E | N | NVIDIA Corporation |
0x50 | P | Applied Micro Circuits Corporation |
0x51 | Q | Qualcomm Inc. |
0x56 | V | Marvell International Ltd. |
0x69 | i | Intel Corporation |
ARM can assign codes that are not published in this manual. All values not assigned by ARM are reserved and must not be used.
An IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product.
The permitted values of this field are:
Architecture | Meaning |
---|---|
0001 |
ARMv4 |
0010 |
ARMv4T |
0011 |
ARMv5 (obsolete) |
0100 |
ARMv5T |
0101 |
ARMv5TE |
0110 |
ARMv5TEJ |
0111 |
ARMv6 |
1111 |
Architectural features are individually identified in the ID_* registers, see 'Identification registers, functional group' in the ARMv8 ARM, section G4.18.1. |
All other values are reserved.
An IMPLEMENTATION DEFINED primary part number for the device.
On processors implemented by ARM, if the top four bits of the primary part number are 0x0 or 0x7, the variant and architecture are encoded differently.
An IMPLEMENTATION DEFINED revision number for the device.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
MIDR_EL1 | 11 | 000 | 0000 | 0000 | 000 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
18/04/2017 17:00
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