RMR_EL3, Reset Management Register (EL3)

The RMR_EL3 characteristics are:

Purpose

If EL3 is the implemented and this register is implemented:

This register is part of the Reset management registers functional group.

Configuration

AArch64 System register RMR_EL3 is architecturally mapped to AArch32 System register RMR when EL3 is implemented.

When EL3 is implemented:

See the field descriptions for the reset values. These apply whenever the register is implemented.

Attributes

RMR_EL3 is a 32-bit register.

Field descriptions

The RMR_EL3 bit assignments are:

313029282726252423222120191817161514131211109876543210
000000000000000000000000000000RRAA64

Bits [31:2]

Reserved, RES0.

RR, bit [1]

Reset Request. Setting this bit to 1 requests a Warm reset.

This field resets to 0 on a Warm or Cold reset.

AA64, bit [0]

When EL3 can use AArch32, determines which Execution state the PE boots into after a Warm reset:

AA64Meaning
0

AArch32.

1

AArch64.

On coming out of the Warm reset, execution starts at the IMPLEMENTATION DEFINED reset vector address of the specified Execution state.

If EL3 cannot use AArch32 this bit is RAO/WI.

When implemented as a RW field, this field resets to 1 on a Cold reset.

Accessing the RMR_EL3

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
RMR_EL31111011000000010

Accessibility

The register is accessible as follows:

Configuration Control Accessibility
E2HTGENSEL0EL1EL2EL3
EL3 is the highest implemented Exception levelxx0 - - n/a RW
EL3 is the highest implemented Exception levelx01 - - - RW
EL3 is the highest implemented Exception levelx11 - n/a - RW

This table applies to all instructions that can access this register.

When RMR_EL3 is not implemented, the encoding for this register is UNDEFINED.




18/04/2017 17:00

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