EDPFR, External Debug Processor Feature Register

The EDPFR characteristics are:

Purpose

Provides information about implemented PE features.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.

This register is part of the Identification registers functional group.

Usage constraints

This register is accessible as follows:

OffDLKDefault
IMP DEFIMP DEFRO

Configuration

It is IMPLEMENTATION DEFINED whether EDPFR is implemented in the Core power domain or in the Debug power domain.

Attributes

EDPFR is a 64-bit register.

Field descriptions

The EDPFR bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
0000000000000000000000000000SVE
UNKGICAdvSIMDFPEL3EL2EL1EL0
313029282726252423222120191817161514131211109876543210

Bits [63:36]

Reserved, RES0.

SVE, bits [35:32]
In ARMv8.2:

Scalable Vector Extension. Defined values are:

SVEMeaning
0000

SVE is not implemented.

0001

SVE is implemented.

All other values are reserved.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

UNK, bits [31:28]

When the RAS Extension is implemented, this field is UNKNOWN. Otherwise, this field is RES0.

Note

ARMv8.2 requires the implementation of the RAS Extension.

GIC, bits [27:24]

System register GIC interface support. Defined values are:

GICMeaning
0000

No System register interface to the GIC is supported.

0001

System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported.

All other values are reserved.

In an ARMv8-A implementation that supports AArch64 state in at least one Exception level, this field returns the value of ID_AA64PFR0_EL1.GIC.

AdvSIMD, bits [23:20]

Advanced SIMD. Defined values are:

AdvSIMDMeaning
0000

Advanced SIMD is implemented, including support for the following SISD and SIMD operations:

  • Integer byte, halfword, word and doubleword element operations.
  • Single-precision and double-precision floating-point arithmetic.
  • Conversions between single-precision and half-precision data types, and double-precision and half-precision data types.
0001

As for 0000, and also includes support for half-precision floating-point arithmetic.

1111

Advanced SIMD is not implemented.

All other values are reserved.

This field must have the same value as the FP field.

The permitted values are:

In an ARMv8-A implementation that supports AArch64 state in at least one Exception level, this field returns the value of ID_AA64PFR0_EL1.AdvSIMD.

FP, bits [19:16]

Floating-point. Defined values are:

FPMeaning
0000

Floating-point is implemented, and includes support for:

  • Single-precision and double-precision floating-point types.
  • Conversions between single-precision and half-precision data types, and double-precision and half-precision data types.
0001

As for 0000, and also includes support for half-precision floating-point arithmetic.

1111

Floating-point is not implemented.

All other values are reserved.

This field must have the same value as the AdvSIMD field.

The permitted values are:

In an ARMv8-A implementation that supports AArch64 state in at least one Exception level, this field returns the value of ID_AA64PFR0_EL1.FP.

EL3, bits [15:12]

AArch64 EL3 Exception level handling. Defined values are:

EL3Meaning
0000

EL3 is not implemented or cannot be executed in AArch64 state.

0001

EL3 can be executed in AArch64 state only.

0010

EL3 can be executed in either AArch64 or AArch32 state.

When the value of EDAA32PFR.EL3 is non-zero, this field must be 0000.

All other values are reserved.

In an ARMv8-A implementation that supports AArch64 state in at least one Exception level, this field returns the value of ID_AA64PFR0_EL1.EL3.

EL2, bits [11:8]

AArch64 EL2 Exception level handling. Defined values are:

EL2Meaning
0000

EL2 is not implemented or cannot be executed in AArch64 state.

0001

EL2 can be executed in AArch64 state only.

0010

EL2 can be executed in either AArch64 or AArch32 state.

When the value of EDAA32PFR.EL2 is non-zero, this field must be 0000.

All other values are reserved.

In an ARMv8-A implementation that supports AArch64 state in at least one Exception level, this field returns the value of ID_AA64PFR0_EL1.EL2.

EL1, bits [7:4]

AArch64 EL1 Exception level handling. Defined values are:

EL1Meaning
0000

EL1 can be executed in AArch32 state only.

0001

EL1 can be executed in AArch64 state only.

0010

EL1 can be executed in either AArch64 or AArch32 state.

All other values are reserved.

In an ARMv8-A implementation that supports AArch64 state in at least one Exception level, this field returns the value of ID_AA64PFR0_EL1.EL1.

EL0, bits [3:0]

AArch64 EL0 Exception level handling. Defined values are:

EL0Meaning
0000

EL0 can be executed in AArch32 state only.

0001

EL0 can be executed in AArch64 state only.

0010

EL0 can be executed in either AArch64 or AArch32 state.

All other values are reserved.

In an ARMv8-A implementation that supports AArch64 state in at least one Exception level, this field returns the value of ID_AA64PFR0_EL1.EL0.

Accessing the EDPFR

EDPFR[31:0] can be accessed through the external debug interface:

ComponentOffset
Debug 0xD20

EDPFR[63:32] can be accessed through the external debug interface:

ComponentOffset
Debug 0xD24



18/04/2017 17:00

Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Confidential.