The ATS1HW characteristics are:
Performs stage 1 address translation as defined for PL2 and the Non-secure state, with permissions as if writing to the given virtual address.
This System instruction is part of:
There are no configuration notes.
ATS1HW is a 32-bit System instruction.
The ATS1HW input value bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Input address for translation |
Input address for translation. The resulting address can be read from the PAR.
This instruction takes a VA as input. The resulting address is the PA that is the output address of the translation.
This instruction is executed using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 4, <Rt>, c7, c8, 1 | 100 | 001 | 0111 | 1111 | 1000 |
The instruction is executable as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | - | n/a | WO |
x | 0 | 1 | - | - | WO | WO |
x | 1 | 1 | - | n/a | WO | WO |
This table applies to all syntax that can be used to execute this instruction.
If this instruction is executed in a Secure privileged mode other than Monitor mode, then the behavior is CONSTRAINED UNPREDICTABLE, and one of the following behaviors must occur:
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when executing this System instruction.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HSTR_EL2.T7==1, Non-secure execution of this instruction at EL1 is trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T7==1, Non-secure execution of this instruction at EL1 is trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HSTR.T7==1, Non-secure execution of this instruction at EL1 is trapped to Hyp mode.
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