The DBGDTRTXint characteristics are:
Transfers data from the PE to an external debugger. For example, it is used by a debug target to transfer data to the debugger. It is a component of the Debug Communication Channel.
This register is part of the Debug registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register DBGDTRTXint is architecturally mapped to AArch64 System register DBGDTRTX_EL0.
AArch32 System register DBGDTRTXint is architecturally mapped to External register DBGDTRTX_EL0.
This register is in the Cold reset domain. On a Cold reset RW fields in this register reset to architecturally UNKNOWN values. The register is not affected by a Warm reset.
DBGDTRTXint is a 32-bit register.
The DBGDTRTXint bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Return DTRTX |
Return DTRTX.
If TXfull is set to 0, then writes of this register update the value in DTRTX and set TXfull to 1.
For the full behavior of the Debug Communications Channel, see 'The Debug Communication Channel and Instruction Transfer Register' in the ARM ARM, chapter H4.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p14, 0, <Rt>, c0, c5, 0 | 000 | 000 | 0000 | 1110 | 0101 |
Data can be loaded from memory into this register using LDC (immediate) and LDC (literal).
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | WO | WO | n/a | WO |
x | 0 | 1 | WO | WO | WO | WO |
x | 1 | 1 | WO | n/a | WO | WO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If DBGDSCRext.UDCCdis==1, write accesses to this register from EL0 are trapped to Undefined mode.
If MDSCR_EL1.TDCC==1, write accesses to this register from EL0 are trapped to EL1.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TDA==1, Non-secure write accesses to this register from EL0 and EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HDCR.TDA==1, Non-secure write accesses to this register from EL0 and EL1 are trapped to Hyp mode.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TDA==1, write accesses to this register from EL0, EL1, and EL2 are trapped to EL3.
18/04/2017 17:00
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Confidential.