The EDPIDR0 characteristics are:
Provides information to identify an external debug component.
For more information see 'About the Peripheral identification scheme' in the ARMv8 ARM, section H8 (About the External Debug Registers).
This register is part of the Debug registers functional group.
This register is accessible as follows:
Default |
---|
RO |
EDPIDR0 is in the Debug power domain.
Implementation of this register is OPTIONAL.
This register is required for CoreSight compliance.
EDPIDR0 is a 32-bit register.
The EDPIDR0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | PART_0 |
Reserved, RES0.
Part number, least significant byte.
EDPIDR0 can be accessed through the external debug interface:
Component | Offset |
---|---|
Debug | 0xFE0 |
18/04/2017 17:00
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