ESR_EL2, Exception Syndrome Register (EL2)

The ESR_EL2 characteristics are:

Purpose

Holds syndrome information for an exception taken to EL2.

This register is part of:

Configuration

AArch64 System register ESR_EL2 is architecturally mapped to AArch32 System register HSR.

If EL2 is not implemented, this register is RES0 from EL3.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

ESR_EL2 is a 32-bit register.

Field descriptions

See ESR_ELx.

Accessing the ESR_EL2

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
ESR_EL21110001010010000
ESR_EL11100001010010000

Accessibility

The register is accessible as follows:

<systemreg> Control Accessibility
E2HTGENSEL0EL1EL2EL3
ESR_EL2xx0 - - n/a RW
ESR_EL2001 - - RWRW
ESR_EL2011 - n/a RWRW
ESR_EL2101 - - RWRW
ESR_EL2111 - n/a RWRW
ESR_EL1xx0 - ESR_EL1 n/a ESR_EL1
ESR_EL1001 - ESR_EL1 ESR_EL1 ESR_EL1
ESR_EL1011 - n/a ESR_EL1 ESR_EL1
ESR_EL1101 - ESR_EL1 RW ESR_EL1
ESR_EL1111 - n/a RW ESR_EL1

When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic ESR_EL2 or ESR_EL1 are not guaranteed to be ordered with respect to accesses using the other mnemonic.




18/04/2017 17:00

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