The ICV_CTLR characteristics are:
Controls aspects of the behavior of the GIC virtual CPU interface and provides information about the features implemented.
This register is part of:
AArch32 System register ICV_CTLR is architecturally mapped to AArch64 System register ICV_CTLR_EL1.
ICV_CTLR is a 32-bit register.
The ICV_CTLR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | A3V | SEIS | IDbits | PRIbits | 0 | 0 | 0 | 0 | 0 | 0 | EOImode | CBPR |
Reserved, RES0.
Affinity 3 Valid. Read-only and writes are ignored. Possible values are:
A3V | Meaning |
---|---|
0 |
The virtual CPU interface logic only supports zero values of Affinity 3 in SGI generation System registers. |
1 |
The virtual CPU interface logic supports non-zero values of Affinity 3 in SGI generation System registers. |
SEI Support. Read-only and writes are ignored. Indicates whether the virtual CPU interface supports local generation of SEIs:
SEIS | Meaning |
---|---|
0 |
The virtual CPU interface logic does not support local generation of SEIs. |
1 |
The virtual CPU interface logic supports local generation of SEIs. |
Identifier bits. Read-only and writes are ignored. The number of virtual interrupt identifier bits supported:
IDbits | Meaning |
---|---|
000 |
16 bits. |
001 |
24 bits. |
All other values are reserved.
Priority bits. Read-only and writes are ignored. The number of priority bits implemented, minus one.
An implementation must implement at least 32 levels of physical priority (5 priority bits).
This field always returns the number of priority bits implemented.
The division between group priority and subpriority is defined in the binary point registers ICV_BPR0 and ICV_BPR1.
Reserved, RES0.
Virtual EOI mode. Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt:
EOImode | Meaning |
---|---|
0 |
ICV_EOIR0 and ICV_EOIR1 provide both priority drop and interrupt deactivation functionality. Accesses to ICV_DIR are UNPREDICTABLE. |
1 |
ICV_EOIR0 and ICV_EOIR1 provide priority drop functionality only. ICV_DIR provides interrupt deactivation functionality. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Common Binary Point Register. Controls whether the same register is used for interrupt preemption of both virtual Group 0 and virtual Group 1 interrupts:
CBPR | Meaning |
---|---|
0 |
ICV_BPR0 determines the preemption group for virtual Group 0 interrupts only. ICV_BPR1 determines the preemption group for virtual Group 1 interrupts. |
1 |
ICV_BPR0 determines the preemption group for both virtual Group 0 and virtual Group 1 interrupts. Reads of ICV_BPR1 return ICV_BPR0 plus one, saturated to 0b111. Writes to ICV_BPR1 are ignored. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c12, c12, 4 | 000 | 100 | 1100 | 1111 | 1100 |
When HCR.{FMO, IMO} == {0, 0}, execution of this encoding at Non-secure EL1 results in an access to ICC_CTLR.
The register is accessible as follows:
Control | Accessibility | ||||||
---|---|---|---|---|---|---|---|
FMO | IMO | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | x | 0 | - | ICC_CTLR | n/a | ICC_CTLR |
x | x | 1 | 1 | - | n/a | ICC_CTLR | ICC_CTLR |
x | 1 | 0 | 1 | - | RW | ICC_CTLR | ICC_CTLR |
1 | x | 0 | 1 | - | RW | ICC_CTLR | ICC_CTLR |
0 | 0 | 0 | 1 | - | ICC_CTLR | ICC_CTLR | ICC_CTLR |
This table applies to all instructions that can access this register.
ICV_CTLR is only accessible at Non-secure EL1 when HCR.{FMO, IMO} != {0, 0}.
When HCR.{FMO, IMO} == {0, 0}, at Non-secure EL1, the instruction encoding used to access ICV_CTLR results in an access to ICC_CTLR.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_SRE.SRE==0, Non-secure accesses to this register from EL1 are UNDEFINED.
If ICC_SRE_EL1.SRE==0, Non-secure accesses to this register from EL1 are trapped to EL1.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==0 :
If HSTR_EL2.T12==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T12==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HSTR.T12==1, Non-secure accesses to this register from EL1 are trapped to Hyp mode.
When SCR_EL3.NS==1 :
If ICH_HCR.TC==1, Non-secure accesses to this register from EL1 are trapped to EL2.
If ICH_HCR_EL2.TC==1, Non-secure accesses to this register from EL1 are trapped to EL2.
18/04/2017 17:00
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Confidential.