The MDRAR_EL1 characteristics are:
Defines the base physical address of a 4KB-aligned memory-mapped debug component, usually a ROM table that locates and describes the memory-mapped debug components in the system. ARMv8 deprecates any use of this register.
This register is part of the Debug registers functional group.
AArch64 System register MDRAR_EL1 is architecturally mapped to AArch32 System register DBGDRAR.
MDRAR_EL1 is a 64-bit register.
The MDRAR_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ROMADDR[51:48] | ROMADDR[47:12] | ||||||||||||||||||
ROMADDR[47:12] | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Valid | ||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Extension to ROMADDR[47:12]. See ROMADDR[47:12] for more details.
Reserved, RES0.
Bits[47:12] of the ROM table physical address.
When ARMv8.2-LPA is implemented, and 52-bit addresses and a 64KB translation granule are in use, ROMADDR[52:49] forms the upper part of the address value. Otherwise, ROMADDR[52:49] is RES0.
If the physical address size in bits (PAsize) is less than 52 then the register bits corresponding to ROMADDR [51:PAsize] are RES0.
Bits [11:0] of the ROM table physical address are zero.
ARM strongly recommends that bits ROMADDR[(PAsize-1):32] are zero in any system that supports AArch32 at the highest implemented Exception level.
In an implementation that includes EL3, ROMADDR is an address in Non-secure memory. It is IMPLEMENTATION DEFINED whether the ROM table is also accessible in Secure memory.
Reserved, RES0.
This field indicates whether the ROM Table address is valid. The permitted values of this field are:
Valid | Meaning |
---|---|
00 |
ROM Table address is not valid. Software must ignore ROMADDR. |
11 |
ROM Table address is valid. |
Other values are reserved.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
MDRAR_EL1 | 10 | 000 | 0001 | 0000 | 000 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TDRA==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TDA==1, read accesses to this register from EL1 and EL2 are trapped to EL3.
18/04/2017 17:00
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