The PMCCNTR_EL0 characteristics are:
Holds the value of the processor Cycle Counter, CCNT, that counts processor clock cycles. See 'Time as measured by the Performance Monitors cycle counter' in the ARMv8 ARM, section D5 for more information.
PMCCFILTR_EL0 determines the modes and states in which the PMCCNTR_EL0 can increment.
This register is part of the Performance Monitors registers functional group.
This register is accessible as follows:
Off | DLK | OSLK | EPMAD | SLK | Default |
---|---|---|---|---|---|
Error | Error | Error | Error | RO | RW |
External register PMCCNTR_EL0 is architecturally mapped to AArch64 System register PMCCNTR_EL0.
External register PMCCNTR_EL0 is architecturally mapped to AArch32 System register PMCCNTR.
PMCCNTR_EL0 is in the Core power domain. RW fields in this register reset to architecturally UNKNOWN values. These apply on a Warm or Cold reset. The register is not affected by an External debug reset.
PMCCNTR_EL0 is a 64-bit register.
The PMCCNTR_EL0 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
CCNT | |||||||||||||||||||||||||||||||
CCNT | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Cycle count. Depending on the values of PMCR_EL0.{LC,D}, the cycle count increments in one of the following ways:
Writing 1 to PMCR_EL0.C sets this field to 0.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
PMCCNTR_EL0[31:0] can be accessed through the external debug interface:
Component | Offset |
---|---|
PMU | 0x0F8 |
PMCCNTR_EL0[63:32] can be accessed through the external debug interface:
Component | Offset |
---|---|
PMU | 0x0FC |
18/04/2017 17:00
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