The DBGDEVID1 characteristics are:
Adds to the information given by the DBGDIDR by describing other features of the debug implementation.
This register is part of the Debug registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
This register is required in all implementations.
DBGDEVID1 is a 32-bit register.
The DBGDEVID1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | PCSROffset |
Reserved, RES0.
This field indicates the offset applied to PC samples returned by reads of EDPCSR. Permitted values of this field in ARMv8 are:
PCSROffset | Meaning |
---|---|
0000 |
EDPCSR not implemented. |
0010 |
EDPCSR implemented. Samples have no offset applied and do not sample the instruction set state in AArch32 state. Note
In ARMv7, a PCSROffset value of 0000 has an alternative meaning that EDPCSR is implemented and returns values that have an offset applied and indicate the Instruction set state. This implementation option is not permitted in ARMv8. |
From ARMv8.2 onwards, the only permitted value is 0b0000. The architecture defines the functionality in a different set of registers, see PMDEVID.
This register can be read using MRC with the following syntax:
MRC <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p14, 0, <Rt>, c7, c1, 7 | 000 | 111 | 0111 | 1110 | 0001 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TDA==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HDCR.TDA==1, Non-secure read accesses to this register from EL1 are trapped to Hyp mode.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TDA==1, read accesses to this register from EL1 and EL2 are trapped to EL3.
18/04/2017 17:00
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