The AMAIR_EL2 characteristics are:
Provides IMPLEMENTATION DEFINED memory attributes for the memory regions specified by MAIR_EL2.
This register is part of:
AArch64 System register AMAIR_EL2 bits [31:0] are architecturally mapped to AArch32 System register HAMAIR0.
AArch64 System register AMAIR_EL2 bits [63:32] are architecturally mapped to AArch32 System register HAMAIR1.
If EL2 is not implemented, this register is RES0 from EL3.
RW fields in this register reset to architecturally UNKNOWN values.
AMAIR_EL2 is a 64-bit register.
The AMAIR_EL2 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AMAIR_EL2 is permitted to be cached in a TLB.
IMPLEMENTATION DEFINED.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
AMAIR_EL2 | 11 | 100 | 1010 | 0011 | 000 |
AMAIR_EL1 | 11 | 000 | 1010 | 0011 | 000 |
The register is accessible as follows:
<systemreg> | Control | Accessibility | |||||
---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | |
AMAIR_EL2 | x | x | 0 | - | - | n/a | RW |
AMAIR_EL2 | 0 | 0 | 1 | - | - | RW | RW |
AMAIR_EL2 | 0 | 1 | 1 | - | n/a | RW | RW |
AMAIR_EL2 | 1 | 0 | 1 | - | - | RW | RW |
AMAIR_EL2 | 1 | 1 | 1 | - | n/a | RW | RW |
AMAIR_EL1 | x | x | 0 | - | AMAIR_EL1 | n/a | AMAIR_EL1 |
AMAIR_EL1 | 0 | 0 | 1 | - | AMAIR_EL1 | AMAIR_EL1 | AMAIR_EL1 |
AMAIR_EL1 | 0 | 1 | 1 | - | n/a | AMAIR_EL1 | AMAIR_EL1 |
AMAIR_EL1 | 1 | 0 | 1 | - | AMAIR_EL1 | RW | AMAIR_EL1 |
AMAIR_EL1 | 1 | 1 | 1 | - | n/a | RW | AMAIR_EL1 |
When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic AMAIR_EL2 or AMAIR_EL1 are not guaranteed to be ordered with respect to accesses using the other mnemonic.
18/04/2017 17:00
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