The CPTR_EL2 characteristics are:
Controls:
This register is part of the Virtualization registers functional group.
AArch64 System register CPTR_EL2 is architecturally mapped to AArch32 System register HCPTR.
If EL2 is not implemented, this register is RES0 from EL3.
RW fields in this register reset to architecturally UNKNOWN values.
CPTR_EL2 is a 32-bit register.
The CPTR_EL2 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TCPAC | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | TTA | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | TFP | 1 | TZ | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
This format applies in all ARMv8.0 implementations.
Traps Non-secure EL1 accesses to CPACR_EL1 or CPACR to EL2, from both Execution states.
TCPAC | Meaning |
---|---|
0 |
This control does not cause any instructions to be trapped. |
1 |
Non-secure EL1 accesses to CPACR_EL1 and CPACR are trapped to EL2. |
Reserved, RES0.
Traps Non-secure System register accesses to all implemented trace registers to EL2, from both Execution states.
TTA | Meaning |
---|---|
0 |
This control does not cause any instructions to be trapped. |
1 |
Any attempt at EL2, or Non-secure EL0 or EL1, to execute a System register access to an implemented trace register is trapped to EL2, unless it is trapped by CPACR.NSTRCDIS or CPACR_EL1.TTA. |
System register accesses to the trace registers can have side-effects. When a System register access is trapped, any side-effects that are normally associated with the access do not occur before the exception is taken.
If System register access to the trace functionality is not supported, this bit is RES0.
Reserved, RES0.
Reserved, RES1.
Reserved, RES0.
Traps Non-secure accesses to SVE, Advanced SIMD and floating-point functionality to EL2, from both Execution states.
TFP | Meaning |
---|---|
0 |
This control does not cause any instructions to be trapped. |
1 |
Any attempt at EL2, or Non-secure EL0 or EL1, to execute an instruction that uses the registers associated with SVE, Advanced SIMD and floating-point execution is trapped to EL2, unless it is trapped by CPACR.cp10, CPACR_EL1.FPEN, and if SVE is implemented, CPACR_EL1.ZEN, or CPTR_EL2.TZ. |
Reserved, RES1.
Present only if SVE is implemented.
Traps Non-secure execution at EL2, EL1, or EL0 of SVE instructions and instructions that access SVE System registers to EL2. Defined values are:
TZ | Meaning |
---|---|
0 |
This control does not cause any instruction to be trapped. |
1 |
This control causes these instructions to be trapped, unless HCR_EL2.TGE is 0 and they are trapped by CPACR_EL1. |
If SVE is not implemented, this field is RES1.
Reserved, RES1.
Reserved, RES1.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TCPAC | 0 | 0 | TTA | 0 | 0 | 0 | 0 | 0 | 0 | FPEN | 0 | 0 | ZEN | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
When HCR_EL2.TGE is 0, traps Non-secure EL1 accesses to CPACR_EL1 and CPACR to EL2, from both Execution states.
TCPAC | Meaning |
---|---|
0 |
This control does not cause any instructions to be trapped. |
1 |
Non-secure EL1 accesses to CPACR_EL1 and CPACR are trapped to EL2. |
When HCR_EL2.TGE is 1, this control does not cause any instructions to be trapped.
Reserved, RES0.
Traps Non-secure System register accesses to all implemented trace registers to EL2, from both Execution states.
TTA | Meaning |
---|---|
0 |
This control does not cause any instructions to be trapped. |
1 |
Any attempt at EL2, or Non-secure EL0 or EL1, to execute a System register access to an implemented trace register is trapped to EL2, unless HCR_EL2.TGE is 0 and it is trapped by CPACR.NSTRCDIS or CPACR_EL1.TTA. When HCR_EL2.TGE is 1, any attempt at EL2, or Non-secure EL0, to execute a System register access to an implemented trace register is trapped to EL2. |
System register accesses to the trace registers can have side-effects. When a System register access is trapped, any side-effects that are normally associated with the access do not occur before the exception is taken.
If System register access to the trace functionality is not supported, this bit is RES0.
Reserved, RES0.
Traps EL2, Non-secure EL0 and, when HCR_EL2.TGE is 0, Non-secure EL1 accesses to the SVE, Advanced SIMD and floating-point registers to EL2, from both Execution states.
FPEN | Meaning |
---|---|
00 |
This control causes any instructions at Non-secure EL0, EL1, or EL2 that use the registers associated with SVE, Advanced SIMD and floating-point execution to be trapped, unless HCR_EL2.TGE is 0 and they are trapped by CPACR.cp10, CPACR_EL1.FPEN, CPACR_EL1.ZEN, or CPTR_EL2.ZEN. |
01 |
When HCR_EL2.TGE is 0, this control does not cause any instructions to be trapped. When HCR_EL2.TGE is 1, this control causes instructions at Non-secure EL0 that use the registers associated with SVE, Advanced SIMD and floating-point execution to be trapped, unless they are trapped by CPTR_EL2.ZEN. |
10 |
This control causes any instructions at Non-secure EL0, EL1, or EL2 that use the registers associated with SVE, Advanced SIMD and floating-point execution to be trapped, unless HCR_EL2.TGE is 0 and they are trapped by CPACR.cp10, CPACR_EL1.FPEN, CPACR_EL1.ZEN, or CPTR_EL2.ZEN. |
11 |
This control does not cause any instructions to be trapped. |
Writes to MVFR0, MVFR1, and MVFR2 from EL1 or higher are CONSTRAINED UNPREDICTABLE and whether these accesses can be trapped by this control depends on implemented CONSTRAINED UNPREDICTABLE behavior.
Reserved, RES0.
Present only if SVE is implemented.
Traps Non-secure execution at EL2, EL1, and EL0 of SVE instructions or instructions that access SVE System registers to EL2.
Defined values are:
ZEN | Meaning |
---|---|
00 |
This control causes Non-secure execution at EL2, EL1, and EL0 of these instructions to be trapped, unless HCR_EL2.TGE is 0 and they are trapped by CPACR_EL1. |
01 |
When HCR_EL2.TGE is 0, this control does not cause any instruction to be trapped. When HCR_EL2.TGE is 1, this control causes these instructions executed at Non-secure EL0 to be trapped, but does not cause any instruction at EL2 to be trapped. |
10 |
This control causes Non-secure execution at EL2, EL1, and EL0 of these instructions to be trapped, unless HCR_EL2.TGE is 0 and they are trapped by CPACR_EL1. |
11 |
This control does not cause any instruction to be trapped. |
If SVE is not implemented, this field is RES0.
Reserved, RES0.
Reserved, RES0.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
CPTR_EL2 | 11 | 100 | 0001 | 0001 | 010 |
CPACR_EL1 | 11 | 000 | 0001 | 0000 | 010 |
The register is accessible as follows:
<systemreg> | Control | Accessibility | |||||
---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | |
CPTR_EL2 | x | x | 0 | - | - | n/a | RW |
CPTR_EL2 | 0 | 0 | 1 | - | - | RW | RW |
CPTR_EL2 | 0 | 1 | 1 | - | n/a | RW | RW |
CPTR_EL2 | 1 | 0 | 1 | - | - | RW | RW |
CPTR_EL2 | 1 | 1 | 1 | - | n/a | RW | RW |
CPACR_EL1 | x | x | 0 | - | CPACR_EL1 | n/a | CPACR_EL1 |
CPACR_EL1 | 0 | 0 | 1 | - | CPACR_EL1 | CPACR_EL1 | CPACR_EL1 |
CPACR_EL1 | 0 | 1 | 1 | - | n/a | CPACR_EL1 | CPACR_EL1 |
CPACR_EL1 | 1 | 0 | 1 | - | CPACR_EL1 | RW | CPACR_EL1 |
CPACR_EL1 | 1 | 1 | 1 | - | n/a | RW | CPACR_EL1 |
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL3 is implemented and is using AArch64 :
If CPTR_EL3.TCPAC==1, accesses to this register from EL2 are trapped to EL3.
18/04/2017 17:00
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