The EDITR characteristics are:
Used in Debug state for passing instructions to the PE for execution.
This register is part of the Debug registers functional group.
This register is accessible as follows:
Off | DLK | OSLK | SLK | Default |
---|---|---|---|---|
Error | Error | Error | WI | WO |
If EDSCR.ITE == 0 when the PE exits Debug state on receiving a Restart request trigger event, the behavior of any instruction issued through the ITR in Normal access mode that has not completed execution is CONSTRAINED UNPREDICTABLE, and must do one of the following:
EDITR ignores writes if the PE is in Non-debug state.
EDITR is in the Core power domain.
EDITR is a 32-bit register.
The EDITR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
T32Second | T32First |
Second halfword of the T32 instruction to be executed on the PE. When EDITR contains a 16-bit T32 instruction, this field is ignored. For more information see 'Behavior in Debug state' in the ARMv8 ARM, section H2, Debug State.
First halfword of the T32 instruction to be executed on the PE.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
A64 instruction to be executed on the PE |
A64 instruction to be executed on the PE.
EDITR can be accessed through the external debug interface:
Component | Offset |
---|---|
Debug | 0x084 |
18/04/2017 17:00
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