The ID_ISAR2 characteristics are:
Provides information about the instruction sets implemented by the PE in AArch32 state.
Must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR3, ID_ISAR4, and ID_ISAR5.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section G4.14.6.
This register is part of the Identification registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register ID_ISAR2 is architecturally mapped to AArch64 System register ID_ISAR2_EL1.
ID_ISAR2 is a 32-bit register.
The ID_ISAR2 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reversal | PSR_AR | MultU | MultS | Mult | MultiAccessInt | MemHint | LoadStore |
Indicates the implemented Reversal instructions. Defined values are:
Reversal | Meaning |
---|---|
0000 |
None implemented. |
0001 |
Adds the REV, REV16, and REVSH instructions. |
0010 |
As for 0001, and adds the RBIT instruction. |
All other values are reserved.
In ARMv8-A the only permitted value is 0010.
Indicates the implemented A and R profile instructions to manipulate the PSR. Defined values are:
PSR_AR | Meaning |
---|---|
0000 |
None implemented. |
0001 |
Adds the MRS and MSR instructions, and the exception return forms of data-processing instructions. |
All other values are reserved.
In ARMv8-A the only permitted value is 0001.
The exception return forms of the data-processing instructions are:
Indicates the implemented advanced unsigned Multiply instructions. Defined values are:
MultU | Meaning |
---|---|
0000 |
None implemented. |
0001 |
Adds the UMULL and UMLAL instructions. |
0010 |
As for 0001, and adds the UMAAL instruction. |
All other values are reserved.
In ARMv8-A the only permitted value is 0010.
Indicates the implemented advanced signed Multiply instructions. Defined values are:
MultS | Meaning |
---|---|
0000 |
None implemented. |
0001 |
Adds the SMULL and SMLAL instructions. |
0010 |
As for 0001, and adds the SMLABB, SMLABT, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, and SMULWT instructions. Also adds the Q bit in the PSRs. |
0011 |
As for 0010, and adds the SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, and SMUSDX instructions. |
All other values are reserved.
In ARMv8-A the only permitted value is 0011.
Indicates the implemented additional Multiply instructions. Defined values are:
Mult | Meaning |
---|---|
0000 |
No additional instructions implemented. This means only MUL is implemented. |
0001 |
Adds the MLA instruction. |
0010 |
As for 0001, and adds the MLS instruction. |
All other values are reserved.
In ARMv8-A the only permitted value is 0010.
Indicates the support for interruptible multi-access instructions. Defined values are:
MultiAccessInt | Meaning |
---|---|
0000 |
No support. This means the LDM and STM instructions are not interruptible. |
0001 |
LDM and STM instructions are restartable. |
0010 |
LDM and STM instructions are continuable. |
All other values are reserved.
In ARMv8-A the only permitted value is 0000.
Indicates the implemented Memory Hint instructions. Defined values are:
MemHint | Meaning |
---|---|
0000 |
None implemented. |
0001 |
Adds the PLD instruction. |
0010 |
Adds the PLD instruction. (0001 and 0010 have identical effects.) |
0011 |
As for 0001 (or 0010), and adds the PLI instruction. |
0100 |
As for 0011, and adds the PLDW instruction. |
All other values are reserved.
In ARMv8-A the only permitted value is 0100.
Indicates the implemented additional load/store instructions. Defined values are:
LoadStore | Meaning |
---|---|
0000 |
No additional load/store instructions implemented. |
0001 |
Adds the LDRD and STRD instructions. |
0010 |
As for 0001, and adds the Load Acquire (LDAB, LDAH, LDA, LDAEXB, LDAEXH, LDAEX, LDAEXD) and Store Release (STLB, STLH, STL, STLEXB, STLEXH, STLEX, STLEXD) instructions. |
All other values are reserved.
In ARMv8-A the only permitted value is 0010.
This register can be read using MRC with the following syntax:
MRC <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c0, c2, 2 | 000 | 010 | 0000 | 1111 | 0010 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HSTR_EL2.T0==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HSTR_EL2.T0==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
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