The SDCR characteristics are:
When EL3 is implemented and can use AArch32, controls debug and performance monitors functionality in Secure state.
This register is part of:
This register is only accessible in Secure state.
AArch32 System register SDCR can be mapped to AArch64 System register MDCR_EL3, but this is not architecturally mandated.
This register is in the Warm reset domain. Some or all RW fields of this register have defined reset values. On a Warm or Cold reset these apply only if the PE resets into an Exception level that is using AArch32. Otherwise, on a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.
SDCR is a 32-bit register.
The SDCR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | EPMAD | EDAD | 0 | 0 | SPME | 0 | SPD | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Reserved, RES0.
External debug interface Performance Monitors registers disable. This disables access to these registers by an external debugger:
EPMAD | Meaning |
---|---|
0 |
Access to Performance Monitors registers from external debugger is permitted. |
1 |
Access to Performance Monitors registers from external debugger is disabled, unless overridden by the IMPLEMENTATION DEFINED authentication interface. |
If the Performance Monitors Extension is not implemented or does not support external debug interface accesses this bit is RES0.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.
External debug interface breakpoint and watchpoint register access disable. This disables access to these registers by an external debugger:
EDAD | Meaning |
---|---|
0 |
Access to breakpoint and watchpoint registers from external debugger is permitted. |
1 |
Access to breakpoint and watchpoint registers from external debugger is disabled, unless overridden by the IMPLEMENTATION DEFINED authentication interface. |
When this register has an architecturally-defined reset value, this field resets to 0.
Reserved, RES0.
Secure Performance Monitors enable. This allows event counting in Secure state:
SPME | Meaning |
---|---|
0 |
Event counting prohibited in Secure state. In an ARMv8.0 or ARMv8.1 implementation, event counting is prohibited unless ExternalSecureNoninvasiveDebugEnabled() is TRUE, meaning this control is overridden by the IMPLEMENTATION DEFINED authentication interface. |
1 |
Event counting allowed in Secure state. |
If the Performance Monitors Extension is not implemented, this field is RES0.
When this register has an architecturally-defined reset value, this field resets to 0.
Reserved, RES0.
AArch32 Secure privileged debug. Enables or disables debug exceptions from Secure state, other than Breakpoint Instruction exceptions. Valid values for this field are:
SPD | Meaning |
---|---|
00 |
Legacy mode. Debug exceptions from Secure EL1 are enabled by the authentication interface. |
10 |
Secure privileged debug disabled. Debug exceptions from Secure EL1 are disabled. |
11 |
Secure privileged debug enabled. Debug exceptions from Secure EL1 are enabled. |
Other values are reserved, and have the CONSTRAINED UNPREDICTABLE behavior that they must have the same behavior as 0b00. Software must not rely on this property as the behavior of reserved values might change in a future revision of the architecture.
If debug exceptions from Secure EL1 are enabled, then debug exceptions from Secure EL0 are also enabled.
Otherwise, debug exceptions from Secure EL0 are enabled only if SDER32_EL3.SUIDEN == 1.
Ignored in Non-secure state. Debug exceptions from Breakpoint Instruction exceptions are always enabled.
When this register has an architecturally-defined reset value, this field resets to 0.
Reserved, RES0.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c1, c3, 1 | 000 | 001 | 0001 | 1111 | 0011 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | - | n/a | RW |
x | 0 | 1 | - | - | - | RW |
x | 1 | 1 | - | n/a | - | RW |
This table applies to all instructions that can access this register.
If EL3 is implemented and is using AArch64, any read or write to SDCR from Secure EL1 using AArch32 is trapped as an exception to EL3.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HSTR_EL2.T1==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T1==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HSTR.T1==1, Non-secure accesses to this register from EL1 are trapped to Hyp mode.
18/04/2017 17:00
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