The TTBR0 characteristics are:
Holds the base address of the translation table for the initial lookup for stage 1 of the translation of an address from the lower VA range in the PL1&0 translation regime, and other information for this translation regime.
This register is part of the Virtual memory control registers functional group.
AArch32 System register TTBR0 is architecturally mapped to AArch64 System register TTBR0_EL1.
TTBCR.EAE determines which TTBR0 format is used:
When EL3 is using AArch32, write access to TTBR0(S) is disabled when the CP15SDISABLE signal is asserted HIGH.
Used in conjunction with the TTBCR. When the 64-bit TTBR0 format is used, cacheability and shareability information is held in the TTBCR, not in TTBR0.
RW fields in this register reset to architecturally UNKNOWN values.
TTBR0 is a 64-bit register that can also be accessed as a 32-bit value. If it is accessed as a 32-bit register, accesses read and write bits [31:0] and do not modify bits [63:32].
The TTBR0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TTB0 | IRGN[0] | NOS | RGN | IMP | S | IRGN[1] |
Translation table base address, bits[31:x], where x is 14-(TTBCR.N). Register bits [x-1:7] are RES0, with the additional requirement that if these bits are not all zero, this is a misaligned translation table base address, with effects that are CONSTRAINED UNPREDICTABLE, and must be one of the following:
See the IRGN[1] description.
Not Outer Shareable. When the value of TTBR0.S is 1, indicates whether the memory associated with a translation table walk is Inner Shareable or Outer Shareable:
NOS | Meaning |
---|---|
0 |
Memory is Outer Shareable. |
1 |
Memory is Inner Shareable. |
This bit is ignored when the value of TTBR0.S is 0.
Region bits. Indicates the Outer cacheability attributes for the memory associated with the translation table walks:
RGN | Meaning |
---|---|
00 |
Normal memory, Outer Non-cacheable. |
01 |
Normal memory, Outer Write-Back Write-Allocate Cacheable. |
10 |
Normal memory, Outer Write-Through Cacheable. |
11 |
Normal memory, Outer Write-Back no Write-Allocate Cacheable. |
The effect of this bit is IMPLEMENTATION DEFINED. If the translation table implementation does not include any IMPLEMENTATION DEFINED features this bit is UNK/SBZP.
Shareable. Indicates whether the memory associated with the translation table walks is Non-shareable:
S | Meaning |
---|---|
0 |
Memory is Non-shareable. |
1 |
Memory is shareable. The TTBR0.NOS field indicates whether the memory is Inner Shareable or Outer Shareable. |
Inner region bits. IRGN[1:0] indicate the Inner Cacheability attributes for the memory associated with the translation table walks. The possible values of IRGN[1:0] are:
IRGN | Meaning |
---|---|
00 |
Normal memory, Inner Non-cacheable. |
01 |
Normal memory, Inner Write-Back Write-Allocate Cacheable. |
10 |
Normal memory, Inner Write-Through Cacheable. |
11 |
Normal memory, Inner Write-Back no Write-Allocate Cacheable. |
The encoding of the IRGN bits is counter-intuitive, with register bit[6] being IRGN[0] and register bit[0] being IRGN[1]. This encoding is chosen to give a consistent encoding of memory region types and to ensure that software written for ARMv7 without the Multiprocessing Extensions can run unmodified on an implementation that includes the functionality introduced by the ARMv7 Multiprocessing Extensions.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ASID | BADDR | ||||||||||||||||||||||
BADDR | CnP | ||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
An ASID for the translation table base address. The TTBCR.A1 field selects either TTBR0.ASID or TTBR1.ASID.
Translation table base address, bits[47:x], Bits [x-1:1] are RES0, with the additional requirement that if bits[x-1:3] are not all zero, this is a misaligned translation table base address, with effects that are CONSTRAINED UNPREDICTABLE, and must be one of the following:
x is determined from the value of TTBCR.T0SZ as follows:
If bits[47:40] of the translation table base address are not zero, an Address size fault is generated.
Common not Private. In an implementation that includes ARMv8.2-TTCNP, when TTBCR.EAE ==1, indicates whether each entry that is pointed to by TTBR0 is a member of a common set that can be used by every PE in the Inner Shareable domain for which the value of TTBR0.CnP is 1.
CnP | Meaning |
---|---|
0 |
The translation table entries pointed to by this instance of TTBR0, for the current ASID, are permitted to differ from corresponding entries for this instance of TTBR0 for other PEs in the Inner Shareable domain. This is not affected by:
|
1 |
The translation table entries pointed to by this instance of TTBR0 are the same as the translation table entries for every other PE in the Inner Shareable domain for which the value of TTBR0.CnP is 1 for this instance of TTBR0 and all of the following apply:
|
When a TLB combines entries from stage 1 translation and stage 2 translation into a single entry, that entry can only be shared between different PEs if the value of the CnP bit is 1 for both stage 1 and stage 2.
If the value of the TTBR0.CnP bit is 1 on multiple PEs in the same Inner Shareable domain and those TTBR0s do not point to the same translation table entries when the other conditions specified for the case when the value of CnP is 1 apply, then the results of translations are CONSTRAINED UNPREDICTABLE, see 'CONSTRAINED UNPREDICTABLE behaviors due to caching of control or data values' in the ARMv8-A ARM appendix K1.
In an implementation that does not include ARMv8.2-TTCNP this field is RES0.
Reserved, RES0.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c2, c0, 0 | 000 | 000 | 0010 | 1111 | 0000 |
This register can be read using MRRC with the following syntax:
MRRC <syntax>
This register can be written using MCRR with the following syntax:
MCRR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | coproc | CRm |
---|---|---|---|
p15, 0, <Rt>, <Rt2>, c2 | 0000 | 1111 | 0010 |
The register is accessible as follows:
Configuration | Control | Accessibility | Instance | |||||
---|---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | ||
EL3 not implemented | x | x | 0 | - | RW | n/a | n/a | TTBR0 |
EL3 not implemented | x | 0 | 1 | - | RW | RW | n/a | TTBR0 |
EL3 not implemented | x | 1 | 1 | - | n/a | RW | n/a | TTBR0 |
EL3 using AArch64 | x | x | 0 | - | RW | n/a | n/a | TTBR0 |
EL3 using AArch64 | x | 0 | 1 | - | RW | RW | n/a | TTBR0 |
EL3 using AArch64 | x | 1 | 1 | - | n/a | RW | n/a | TTBR0 |
EL3 using AArch32 | x | x | 0 | - | n/a | n/a | RW | TTBR0_s |
EL3 using AArch32 | x | 0 | 1 | - | RW | RW | RW | TTBR0_ns |
EL3 using AArch32 | x | 1 | 1 | - | n/a | RW | RW | TTBR0_ns |
This table applies to all instructions that can access this register.
When EL3 is using AArch32, write access to TTBR0_s is UNDEFINED when the CP15SDISABLE signal is asserted HIGH.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TVM==1, Non-secure write accesses to this register from EL1 are trapped to EL2.
If HCR_EL2.TRVM==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HSTR_EL2.T2==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TVM==1, Non-secure write accesses to this register from EL1 are trapped to EL2.
If HCR_EL2.TRVM==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HSTR_EL2.T2==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
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