CPTR_EL3, Architectural Feature Trap Register (EL3)

The CPTR_EL3 characteristics are:

Purpose

Controls trapping to EL3 of access to CPACR_EL1, CPTR_EL2, trace functionality and registers associated with SVE, Advanced SIMD and floating-point execution. Also controls EL3 access to trace functionality and registers associated with SVE, Advanced SIMD and floating-point execution.

This register is part of the Security registers functional group.

Configuration

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

CPTR_EL3 is a 32-bit register.

Field descriptions

The CPTR_EL3 bit assignments are:

313029282726252423222120191817161514131211109876543210
TCPAC0000000000TTA000000000TFP0EZ00000000

TCPAC, bit [31]

Traps all of the following to EL3, from both Security states and both Execution states.

When CPTR_EL3.TCPAC is:

TCPACMeaning
0

This control does not cause any instructions to be trapped.

1

EL2 accesses to the CPTR_EL2 or HCPTR, and EL2 and EL1 accesses to the CPACR_EL1 or CPACR, are trapped to EL3, unless they are trapped by CPTR_EL2.TCPAC.

Bits [30:21]

Reserved, RES0.

TTA, bit [20]

Traps System register accesses to the trace registers, from all Exception levels, both Security states, and both Execution states, to EL3.

TTAMeaning
0

This control does not cause any instructions to be trapped.

1

Any System register access to the trace registers is trapped to EL3, subject to the exception prioritization rules, unless it is trapped by CPACR.NSTRCDIS, CPACR_EL1.TTA or CPTR_EL2.TTA.

If System register access to trace functionality is not supported, this bit is RES0.

Bits [19:11]

Reserved, RES0.

TFP, bit [10]

Traps all accesses to SVE, Advanced SIMD and floating-point functionality, from all Exception levels, both Security states, and both Execution states, to EL3. Defined values are:

TFPMeaning
0

This control does not cause any instructions to be trapped.

1

Any attempt at any Exception level to execute an instruction that uses the registers associated with SVE, Advanced SIMD and floating-point is trapped to EL3, subject to the exception prioritization rules, unless it is trapped by CPACR.cp10, CPACR_EL1.FPEN, CPTR_EL2.TFP, and if SVE is implemented, CPACR_EL1.ZEN, CPTR_EL2.FPEN, CPTR_EL2.ZEN, or CPTR_EL2.TZ.

Bit [9]

Reserved, RES0.

EZ, bit [8]
In ARMv8.2:

Present only if SVE is implemented.

Traps all accesses to SVE functionality and registers from all Exception levels, and both Security states, to EL3. Defined values are:

EZMeaning
0

This control causes these instructions executed at any Exception level to be trapped unless they are trapped by CPTR_EL2 or CPACR_EL1.

1

This control does not cause any instruction to be trapped.

If SVE is not implemented, this field is RES0.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

Bits [7:0]

Reserved, RES0.

Accessing the CPTR_EL3

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
CPTR_EL31111000010001010

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - - n/a RW
x01 - - - RW
x11 - n/a - RW

This table applies to all instructions that can access this register.




18/04/2017 17:00

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