The HACR_EL2 characteristics are:
Controls trapping to EL2 of IMPLEMENTATION DEFINED aspects of Non-secure EL1 or EL0 operation.
ARM recommends the values in this register do not cause unnecessary traps to EL2 when HCR_EL2.{E2H, TGE} == {1, 1}.
This register is part of:
AArch64 System register HACR_EL2 is architecturally mapped to AArch32 System register HACR.
If EL2 is not implemented, this register is RES0 from EL3.
RW fields in this register reset to architecturally UNKNOWN values.
HACR_EL2 is a 32-bit register.
The HACR_EL2 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED |
IMPLEMENTATION DEFINED.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
HACR_EL2 | 11 | 100 | 0001 | 0001 | 111 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | - | n/a | RW |
0 | 0 | 1 | - | - | RW | RW |
0 | 1 | 1 | - | n/a | RW | RW |
1 | 0 | 1 | - | - | RW | RW |
1 | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
18/04/2017 17:00
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