The EDSCR characteristics are:
Main control register for the debug implementation.
This register is part of the Debug registers functional group.
This register is accessible as follows:
Off | DLK | OSLK | SLK | Default |
---|---|---|---|---|
Error | Error | Error | RO | RW |
EDSCR is in the Core power domain. Some or all RW fields of this register have defined reset values. These apply only on a Cold reset. The register is not affected by a Warm reset and is not affected by an External debug reset.
EDSCR is a 32-bit register.
The EDSCR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | RXfull | TXfull | ITO | RXO | TXU | PipeAdv | ITE | INTdis | TDA | MA | SC2 | NS | 0 | SDD | 0 | HDE | RW | EL | A | ERR | STATUS |
Reserved, RES0.
DTRRX full. This bit is RO.
When this register has an architecturally-defined reset value, this field resets to 0.
DTRTX full. This bit is RO.
When this register has an architecturally-defined reset value, this field resets to 0.
ITR overrun. This bit is RO.
If the PE is in Non-debug state, this bit is UNKNOWN. ITO is set to 0 on entry to Debug state.
DTRRX overrun. This bit is RO.
When this register has an architecturally-defined reset value, this field resets to 0.
DTRTX underrun. This bit is RO.
When this register has an architecturally-defined reset value, this field resets to 0.
Pipeline advance. This bit is RO. Set to 1 every time the PE pipeline retires one or more instructions. Cleared to 0 by a write to EDRCR.CSPA.
The architecture does not define precisely when this bit is set to 1. It requires only that this happen periodically in Non-debug state to indicate that software execution is progressing.
ITR empty. This bit is RO.
If the PE is in Non-debug state, this bit is UNKNOWN. It is always valid in Debug state.
Interrupt disable. Disables taking interrupts (including virtual interrupts and System Error interrupts) in Non-Debug state.
If ExternalInvasiveDebugEnabled() = FALSE, the value of this field is ignored.
If ExternalInvasiveDebugEnabled() = TRUE, the possible values of this field are:
INTdis | Meaning |
---|---|
00 |
Do not disable interrupts. |
01 |
Disable interrupts taken to Non-secure EL1. |
10 |
Disable interrupts taken only to Non-secure EL1 and Non-secure EL2. If external secure invasive debug is enabled, also disable interrupts taken to Secure EL1. |
11 |
Disable interrupts taken only to Non-secure EL1 and Non-secure EL2. If external secure invasive debug is enabled, also disable all other interrupts. |
The value of INTdis does not affect whether an interrupt is a WFI wake-up event, but can mask an interrupt as a WFE wake-up event.
If EL3 and EL2 are not implemented, the values 0b01 and 0b10 are reserved. If programmed with a reserved value the PE behaves as if INTdis has been programmed with a defined value, other than for a direct read of EDSCR, and the value returned by a read of EDSCR.INTdis is UNKNOWN.
When this register has an architecturally-defined reset value, this field resets to 0.
Traps accesses to the following Debug System registers:
The possible values of this field are:
TDA | Meaning |
---|---|
0 |
Accesses to Debug System registers do not generate a Software Access debug event. |
1 |
Accesses to Debug System registers generate a Software Access debug event, if OSLSR.OSLK is 0 and if halting is allowed. |
When this register has an architecturally-defined reset value, this field resets to 0.
Memory access mode. Controls use of memory-access mode for accessing ITR and the DCC. This bit is ignored if in Non-debug state and set to zero on entry to Debug state.
Possible values of this field are:
MA | Meaning |
---|---|
0 |
Normal access mode. |
1 |
Memory access mode. |
Reserved, RES0.
Sample CONTEXTIDR_EL2. Controls whether the Sample-based Profiling Extension samples CONTEXTIDR_EL2 or VTTBR_EL2.VMID.
SC2 | Meaning |
---|---|
0 |
Sample VTTBR_EL2.VMID. |
1 |
Sample CONTEXTIDR_EL2. |
If the PC Sample-based Profiling Extension is not implemented, then this field is RES0.
Non-secure status. Read-only. When in Debug state, gives the current Security state:
NS | Meaning |
---|---|
0 |
Secure state, IsSecure() == TRUE. |
1 |
Non-secure state, IsSecure() == FALSE. |
In Non-debug state, this bit is UNKNOWN.
Reserved, RES0.
Secure debug disabled. This bit is RO.
On entry to Debug state:
In Debug state, the value of the SDD bit does not change, even if ExternalSecureInvasiveDebugEnabled() changes.
In Non-debug state:
If EL3 is not implemented and the implementation is Non-secure, this bit is RES1.
Reserved, RES0.
Halting debug enable. The possible values of this field are:
HDE | Meaning |
---|---|
0 |
Halting disabled for Breakpoint, Watchpoint and Halt Instruction debug events. |
1 |
Halting enabled for Breakpoint, Watchpoint and Halt Instruction debug events. |
When this register has an architecturally-defined reset value, this field resets to 0.
Exception level Execution state status. Read-only. In Debug state, each bit gives the current Execution state of each EL:
RW | Meaning |
---|---|
1111 | All Exception levels are using AArch64. |
1110 | EL0 is using AArch32. All other Exception levels are using AArch64. |
110x | EL0 and EL1 are using AArch32. All other Exception levels are using AArch64. Never seen if EL2 is not implemented in the current Security state. |
10xx | EL0, EL1, and, if implemented in the current Security state, EL2 are using AArch32. All other Exception levels are using AArch64. |
0xxx | All Exception levels are using AArch32. |
However:
In Non-debug state, this field is RAO.
Exception level. Read-only. In Debug state, this gives the current EL of the PE.
In Non-debug state, this field is RAZ.
System Error interrupt pending. Read-only. In Debug state, indicates whether a SError interrupt is pending:
A | Meaning |
---|---|
0 |
No SError interrupt pending. |
1 |
SError interrupt pending. |
A debugger can read EDSCR to check whether an SError interrupt is pending without having to execute further instructions. A pending SError might indicate data from target memory is corrupted.
UNKNOWN in Non-debug state.
Cumulative error flag. This field is RO. It is set to 1 following exceptions in Debug state and on any signaled overrun or underrun on the DTR or EDITR.
When this register has an architecturally-defined reset value, this field resets to 0.
Debug status flags. This field is RO.
The possible values of this field are:
STATUS | Meaning |
---|---|
000010 |
PE is in Non-debug state. |
000001 |
PE is restarting, exiting Debug state. |
000111 |
Breakpoint. |
010011 |
External debug request. |
011011 |
Halting step, normal. |
011111 |
Halting step, exclusive. |
100011 |
OS Unlock Catch. |
100111 |
Reset Catch. |
101011 |
Watchpoint. |
101111 |
HLT instruction. |
110011 |
Software access to debug register. |
110111 |
Exception Catch. |
111011 |
Halting step, no syndrome. |
All other values of STATUS are reserved.
EDSCR can be accessed through the external debug interface:
Component | Offset |
---|---|
Debug | 0x088 |
18/04/2017 17:00
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Confidential.