The ID_AA64PFR0_EL1 characteristics are:
Provides additional information about implemented PE features in AArch64 state.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.
This register is part of the Identification registers functional group.
The external register EDPFR gives information from this register.
ID_AA64PFR0_EL1 is a 64-bit register.
The ID_AA64PFR0_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SVE | |||
RAS | GIC | AdvSIMD | FP | EL3 | EL2 | EL1 | EL0 | ||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Scalable Vector Extension. Defined values are:
SVE | Meaning |
---|---|
0000 |
SVE is not implemented. |
0001 |
SVE is implemented. |
All other values are reserved.
Reserved, RES0.
RAS Extension version. The defined values of this field are:
RAS | Meaning |
---|---|
0000 |
No RAS Extension. |
0001 |
Version 1 of the RAS Extension present. |
All other values are reserved.
System register GIC interface support. Defined values are:
GIC | Meaning |
---|---|
0000 |
No System register interface to the GIC is supported. |
0001 |
System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported. |
All other values are reserved.
Advanced SIMD. Defined values are:
AdvSIMD | Meaning |
---|---|
0000 |
Advanced SIMD is implemented, including support for the following SISD and SIMD operations:
|
0001 |
As for 0000, and also includes support for half-precision floating-point arithmetic. |
1111 |
Advanced SIMD is not implemented. |
All other values are reserved.
This field must have the same value as the FP field.
The permitted values are:
Floating-point. Defined values are:
FP | Meaning |
---|---|
0000 |
Floating-point is implemented, and includes support for:
|
0001 |
As for 0000, and also includes support for half-precision floating-point arithmetic. |
1111 |
Floating-point is not implemented. |
All other values are reserved.
This field must have the same value as the AdvSIMD field.
The permitted values are:
EL3 Exception level handling. Defined values are:
EL3 | Meaning |
---|---|
0000 |
EL3 is not implemented. |
0001 |
EL3 can be executed in AArch64 state only. |
0010 |
EL3 can be executed in either AArch64 or AArch32 state. |
All other values are reserved.
EL2 Exception level handling. Defined values are:
EL2 | Meaning |
---|---|
0000 |
EL2 is not implemented. |
0001 |
EL2 can be executed in AArch64 state only. |
0010 |
EL2 can be executed in either AArch64 or AArch32 state. |
All other values are reserved.
EL1 Exception level handling. Defined values are:
EL1 | Meaning |
---|---|
0001 |
EL1 can be executed in AArch64 state only. |
0010 |
EL1 can be executed in either AArch64 or AArch32 state. |
All other values are reserved.
EL0 Exception level handling. Defined values are:
EL0 | Meaning |
---|---|
0001 |
EL0 can be executed in AArch64 state only. |
0010 |
EL0 can be executed in either AArch64 or AArch32 state. |
All other values are reserved.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
ID_AA64PFR0_EL1 | 11 | 000 | 0000 | 0100 | 000 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
18/04/2017 17:00
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