The DBGBVR<n>_EL1 characteristics are:
Holds a virtual address, or a VMID and/or a context ID, for use in breakpoint matching. Forms breakpoint n together with control register DBGBCR<n>_EL1.
This register is part of the Debug registers functional group.
AArch64 System register DBGBVR<n>_EL1 bits [31:0] are architecturally mapped to AArch32 System register DBGBVR<n>.
AArch64 System register DBGBVR<n>_EL1 bits [63:32] are architecturally mapped to AArch32 System register DBGBXVR<n>.
AArch64 System register DBGBVR<n>_EL1 is architecturally mapped to External register DBGBVR<n>_EL1.
If breakpoint n is not implemented then this register is unallocated.
This register is in the Cold reset domain. On a Cold reset RW fields in this register reset to architecturally UNKNOWN values. The register is not affected by a Warm reset.
How this register is interpreted depends on the value of DBGBCR<n>_EL1.BT.
For other values of DBGBCR<n>_EL1.BT, this register is RES0.
The DBGBVR<n>_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
RESS[14:4] | VA[52:49] | VA[48:2] | |||||||||||||||||||||||||||||
VA[48:2] | 0 | 0 | |||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, Sign extended. Software must treat this field as RES0 if the most significant bit of VA is 0 or RES0, and as RES1 if the most significant bit of VA is 1.
Hardware always ignores the value of these bits and it is IMPLEMENTATION DEFINED whether:
Extension to VA[48:2]. See VA[48:2] for more details.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Extension to RESS[14:4]. See RESS[14:4] for more details.
Bits[48:2] of the address value for comparison.
When ARMv8.2-LVA is implemented, and 52-bit addresses and a 64KB translation granule are in use, VA[52:49] form the upper part of the address value. Otherwise, VA[52:49] are RESS.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Reserved, RES0.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
ContextID | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Context ID value for comparison.
The value is compared against CONTEXTIDR_EL1 in the following cases:
When ARMv8.1-VHE is implemented, HCR_EL2.E2H is 1, the value is compared against CONTEXTIDR_EL2 in the following cases:
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
ContextID | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Context ID value for comparison against CONTEXTIDR_EL1.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | VMID[15:8] | VMID[7:0] | ||||||||||||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Extension to VMID[7:0]. See VMID[7:0] for more details.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Reserved, RES0.
VMID value for comparison.
The VMID is 8 bits in the following cases.
When ARMv8.1-VMID16 is implemented and EL2 is using AArch64, it is IMPLEMENTATION DEFINED whether the VMID is 8 bits or 16 bits.
VMID[15:8] is RES0 if any of the following applies:
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Reserved, RES0.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | VMID[15:8] | VMID[7:0] | ||||||||||||||
ContextID | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Extension to VMID[7:0]. See VMID[7:0] for more details.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Reserved, RES0.
VMID value for comparison.
The VMID is 8 bits in the following cases.
When ARMv8.1-VMID16 is implemented and EL2 is using AArch64, it is IMPLEMENTATION DEFINED whether the VMID is 8 bits or 16 bits.
VMID[15:8] is RES0 if any of the following applies:
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Context ID value for comparison against CONTEXTIDR_EL1.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
ContextID2 | |||||||||||||||||||||||||||||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Context ID value for comparison against CONTEXTIDR_EL2.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Reserved, RES0.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
ContextID2 | |||||||||||||||||||||||||||||||
ContextID | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Context ID value for comparison against CONTEXTIDR_EL2.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Context ID value for comparison against CONTEXTIDR_EL1.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
DBGBVR<n>_EL1 | 10 | 000 | 0000 | n<3:0> | 100 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RW | n/a | RW |
x | 0 | 1 | - | RW | RW | RW |
x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If EDSCR.TDA==1, and OSLSR_EL1.OSLK==0, accesses to this register from EL1, EL2, and EL3 are trapped to Debug state.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TDA==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TDA==1, accesses to this register from EL1 and EL2 are trapped to EL3.
18/04/2017 17:00
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