The MAIR_EL1 characteristics are:
Provides the memory attribute encodings corresponding to the possible AttrIndx values in a Long-descriptor format translation table entry for stage 1 translations at EL1.
This register is part of the Virtual memory control registers functional group.
AArch64 System register MAIR_EL1 bits [31:0] are architecturally mapped to AArch32 System register PRRR when TTBCR.EAE==0.
AArch64 System register MAIR_EL1 bits [31:0] are architecturally mapped to AArch32 System register MAIR0 when TTBCR.EAE==1.
AArch64 System register MAIR_EL1 bits [63:32] are architecturally mapped to AArch32 System register NMRR when TTBCR.EAE==0.
AArch64 System register MAIR_EL1 bits [63:32] are architecturally mapped to AArch32 System register MAIR1 when TTBCR.EAE==1.
RW fields in this register reset to architecturally UNKNOWN values.
MAIR_EL1 is a 64-bit register.
The MAIR_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
Attr7 | Attr6 | Attr5 | Attr4 | ||||||||||||||||||||||||||||
Attr3 | Attr2 | Attr1 | Attr0 | ||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAIR_EL1 is permitted to be cached in a TLB.
The memory attribute encoding for an AttrIndx[2:0] entry in a Long descriptor format translation table entry, where AttrIndx[2:0] gives the value of <n> in Attr<n>.
Bits [7:4] are encoded as follows:
Attr<n>[7:4] | Meaning |
---|---|
0000 | Device memory. See encoding of Attr<n>[3:0] for the type of Device memory. |
00RW, RW not 00 | Normal memory, Outer Write-Through Transient |
0100 | Normal memory, Outer Non-cacheable |
01RW, RW not 00 | Normal memory, Outer Write-Back Transient |
10RW | Normal memory, Outer Write-Through Non-transient |
11RW | Normal memory, Outer Write-Back Non-transient |
R = Outer Read-Allocate policy, W = Outer Write-Allocate policy.
The meaning of bits [3:0] depends on the value of bits [7:4]:
Attr<n>[3:0] | Meaning when Attr<n>[7:4] is 0000 | Meaning when Attr<n>[7:4] is not 0000 |
---|---|---|
0000 | Device-nGnRnE memory | UNPREDICTABLE |
00RW, RW not 00 | UNPREDICTABLE | Normal memory, Inner Write-Through Transient |
0100 | Device-nGnRE memory | Normal memory, Inner Non-cacheable |
01RW, RW not 00 | UNPREDICTABLE | Normal memory, Inner Write-Back Transient |
1000 | Device-nGRE memory | Normal memory, Inner Write-Through Non-transient (RW=00) |
10RW, RW not 00 | UNPREDICTABLE | Normal memory, Inner Write-Through Non-transient |
1100 | Device-GRE memory | Normal memory, Inner Write-Back Non-transient (RW=00) |
11RW, RW not 00 | UNPREDICTABLE | Normal memory, Inner Write-Back Non-transient |
R = Inner Read-Allocate policy, W = Inner Write-Allocate policy.
The R and W bits in some Attr<n> fields have the following meanings:
R or W | Meaning |
---|---|
0 | No Allocate |
1 | Allocate |
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
MAIR_EL1 | 11 | 000 | 1010 | 0010 | 000 |
MAIR_EL12 | 11 | 101 | 1010 | 0010 | 000 |
The register is accessible as follows:
<systemreg> | Control | Accessibility | |||||
---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | |
MAIR_EL1 | x | x | 0 | - | RW | n/a | RW |
MAIR_EL1 | 0 | 0 | 1 | - | RW | RW | RW |
MAIR_EL1 | 0 | 1 | 1 | - | n/a | RW | RW |
MAIR_EL1 | 1 | 0 | 1 | - | RW | MAIR_EL2 | RW |
MAIR_EL1 | 1 | 1 | 1 | - | n/a | MAIR_EL2 | RW |
MAIR_EL12 | x | x | 0 | - | - | n/a | - |
MAIR_EL12 | 0 | 0 | 1 | - | - | - | - |
MAIR_EL12 | 0 | 1 | 1 | - | n/a | - | - |
MAIR_EL12 | 1 | 0 | 1 | - | - | RW | RW |
MAIR_EL12 | 1 | 1 | 1 | - | n/a | RW | RW |
When HCR_EL2.E2H is 1, without explicit synchronization, access from EL3 using the mnemonic MAIR_EL1 or MAIR_EL12 are not guaranteed to be ordered with respect to accesses using the other mnemonic.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TRVM==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HCR_EL2.TVM==1, Non-secure write accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
18/04/2017 17:00
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