The DCZID_EL0 characteristics are:
Indicates the block size that is written with byte values of 0 by the DC ZVA (Data Cache Zero by Address) system instruction.
This register is part of the Identification registers functional group.
There are no configuration notes.
DCZID_EL0 is a 32-bit register.
The DCZID_EL0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DZP | BS |
Reserved, RES0.
Data Zero prohibited. Permitted values are:
DZP | Meaning |
---|---|
0 |
DC ZVA instruction is permitted. |
1 |
DC ZVA instruction is prohibited. |
The value read from this field is governed by the access state and the values of the HCR_EL2.TDZ and SCTLR_EL1.DZE bits.
Log2 of the block size in words. The maximum size supported is 2KB (value == 9).
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
DCZID_EL0 | 11 | 011 | 0000 | 0000 | 111 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | RO | RO | n/a | RO |
x | 0 | 1 | RO | RO | RO | RO |
x | 1 | 1 | RO | n/a | RO | RO |
This table applies to all instructions that can access this register.
18/04/2017 17:00
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