ID_PFR0_EL1, AArch32 Processor Feature Register 0

The ID_PFR0_EL1 characteristics are:

Purpose

Gives top-level information about the instruction sets supported by the PE in AArch32 state.

Must be interpreted with ID_PFR1_EL1.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.

This register is part of the Identification registers functional group.

Configuration

AArch64 System register ID_PFR0_EL1 is architecturally mapped to AArch32 System register ID_PFR0.

In an implementation that supports only AArch64 state, this register is UNKNOWN.

Attributes

ID_PFR0_EL1 is a 32-bit register.

Field descriptions

The ID_PFR0_EL1 bit assignments are:

313029282726252423222120191817161514131211109876543210
RAS000000000000State3State2State1State0

RAS, bits [31:28]

RAS Extension version. The defined values of this field are:

RASMeaning
0000

No RAS Extension.

0001

Version 1 of the RAS Extension present.

All other values are reserved.

Bits [27:16]

Reserved, RES0.

State3, bits [15:12]

T32EE instruction set support. Defined values are:

State3Meaning
0000

Not implemented.

0001

T32EE instruction set implemented.

All other values are reserved.

In ARMv8-A the only permitted value is 0000.

State2, bits [11:8]

Jazelle extension support. Defined values are:

State2Meaning
0000

Not implemented.

0001

Jazelle extension implemented, without clearing of JOSCR.CV on exception entry.

0010

Jazelle extension implemented, with clearing of JOSCR.CV on exception entry.

All other values are reserved.

In ARMv8-A the only permitted value is 0001.

State1, bits [7:4]

T32 instruction set support. Defined values are:

State1Meaning
0000

T32 instruction set not implemented.

0001

T32 encodings before the introduction of Thumb-2 technology implemented:

  • All instructions are 16-bit.
  • A BL or BLX is a pair of 16-bit instructions.
  • 32-bit instructions other than BL and BLX cannot be encoded.
0011

T32 encodings after the introduction of Thumb-2 technology implemented, for all 16-bit and 32-bit T32 basic instructions.

All other values are reserved.

In ARMv8-A the only permitted value is 0011.

State0, bits [3:0]

A32 instruction set support. Defined values are:

State0Meaning
0000

A32 instruction set not implemented.

0001

A32 instruction set implemented.

All other values are reserved.

In ARMv8-A the only permitted value is 0001.

Accessing the ID_PFR0_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
ID_PFR0_EL11100000000001000

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RO n/a RO
x01 - RORORO
x11 - n/a RORO

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :




18/04/2017 17:00

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