PMEVCNTR<n>_EL0, Performance Monitors Event Count Registers, n = 0 - 30

The PMEVCNTR<n>_EL0 characteristics are:

Purpose

Holds event counter n, which counts events, where n is 0 to 30.

This register is part of the Performance Monitors registers functional group.

Usage constraints

This register is accessible as follows:

OffDLKOSLKEPMADSLKDefault
ErrorErrorErrorErrorRORW

External accesses to the performance monitors ignore PMUSERENR_EL0 and, if implemented, MDCR_EL2.{TPM, TPMCR, HPMN} and MDCR_EL3.TPM. This means that all counters are accessible regardless of the current EL or privilege of the access.

Configuration

External register PMEVCNTR<n>_EL0 is architecturally mapped to AArch64 System register PMEVCNTR<n>_EL0.

External register PMEVCNTR<n>_EL0 is architecturally mapped to AArch32 System register PMEVCNTR<n>.

PMEVCNTR<n>_EL0 is in the Core power domain. RW fields in this register reset to architecturally UNKNOWN values. These apply on a Warm or Cold reset. The register is not affected by an External debug reset.

Attributes

PMEVCNTR<n>_EL0 is a 32-bit register.

Field descriptions

The PMEVCNTR<n>_EL0 bit assignments are:

313029282726252423222120191817161514131211109876543210
Event counter n

Bits [31:0]

Event counter n. Value of event counter n, where n is the number of this register and is a number from 0 to 30.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Accessing the PMEVCNTR<n>_EL0

PMEVCNTR<n>_EL0 can be accessed through the external debug interface:

ComponentOffset
PMU0x000 + 8n



18/04/2017 17:00

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