The DBGDEVID characteristics are:
Adds to the information given by the DBGDIDR by describing other features of the debug implementation.
This register is part of the Debug registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
This register is required in all implementations.
DBGDEVID is a 32-bit register.
The DBGDEVID bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CIDMask | AuxRegs | DoubleLock | VirtExtns | VectorCatch | BPAddrMask | WPAddrMask | PCSample |
Indicates the level of support for the Context ID matching breakpoint masking capability. Permitted values of this field are:
CIDMask | Meaning |
---|---|
0000 |
Context ID masking is not implemented. |
0001 |
Context ID masking is implemented. |
All other values are reserved. The value of this for ARMv8 is 0000.
Indicates support for Auxiliary registers. Permitted values for this field are:
AuxRegs | Meaning |
---|---|
0000 |
None supported. |
0001 |
Support for External Debug Auxiliary Control Register, EDACR. |
All other values are reserved.
Indicates the presence of the DBGOSDLR, OS Double Lock Register. Permitted values of this field are:
DoubleLock | Meaning |
---|---|
0000 |
The DBGOSDLR is not present. |
0001 |
The DBGOSDLR is present. |
All other values are reserved. The value of this for ARMv8 is 0001.
Indicates whether EL2 is implemented. Permitted values of this field are:
VirtExtns | Meaning |
---|---|
0000 |
EL2 is not implemented. |
0001 |
EL2 is implemented. |
All other values are reserved.
Defines the form of Vector Catch exception implemented. Permitted values of this field are:
VectorCatch | Meaning |
---|---|
0000 |
Address matching Vector Catch exception implemented. |
0001 |
Exception matching Vector Catch exception implemented. |
All other values are reserved.
Indicates the level of support for the instruction address matching breakpoint masking capability. Permitted values of this field are:
BPAddrMask | Meaning |
---|---|
0000 |
Breakpoint address masking might be implemented. If not implemented, DBGBCR<n>[28:24] is RAZ/WI. |
0001 |
Breakpoint address masking is implemented. |
1111 |
Breakpoint address masking is not implemented. DBGBCR<n>[28:24] is RES0. |
All other values are reserved. The value of this for ARMv8 is 1111.
Indicates the level of support for the data address matching watchpoint masking capability. Permitted values of this field are:
WPAddrMask | Meaning |
---|---|
0000 |
Watchpoint address masking might be implemented. If not implemented, DBGWCR<n>.MASK (Address mask) is RAZ/WI. |
0001 |
Watchpoint address masking is implemented. |
1111 |
Watchpoint address masking is not implemented. DBGWCR<n>.MASK (Address mask) is RES0. |
All other values are reserved. The value of this for ARMv8 is 0001.
Indicates the level of PC Sample-based Profiling support using external debug registers. Permitted values of this field are:
PCSample | Meaning |
---|---|
0000 |
Architecture-defined form of PC Sample-based Profiling not implemented using external debug registers. |
0010 |
Only EDPCSR and EDCIDSR are implemented. This option is only permitted if EL3 and EL2 are not implemented. |
0011 |
All other values are reserved.
From ARMv8.2 onwards, the only permitted value is 0b0000. The architecture defines the functionality in a different set of registers, see PMDEVID.
This register can be read using MRC with the following syntax:
MRC <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p14, 0, <Rt>, c7, c2, 7 | 000 | 111 | 0111 | 1110 | 0010 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TDA==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HDCR.TDA==1, Non-secure read accesses to this register from EL1 are trapped to Hyp mode.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TDA==1, read accesses to this register from EL1 and EL2 are trapped to EL3.
18/04/2017 17:00
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