GICV_EOIR, Virtual Machine End Of Interrupt Register

The GICV_EOIR characteristics are:

Purpose

A write to this register performs a priority drop for the specified Group 0 virtual interrupt and, if GICV_CTLR.EOImode == 0, also deactivates the interrupt.

This register corresponds to the physical CPU interface register GICC_EOIR.

This register is part of the GIC virtual CPU interface registers functional group.

Usage constraints

This register is accessible as follows:

Security disabledSecureNon-secure
WOWOWO

This register is used only when System register access is not enabled. When System register access is enabled:

This register is used for Group 0 interrupts only. GICV_AEOIR provides equivalent functionality for Group 1 interrupts.

When affinity routing is enabled, it is a programming error to use memory-mapped registers to access the GIC.

Configuration

This register is available when the GIC implementation supports interrupt virtualization.

Attributes

GICV_EOIR is a 32-bit register.

Field descriptions

The GICV_EOIR bit assignments are:

313029282726252423222120191817161514131211109876543210
0000000INTID

Bits [31:25]

Reserved, RES0.

INTID, bits [24:0]

The INTID of the signaled interrupt.

Note

INTIDs 1020-1023 are reserved and convey additional information such as spurious interrupts.

When affinity routing is not enabled:

The behavior of this register depends on the setting of GICV_CTLR.EOImode:

GICV_CTLR.EOImode Behavior
0 Both the priority drop and the deactivate interrupt effects occur.
1 Only the priority drop effect occurs.

A successful EOI request means that:

Note

Only Group 1 interrupts can target the hypervisor, and therefore only Group 1 interrupts are deactivated in the Distributor.

Accessing the GICV_EOIR

GICV_EOIR can be accessed through its memory-mapped interface:

ComponentOffset
GIC Virtual CPU interface 0x0010



18/04/2017 17:00

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