CNTHP_CVAL, Counter-timer Hyp Physical CompareValue register

The CNTHP_CVAL characteristics are:

Purpose

Holds the compare value for the Hyp mode physical timer.

This register is part of:

Configuration

AArch32 System register CNTHP_CVAL is architecturally mapped to AArch64 System register CNTHP_CVAL_EL2.

If EL2 is not implemented, this register is RES0 from EL3.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

CNTHP_CVAL is a 64-bit register.

Field descriptions

The CNTHP_CVAL bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
CompareValue
CompareValue
313029282726252423222120191817161514131211109876543210

CompareValue, bits [63:0]

Holds the EL2 physical timer CompareValue.

When CNTHP_CTL.ENABLE is 1, the timer condition is met when (CNTPCT - CompareValue) is greater than zero. This means that CompareValue acts like a 64-bit upcounter timer. When the timer condition is met:

When CNTHP_CTL.ENABLE is 0, the timer condition is not met, but CNTPCT continues to count.

Accessing the CNTHP_CVAL

This register can be read using MRRC with the following syntax:

MRRC <syntax>

This register can be written using MCRR with the following syntax:

MCRR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1coprocCRm
p15, 6, <Rt>, <Rt2>, c14011011111110
p15, 2, <Rt>, <Rt2>, c14001011111110

Accessibility

The register is accessible as follows:

<syntax> Control Accessibility
E2HTGENSEL0EL1EL2EL3
p15, 6, <Rt>, <Rt2>, c14xx0 - - n/a -
p15, 6, <Rt>, <Rt2>, c14x01 - - RWRW
p15, 6, <Rt>, <Rt2>, c14x11 - n/a RWRW
p15, 2, <Rt>, <Rt2>, c14xx0 CNTP_CVAL CNTP_CVAL n/a CNTP_CVAL
p15, 2, <Rt>, <Rt2>, c14001 CNTP_CVAL CNTP_CVAL CNTP_CVAL CNTP_CVAL
p15, 2, <Rt>, <Rt2>, c14011 CNTP_CVAL n/a CNTP_CVAL CNTP_CVAL
p15, 2, <Rt>, <Rt2>, c14101 CNTP_CVAL CNTP_CVAL n/a n/a
p15, 2, <Rt>, <Rt2>, c14111RW n/a n/a n/a

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==1 :




18/04/2017 17:00

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