The ICH_HCR_EL2 characteristics are:
Controls the environment for VMs.
This register is part of:
AArch64 System register ICH_HCR_EL2 is architecturally mapped to AArch32 System register ICH_HCR.
If EL2 is not implemented, this register is RES0 from EL3.
ICH_HCR_EL2 is a 32-bit register.
The ICH_HCR_EL2 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EOIcount | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | TDIR | TSEI | TALL1 | TALL0 | TC | 0 | 0 | VGrp1DIE | VGrp1EIE | VGrp0DIE | VGrp0EIE | NPIE | LRENPIE | UIE | En |
This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation. That is either:
This allows software to manage more active interrupts than there are implemented List Registers.
It is CONSTRAINED UNPREDICTABLE whether a virtual write to EOIR that does not clear a bit in the Active Priorities registers (ICH_AP0R<n>_EL2/ICH_AP1R<n>_EL2) increments EOIcount. Permitted behaviors are:
When this register has an architecturally-defined reset value, this field resets to 0.
Reserved, RES0.
Trap Non-secure EL1 writes to ICC_DIR_EL1 and ICV_DIR_EL1.
TDIR | Meaning |
---|---|
0 |
Non-secure EL1 writes of ICC_DIR_EL1 and ICV_DIR_EL1 are not trapped to EL2, unless trapped by other mechanisms. |
1 |
Non-secure EL1 writes of ICC_DIR_EL1 and ICV_DIR_EL1 are trapped to EL2. |
Support for this bit is OPTIONAL, with support indicated by ICH_VTR_EL2.
If the implementation does not support this trap, this bit is RES0.
ARM deprecates not including this trap bit.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.
Trap all locally generated SEIs. This bit allows the hypervisor to intercept locally generated SEIs that would otherwise be taken at Non-secure EL1.
TSEI | Meaning |
---|---|
0 |
Locally generated SEIs do not cause a trap to EL2. |
1 |
Locally generated SEIs trap to EL2. |
If ICH_VTR_EL2.SEIS is 0, this bit is RES0.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.
Trap all Non-secure EL1 accesses to ICC_* and ICV_* System registers for Group 1 interrupts to EL2.
TALL1 | Meaning |
---|---|
0 |
Non-Secure EL1 accesses to ICC_* and ICV_* registers for Group 1 interrupts proceed as normal. |
1 |
Non-secure EL1 accesses to ICC_* and ICV_* registers for Group 1 interrupts trap to EL2. |
When this register has an architecturally-defined reset value, this field resets to 0.
Trap all Non-secure EL1 accesses to ICC_* and ICV_* System registers for Group 0 interrupts to EL2.
TALL0 | Meaning |
---|---|
0 |
Non-Secure EL1 accesses to ICC_* and ICV_* registers for Group 0 interrupts proceed as normal. |
1 |
Non-secure EL1 accesses to ICC_* and ICV_* registers for Group 0 interrupts trap to EL2. |
When this register has an architecturally-defined reset value, this field resets to 0.
Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2.
TC | Meaning |
---|---|
0 |
Non-secure EL1 accesses to common registers proceed as normal. |
1 |
Non-secure EL1 accesses to common registers trap to EL2. |
This affects accesses to ICC_SGI0R_EL1, ICC_SGI1R_EL1, ICC_ASGI1R_EL1, ICC_CTLR_EL1, ICC_DIR_EL1, ICC_PMR_EL1, ICC_RPR_EL1, ICV_SGI0R_EL1, ICV_SGI1R_EL1, ICV_ASGI1R_EL1, ICV_CTLR_EL1, ICV_DIR_EL1, ICV_PMR_EL1, and ICV_RPR_EL1.
When this register has an architecturally-defined reset value, this field resets to 0.
Reserved, RES0.
VM Group 1 Disabled Interrupt Enable. Enables the signaling of a maintenance interrupt while signaling of Group 1 interrupts from the virtual CPU interface to the connected vPE is disabled:
VGrp1DIE | Meaning |
---|---|
0 |
Maintenance interrupt disabled. |
1 |
Maintenance interrupt signaled when ICH_VMCR_EL2.VENG1 is 0. |
When this register has an architecturally-defined reset value, this field resets to 0.
VM Group 1 Enabled Interrupt Enable. Enables the signaling of a maintenance interrupt while signaling of Group 1 interrupts from the virtual CPU interface to the connected vPE is enabled:
VGrp1EIE | Meaning |
---|---|
0 |
Maintenance interrupt disabled. |
1 |
Maintenance interrupt signaled when ICH_VMCR_EL2.VENG1 is 1. |
When this register has an architecturally-defined reset value, this field resets to 0.
VM Group 0 Disabled Interrupt Enable. Enables the signaling of a maintenance interrupt while signaling of Group 0 interrupts from the virtual CPU interface to the connected vPE is disabled:
VGrp0DIE | Meaning |
---|---|
0 |
Maintenance interrupt disabled. |
1 |
Maintenance interrupt signaled when ICH_VMCR_EL2.VENG0 is 0. |
When this register has an architecturally-defined reset value, this field resets to 0.
VM Group 0 Enabled Interrupt Enable. Enables the signaling of a maintenance interrupt while signaling of Group 0 interrupts from the virtual CPU interface to the connected vPE is enabled:
VGrp0EIE | Meaning |
---|---|
0 |
Maintenance interrupt disabled. |
1 |
Maintenance interrupt signaled when ICH_VMCR_EL2.VENG0 is 1. |
When this register has an architecturally-defined reset value, this field resets to 0.
No Pending Interrupt Enable. Enables the signaling of a maintenance interrupt while no pending interrupts are present in the List registers:
NPIE | Meaning |
---|---|
0 |
Maintenance interrupt disabled. |
1 |
Maintenance interrupt signaled while the List registers contain no interrupts in the pending state. |
When this register has an architecturally-defined reset value, this field resets to 0.
List Register Entry Not Present Interrupt Enable. Enables the signaling of a maintenance interrupt while the virtual CPU interface does not have a corresponding valid List register entry for an EOI request:
LRENPIE | Meaning |
---|---|
0 |
Maintenance interrupt disabled. |
1 |
Maintenance interrupt is asserted while the EOIcount field is not 0. |
When this register has an architecturally-defined reset value, this field resets to 0.
Underflow Interrupt Enable. Enables the signaling of a maintenance interrupt when the List registers are empty, or hold only one valid entry:
UIE | Meaning |
---|---|
0 |
Maintenance interrupt disabled. |
1 |
Maintenance interrupt is asserted if none, or only one, of the List register entries is marked as a valid interrupt. |
When this register has an architecturally-defined reset value, this field resets to 0.
Enable. Global enable bit for the virtual CPU interface:
En | Meaning |
---|---|
0 |
Virtual CPU interface operation disabled. |
1 |
Virtual CPU interface operation enabled. |
When this field is set to 0:
When this register has an architecturally-defined reset value, this field resets to 0.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op1 | CRn | CRm | op2 |
---|---|---|---|---|
ICH_HCR_EL2 | 100 | 1100 | 1011 | 000 |
The register is accessible as follows:
Control | Accessibility | ||||
---|---|---|---|---|---|
TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | 0 | - | - | n/a | RW |
0 | 1 | - | - | RW | RW |
1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_SRE_EL2.SRE==0, accesses to this register from EL2 are trapped to EL2.
If ICC_SRE_EL3.SRE==0, accesses to this register from EL3 are trapped to EL3.
18/04/2017 17:00
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