MVFR1_EL1, AArch32 Media and VFP Feature Register 1

The MVFR1_EL1 characteristics are:

Purpose

Describes the features provided by the AArch32 Advanced SIMD and Floating-point implementation.

Must be interpreted with MVFR0_EL1 and MVFR2_EL1.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.

This register is part of:

Configuration

AArch64 System register MVFR1_EL1 is architecturally mapped to AArch32 System register MVFR1.

In an implementation where at least one Exception level supports execution in AArch32 state, but there is no support for Advanced SIMD and floating-point operation, this register is RAZ.

In an AArch64-only implementation, this register is UNKNOWN.

Attributes

MVFR1_EL1 is a 32-bit register.

Field descriptions

The MVFR1_EL1 bit assignments are:

313029282726252423222120191817161514131211109876543210
SIMDFMACFPHPSIMDHPSIMDSPSIMDIntSIMDLSFPDNaNFPFtZ

SIMDFMAC, bits [31:28]

Advanced SIMD Fused Multiply-Accumulate. Indicates whether the Advanced SIMD implementation provides fused multiply accumulate instructions. Defined values are:

SIMDFMACMeaning
0000

Not implemented.

0001

Implemented.

All other values are reserved.

In ARMv8-A the permitted values are 0000 and 0001.

The Advanced SIMD and floating-point implementations must provide the same level of support for these instructions.

FPHP, bits [27:24]

Floating Point Half Precision. Indicates the level of half-precision floating-point support. Defined values are:

FPHPMeaning
0000

Not supported.

0001

Floating-point half-precision conversion instructions are supported for conversion between single-precision and half-precision.

0010

Floating-point half-precision conversion instructions are supported for conversion between single-precision and half-precision and between double-precision and half-precision.

0011

As for 0010, and also includes support for half-precision floating-point arithmetic.

All other values are reserved.

The permitted values are:

SIMDHP, bits [23:20]

Advanced SIMD Half Precision. Indicates the level of half-precision floating-point support. Defined values are:

SIMDHPMeaning
0000

Not supported.

0001

SIMD half-precision conversion instructions are supported for conversion between single-precision and half-precision.

0010

As for 0010, and also includes support for half-precision floating-point arithmetic.

All other values are reserved.

The permitted values are:

SIMDSP, bits [19:16]

Advanced SIMD Single Precision. Indicates whether the Advanced SIMD and floating-point implementation provides single-precision floating-point instructions. Defined values are:

SIMDSPMeaning
0000

Not implemented.

0001

Implemented. This value is permitted only if the SIMDInt field is 0001.

All other values are reserved.

In ARMv8-A the permitted values are 0000 and 0001.

SIMDInt, bits [15:12]

Advanced SIMD Integer. Indicates whether the Advanced SIMD and floating-point implementation provides integer instructions. Defined values are:

SIMDIntMeaning
0000

Not implemented.

0001

Implemented.

All other values are reserved.

In ARMv8-A the permitted values are 0000 and 0001.

SIMDLS, bits [11:8]

Advanced SIMD Load/Store. Indicates whether the Advanced SIMD and floating-point implementation provides load/store instructions. Defined values are:

SIMDLSMeaning
0000

Not implemented.

0001

Implemented.

All other values are reserved.

In ARMv8-A the permitted values are 0000 and 0001.

FPDNaN, bits [7:4]

Default NaN mode. Indicates whether the floating-point implementation provides support only for the Default NaN mode. Defined values are:

FPDNaNMeaning
0000

Not implemented, or hardware supports only the Default NaN mode.

0001

Hardware supports propagation of NaN values.

All other values are reserved.

In ARMv8-A the permitted values are 0000 and 0001.

FPFtZ, bits [3:0]

Flush to Zero mode. Indicates whether the floating-point implementation provides support only for the Flush-to-Zero mode of operation. Defined values are:

FPFtZMeaning
0000

Not implemented, or hardware supports only the Flush-to-Zero mode of operation.

0001

Hardware supports full denormalized number arithmetic.

All other values are reserved.

In ARMv8-A the permitted values are 0000 and 0001.

Accessing the MVFR1_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
MVFR1_EL11100000000011001

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RO n/a RO
x01 - RORORO
x11 - n/a RORO

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :




02/05/2017 15:43

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