GICC_STATUSR, CPU Interface Status Register

The GICC_STATUSR characteristics are:

Purpose

Provides software with a mechanism to detect:

This register is part of the GIC physical CPU interface registers functional group.

Usage constraints

In an implementation that supports two Security states, there are separate Secure and Non-secure instances of this register:

Security disabledSecureNon-secure
GICC_STATUSR(S)RWRW-
GICC_STATUSR(NS)RW-RW

This is an optional register. If the register is not implemented, the location is RAZ/WI.

If this register is implemented, GICV_STATUSR must also be implemented.

Configuration

If the GIC implementation supports two Security states this register is Banked to provide Secure and Non-secure copies.

This register is used only when System register access is not enabled. If System register access is enabled, this register is not updated. Equivalent functionality might be provided by appropriate traps and exceptions.

Attributes

GICC_STATUSR is a 32-bit register.

Field descriptions

The GICC_STATUSR bit assignments are:

313029282726252423222120191817161514131211109876543210
000000000000000000000000000ASVWRODRWODWRDRRD

Bits [31:5]

Reserved, RES0.

ASV, bit [4]

Attempted security violation.

ASVMeaning
0

Normal operation.

1

A Non-secure access to a Secure register has been detected.

Note

This bit is not set to 1 for registers where any of the fields are Non-secure.

WROD, bit [3]

Write to an RO location.

WRODMeaning
0

Normal operation.

1

A write to an RO location has been detected.

When a violation is detected, software must write 1 to this register to reset it.

RWOD, bit [2]

Read of a WO location.

RWODMeaning
0

Normal operation.

1

A read of a WO location has been detected.

When a violation is detected, software must write 1 to this register to reset it.

WRD, bit [1]

Write to a reserved location.

WRDMeaning
0

Normal operation.

1

A write to a reserved location has been detected.

When a violation is detected, software must write 1 to this register to reset it.

RRD, bit [0]

Read of a reserved location.

RRDMeaning
0

Normal operation.

1

A read of a reserved location has been detected.

When a violation is detected, software must write 1 to this register to reset it.

Accessing the GICC_STATUSR

GICC_STATUSR can be accessed through its memory-mapped interface:

ComponentOffset
GIC CPU interface 0x002C



02/05/2017 15:43

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