PMCEID0, Performance Monitors Common Event Identification register 0

The PMCEID0 characteristics are:

Purpose

Defines which common architectural and common microarchitectural feature events in the range 0x000 to 0x01F are implemented. If a particular bit is set to 1, then the event for that bit is implemented.

Note

This view of the register has previously been called PMCEID0_EL0.

This register is part of the Performance Monitors registers functional group.

Usage constraints

This register is accessible as follows:

OffDLKOSLKEPMADSLKDefault
ErrorErrorErrorErrorRORO

Configuration

External register PMCEID0 is architecturally mapped to AArch64 System register PMCEID0_EL0[31:0] .

External register PMCEID0 bits [31:0] are architecturally mapped to AArch32 System register PMCEID0.

PMCEID0 is in the Core power domain.

Attributes

PMCEID0 is a 32-bit register.

Field descriptions

The PMCEID0 bit assignments are:

313029282726252423222120191817161514131211109876543210
ID[31:0]

ID[31:0], bits [31:0]

PMCEID0[n] maps to event n. For a list of event numbers and descriptions, see 'Event numbers and mnemonics' in the ARM ARM, section D5.10.

For each bit:

ID[31:0]Meaning
0

The common event is not implemented.

1

The common event is implemented.

Bits that map to reserved event numbers are reserved to identify events that might be defined in future revisions to the architecture.

Events that do not require additional features in the PMU can be defined retrospectively, meaning that they can be implemented as part of a PMUv3 implementation.

Accessing the PMCEID0

PMCEID0 can be accessed through the external debug interface:

ComponentOffset
PMU 0xE20



02/05/2017 15:43

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