The ICV_PMR characteristics are:
Provides a virtual interrupt priority filter. Only virtual interrupts with a higher priority than the value in this register are signaled to the PE.
This register is part of:
AArch32 System register ICV_PMR is architecturally mapped to AArch64 System register ICV_PMR_EL1.
To allow software to ensure appropriate observability of actions initiated by GIC register accesses, the PE and CPU interface logic must ensure that writes to this register are self-synchronising. This ensures that no interrupts below the written PMR value will be taken after a write to this register is architecturally executed. See Observability of the effects of accesses to the GIC registers, for more information.
ICV_PMR is a 32-bit register.
The ICV_PMR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Priority |
Reserved, RES0.
The priority mask level for the virtual CPU interface. If the priority of a virtual interrupt is higher than the value indicated by this field, the interface signals the virtual interrupt to the PE.
The possible priority field values are as follows:
Implemented priority bits | Possible priority field values | Number of priority levels |
---|---|---|
[7:0] | 0x00-0xFF (0-255), all values | 256 |
[7:1] | 0x00-0xFE (0-254), even values only | 128 |
[7:2] | 0x00-0xFC (0-252), in steps of 4 | 64 |
[7:3] | 0x00-0xF8 (0-248), in steps of 8 | 32 |
[7:4] | 0x00-0xF0 (0-240), in steps of 16 | 16 |
Unimplemented priority bits are RAZ/WI.
When this register has an architecturally-defined reset value, this field resets to 0.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c4, c6, 0 | 000 | 000 | 0100 | 1111 | 0110 |
When HCR.{FMO, IMO} == {0, 0}, execution of this encoding at Non-secure EL1 results in an access to ICC_PMR.
The register is accessible as follows:
Control | Accessibility | ||||||
---|---|---|---|---|---|---|---|
FMO | IMO | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | x | 0 | - | ICC_PMR | n/a | ICC_PMR |
x | x | 1 | 1 | - | n/a | ICC_PMR | ICC_PMR |
x | 1 | 0 | 1 | - | RW | ICC_PMR | ICC_PMR |
1 | x | 0 | 1 | - | RW | ICC_PMR | ICC_PMR |
0 | 0 | 0 | 1 | - | ICC_PMR | ICC_PMR | ICC_PMR |
This table applies to all instructions that can access this register.
ICV_PMR is only accessible at Non-secure EL1 when HCR.{FMO, IMO} != {0, 0}.
When HCR.{FMO, IMO} == {0, 0}, at Non-secure EL1, the instruction encoding used to access ICV_PMR results in an access to ICC_PMR.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_SRE.SRE==0, Non-secure accesses to this register from EL1 are UNDEFINED.
If ICC_SRE_EL1.SRE==0, Non-secure accesses to this register from EL1 are trapped to EL1.
When SCR_EL3.NS==1 :
If ICH_HCR.TC==1, Non-secure accesses to this register from EL1 are trapped to EL2.
If ICH_HCR_EL2.TC==1, Non-secure accesses to this register from EL1 are trapped to EL2.
02/05/2017 15:43
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