The ICH_VTR characteristics are:
Reports supported GIC virtualisartion features.
This register is part of:
AArch32 System register ICH_VTR is architecturally mapped to AArch64 System register ICH_VTR_EL2.
If EL2 is not implemented, all bits in this register are RES0 from EL3, except for nV4, which is RES1 from EL3.
ICH_VTR is a 32-bit register.
The ICH_VTR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRIbits | PREbits | IDbits | SEIS | A3V | nV4 | TDS | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ListRegs |
Priority bits. The number of virtual priority bits implemented, minus one.
An implementation must implement at least 32 levels of virtual priority (5 priority bits).
This field is an alias of ICV_CTLR.PRIbits.
The number of virtual preemption bits implemented, minus one.
An implementation must implement at least 32 levels of virtual preemption priority (5 preemption bits).
The value of this field must be less than or equal to the value of ICH_VTR.PRIbits.
The number of virtual interrupt identifier bits supported:
IDbits | Meaning |
---|---|
000 |
16 bits. |
001 |
24 bits. |
All other values are reserved.
This field is an alias of ICV_CTLR.IDbits.
SEI Support. Indicates whether the virtual CPU interface supports generation of SEIs:
SEIS | Meaning |
---|---|
0 |
The virtual CPU interface logic does not support generation of SEIs. |
1 |
The virtual CPU interface logic supports generation of SEIs. |
This bit is an alias of ICV_CTLR.SEIS.
Affinity 3 Valid. Possible values are:
A3V | Meaning |
---|---|
0 |
The virtual CPU interface logic only supports zero values of Affinity 3 in SGI generation System registers. |
1 |
The virtual CPU interface logic supports non-zero values of Affinity 3 in SGI generation System registers. |
This bit is an alias of ICV_CTLR.A3V.
Direct injection of virtual interrupts not supported. Possible values are:
nV4 | Meaning |
---|---|
0 |
The CPU interface logic supports direct injection of virtual interrupts. |
1 |
The CPU interface logic does not support direct injection of virtual interrupts. |
In GICv3 this bit is RES1.
Separate trapping of Non-secure EL1 writes to ICV_DIR supported.
TDS | Meaning |
---|---|
0 |
Implementation does not support ICH_HCR.TDIR. |
1 |
Implementation supports ICH_HCR.TDIR. |
Reserved, RES0.
The number of implemented List registers, minus one. For example, a value of 0b01111 indicates that the maximum of 16 List registers are implemented.
This register can be read using MRC with the following syntax:
MRC <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 4, <Rt>, c12, c11, 1 | 100 | 001 | 1100 | 1111 | 1011 |
The register is accessible as follows:
Control | Accessibility | ||||
---|---|---|---|---|---|
TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | 0 | - | - | n/a | - |
0 | 1 | - | - | RO | RO |
1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_HSRE.SRE==0, read accesses to this register from EL2 are UNDEFINED.
If ICC_MSRE.SRE==0, Non-secure read accesses to this register from EL3 are UNDEFINED.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==0 :
If HSTR_EL2.T12==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T12==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HSTR.T12==1, Non-secure accesses to this register from EL1 are trapped to Hyp mode.
02/05/2017 15:43
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