HMAIR0, Hyp Memory Attribute Indirection Register 0

The HMAIR0 characteristics are:

Purpose

Along with HMAIR1, provides the memory attribute encodings corresponding to the possible AttrIndx values in a Long-descriptor format translation table entry for stage 1 translations for memory accesses from Hyp mode.

AttrIndx[2] indicates the HMAIR register to be used:

This register is part of:

Configuration

AArch32 System register HMAIR0 is architecturally mapped to AArch64 System register MAIR_EL2[31:0] .

If EL2 is not implemented, this register is RES0 from EL3.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

HMAIR0 is a 32-bit register.

Field descriptions

The HMAIR0 bit assignments are:

When TTBCR.EAE==1:

313029282726252423222120191817161514131211109876543210
Attr3Attr2Attr1Attr0

Attr<n>, bits [8n+7:8n], for n = 0 to 3

The memory attribute encoding for an AttrIndx[2:0] entry in a Long descriptor format translation table entry, where:

Bits [7:4] are encoded as follows:

Attr<n>[7:4] Meaning
0000 Device memory. See encoding of Attr<n>[3:0] for the type of Device memory.
00RW, RW not 00 Normal memory, Outer Write-Through Transient
0100 Normal memory, Outer Non-cacheable
01RW, RW not 00 Normal memory, Outer Write-Back Transient
10RW Normal memory, Outer Write-Through Non-transient
11RW Normal memory, Outer Write-Back Non-transient

R = Outer Read-Allocate policy, W = Outer Write-Allocate policy.

The meaning of bits [3:0] depends on the value of bits [7:4]:

Attr<n>[3:0] Meaning when Attr<n>[7:4] is 0000 Meaning when Attr<n>[7:4] is not 0000
0000 Device-nGnRnE memory UNPREDICTABLE
00RW, RW not 00 UNPREDICTABLE Normal memory, Inner Write-Through Transient
0100 Device-nGnRE memory Normal memory, Inner Non-cacheable
01RW, RW not 00 UNPREDICTABLE Normal memory, Inner Write-Back Transient
1000 Device-nGRE memory Normal memory, Inner Write-Through Non-transient (RW=00)
10RW, RW not 00 UNPREDICTABLE Normal memory, Inner Write-Through Non-transient
1100 Device-GRE memory Normal memory, Inner Write-Back Non-transient (RW=00)
11RW, RW not 00 UNPREDICTABLE Normal memory, Inner Write-Back Non-transient

R = Inner Read-Allocate policy, W = Inner Write-Allocate policy.

The R and W bits in some Attr<n> fields have the following meanings:

R or W Meaning
0 No Allocate
1 Allocate

Accessing the HMAIR0

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 4, <Rt>, c10, c2, 0100000101011110010

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - - n/a -
x01 - - RWRW
x11 - n/a RWRW

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :




02/05/2017 15:43

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