The VTCR_EL2 characteristics are:
The control register for stage 2 of the EL1&0 translation regime.
This register is part of:
AArch64 System register VTCR_EL2 is architecturally mapped to AArch32 System register VTCR.
If EL2 is not implemented, this register is RES0 from EL3.
RW fields in this register reset to architecturally UNKNOWN values.
VTCR_EL2 is a 32-bit register.
The VTCR_EL2 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 0 | 0 | HWU62 | HWU61 | HWU60 | HWU59 | 0 | 0 | HD | HA | 0 | VS | PS | TG0 | SH0 | ORGN0 | IRGN0 | SL0 | T0SZ |
Any of the bits in VTCR_EL2 are permitted to be cached in a TLB.
Reserved, RES1.
Reserved, RES0.
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[62] of the stage 2 translation table block or level 3 entry.
Defined values are:
HWU62 | Meaning |
---|---|
0 |
The stage 2 translation table entry block or level 3 bit cannot be interpreted by hardware for an IMPLEMENTATION DEFINED purpose. |
1 |
The stage 2 translation table entry block or level 3 bit can be interpreted by hardware for an IMPLEMENTATION DEFINED purpose. |
This bit is RES0, if ARMv8.2-TTPBHA is not implemented.
Reserved, RES0.
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[61] of the stage 2 translation table block or level 3 entry.
Defined values are:
HWU61 | Meaning |
---|---|
0 |
The stage 2 translation table entry block or level 3 bit cannot be interpreted by hardware for an IMPLEMENTATION DEFINED purpose. |
1 |
The stage 2 translation table entry block or level 3 bit can be interpreted by hardware for an IMPLEMENTATION DEFINED purpose. |
This bit is RES0, if ARMv8.2-TTPBHA is not implemented.
Reserved, RES0.
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[60] of the stage 2 translation table block or level 3 entry.
Defined values are:
HWU60 | Meaning |
---|---|
0 |
The stage 2 translation table entry block or level 3 bit cannot be interpreted by hardware for an IMPLEMENTATION DEFINED purpose. |
1 |
The stage 2 translation table entry block or level 3 bit can be interpreted by hardware for an IMPLEMENTATION DEFINED purpose. |
This bit is RES0 if ARMv8.2-TTPBHA is not implemented.
Reserved, RES0.
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[59] of the stage 2 translation table block or level 3 entry.
Defined values are:
HWU59 | Meaning |
---|---|
0 |
The stage 2 translation table entry block or level 3 bit cannot be interpreted by hardware for an IMPLEMENTATION DEFINED purpose. |
1 |
The stage 2 translation table entry block or level 3 bit can be interpreted by hardware for an IMPLEMENTATION DEFINED purpose. |
This bit is RES0 if ARMv8.2-TTPBHA is not implemented.
Reserved, RES0.
Reserved, RES0.
Hardware management of dirty state in stage 2 translations from Non-secure EL0 and EL1.
Defined values are:
HD | Meaning |
---|---|
0 |
Stage 2 hardware management of dirty state disabled. |
1 |
Stage 2 hardware management of dirty state enabled, only if the HA bit is also set to 1. |
This bit is RES0 if ARMv8.1-TTHM is not implemented.
Reserved, RES0.
Hardware Access flag update in stage 2 translations from Non-secure EL0 and EL1.
Defined values are:
HA | Meaning |
---|---|
0 |
Stage 2 Access flag update disabled. |
1 |
Stage 2 Access flag update enabled. |
This bit is RES0 if ARMv8.1-TTHM is not implemented.
Reserved, RES0.
Reserved, RES0.
VMID Size.
Defined values are:
VS | Meaning |
---|---|
0 |
8 bit - the upper 8 bits of VTTBR_EL2 are ignored by the hardware, and treated as if they are all zeros, for every purpose except when reading back the register. |
1 |
16 bit - the upper 8 bits of VTTBR_EL2 are used for allocation and matching in the TLB. |
If the implementation only supports an 8-bit VMID, this field is RES0.
This bit is RES0 if ARMv8.1-VMID16 is not implemented.
Reserved, RES0.
Physical Address Size.
PS | Meaning |
---|---|
000 |
32 bits, 4GB. |
001 |
36 bits, 64GB. |
010 |
40 bits, 1TB. |
011 |
42 bits, 4TB. |
100 |
44 bits, 16TB. |
101 |
48 bits, 256TB. |
110 |
52 bits, 4PB |
Other values are reserved.
The reserved values behave in the same way as the 101 encoding, but software must not rely on this property as the behavior of the reserved values might change in a future revision of the architecture.
The value 110 is permitted only if ARMv8.2-LPA is implemented and the translation granule size is 64KB.
In an implementation that supports 52-bit PAs, if the value of this field is not 110, then bits[51:48] of every translation table base address for the stage of translation controlled by VTCR_EL2 are 0000.
Granule size for the VTTBR_EL2.
TG0 | Meaning |
---|---|
00 |
4KB |
01 |
64KB |
10 |
16KB |
Other values are reserved.
If the value is programmed to either a reserved value, or a size that has not been implemented, then the hardware will treat the field as if it has been programmed to an IMPLEMENTATION DEFINED choice of the sizes that has been implemented for all purposes other than the value read back from this register.
It is IMPLEMENTATION DEFINED whether the value read back is the value programmed or the value that corresponds to the size chosen.
Shareability attribute for memory associated with translation table walks using VTTBR_EL2.
SH0 | Meaning |
---|---|
00 |
Non-shareable |
10 |
Outer Shareable |
11 |
Inner Shareable |
Other values are reserved. The effect of programming this field to a Reserved value is that behavior is CONSTRAINED UNPREDICTABLE, as described in 'Reserved values in AArch64 System registers and translation table entries' in the ARM ARM, section K1.2.2.
Outer cacheability attribute for memory associated with translation table walks using VTTBR_EL2.
ORGN0 | Meaning |
---|---|
00 |
Normal memory, Outer Non-cacheable |
01 |
Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable |
10 |
Normal memory, Outer Write-Through Read-Allocate No Write-Allocate Cacheable |
11 |
Normal memory, Outer Write-Back Read-Allocate No Write-Allocate Cacheable |
Inner cacheability attribute for memory associated with translation table walks using VTTBR_EL2.
IRGN0 | Meaning |
---|---|
00 |
Normal memory, Inner Non-cacheable |
01 |
Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable |
10 |
Normal memory, Inner Write-Through Read-Allocate No Write-Allocate Cacheable |
11 |
Normal memory, Inner Write-Back Read-Allocate No Write-Allocate Cacheable |
Starting level of the VTCR_EL2 addressed region. The meaning of this field depends on the value of VTCR_EL2.TG0 (the granule size).
SL0 | Meaning |
---|---|
00 |
If TG0 is 00 (4KB granule), start at level 2. If TG0 is 10 (16KB granule) or 01 (64KB granule), start at level 3. |
01 |
If TG0 is 00 (4KB granule), start at level 1. If TG0 is 10 (16KB granule) or 01 (64KB granule), start at level 2. |
10 |
If TG0 is 00 (4KB granule), start at level 0. If TG0 is 10 (16KB granule) or 01 (64KB granule), start at level 1. |
All other values are reserved. If this field is programmed to a reserved value, or to a value that is not consistent with the programming of T0SZ, then a stage 2 level 0 Translation fault is generated.
The size offset of the memory region addressed by VTTBR_EL2. The region size is 2(64-T0SZ) bytes.
The maximum and minimum possible values for T0SZ depend on the level of translation table and the memory translation granule size, as described in the AArch64 Virtual Memory System Architecture chapter.
If this field is programmed to a value that is not consistent with the programming of SL0 then a stage 2 level 0 Translation fault is generated.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
VTCR_EL2 | 11 | 100 | 0010 | 0001 | 010 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | - | n/a | RW |
x | 0 | 1 | - | - | RW | RW |
x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
02/05/2017 15:43
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