The PMLAR characteristics are:
Allows or disallows access to the Performance Monitors registers through a memory-mapped interface.
This register is part of the Performance Monitors registers functional group.
This register is accessible as follows:
Default |
---|
WO |
PMLAR is in the Debug power domain.
If OPTIONAL memory-mapped access to the external debug interface is supported then an OPTIONAL Software Lock can be implemented as part of CoreSight compliance.
PMLAR ignores writes if the Software Lock is not implemented and ignores writes for other accesses to the external debug interface.
The Software Lock provides a lock to prevent memory-mapped writes to the Performance Monitors registers. Use of this lock mechanism reduces the risk of accidental damage to the contents of the Performance Monitors registers. It does not, and cannot, prevent all accidental or malicious damage.
Software uses PMLAR to set or clear the lock, and PMLSR to check the current status of the lock.
PMLAR is a 32-bit register.
The PMLAR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
KEY |
Lock Access control. Writing the key value 0xC5ACCE55 to this field unlocks the lock, enabling write accesses to this component's registers through a memory-mapped interface.
Writing any other value to this register locks the lock, disabling write accesses to this component's registers through a memory mapped interface.
PMLAR can be accessed through a memory-mapped access to the external debug interface:
Component | Offset |
---|---|
PMU | 0xFB0 |
02/05/2017 15:43
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