The ID_AA64ISAR0_EL1 characteristics are:
Provides information about the instructions implemented in AArch64 state.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.
This register is part of the Identification registers functional group.
There are no configuration notes.
ID_AA64ISAR0_EL1 is a 64-bit register.
The ID_AA64ISAR0_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
RDM | 0 | 0 | 0 | 0 | Atomic | CRC32 | SHA2 | SHA1 | AES | 0 | 0 | 0 | 0 | ||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
SQRDMLAH and SQRDMLSH instructions implemented in AArch64 state. Defined values are:
RDM | Meaning |
---|---|
0000 |
No SQRDMLAH and SQRDMLSH instructions implemented. |
0001 |
SQRDMLAH and SQRDMLSH instructions implemented. |
All other values are reserved.
In ARMv8.0 the only permitted value is 0000.
From ARMv8.1 the only permitted value is 0001. This feature is identified by the name ARMv8.1-RDMA.
Reserved, RES0.
Reserved, RES0.
Atomic instructions implemented in AArch64 state. Defined values are:
Atomic | Meaning |
---|---|
0000 |
No Atomic instructions implemented. |
0010 |
LDADD, LDCLR, LDEOR, LDSET, LDSMAX, LDSMIN, LDUMAX, LDUMIN, CAS, CASP, and SWP instructions implemented. |
All other values are reserved.
In ARMv8.0 the only permitted value is 0000.
From ARMv8.1 the only permitted value is 0010. This feature is identified by the name ARMv8.1-LSE.
Reserved, RES0.
CRC32 instructions implemented in AArch64 state. Defined values are:
CRC32 | Meaning |
---|---|
0000 |
No CRC32 instructions implemented. |
0001 |
CRC32B, CRC32H, CRC32W, CRC32X, CRC32CB, CRC32CH, CRC32CW, and CRC32CX instructions implemented. |
All other values are reserved.
In ARMv8.0 the permitted values are 0000 and 0001.
From ARMv8.1 the only permitted value is 0001.
SHA2 instructions implemented in AArch64 state. Defined values are:
SHA2 | Meaning |
---|---|
0000 |
No SHA2 instructions implemented. |
0001 |
SHA256H, SHA256H2, SHA256SU0, and SHA256SU1 instructions implemented. |
All other values are reserved.
SHA1 instructions implemented in AArch64 state. Defined values are:
SHA1 | Meaning |
---|---|
0000 |
No SHA1 instructions implemented. |
0001 |
SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0, and SHA1SU1 instructions implemented. |
All other values are reserved.
AES instructions implemented in AArch64 state. Defined values are:
AES | Meaning |
---|---|
0000 |
No AES instructions implemented. |
0001 |
AESE, AESD, AESMC, and AESIMC instructions implemented. |
0010 |
As for 0001, plus PMULL/PMULL2 instructions operating on 64-bit data quantities. |
All other values are reserved.
Reserved, RES0.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
ID_AA64ISAR0_EL1 | 11 | 000 | 0000 | 0110 | 000 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
02/05/2017 15:43
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