GITS_BASER<n>, ITS Translation Table Descriptors, n = 0 - 7

The GITS_BASER<n> characteristics are:

Purpose

Specifies the base address and size of the ITS translation tables.

This register is part of the GIC ITS registers functional group.

Usage constraints

This register is accessible as follows:

Security disabledSecureNon-secure
RWRWRW

Configuration

Some or all RW fields of this register have defined reset values.

A copy of this register is provided for each ITS translation table.

Bits [63:32] and bits [31:0] are accessible independently.

A maximum of 8 GITS_BASER<n> registers can be provided. Unimplemented registers are RES0.

When GITS_CTLR.Enabled == 1 or GITS_CTLR.Quiescent == 0, writing this register is UNPREDICTABLE.

Attributes

GITS_BASER<n> is a 64-bit register.

Field descriptions

The GITS_BASER<n> bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
ValidIndirectInnerCacheTypeOuterCacheEntry_SizePhysical_Address
Physical_AddressShareabilityPage_SizeSize
313029282726252423222120191817161514131211109876543210

Valid, bit [63]

Indicates whether software has allocated memory for the translation table:

ValidMeaning
0

No memory is allocated for the translation table. The ITS discards any writes to the interrupt translation page when either:

  • GITS_BASER<n>.Type specifies any valid table entry type other than interrupt collections, that is, any value other than 100.
  • GITS_BASER<n>.Type specifies an interrupt collection and GITS_TYPER.HCC == 0.
1

Memory is allocated to the translation table.

When this register has an architecturally-defined reset value, this field resets to 0.

Indirect, bit [62]

This field indicates whether an implemented register specifies a single, flat table or a two-level table where the first level contains a list of descriptors.

Note

This field is RAZ/WI for implementations that only support flat tables.

IndirectMeaning
0

Single Level. The Size field indicates the number of pages used by the ITS to store data associated with each table entry.

1

Two Level. The Size field indicates the number of pages which contain an array of 64-bit descriptors to pages that are used to store the data associated with each table entry. A little endian memory order model is used.

See The ITS tables for more information.

This field is RAZ/WI for GIC implementations that only support flat tables.

When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to a value that is architecturally UNKNOWN.

InnerCache, bits [61:59]

Indicates the Inner Cacheability attributes of accesses to the table. The possible values of this field are:

InnerCacheMeaning
000

Device-nGnRnE.

001

Normal Inner Non-cacheable.

010

Normal Inner Cacheable Read-allocate, Write-through.

011

Normal Inner Cacheable Read-allocate, Write-back.

100

Normal Inner Cacheable Write-allocate, Write-through.

101

Normal Inner Cacheable Write-allocate, Write-back.

110

Normal Inner Cacheable Read-allocate, Write-allocate, Write-through.

111

Normal Inner Cacheable Read-allocate, Write-allocate, Write-back.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Type, bits [58:56]

Read only. Specifies the type of entity that requires entries in the corresponding translation table. The possible values of the field are:

TypeMeaning
000

Unimplemented. This register does not correspond to a translation table.

001

Devices. This register corresponds to a translation table that scales with the width of the DeviceID. Only a single GITS_BASER<n> register reports this type.

010

vPEs. GICv4 only. This register corresponds to a translation table that scales with the number of vPEs in the system. The translation table requires (ENTRY_SIZE * N) bytes of memory, where N is the number of vPEs in the system. Only a single GITS_BASER<n> register reports this type.

100

Interrupt collections. This register corresponds to a translation table that scales with the number of interrupt collections in the system. The translation table requires (ENTRY_SIZE * N) bytes of memory, where N is the number of interrupt collections. Not more than one GITS_BASER<n> register will report this type.

Other values are reserved.

Note

The minimum number of entries that an ITS must support is N+1, where N is the number of physical PEs in the system.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

OuterCache, bits [55:53]

Indicates the Outer Cacheability attributes of accesses to the table. The possible values of this field are:

OuterCacheMeaning
000

Memory type defined in InnerCache field. For Normal memory, Outer Cacheability is the same as Inner Cacheability.

001

Normal Outer Non-cacheable.

010

Normal Outer Cacheable Read-allocate, Write-through.

011

Normal Outer Cacheable Read-allocate, Write-back.

100

Normal Outer Cacheable Write-allocate, Write-through.

101

Normal Outer Cacheable Write-allocate, Write-back.

110

Normal Outer Cacheable Read-allocate, Write-allocate, Write-through.

111

Normal Outer Cacheable Read-allocate, Write-allocate, Write-back.

It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.

When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to a value that is architecturally UNKNOWN.

Entry_Size, bits [52:48]

Read-only. Specifies the number of bytes per translation table entry, minus one.

Physical_Address, bits [47:12]

Physical Address. When Page_Size is 4KB or 16KB:

When Page_Size is 64KB:

In implementations that support fewer than 52 bits of physical address, any unimplemented upper bits might be RAZ/WI.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Shareability, bits [11:10]

Indicates the Shareability attributes of accesses to the table. The possible values of this field are:

ShareabilityMeaning
00

Non-shareable.

01

Inner Shareable.

10

Outer Shareable.

11

Reserved. Treated as 00.

It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.

When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to a value that is architecturally UNKNOWN.

Page_Size, bits [9:8]

The size of page that the translation table uses:

Page_SizeMeaning
00

4KB.

01

16KB.

10

64KB.

11

Reserved. Treated as 10.

Note

If the GIC implementation supports only a single, fixed page size, this field might be RO.

When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to a value that is architecturally UNKNOWN.

Size, bits [7:0]

The number of pages of physical memory allocated to the table, minus one. GITS_BASER<n>.Page_Size specifies the size of each page.

If GITS_BASER<n>.Type == 0, this field is RAZ/WI.

When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to a value that is architecturally UNKNOWN.

Accessing the GITS_BASER<n>

GITS_BASER<n> can be accessed through its memory-mapped interface:

ComponentOffset
GIC ITS control0x0100 + 8n



02/05/2017 15:43

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