SPSR_EL1, Saved Program Status Register (EL1)

The SPSR_EL1 characteristics are:

Purpose

Holds the saved process state when an exception is taken to EL1.

This register is part of the Special-purpose registers functional group.

Configuration

AArch64 System register SPSR_EL1 is architecturally mapped to AArch32 System register SPSR_svc.

Attributes

SPSR_EL1 is a 32-bit register.

Field descriptions

The SPSR_EL1 bit assignments are:

When exception taken from AArch32:

313029282726252423222120191817161514131211109876543210
NZCVQIT[1:0]J0PANSSILGEIT[7:2]EAIFTM[4]M[3:0]

An exception return from EL1 using AArch64 makes SPSR_EL1 become UNKNOWN.

N, bit [31]

Set to the value of CPSR.N on taking an exception to Supervisor mode, and copied to CPSR.N on executing an exception return operation in Supervisor mode.

Z, bit [30]

Set to the value of CPSR.Z on taking an exception to Supervisor mode, and copied to CPSR.Z on executing an exception return operation in Supervisor mode.

C, bit [29]

Set to the value of CPSR.C on taking an exception to Supervisor mode, and copied to CPSR.C on executing an exception return operation in Supervisor mode.

V, bit [28]

Set to the value of CPSR.V on taking an exception to Supervisor mode, and copied to CPSR.V on executing an exception return operation in Supervisor mode.

Q, bit [27]

Cumulative saturation bit. Set to 1 to indicate that overflow or saturation occurred in some instructions.

IT[1:0], bits [26:25]

IT block state bits for the T32 IT (If-Then) instruction. See IT[7:2] for explanation of this field.

J, bit [24]

RES0.

In previous versions of the architecture, the {J, T} bits determined the AArch32 Instruction set state. ARMv8 does not support either Jazelle state or T32EE state, and the T bit determines the Instruction set state.

Bit [23]

Reserved, RES0.

PAN, bit [22]
In ARMv8.2 and ARMv8.1:

When ARMv8.1-PAN is implemented, set to the value of CPSR.PAN on taking an exception to Supervisor mode, and copied to CPSR.PAN on executing an exception return operation in Supervisor mode.

When ARMv8.1-PAN is not implemented, this bit is RES0.


In ARMv8.0:

Reserved, RES0.

SS, bit [21]

Software step. Shows the value of PSTATE.SS immediately before the exception was taken.

IL, bit [20]

Illegal Execution state bit. Shows the value of PSTATE.IL immediately before the exception was taken.

GE, bits [19:16]

Greater than or Equal flags, for parallel addition and subtraction.

IT[7:2], bits [15:10]

IT block state bits for the T32 IT (If-Then) instruction. This field must be interpreted in two parts.

The IT field is 0b00000000 when no IT block is active.

E, bit [9]

Endianness state bit. Controls the load and store endianness for data accesses:

EMeaning
0

Little-endian operation

1

Big-endian operation.

Instruction fetches ignore this bit.

When the reset value of the SCTLR.EE bit is defined by a configuration input signal, that value also applies to the CPSR.E bit on reset, and therefore applies to software execution from reset.

If an implementation does not provide Big-endian support, this bit is RES0. If it does not provide Little-endian support, this bit is RES1.

If an implementation provides Big-endian support but only at EL0, this bit is RES0 for an exception return to any Exception level other than EL0.

Likewise, if it provides Little-endian support only at EL0, this bit is RES1 for an exception return to any Exception level other than EL0.

A, bit [8]

SError interrupt mask bit. The possible values of this bit are:

AMeaning
0

Exception not masked.

1

Exception masked.

I, bit [7]

IRQ mask bit. The possible values of this bit are:

IMeaning
0

Exception not masked.

1

Exception masked.

F, bit [6]

FIQ mask bit. The possible values of this bit are:

FMeaning
0

Exception not masked.

1

Exception masked.

T, bit [5]

T32 Instruction set state bit. Determines the AArch32 instruction set state that the exception was taken from. Possible values of this bit are:

TMeaning
0

Taken from A32 state.

1

Taken from T32 state.

M[4], bit [4]

Execution state that the exception was taken from. Possible values of this bit are:

M[4]Meaning
1

Exception taken from AArch32.

M[3:0], bits [3:0]

AArch32 mode that an exception was taken from. The possible values are:

M[3:0] Mode
0b0000 User
0b0001 FIQ
0b0010 IRQ
0b0011 Supervisor
0b0111 Abort
0b1011 Undefined
0b1111 System

Other values are reserved. The effect of programming this field to a Reserved value is that behavior is CONSTRAINED UNPREDICTABLE, as described in 'Reserved values in AArch64 System registers and translation table entries' in the ARM ARM, section K1.2.2.

When exception taken from AArch64:

313029282726252423222120191817161514131211109876543210
NZCV0000UAOPANSSIL0000000000DAIF0M[4]M[3:0]

An exception return from EL1 using AArch64 makes SPSR_EL1 become UNKNOWN.

N, bit [31]

Set to the value of the N condition flag on taking an exception to EL1, and copied to the N condition flag on executing an exception return operation in EL1.

Z, bit [30]

Set to the value of the Z condition flag on taking an exception to EL1, and copied to the Z condition flag on executing an exception return operation in EL1.

C, bit [29]

Set to the value of the C condition flag on taking an exception to EL1, and copied to the C condition flag on executing an exception return operation in EL1.

V, bit [28]

Set to the value of the V condition flag on taking an exception to EL1, and copied to the V condition flag on executing an exception return operation in EL1.

Bits [27:24]

Reserved, RES0.

UAO, bit [23]
In ARMv8.2:

When ARMv8.2-UAO is implemented, set to the value of PSTATE.UAO on taking an exception to EL1, and copied to PSTATE.UAO on executing an exception return operation in EL1.

When ARMv8.2-UAO is not implemented, this bit is RES0.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

PAN, bit [22]
In ARMv8.2 and ARMv8.1:

When ARMv8.1-PAN is implemented, set to the value of PSTATE.PAN on taking an exception to EL1, and copied to PSTATE.PAN on executing an exception return operation in EL1.

When ARMv8.1-PAN is not implemented, this bit is RES0.


In ARMv8.0:

Reserved, RES0.

SS, bit [21]

Software step. Shows the value of PSTATE.SS immediately before the exception was taken.

IL, bit [20]

Illegal Execution state bit. Shows the value of PSTATE.IL immediately before the exception was taken.

Bits [19:10]

Reserved, RES0.

D, bit [9]

Process state D mask. The possible values of this bit are:

DMeaning
0

Watchpoint, Breakpoint, and Software Step exceptions targeted at the current Exception level are not masked.

1

Watchpoint, Breakpoint, and Software Step exceptions targeted at the current Exception level are masked.

When the target Exception level of the debug exception is higher than the current Exception level, the exception is not masked by this bit.

A, bit [8]

SError interrupt mask bit. The possible values of this bit are:

AMeaning
0

Exception not masked.

1

Exception masked.

I, bit [7]

IRQ mask bit. The possible values of this bit are:

IMeaning
0

Exception not masked.

1

Exception masked.

F, bit [6]

FIQ mask bit. The possible values of this bit are:

FMeaning
0

Exception not masked.

1

Exception masked.

Bit [5]

Reserved, RES0.

M[4], bit [4]

Execution state that the exception was taken from. Possible values of this bit are:

M[4]Meaning
0

Exception taken from AArch64.

M[3:0], bits [3:0]

AArch64 state (Exception level and selected SP) that an exception was taken from. The possible values are:

M[3:0] State
0b0000 EL0t
0b0100 EL1t
0b0101 EL1h

Other values are reserved, and returning to an Exception level that is using AArch64 with a reserved value in this field is treated as an illegal exception return.

The bits in this field are interpreted as follows:

Accessing the SPSR_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
SPSR_EL11100001000000000
SPSR_EL121110101000000000

Accessibility

The register is accessible as follows:

<systemreg> Control Accessibility
E2HTGENSEL0EL1EL2EL3
SPSR_EL1xx0 - RW n/a RW
SPSR_EL1001 - RWRWRW
SPSR_EL1011 - n/a RWRW
SPSR_EL1101 - RW SPSR_EL2 RW
SPSR_EL1111 - n/a SPSR_EL2 RW
SPSR_EL12xx0 - - n/a -
SPSR_EL12001 - - - -
SPSR_EL12011 - n/a - -
SPSR_EL12101 - - RWRW
SPSR_EL12111 - n/a RWRW

When HCR_EL2.E2H is 1, without explicit synchronization, access from EL3 using the mnemonic SPSR_EL1 or SPSR_EL12 are not guaranteed to be ordered with respect to accesses using the other mnemonic.




02/05/2017 15:43

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