The ICH_ELRSR_EL2 characteristics are:
These registers can be used to locate a usable List register when the hypervisor is delivering an interrupt to a VM.
This register is part of:
AArch64 System register ICH_ELRSR_EL2 is architecturally mapped to AArch32 System register ICH_ELRSR.
If EL2 is not implemented, this register is RES0 from EL3.
ICH_ELRSR_EL2 is a 32-bit register.
The ICH_ELRSR_EL2 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Status<n>, bit [n], for n = 0 to 15 |
Reserved, RES0.
Status bit for List register <n>, ICH_LR<n>_EL2:
Status<n> | Meaning |
---|---|
0 |
List register ICH_LR<n>_EL2, if implemented, contains a valid interrupt. Using this List register can result in overwriting a valid interrupt. |
1 |
List register ICH_LR<n>_EL2 does not contain a valid interrupt. The List register is empty and can be used without overwriting a valid interrupt or losing an EOI maintenance interrupt. |
For any List register <n>, the corresponding status bit is set to 1 if ICH_LR<n>_EL2.State is 0b00 and either ICH_LR<n>_EL2.HW is 1 or ICH_LR<n>_EL2.EOI (bit [41]) is 0.
Otherwise the status bit takes the value 0.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op1 | CRn | CRm | op2 |
---|---|---|---|---|
ICH_ELRSR_EL2 | 100 | 1100 | 1011 | 101 |
The register is accessible as follows:
Control | Accessibility | ||||
---|---|---|---|---|---|
TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | 0 | - | - | n/a | RO |
0 | 1 | - | - | RO | RO |
1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_SRE_EL2.SRE==0, read accesses to this register from EL2 are trapped to EL2.
If ICC_SRE_EL3.SRE==0, read accesses to this register from EL3 are trapped to EL3.
02/05/2017 15:43
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