ICV_RPR, Interrupt Controller Virtual Running Priority Register

The ICV_RPR characteristics are:

Purpose

Indicates the Running priority of the virtual CPU interface.

This register is part of:

Configuration

AArch32 System register ICV_RPR performs the same function as AArch64 System register ICV_RPR_EL1.

Attributes

ICV_RPR is a 32-bit register.

Field descriptions

The ICV_RPR bit assignments are:

313029282726252423222120191817161514131211109876543210
000000000000000000000000Priority

Bits [31:8]

Reserved, RES0.

Priority, bits [7:0]

The current running priority on the virtual CPU interface. This is the group priority of the current active virtual interrupt.

The priority returned is the group priority as if the BPR for the current Exception level and Security state was set to the minimum value of BPR for the number of implemented priority bits.

Note

If 8 bits of priority are implemented the group priority is bits[7:1] of the priority.

Accessing the ICV_RPR

This register can be read using MRC with the following syntax:

MRC <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 0, <Rt>, c12, c11, 3000011110011111011

When HCR.{FMO, IMO} == {0, 0}, execution of this encoding at Non-secure EL1 results in an access to ICC_RPR.

Accessibility

The register is accessible as follows:

Control Accessibility
FMOIMOTGENSEL0EL1EL2EL3
xxx0 - ICC_RPR n/a ICC_RPR
xx11 - n/a ICC_RPR ICC_RPR
x101 - RO ICC_RPR ICC_RPR
1x01 - RO ICC_RPR ICC_RPR
0001 - ICC_RPR ICC_RPR ICC_RPR

This table applies to all instructions that can access this register.

ICV_RPR is only accessible at Non-secure EL1 when HCR.{FMO, IMO} != {0, 0}.

Note

When HCR.{FMO, IMO} == {0, 0}, at Non-secure EL1, the instruction encoding used to access ICV_RPR results in an access to ICC_RPR.

If there are no active interrupts on the virtual CPU interface, or all active interrupts have undergone a priority drop, the value returned is the Idle priority.

Software cannot determine the number of implemented priority bits from a read of this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :

When SCR_EL3.NS==1 :




02/05/2017 15:43

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