The DBGDIDR characteristics are:
Specifies which version of the Debug architecture is implemented, and some features of the debug implementation.
This register is part of the Debug registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
If EL1 cannot use AArch32 then the implementation of this register is OPTIONAL and deprecated.
DBGDIDR is a 32-bit register.
The DBGDIDR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WRPs | BRPs | CTX_CMPs | Version | 1 | nSUHD_imp | 0 | SE_imp | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
The number of watchpoints implemented, minus 1.
Permitted values of this field are from 0b0001 for 2 implemented watchpoints, to 0b1111 for 16 implemented watchpoints.
The value of 0b0000 is reserved.
If AArch64 is implemented, this field has the same value as ID_AA64DFR0_EL1.WRPs.
The number of breakpoints implemented, minus 1.
Permitted values of this field are from 0b0001 for 2 implemented breakpoint, to 0b1111 for 16 implemented breakpoints.
The value of 0b0000 is reserved.
If AArch64 is implemented, this field has the same value as ID_AA64DFR0_EL1.BRPs.
The number of breakpoints that can be used for Context matching, minus 1.
Permitted values of this field are from 0b0000 for 1 Context matching breakpoint, to 0b1111 for 16 Context matching breakpoints.
The Context matching breakpoints must be the highest addressed breakpoints. For example, if six breakpoints are implemented and two are Context matching breakpoints, they must be breakpoints 4 and 5.
If AArch64 is implemented, this field has the same value as ID_AA64DFR0_EL1.CTX_CMPs.
The Debug architecture version. Defined values are:
Version | Meaning |
---|---|
0001 |
ARMv6, v6 Debug architecture. |
0010 |
ARMv6, v6.1 Debug architecture. |
0011 |
ARMv7, v7 Debug architecture, with baseline CP14 registers implemented. |
0100 |
ARMv7, v7 Debug architecture, with all CP14 registers implemented. |
0101 |
ARMv7, v7.1 Debug architecture. |
0110 |
ARMv8, v8 Debug architecture. |
0111 |
ARMv8.1, v8 Debug architecture, with Virtualization Host Extensions. |
1000 |
ARMv8.2, v8.2 Debug architecture. |
All other values are reserved.
Reserved, RES1.
In ARMv7-A, was Secure User Halting Debug not implemented.
The value of this bit must match the value of the SE_imp bit.
Reserved, RES0.
EL3 implemented. The meanings of the values of this bit are:
SE_imp | Meaning |
---|---|
0 |
EL3 not implemented. |
1 |
EL3 implemented. |
The value of this bit must match the value of the nSUHD_imp bit.
Reserved, RES0.
This register can be read using MRC with the following syntax:
MRC <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p14, 0, <Rt>, c0, c0, 0 | 000 | 000 | 0000 | 1110 | 0000 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | RO | RO | n/a | RO |
x | 0 | 1 | RO | RO | RO | RO |
x | 1 | 1 | RO | n/a | RO | RO |
This table applies to all instructions that can access this register.
ARM deprecates any access to this register from EL0.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If DBGDSCRext.UDCCdis==1, read accesses to this register from EL0 are trapped to Undefined mode.
If MDSCR_EL1.TDCC==1, read accesses to this register from EL0 are trapped to EL1.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TDA==1, Non-secure read accesses to this register from EL0 and EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HDCR.TDA==1, Non-secure read accesses to this register from EL0 and EL1 are trapped to Hyp mode.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TDA==1, read accesses to this register from EL0, EL1, and EL2 are trapped to EL3.
02/05/2017 15:43
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