MDCR_EL2, Monitor Debug Configuration Register (EL2)

The MDCR_EL2 characteristics are:

Purpose

Provides EL2 configuration options for self-hosted debug and the Performance Monitors Extension.

This register is part of:

Configuration

AArch64 System register MDCR_EL2 is architecturally mapped to AArch32 System register HDCR.

If EL2 is not implemented, this register is RES0 from EL3.

This register is in the Warm reset domain. Some or all RW fields of this register have defined reset values. On a Warm or Cold reset these apply only if the PE resets into an Exception level that is using AArch64. Otherwise, on a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.

Attributes

MDCR_EL2 is a 32-bit register.

Field descriptions

The MDCR_EL2 bit assignments are:

313029282726252423222120191817161514131211109876543210
00000000000000HPMD00TPMSE2PBTDRATDOSATDATDEHPMETPMTPMCRHPMN

Bits [31:18]

Reserved, RES0.

HPMD, bit [17]
In ARMv8.2 and ARMv8.1:

Guest Performance Monitors Disable. This control prohibits event counting at EL2. Permitted values are:

HPMDMeaning
0

Event counting allowed at EL2.

1

Event counting prohibited at EL2.

In an ARMv8.1 implementation, event counting is prohibited unless enabled by the IMPLEMENTATION DEFINED authentication interface ExternalSecureNoninvasiveDebugEnabled().

This control applies only to:

The other event counters are unaffected, and when PMCR_EL0.DP is set to 0, PMCCNTR_EL0 is unaffected.

When this register has an architecturally-defined reset value, this field resets to 0.


In ARMv8.0:

Reserved, RES0.

Bits [16:15]

Reserved, RES0.

TPMS, bit [14]
In ARMv8.2:

Trap Performance Monitor Sampling. When the Statistical Profiling Extension is implemented this field controls access to Statistical Profiling control registers from Non-secure EL1 and EL0. The possible values of this bit are:

TPMSMeaning
0

Do not trap Statistical Profiling controls to EL2.

1

Accesses to Statistical Profiling controls at Non-secure EL1 generate a Trap exception to EL2.

If EL2 is not implemented, the PE behaves as if TPMS == 0, other than for a direct read of the register.

When the Statistical Profiling Extension is not implemented this field is reserved, RES0.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

E2PB, bits [13:12]
In ARMv8.2:

EL2 Profiling Buffer. When the Statistical Profiling Extension is implemented this field controls the owning translation regime and access to Profiling Buffer control registers from Non-secure EL1. The possible values of this field are:

E2PBMeaning
00

Profiling Buffer uses the EL2 stage 1 translation regime. Accesses to Profiling Buffer controls at Non-secure EL1 generate a Trap exception to EL2.

10

Profiling Buffer uses the EL1&0 stage 1 translation regime. Accesses to Profiling Buffer controls at Non-secure EL1 generate a Trap exception to EL2.

11

Profiling Buffer uses the EL1&0 stage 1 translation regime. Accesses to Profiling Buffer controls at Non-secure EL1 are not trapped to EL2.

All other values are reserved. If this field is programmed with a reserved value, the PE behaves as if this field has a defined value, other than for a direct read of the register. Software must not rely on the behavior of reserved values, as they might change in a future version of the architecture.

If EL2 is not implemented, the PE behaves as if E2PB == 0b11, other than for a direct read of the register.

When the Statistical Profiling Extension is not implemented this field is reserved, RES0.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

TDRA, bit [11]

Trap Debug ROM Address register access. Traps Non-secure System register accesses to the Debug ROM registers to EL2. This trap is from:

TDRAMeaning
0

This control does not cause any instructions to be trapped.

1

Non-secure EL0 and EL1 System register accesses to the Debug ROM registers are trapped to EL2, unless it is trapped by DBGDSCRext.UDCCdis or MDSCR_EL1.TDCC.

The registers for which accesses are trapped are as follows:

AArch64: MDRAR_EL1.

AArch32: DBGDRAR, DBGDSAR.

If MDCR_EL2.TDE == 1 or HCR_EL2.TGE == 1, behavior is as if this bit is 1 other than for the purpose of a direct read.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

TDOSA, bit [10]

Trap debug OS-related register access. Traps Non-secure EL1 System register accesses to the powerdown debug registers to EL2, from both Execution states:

TDOSAMeaning
0

This control does not cause any instructions to be trapped.

1

Non-secure EL1 System register accesses to the powerdown debug registers are trapped to EL2.

The registers for which accesses are trapped are as follows:

AArch64: OSLAR_EL1, OSLSR_EL1, OSDLR_EL1, and the DBGPRCR_EL1.

AArch32: DBGOSLSR, DBGOSLAR, DBGOSDLR, and the DBGPRCR.

AArch64 and AArch32: Any IMPLEMENTATION DEFINED register with similar functionality that the implementation specifies as trapped by this bit.

Note

These registers are not accessible at EL0.

If MDCR_EL2.TDE == 1 or HCR_EL2.TGE == 1, behavior is as if this bit is 1 other than for the purpose of a direct read.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

TDA, bit [9]

Trap Debug Access. Traps Non-secure EL0 and EL1 System register accesses to those debug System registers that are not trapped by either of the following:

TDAMeaning
0

This control does not cause any instructions to be trapped.

1

Non-secure EL0 or EL1 System register accesses to the debug registers, other than the registers trapped by MDCR_EL2.TDRA and MDCR_EL2.TDOSA, are trapped to EL2, from both Execution states, unless it is trapped by DBGDSCRext.UDCCdis or MDSCR_EL1.TDCC.

Traps of AArch32 accesses to DBGDTRRXint and DBGDTRTXint are ignored in Debug state.

Traps of AArch64 accesses to DBGDTR_EL0, DBGDTRRX_EL0, and DBGDTRTX_EL0 are ignored in Debug state.

If MDCR_EL2.TDE == 1 or HCR_EL2.TGE == 1, behavior is as if this bit is 1 other than for the purpose of a direct read.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

TDE, bit [8]

Trap Debug exceptions. The possible values of this field are:

TDEMeaning
0

This control has no effect on the routing of debug exceptions, and has no effect on Non-secure accesses to debug registers.

1

In Non-secure state:

  • Debug exceptions generated at EL1 or EL0 are routed to EL2.
  • The MDCR_EL2.{TDRA, TDOSA, TDA} fields are treated as being 1 for all purposes other than returning the result of a direct read of the register.

When HCR_EL2.TGE == 1, the PE behaves as if the value of this field is 1 for all purposes other than returning the value of a direct read of the register.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

HPME, bit [7]

Hypervisor Performance Monitors Counters Enable. The possible values of this bit are:

HPMEMeaning
0

EL2 Performance Monitors counters disabled.

1

EL2 Performance Monitors counters enabled.

When the value of this bit is 1, the Performance Monitors counters that are reserved for use from EL2 or Secure state are enabled. For more information see the description of the HPMN field.

If the Performance Monitors Extension is not implemented, this field is RES0.

When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to a value that is architecturally UNKNOWN.

TPM, bit [6]

Trap Performance Monitors accesses. Traps Non-secure EL0 and EL1 accesses to all Performance Monitors registers to EL2, from both Execution states:

TPMMeaning
0

This control does not cause any instructions to be trapped.

1

Non-secure EL0 and EL1 accesses to all Performance Monitors registers are trapped to EL2.

Note

EL2 does not provide traps on Performance Monitor register accesses through the optional memory-mapped external debug interface.

If the Performance Monitors Extension is not implemented, this field is RES0.

When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to a value that is architecturally UNKNOWN.

TPMCR, bit [5]

Trap PMCR_EL0 or PMCR accesses. Traps Non-secure EL0 and EL1 accesses to the PMCR_EL0 or PMCR to EL2.

TPMCRMeaning
0

This control does not cause any instructions to be trapped.

1

Non-secure EL0 and EL1 accesses to the PMCR_EL0 or PMCR are trapped to EL2, unless it is trapped by PMUSERENR.EN or PMUSERENR_EL0.EN.

Note

EL2 does not provide traps on Performance Monitor register accesses through the optional memory-mapped external debug interface.

If the Performance Monitors Extension is not implemented, this field is RES0.

When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to a value that is architecturally UNKNOWN.

HPMN, bits [4:0]

Defines the number of Performance Monitors counters that are accessible from Non-secure EL0 and EL1 modes.

If the Performance Monitors Extension is not implemented, this field is RES0.

In Non-secure state, HPMN divides the Performance Monitors counters as follows. For counter n in Non-secure state:

If this field is set to 0, or to a value larger than PMCR_EL0.N, then the following CONSTRAINED UNPREDICTABLE behavior applies:

When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to the value of PMCR_EL0.N.

Accessing the MDCR_EL2

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
MDCR_EL21110000010001001

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - - n/a RW
x01 - - RWRW
x11 - n/a RWRW

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL3 is implemented and is using AArch64 :




02/05/2017 15:43

Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.