The DBGDTRTX_EL0 characteristics are:
Transfers data from the PE to an external debugger. For example, it is used by a debug target to transfer data to the debugger. It is a component of the Debug Communication Channel.
This register is part of the Debug registers functional group.
This register is accessible as follows:
Off | DLK | OSLK | SLK | Default |
---|---|---|---|---|
Error | Error | Error | RO | RW |
If EDSCR.ITE == 0 when the PE exits Debug state on receiving a Restart request trigger event, the behavior of any operation issued by a DTR access in memory access mode that has not completed execution is CONSTRAINED UNPREDICTABLE, and must do one of the following:
External register DBGDTRTX_EL0 is architecturally mapped to AArch64 System register DBGDTRTX_EL0.
External register DBGDTRTX_EL0 is architecturally mapped to AArch32 System register DBGDTRTXint.
DBGDTRTX_EL0 is in the Core power domain. RW fields in this register reset to architecturally UNKNOWN values. These apply only on a Cold reset. The register is not affected by a Warm reset and is not affected by an External debug reset.
DBGDTRTX_EL0 is a 32-bit register.
The DBGDTRTX_EL0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Return DTRTX |
Return DTRTX.
If TXfull is set to 1, then reads of this register return the value in DTRTX and clear TXfull to 0.
Writes of this register update the value in DTRTX and do not change TXfull.
For the full behavior of the Debug Communications Channel, see 'The Debug Communication Channel and Instruction Transfer Register' in the ARM ARM, chapter H4.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
DBGDTRTX_EL0 can be accessed through the external debug interface:
Component | Offset |
---|---|
Debug | 0x08C |
02/05/2017 15:43
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