CNTPCT, Counter-timer Physical Count

The CNTPCT characteristics are:

Purpose

Holds the 64-bit physical count value.

This register is part of the Generic Timer registers functional group.

Usage constraints

This register is accessible as follows:

Default
RO

CNTPCT can be implemented in any implemented CNTBaseN frame, and in the corresponding CNTEL0BaseN frame, as a RO register.

'CNTCTLBase status and control fields for the CNTBaseN and CNTEL0BaseN frames' in Chapter I1 of the ARMv8 ARM describes the status fields that identify whether a CNTBaseN frame is implemented, and for an implemented frame:

For an implemented CNTBaseN frame:

For an implemented CNTEL0BaseN frame:

If the implementation supports 64-bit atomic accesses, then the CNTPCT register must be accessible as an atomic 64-bit value.

Configuration

The power domain of CNTPCT is IMPLEMENTATION DEFINED.

For more information see 'Power and reset domains for the system level implementation of the Generic Timer' in Chapter I1 of the ARMv8 ARM.

Attributes

CNTPCT is a 64-bit register.

Field descriptions

The CNTPCT bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
Physical count value
Physical count value
313029282726252423222120191817161514131211109876543210

Bits [63:0]

Physical count value.

Accessing the CNTPCT

CNTPCT[31:0] can be accessed through its memory-mapped interface:

ComponentFrameOffset
TimerCNTBaseN 0x000
TimerCNTEL0BaseN 0x000

CNTPCT[63:32] can be accessed through its memory-mapped interface:

ComponentFrameOffset
TimerCNTBaseN 0x004
TimerCNTEL0BaseN 0x004



02/05/2017 15:43

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