EDPCSR, External Debug Program Counter Sample Register

The EDPCSR characteristics are:

Purpose

Holds a sampled instruction address value.

This register is part of the Debug registers functional group.

Usage constraints

This register is accessible as follows:

OffDLKOSLKSLKDefault
ErrorErrorErrorRORO

Configuration

EDPCSR is in the Core power domain.

Fields in this register reset to architecturally UNKNOWN values. These apply only on a Cold reset. The register is not affected by a Warm reset and is not affected by an External debug reset.

Implemented only if the OPTIONAL PC Sample-based Profiling Extension is implemented and ARMv8.2-PCSample is not implemented. If ARMv8.2-PCSample is implemented, this register is RES0 and the architecture defines the functionality in PMPCSR.

Attributes

EDPCSR is a pair of 32-bit registers.

If ARMv8.1-VHE is implemented, the format of this register differs depending on the value of EDSCR.SC2.

Field descriptions

The EDPCSR bit assignments are:

When ARMv8.1-VHE is not implemented:

6362616059585756555453525150494847464544434241403938373635343332
PC Sample high word, EDPCSRhi
PC Sample low word
313029282726252423222120191817161514131211109876543210

Bits [63:32]

PC Sample high word, EDPCSRhi. If EDVIDSR.HV == 0 then this field is RAZ, otherwise bits [63:32] of the sampled instruction address value. The translation regime that EDPCSR samples can be determined from EDVIDSR.{NS,E2,E3}.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bits [31:0]

PC Sample low word. EDPCSRlo, bits[31:0] of the sampled instruction address value. The translation regime that EDPCSR samples can be determined from EDVIDSR.{NS,E2,E3}.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

When ARMv8.1-VHE is implemented and EDSCR.SC2 == 0:

6362616059585756555453525150494847464544434241403938373635343332
PC Sample high word, EDPCSRhi
PC Sample low word
313029282726252423222120191817161514131211109876543210

Bits [63:32]

PC Sample high word, EDPCSRhi. If EDVIDSR.HV == 0 then this field is RAZ, otherwise bits [63:32] of the sampled instruction address value. The translation regime that EDPCSR samples can be determined from EDVIDSR.{NS,E2,E3}.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bits [31:0]

PC Sample low word. EDPCSRlo, bits[31:0] of the sampled instruction address value. The translation regime that EDPCSR samples can be determined from EDVIDSR.{NS,E2,E3}.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

When ARMv8.1-VHE is implemented and EDSCR.SC2 == 1:

6362616059585756555453525150494847464544434241403938373635343332
NSEL00000PC Sample high word, EDPCSRhi
PC Sample low word
313029282726252423222120191817161514131211109876543210

NS, bit [63]

Non-secure state sample. Indicates the Security state that is associated with the most recent EDPCSR sample or, when it is read as a single atomic 64-bit read, the current EDPCSR sample. The translation regime that EDPCSR samples can be determined from EDPCSR.{NS,EL}.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

EL, bits [62:61]

Exception level status sample. Indicates the Exception level that is associated with the most recent EDPCSR sample or, when it is read as a single atomic 64-bit read, the current EDPCSR sample. The translation regime that EDPCSR samples can be determined from EDPCSR.{NS,EL}.

ELMeaning
00

Sample is from EL0.

01

Sample is from EL1.

10

Sample is from EL2.

11

Sample is from EL3.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bits [60:56]

Reserved, RES0.

Bits [55:32]

PC Sample high word, EDPCSRhi. Bits [55:32] of the sampled instruction address value. The translation regime that EDPCSR samples can be determined from EDPCSR.{NS,EL}.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bits [31:0]

PC Sample low word. EDPCSRlo, bits[31:0] of the sampled instruction address value. The translation regime that EDPCSR samples can be determined from EDVIDSR.{NS,E2,E3}.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

When ARMv8.2-PCSample is implemented:

6362616059585756555453525150494847464544434241403938373635343332
00000000000000000000000000000000
00000000000000000000000000000000
313029282726252423222120191817161514131211109876543210

Bits [63:0]

Reserved, RES0.

Accessing the EDPCSR

EDPCSR[31:0] can be accessed through its memory-mapped interface:

ComponentOffset
Debug 0x0A0

EDPCSR[63:32] can be accessed through its memory-mapped interface:

ComponentOffset
Debug 0x0AC



02/05/2017 15:43

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