ELR_EL1, Exception Link Register (EL1)

The ELR_EL1 characteristics are:

Purpose

When taking an exception to EL1, holds the address to return to.

This register is part of the Special-purpose registers functional group.

Configuration

There are no configuration notes.

Attributes

ELR_EL1 is a 64-bit register.

Field descriptions

The ELR_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
Return address
Return address
313029282726252423222120191817161514131211109876543210

Bits [63:0]

Return address.

An exception return from EL1 using AArch64 makes ELR_EL1 become UNKNOWN.

Accessing the ELR_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
ELR_EL11100001000000001
ELR_EL121110101000000001

Accessibility

The register is accessible as follows:

<systemreg> Control Accessibility
E2HTGENSEL0EL1EL2EL3
ELR_EL1xx0 - RW n/a RW
ELR_EL1001 - RWRWRW
ELR_EL1011 - n/a RWRW
ELR_EL1101 - RW ELR_EL2 RW
ELR_EL1111 - n/a ELR_EL2 RW
ELR_EL12xx0 - - n/a -
ELR_EL12001 - - - -
ELR_EL12011 - n/a - -
ELR_EL12101 - - RWRW
ELR_EL12111 - n/a RWRW

When HCR_EL2.E2H is 1, without explicit synchronization, access from EL3 using the mnemonic ELR_EL1 or ELR_EL12 are not guaranteed to be ordered with respect to accesses using the other mnemonic.




02/05/2017 15:43

Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.