CNTTIDR, Counter-timer Timer ID Register

The CNTTIDR characteristics are:

Purpose

Indicates the implemented timers in the memory map, and their features. For each value of N from 0 to 7 it indicates whether:

This register is part of the Generic Timer registers functional group.

Usage constraints

This register is accessible as follows:

Default
RO

In a system that recognizes two Security states this register is accessible by both Secure and Non-secure accesses.

Configuration

The power domain of CNTTIDR is IMPLEMENTATION DEFINED.

For more information see 'Power and reset domains for the system level implementation of the Generic Timer' in Chapter I1 of the ARMv8 ARM.

Attributes

CNTTIDR is a 32-bit register.

Field descriptions

The CNTTIDR bit assignments are:

313029282726252423222120191817161514131211109876543210
Frame7Frame6Frame5Frame4Frame3Frame2Frame1Frame0

Frame<n>, bits [4n+3:4n], for n = 0 to 7

A 4-bit field indicating the features of frame CNTBase<n>.

Bit[3] of the field is RES0.

Bit[2] indicates whether frame CNTBase<n> has a second view, CNTEL0Base<n>. The possible values of this bit are:

Bit[2] Meaning
0 Frame <n> does not have a second view. CNTEL0Base<n> is RES0.
1 Frame <n> has a second view, CNTEL0Base<n>.

If bit[0] is 0, bit[2] is RES0.

Bit[1] indicates whether both:

The possible values of bit[1] are:

Bit[1] Meaning
0 Frame <n> does not have virtual capability. The virtual time and offset registers are RES0.
1 Frame <n> has virtual capability. The virtual time and offset registers are implemented.

If bit[0] is 0, bit[1] is RES0.

Bit[0] indicates whether frame CNTBase<n> is implemented. The possible values of this bit are:

Bit[0] Meaning
0 Frame <n> not implemented. All registers associated with the frame are RES0.
1 Frame <n> is implemented.

Accessing the CNTTIDR

CNTTIDR can be accessed through its memory-mapped interface:

ComponentFrameOffset
TimerCNTCTLBase 0x008



02/05/2017 15:43

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