NMRR, Normal Memory Remap Register

The NMRR characteristics are:

Purpose

Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in the PRRR.

Used in conjunction with the PRRR.

This register is part of the Virtual memory control registers functional group.

Configuration

AArch32 System register NMRR is architecturally mapped to AArch64 System register MAIR_EL1[63:32] when TTBCR.EAE==0.

MAIR1 and NMRR are the same register, with a different view depending on the value of TTBCR.EAE:

When EL3 is using AArch32, write access to NMRR(S) is disabled when the CP15SDISABLE signal is asserted HIGH.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

NMRR is a 32-bit register.

Field descriptions

The NMRR bit assignments are:

When TTBCR.EAE==0:

313029282726252423222120191817161514131211109876543210
OR7OR6OR5OR4OR3OR2OR1OR0IR7IR6IR5IR4IR3IR2IR1IR0

OR<n>, bits [2n+17:2n+16], for n = 0 to 7

Outer Cacheable property mapping for memory attributes n, if the region is mapped as Normal memory by the PRRR.TR<n> entry. n is the value of the TEX[0], C, and B bits concatenated. The possible values of this field are:

OR<n>Meaning
00

Region is Non-cacheable.

01

Region is Write-Back, Write-Allocate.

10

Region is Write-Through, no Write-Allocate.

11

Region is Write-Back, no Write-Allocate.

The meaning of the field with n = 6 is IMPLEMENTATION DEFINED and might differ from the meaning given here. This is because the meaning of the attribute combination {TEX[0] = 1, C = 1, B = 0} is IMPLEMENTATION DEFINED.

IR<n>, bits [2n+1:2n], for n = 0 to 7

Inner Cacheable property mapping for memory attributes n, if the region is mapped as Normal memory by the PRRR.TR<n> entry. n is the value of the TEX[0], C, and B bits concatenated. The possible values of this field are:

IR<n>Meaning
00

Region is Non-cacheable.

01

Region is Write-Back, Write-Allocate.

10

Region is Write-Through, no Write-Allocate.

11

Region is Write-Back, no Write-Allocate.

The meaning of the field with n = 6 is IMPLEMENTATION DEFINED and might differ from the meaning given here. This is because the meaning of the attribute combination {TEX[0] = 1, C = 1, B = 0} is IMPLEMENTATION DEFINED.

Accessing the NMRR

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 0, <Rt>, c10, c2, 1000001101011110010

Accessibility

The register is accessible as follows:

Configuration Control Accessibility Instance
E2HTGENSEL0EL1EL2EL3
EL3 using AArch32xx0 - n/a n/a RWNMRR_s
EL3 not implemented xx0 - RW n/a n/a NMRR
EL3 not implemented x01 - RWRW n/a NMRR
EL3 not implemented x11 - n/a RW n/a NMRR
EL3 using AArch64xx0 - RW n/a n/a NMRR
EL3 using AArch64x01 - RWRW n/a NMRR
EL3 using AArch64x11 - n/a RW n/a NMRR
EL3 using AArch32x01 - RWRWRWNMRR_ns
EL3 using AArch32x11 - n/a RWRWNMRR_ns

This table applies to all instructions that can access this register.

When EL3 is using AArch32, write access to NMRR_s is UNDEFINED when the CP15SDISABLE signal is asserted HIGH.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :




02/05/2017 15:43

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