The PMCR characteristics are:
Provides details of the Performance Monitors implementation, including the number of counters implemented, and configures and controls the counters.
This register is part of the Performance Monitors registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register PMCR is architecturally mapped to AArch64 System register PMCR_EL0.
AArch32 System register PMCR bits [6:0] are architecturally mapped to External register PMCR_EL0[6:0] .
This register is in the Warm reset domain. Some or all RW fields of this register have defined reset values. On a Warm or Cold reset these apply only if the PE resets into an Exception level that is using AArch32. Otherwise, on a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.
PMCR is a 32-bit register.
The PMCR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMP | IDCODE | N | 0 | 0 | 0 | 0 | LC | DP | X | D | C | P | E |
Implementer code. This field is RO with an IMPLEMENTATION DEFINED value.
The implementer codes are allocated by ARM. Values have the same interpretation as bits [31:24] of the MIDR.
Identification code. This field is RO with an IMPLEMENTATION DEFINED value.
Each implementer must maintain a list of identification codes that is specific to the implementer. A specific implementation is identified by the combination of the implementer code and the identification code.
Number of event counters. A RO field that indicates the number counters implemented. A value of 0b00000 in this field indicates that only the Cycle Count Register PMCCNTR is implemented.
The value of this field is the number of event counters implemented. This value is in the range of 0b00000, in which case only the PMCCNTR is implemented, to 0b11111, which indicates that the PMCCNTR and 31 event counters are implemented.
In an implementation that includes EL2, reads of this field from Non-secure EL1 and Non-secure EL0 return the value of HDCR.HPMN if EL2 is using AArch32, or the value of MDCR_EL2.HPMN if EL2 is using AArch64.
Reserved, RES0.
Long cycle counter enable. Determines which PMCCNTR bit generates an overflow recorded by PMOVSR[31].
LC | Meaning |
---|---|
0 |
Cycle counter overflow on increment that changes PMCCNTR[31] from 1 to 0. |
1 |
Cycle counter overflow on increment that changes PMCCNTR[63] from 1 to 0. |
ARM deprecates use of PMCR.LC = 0.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Disable cycle counter when event counting is prohibited. The possible values of this bit are:
DP | Meaning |
---|---|
0 |
PMCCNTR, if enabled, counts when event counting is prohibited. |
1 |
PMCCNTR does not count when event counting is prohibited. |
Counting events is never prohibited in Non-secure state. However, there are some restrictions on counting events in Secure state. For more information about the interaction between the Performance Monitors and EL3, see 'Interaction with EL3' in the ARMv8 ARM, section D5.5.1
When EL3 is not implemented, this field is RES0:
Otherwise this field is RW.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.
Enable export of events in an IMPLEMENTATION DEFINED event stream. The possible values of this bit are:
X | Meaning |
---|---|
0 |
Do not export events. |
1 |
Export events where not prohibited. |
This field enables the exporting of events over an event bus to another device, for example to an OPTIONAL trace macrocell. If the implementation does not include such an event bus then this field is RAZ/WI, otherwise it is an RW field.
In an implementation that includes an event bus, no events are exported when counting is prohibited.
This field does not affect the generation of Performance Monitors overflow interrupt requests or signaling to a cross-trigger interface (CTI) that can be implemented as signals exported from the PE.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.
Clock divider. The possible values of this bit are:
D | Meaning |
---|---|
0 |
When enabled, PMCCNTR counts every clock cycle. |
1 |
When enabled, PMCCNTR counts once every 64 clock cycles. |
This bit is RW.
If PMCR.LC == 1, this bit is ignored and the cycle counter counts every clock cycle.
ARM deprecates use of PMCR.D = 1.
When this register has an architecturally-defined reset value, this field resets to 0.
Cycle counter reset. This bit is WO. The effects of writing to this bit are:
C | Meaning |
---|---|
0 |
No action. |
1 |
Reset PMCCNTR to zero. |
This bit is always RAZ.
Resetting PMCCNTR does not clear the PMCCNTR overflow bit to 0.
Event counter reset. This bit is WO. The effects of writing to this bit are:
P | Meaning |
---|---|
0 |
No action. |
1 |
Reset all event counters accessible in the current EL, not including PMCCNTR, to zero. |
This bit is always RAZ.
In Non-secure EL0 and EL1, if EL2 is implemented, a write of 1 to this bit does not reset event counters that HDCR.HPMN or MDCR_EL2.HPMN reserves for EL2 use.
In EL2 and EL3, a write of 1 to this bit resets all the event counters.
Resetting the event counters does not clear any overflow bits to 0.
Enable. The possible values of this bit are:
E | Meaning |
---|---|
0 |
All counters that are accessible at Non-secure EL1, including PMCCNTR, are disabled. |
1 |
All counters that are accessible at Non-secure EL1 are enabled by PMCNTENSET. |
This bit is RW.
If EL2 is implemented, this bit does not affect the operation of event counters that HDCR.HPMN or MDCR_EL2.HPMN reserves for EL2 use.
When this register has an architecturally-defined reset value, this field resets to 0.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c9, c12, 0 | 000 | 000 | 1001 | 1111 | 1100 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | RW | RW | n/a | RW |
x | 0 | 1 | RW | RW | RW | RW |
x | 1 | 1 | RW | n/a | RW | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If PMUSERENR.EN==0, accesses to this register from EL0 are trapped to Undefined mode.
If PMUSERENR_EL0.EN==0, accesses to this register from EL0 are trapped to EL1.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HSTR_EL2.T9==1, Non-secure accesses to this register from EL0 and EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TPM==1, Non-secure accesses to this register from EL0 and EL1 are trapped to EL2.
If MDCR_EL2.TPMCR==1, Non-secure accesses to this register from EL0 and EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T9==1, Non-secure write accesses to this register from EL0 and EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HDCR.TPM==1, Non-secure accesses to this register from EL0 and EL1 are trapped to Hyp mode.
If HDCR.TPMCR==1, Non-secure accesses to this register from EL0 and EL1 are trapped to Hyp mode.
If HSTR.T9==1, Non-secure accesses to this register from EL0 and EL1 are trapped to Hyp mode.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TPM==1, accesses to this register from EL0, EL1, and EL2 are trapped to EL3.
02/05/2017 15:43
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.