DBGDEVID, Debug Device ID register 0

The DBGDEVID characteristics are:

Purpose

Adds to the information given by the DBGDIDR by describing other features of the debug implementation.

This register is part of the Debug registers functional group.

Configuration

There is one instance of this register that is used in both Secure and Non-secure states.

This register is required in all implementations.

Attributes

DBGDEVID is a 32-bit register.

Field descriptions

The DBGDEVID bit assignments are:

313029282726252423222120191817161514131211109876543210
CIDMaskAuxRegsDoubleLockVirtExtnsVectorCatchBPAddrMaskWPAddrMaskPCSample

CIDMask, bits [31:28]

Indicates the level of support for the Context ID matching breakpoint masking capability. Permitted values of this field are:

CIDMaskMeaning
0000

Context ID masking is not implemented.

0001

Context ID masking is implemented.

All other values are reserved. The value of this for ARMv8 is 0000.

AuxRegs, bits [27:24]

Indicates support for Auxiliary registers. Permitted values for this field are:

AuxRegsMeaning
0000

None supported.

0001

Support for External Debug Auxiliary Control Register, EDACR.

All other values are reserved.

DoubleLock, bits [23:20]

Indicates the presence of the DBGOSDLR, OS Double Lock Register. Permitted values of this field are:

DoubleLockMeaning
0000

The DBGOSDLR is not present.

0001

The DBGOSDLR is present.

All other values are reserved. The value of this for ARMv8 is 0001.

VirtExtns, bits [19:16]

Indicates whether EL2 is implemented. Permitted values of this field are:

VirtExtnsMeaning
0000

EL2 is not implemented.

0001

EL2 is implemented.

All other values are reserved.

VectorCatch, bits [15:12]

Defines the form of Vector Catch exception implemented. Permitted values of this field are:

VectorCatchMeaning
0000

Address matching Vector Catch exception implemented.

0001

Exception matching Vector Catch exception implemented.

All other values are reserved.

BPAddrMask, bits [11:8]

Indicates the level of support for the instruction address matching breakpoint masking capability. Permitted values of this field are:

BPAddrMaskMeaning
0000

Breakpoint address masking might be implemented. If not implemented, DBGBCR<n>[28:24] is RAZ/WI.

0001

Breakpoint address masking is implemented.

1111

Breakpoint address masking is not implemented. DBGBCR<n>[28:24] is RES0.

All other values are reserved. The value of this for ARMv8 is 1111.

WPAddrMask, bits [7:4]

Indicates the level of support for the data address matching watchpoint masking capability. Permitted values of this field are:

WPAddrMaskMeaning
0000

Watchpoint address masking might be implemented. If not implemented, DBGWCR<n>.MASK (Address mask) is RAZ/WI.

0001

Watchpoint address masking is implemented.

1111

Watchpoint address masking is not implemented. DBGWCR<n>.MASK (Address mask) is RES0.

All other values are reserved. The value of this for ARMv8 is 0001.

PCSample, bits [3:0]

Indicates the level of PC Sample-based Profiling support using external debug registers. Permitted values of this field are:

PCSampleMeaning
0000

Architecture-defined form of PC Sample-based Profiling not implemented using external debug registers.

0010

Only EDPCSR and EDCIDSR are implemented. This option is only permitted if EL3 and EL2 are not implemented.

0011

EDPCSR, EDCIDSR, and EDVIDSR are implemented.

All other values are reserved.

From ARMv8.2 onwards, the only permitted value is 0b0000. The architecture defines the functionality in a different set of registers, see PMDEVID.

Accessing the DBGDEVID

This register can be read using MRC with the following syntax:

MRC <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p14, 0, <Rt>, c7, c2, 7000111011111100010

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RO n/a RO
x01 - RORORO
x11 - n/a RORO

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :

When EL3 is implemented and is using AArch64 :




02/05/2017 15:43

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