The PMCEID0_EL0 characteristics are:
Defines which common architectural and common microarchitectural feature events in the ranges 0x0000 to 0x001F and 0x4000 to 0x401F are implemented. If a particular bit is set to 1, then the event for that bit is implemented.
This register is part of the Performance Monitors registers functional group.
AArch64 System register PMCEID0_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMCEID0.
AArch64 System register PMCEID0_EL0 bits [63:32] are architecturally mapped to AArch32 System register PMCEID2.
AArch64 System register PMCEID0_EL0 bits [31:0] are architecturally mapped to External register PMCEID0.
AArch64 System register PMCEID0_EL0 bits [63:32] are architecturally mapped to External register PMCEID2.
PMCEID0_EL0 is a 64-bit register.
The PMCEID0_EL0 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
ID[16415:16384] | |||||||||||||||||||||||||||||||
ID[31:0] | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PMCEID0_EL0[63:32] maps to common events 0x4000 to 0x401F. For a list of event numbers and descriptions, see 'Event numbers and mnemonics' in the ARM ARM, section D5.10.
For each bit:
ID[16415:16384] | Meaning |
---|---|
0 |
The common event is not implemented. |
1 |
The common event is implemented. |
Bits that map to reserved event numbers are reserved to identify events that might be defined in future revisions to the architecture.
Events that do not require additional features in the PMU can be defined retrospectively, meaning that they can be implemented as part of a PMUv3 implementation.
Reserved, RES0.
PMCEID0_EL0[31:0] maps to common events 0x0000 to 0x001F. For a list of event numbers and descriptions, see 'Event numbers and mnemonics' in the ARM ARM, section D5.10.
For each bit:
ID[31:0] | Meaning |
---|---|
0 |
The common event is not implemented. |
1 |
The common event is implemented. |
Bits that map to reserved event numbers are reserved to identify events that might be defined in future revisions to the architecture.
Events that do not require additional features in the PMU can be defined retrospectively, meaning that they can be implemented as part of a PMUv3 implementation.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
PMCEID0_EL0 | 11 | 011 | 1001 | 1100 | 110 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | RO | RO | n/a | RO |
x | 0 | 1 | RO | RO | RO | RO |
x | 1 | 1 | RO | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If PMUSERENR_EL0.EN==0, read accesses to this register from EL0 are trapped to EL1.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TPM==1, Non-secure read accesses to this register from EL0 and EL1 are trapped to EL2.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TPM==1, read accesses to this register from EL0, EL1, and EL2 are trapped to EL3.
02/05/2017 15:43
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