FPCR, Floating-point Control Register

The FPCR characteristics are:

Purpose

Controls floating-point behavior.

This register is part of:

Configuration

The named fields in this register map to the equivalent fields in the AArch32 FPSCR.

It is IMPLEMENTATION DEFINED whether the Len and Stride fields can be programmed to non-zero values, which will cause some AArch32 floating-point instruction encodings to be UNDEFINED, or whether these fields are RAZ.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

FPCR is a 32-bit register.

Field descriptions

The FPCR bit assignments are:

313029282726252423222120191817161514131211109876543210
00000AHPDNFZRModeStrideFZ16LenIDE00IXEUFEOFEDZEIOE00000000

Bits [31:27]

Reserved, RES0.

AHP, bit [26]

Alternative half-precision control bit:

AHPMeaning
0

IEEE half-precision format selected.

1

Alternative half-precision format selected.

This bit is only used for conversions between half-precision floating-point and other floating-point formats.

The data-processing instructions added as part of the ARMv8.2-FP16 extension always use the IEEE half-precision format, and ignore the value of this bit.

DN, bit [25]

Default NaN mode control bit:

DNMeaning
0

NaN operands propagate through to the output of a floating-point operation.

1

Any operation involving one or more NaNs returns the Default NaN.

The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.

FZ, bit [24]

Flush-to-zero mode control bit:

FZMeaning
0

Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard.

1

Flush-to-zero mode enabled.

The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.

This bit has no effect on half-precision calculations.

RMode, bits [23:22]

Rounding Mode control field. The encoding of this field is:

RModeMeaning
00

Round to Nearest (RN) mode

01

Round towards Plus Infinity (RP) mode

10

Round towards Minus Infinity (RM) mode

11

Round towards Zero (RZ) mode.

The specified rounding mode is used by both scalar and Advanced SIMD floating-point instructions.

Stride, bits [21:20]

This field has no function in AArch64 state, and non-zero values are ignored during execution in AArch64 state. It is included only for context saving and restoration of the AArch32 FPSCR.Stride field.

FZ16, bit [19]
In ARMv8.2:

When ARMv8.2-FP16 is implemented, flush-to-zero mode control bit on half-precision data-processing instructions:

FZ16Meaning
0

Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard.

1

Flush-to-zero mode enabled.

The value of this bit applies to both scalar and Advanced SIMD floating-point half-precision calculations. A half-precision floating-point number that is flushed to zero as a result of the value of the FZ16 bit does not generate an Input Denormal exception.

When ARMv8.2-FP16 is not implemented, this bit is RES0.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

Len, bits [18:16]

This field has no function in AArch64 state, and non-zero values are ignored during execution in AArch64 state. It is included only for context saving and restoration of the AArch32 FPSCR.Len field.

IDE, bit [15]

Input Denormal floating-point exception trap enable. Possible values are:

IDEMeaning
0

Untrapped exception handling selected. If the floating-point exception occurs then the FPSR.IDC bit is set to 1.

1

Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.IDC bit. The trap handling software can decide whether to set the FPSR.IDC bit to 1.

The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.

If the implementation does not support this exception, this bit is RES0.

Bits [14:13]

Reserved, RES0.

IXE, bit [12]

Inexact floating-point exception trap enable. Possible values are:

IXEMeaning
0

Untrapped exception handling selected. If the floating-point exception occurs then the FPSR.IXC bit is set to 1.

1

Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.IXC bit. The trap handling software can decide whether to set the FPSR.IXC bit to 1.

The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.

If the implementation does not support this exception, this bit is RES0.

UFE, bit [11]

Underflow floating-point exception trap enable. Possible values are:

UFEMeaning
0

Untrapped exception handling selected. If the floating-point exception occurs then the FPSR.UFC bit is set to 1.

1

Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.UFC bit. The trap handling software can decide whether to set the FPSR.UFC bit to 1.

The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.

If the implementation does not support this exception, this bit is RES0.

OFE, bit [10]

Overflow floating-point exception trap enable. Possible values are:

OFEMeaning
0

Untrapped exception handling selected. If the floating-point exception occurs then the FPSR.OFC bit is set to 1.

1

Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.OFC bit. The trap handling software can decide whether to set the FPSR.OFC bit to 1.

The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.

If the implementation does not support this exception, this bit is RES0.

DZE, bit [9]

Divide by Zero floating-point exception trap enable. Possible values are:

DZEMeaning
0

Untrapped exception handling selected. If the floating-point exception occurs then the FPSR.DZC bit is set to 1.

1

Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.DZC bit. The trap handling software can decide whether to set the FPSR.DZC bit to 1.

The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.

If the implementation does not support this exception, this bit is RES0.

IOE, bit [8]

Invalid Operation floating-point exception trap enable. Possible values are:

IOEMeaning
0

Untrapped exception handling selected. If the floating-point exception occurs then the FPSR.IOC bit is set to 1.

1

Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.IOC bit. The trap handling software can decide whether to set the FPSR.IOC bit to 1.

The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.

If the implementation does not support this exception, this bit is RES0.

Bits [7:0]

Reserved, RES0.

Accessing the FPCR

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
FPCR1101101000100000

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0RWRW n/a RW
x01RWRWRWRW
x11RW n/a RWRW

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==1 :

When EL3 is implemented and is using AArch64 :




02/05/2017 15:43

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