The ELR_EL2 characteristics are:
When taking an exception to EL2, holds the address to return to.
This register is part of the Special-purpose registers functional group.
AArch64 System register ELR_EL2 is architecturally mapped to AArch32 System register ELR_hyp.
ELR_EL2 is a 64-bit register.
The ELR_EL2 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
Return address | |||||||||||||||||||||||||||||||
Return address | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Return address.
An exception return from EL2 using AArch64 makes ELR_EL2 become UNKNOWN.
When EL2 is in AArch32 Execution state and an exception is taken from EL0, EL1, or EL2 to EL3 and AArch64 execution, the upper 32-bits of ELR_EL2 are either set to 0 or hold the same value that they did before AArch32 execution. Which option is adopted is determined by an implementation, and might vary dynamically within an implementation. Correspondingly software must regard the value as being an UNKNOWN choice between the two values.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
ELR_EL2 | 11 | 100 | 0100 | 0000 | 001 |
ELR_EL1 | 11 | 000 | 0100 | 0000 | 001 |
The register is accessible as follows:
<systemreg> | Control | Accessibility | |||||
---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | |
ELR_EL2 | x | x | 0 | - | - | n/a | RW |
ELR_EL2 | 0 | 0 | 1 | - | - | RW | RW |
ELR_EL2 | 0 | 1 | 1 | - | n/a | RW | RW |
ELR_EL2 | 1 | 0 | 1 | - | - | RW | RW |
ELR_EL2 | 1 | 1 | 1 | - | n/a | RW | RW |
ELR_EL1 | x | x | 0 | - | ELR_EL1 | n/a | ELR_EL1 |
ELR_EL1 | 0 | 0 | 1 | - | ELR_EL1 | ELR_EL1 | ELR_EL1 |
ELR_EL1 | 0 | 1 | 1 | - | n/a | ELR_EL1 | ELR_EL1 |
ELR_EL1 | 1 | 0 | 1 | - | ELR_EL1 | RW | ELR_EL1 |
ELR_EL1 | 1 | 1 | 1 | - | n/a | RW | ELR_EL1 |
When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic ELR_EL2 or ELR_EL1 are not guaranteed to be ordered with respect to accesses using the other mnemonic.
02/05/2017 15:43
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