TPIDRPRW, PL1 Software Thread ID Register

The TPIDRPRW characteristics are:

Purpose

Provides a location where software executing at EL1 or higher can store thread identifying information that is not visible to software executing at EL0, for OS management purposes.

The PE makes no use of this register.

This register is part of the Thread and process ID registers functional group.

Configuration

AArch32 System register TPIDRPRW is architecturally mapped to AArch64 System register TPIDR_EL1[31:0] .

The PE never updates this register. This means the register is always UNKNOWN on reset.

Attributes

TPIDRPRW is a 32-bit register.

Field descriptions

The TPIDRPRW bit assignments are:

313029282726252423222120191817161514131211109876543210
Thread ID

Bits [31:0]

Thread ID. Thread identifying information stored by software running at this Exception level.

Accessing the TPIDRPRW

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 0, <Rt>, c13, c0, 4000100110111110000

Accessibility

The register is accessible as follows:

Configuration Control Accessibility Instance
E2HTGENSEL0EL1EL2EL3
EL3 using AArch32xx0 - n/a n/a RWTPIDRPRW_s
EL3 not implemented xx0 - RW n/a n/a TPIDRPRW
EL3 not implemented x01 - RWRW n/a TPIDRPRW
EL3 not implemented x11 - n/a RW n/a TPIDRPRW
EL3 using AArch64xx0 - RW n/a n/a TPIDRPRW
EL3 using AArch64x01 - RWRW n/a TPIDRPRW
EL3 using AArch64x11 - n/a RW n/a TPIDRPRW
EL3 using AArch32x01 - RWRWRWTPIDRPRW_ns
EL3 using AArch32x11 - n/a RWRWTPIDRPRW_ns

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :




02/05/2017 15:43

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