The PMCEID1 characteristics are:
Defines which common architectural and common microarchitectural feature events in the range 0x020 to 0x03F are implemented. If a particular bit is set to 1, then the event for that bit is implemented.
This view of the register has previously been called PMCEID1_EL0.
This register is part of the Performance Monitors registers functional group.
This register is accessible as follows:
Off | DLK | OSLK | EPMAD | SLK | Default |
---|---|---|---|---|---|
Error | Error | Error | Error | RO | RO |
External register PMCEID1 is architecturally mapped to AArch64 System register PMCEID1_EL0[31:0] .
External register PMCEID1 bits [31:0] are architecturally mapped to AArch32 System register PMCEID1.
PMCEID1 is in the Core power domain.
PMCEID1 is a 32-bit register.
The PMCEID1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ID[63:32] |
PMCEID1[n] maps to event (n + 32). For a list of event numbers and descriptions, see 'Event numbers and mnemonics' in the ARM ARM, section D5.10.
For each bit:
ID[63:32] | Meaning |
---|---|
0 |
The common event is not implemented. |
1 |
The common event is implemented. |
Bits that map to reserved event numbers are reserved to identify events that might be defined in future revisions to the architecture.
Events that do not require additional features in the PMU can be defined retrospectively, meaning that they can be implemented as part of a PMUv3 implementation.
PMCEID1 can be accessed through the external debug interface:
Component | Offset |
---|---|
PMU | 0xE24 |
02/05/2017 15:43
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