The ICV_BPR1 characteristics are:
Defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field. The group priority field determines virtual Group 1 interrupt preemption.
This register is part of:
AArch32 System register ICV_BPR1 is architecturally mapped to AArch64 System register ICV_BPR1_EL1.
ICV_BPR1 is a 32-bit register.
The ICV_BPR1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | BinaryPoint |
Reserved, RES0.
If the GIC is configured to use separate binary point fields for virtual Group 0 and virtual Group 1 interrupts, the value of this field controls how the 8-bit interrupt priority field is split into a group priority field, that determines interrupt preemption, and a subpriority field. This is done as follows:
Binary point value | Group priority field | Subpriority field | Field with binary point |
---|---|---|---|
0 | - | - | - |
1 | [7:1] | [0] | ggggggg.s |
2 | [7:2] | [1:0] | gggggg.ss |
3 | [7:3] | [2:0] | ggggg.sss |
4 | [7:4] | [3:0] | gggg.ssss |
5 | [7:5] | [4:0] | ggg.sssss |
6 | [7:6] | [5:0] | gg.ssssss |
7 | [7] | [6:0] | g.sssssss |
Writing 0 to this field will set this field to its reset value, which is IMPLEMENTATION DEFINED and non-zero.
If ICV_CTLR.CBPR is set to 1, Non-secure EL1 reads return ICV_BPR0 + 1 saturated to 0b111. Non-secure EL1 writes are ignored.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c12, c12, 3 | 000 | 011 | 1100 | 1111 | 1100 |
When HCR.IMO is set to 0, execution of this encoding at Non-secure EL1 results in an access to ICC_BPR1.
The register is accessible as follows:
Control | Accessibility | ||||||
---|---|---|---|---|---|---|---|
FMO | IMO | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | x | 0 | - | ICC_BPR1 | n/a | ICC_BPR1 |
x | x | 1 | 1 | - | n/a | ICC_BPR1 | ICC_BPR1 |
x | 0 | 0 | 1 | - | ICC_BPR1 | ICC_BPR1 | ICC_BPR1 |
x | 1 | 0 | 1 | - | RW | ICC_BPR1 | ICC_BPR1 |
This table applies to all instructions that can access this register.
ICV_BPR1 is only accessible at Non-secure EL1 when HCR.IMO is set to 1.
When HCR.IMO is set to 0, at Non-secure EL1, the instruction encoding used to access ICV_BPR1 results in an access to ICC_BPR1.
The reset value is IMPLEMENTATION DEFINED, but is equal to the minimum value of ICV_BPR0 plus one.
An attempt to program the binary point field to a value less than the reset value sets the field to the reset value.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_SRE.SRE==0, Non-secure accesses to this register from EL1 are UNDEFINED.
If ICC_SRE_EL1.SRE==0, Non-secure accesses to this register from EL1 are trapped to EL1.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==0 :
If HSTR_EL2.T12==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T12==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HSTR.T12==1, Non-secure accesses to this register from EL1 are trapped to Hyp mode.
When SCR_EL3.NS==1 :
If ICH_HCR.TALL1==1, Non-secure accesses to this register from EL1 are trapped to EL2.
If ICH_HCR_EL2.TALL1==1, Non-secure accesses to this register from EL1 are trapped to EL2.
02/05/2017 15:43
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