The GICV_IIDR characteristics are:
Provides information about the implementer and revision of the virtual CPU interface.
This register is part of the GIC virtual CPU interface registers functional group.
This register is accessible as follows:
Security disabled | Secure | Non-secure |
---|---|---|
RO | RO | RO |
This register is available in all configurations of the GIC. If the GIC implementation supports two Security states this register is Common.
GICV_IIDR is a 32-bit register.
The GICV_IIDR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ProductID | Architecture_version | Revision | Implementer |
An IMPLEMENTATION DEFINED product identifier.
The version of the GIC architecture that is implemented.
Architecture_version | Meaning |
---|---|
0001 |
GICv1. |
0010 |
GICv2. |
0011 |
GICv3 memory-mapped interface supported. Support for the System register interface is discoverable from PE registers ID_PFR1 and ID_AA64PFR0_EL1. |
0100 |
GICv4 memory-mapped interface supported. Support for the System register interface is discoverable from PE registers ID_PFR1 and ID_AA64PFR0_EL1. |
Other values are reserved.
An IMPLEMENTATION DEFINED revision number for the CPU interface.
Contains the JEP106 code of the company that implemented the CPU interface.
GICV_IIDR can be accessed through its memory-mapped interface:
Component | Offset |
---|---|
GIC Virtual CPU interface | 0x00FC |
02/05/2017 15:43
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