IC IALLU, Instruction Cache Invalidate All to PoU

The IC IALLU characteristics are:

Purpose

Invalidate all instruction caches to Point of Unification.

This System instruction is part of the Cache maintenance instructions functional group.

Configuration

AArch64 System instruction IC IALLU performs the same function as AArch32 System instruction ICIALLU.

Attributes

IC IALLU is a 64-bit System instruction.

Field descriptions

IC IALLU ignores the value in the register specified by the instruction encoding. Software does not have to write a value to the register before issuing this instruction.

Executing the IC IALLU instruction

This instruction is executed using IC with the following syntax:

IC <ic_op>

This syntax uses the following encoding in the System instruction encoding space:

<ic_op> op0op1CRnCRmop2Rt
IALLU010000111010100011111

Accessibility

The instruction is executable as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - WO n/a WO
x01 - WOWOWO
x11 - n/a WOWO

This table applies to all syntax that can be used to execute this instruction.

When HCR_EL2.FB is 1, at Non-secure EL1 this instruction executes as a IC IALLUIS.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when executing this System instruction.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :




02/05/2017 15:43

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