The EDCIDSR characteristics are:
Contains the sampled value of the Context ID, captured on reading EDPCSR[31:0].
This register is part of the Debug registers functional group.
This register is accessible as follows:
Off | DLK | OSLK | Default |
---|---|---|---|
Error | Error | Error | RO |
EDCIDSR is in the Core power domain.
Fields in this register reset to architecturally UNKNOWN values. These apply only on a Cold reset. The register is not affected by a Warm reset and is not affected by an External debug reset.
Implemented only if the OPTIONAL PC Sample-based Profiling Extension is implemented but not with ARMv8.2-PCSample. If ARMv8.2-PCSample is implemented, this register is RES0 and the architecture defines the functionality in PMCID1SR and PMCID2SR.
EDCIDSR is a 32-bit register.
The EDCIDSR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CONTEXTIDR |
Context ID. The value of CONTEXTIDR that is associated with the most recent EDPCSR sample.
Because the value written to EDCIDSR is an indirect read of CONTEXTIDR, therefore it is CONSTRAINED UNPREDICTABLE whether EDCIDSR is set to the original or new value if a read of EDPCSRlo samples:
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Reserved, RES0.
EDCIDSR can be accessed through the external debug interface:
Component | Offset |
---|---|
Debug | 0x0A4 |
02/05/2017 15:43
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