The DBGCLAIMSET_EL1 characteristics are:
Used by software to set the CLAIM tag bits to 1.
The architecture does not define any functionality for the CLAIM tag bits.
CLAIM tags are typically used for communication between the debugger and target software.
Used in conjunction with the DBGCLAIMCLR_EL1 register.
This register is part of the Debug registers functional group.
AArch64 System register DBGCLAIMSET_EL1 is architecturally mapped to AArch32 System register DBGCLAIMSET.
AArch64 System register DBGCLAIMSET_EL1 is architecturally mapped to External register DBGCLAIMSET_EL1.
An implementation must include 8 CLAIM tag bits.
DBGCLAIMSET_EL1 is a 32-bit register.
The DBGCLAIMSET_EL1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CLAIM |
Reserved, RAZ/SBZ. Software can rely on these bits reading as zero, and must use a should-be-zero policy on writes. Implementations must ignore writes.
Set CLAIM tag bits. RAO.
Writing a 1 to one of these bits sets the corresponding CLAIM tag bit to 1. This is an indirect write to the CLAIM tag bits. A single write operation can set multiple CLAIM tag bits to 1.
Writing 0 to one of these bits has no effect.
A cold reset clears the CLAIM tag bits to 0.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
DBGCLAIMSET_EL1 | 10 | 000 | 0111 | 1000 | 110 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RW | n/a | RW |
x | 0 | 1 | - | RW | RW | RW |
x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TDA==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TDA==1, accesses to this register from EL1 and EL2 are trapped to EL3.
02/05/2017 15:43
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