The ID_AA64MMFR1_EL1 characteristics are:
Provides information about the implemented memory model and memory management support in AArch64 state.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.
This register is part of the Identification registers functional group.
There are no configuration notes.
ID_AA64MMFR1_EL1 is a 64-bit register.
The ID_AA64MMFR1_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
XNX | SpecSEI | PAN | LO | HPDS | VH | VMIDBits | HAFDBS | ||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Indicates support for Execute Never control distinction at stage 2 bit. Defined values are:
XNX | Meaning |
---|---|
0000 |
Distinction between EL0 and EL1 execute permission at stage 2 not supported. |
0001 |
Distinction between EL0 and EL1 execute permission at stage 2 supported. |
All other values are reserved.
In ARMv8.0 and ARMv8.1, the only permitted value is 0000.
From ARMv8.2, the only permitted value is 0001. This feature is identified by the name ARMv8.2-TTS2UXN.
Reserved, RES0.
Describes whether the PE can generate SError interrupt exceptions from speculative reads of memory, including speculative instruction fetches. The defined values of this field are:
SpecSEI | Meaning |
---|---|
0000 |
The PE never generates an SError interrupt due to an external abort on a speculative read. |
0001 |
The PE might generate an SError interrupt due to an external abort on a speculative read. |
All other values are reserved.
When the RAS Extension is not implemented, this field is RAZ.
Privileged Access Never. Indicates support for the PAN bit in PSTATE, SPSR_EL1, SPSR_EL2, SPSR_EL3, and DSPSR_EL0. Defined values are:
PAN | Meaning |
---|---|
0000 |
PAN not supported. |
0001 |
PAN supported. |
0010 |
PAN supported and AT S1E1RP and AT S1E1WP instructions supported. |
All other values are reserved.
In ARMv8.0 the only permitted value is 0000.
In ARMv8.1 the only permitted value is 0001. This feature is identified by the name ARMv8.1-PAN.
From ARMv8.2, the only permitted value is 0010. This feature is identified by the name ARMv8.2-ATS1E1.
Reserved, RES0.
LORegions. Indicates support for LORegions. Defined values are:
LO | Meaning |
---|---|
0000 |
LORegions not supported. |
0001 |
LORegions supported. |
All other values are reserved.
In ARMv8.0 the only permitted value is 0000.
From ARMv8.1, the only permitted value is 0001. This feature is identified by the name ARMv8.1-LOR.
Reserved, RES0.
Hierarchical permission disables bits in translation tables. Defined values are:
HPDS | Meaning |
---|---|
0000 |
Disabling of hierarchical controls not supported. |
0001 |
Disabling of hierarchical controls supported using TCR_EL1.HPD0, TCR_EL1.HPD1, TCR_EL2.HPD, and TCR_EL3.HPD bits. |
0010 |
Disabling of hierarchical controls supported using the TCR_EL1.HPD0, TCR_EL1.HPD1, TCR_EL2.HPD, and TCR_EL3.HPD bits, and hardware allocation of bits[62:59] of the last level page table descriptor for IMPLEMENTATION DEFINED use. |
All other values are reserved.
In ARMv8.0 the only permitted value is 0000.
In ARMv8.1 the only permitted value is 0001. This feature is identified by the name ARMv8.1-HPD.
From ARMv8.2, the permitted values are 0001 and 0010. This feature is identified by the name ARMv8.2-TTPBHA.
Reserved, RES0.
Virtualization Host Extensions. Defined values are:
VH | Meaning |
---|---|
0000 |
Virtualization Host Extensions not supported. |
0001 |
Virtualization Host Extensions supported. |
All other values are reserved.
In ARMv8.0 the only permitted value is 0000.
From ARMv8.1, the only permitted value is 0001. This feature is identified by the name ARMv8.1-VHE.
Reserved, RES0.
Number of VMID bits. Defined values are:
VMIDBits | Meaning |
---|---|
0000 |
8 bits |
0010 |
16 bits |
All other values are reserved.
In ARMv8.0 the only permitted value is 0000.
From ARMv8.1, the permitted values are 0000 and 0010.
Reserved, RES0.
Hardware updates to Access flag and Dirty state in translation tables. Defined values are:
HAFDBS | Meaning |
---|---|
0000 |
No hardware update of the Access flag and dirty state is supported in hardware. |
0001 |
Hardware update of the Access flag is supported in hardware. |
0010 |
Hardware update of both the Access flag and dirty state is supported in hardware. |
All other values are reserved.
From ARMv8.1, the permitted values are 0000, 0001, and 0010. This feature is identified by the name ARMv8.1-VHE.
Reserved, RES0.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
ID_AA64MMFR1_EL1 | 11 | 000 | 0000 | 0111 | 001 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
02/05/2017 15:43
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