The NSACR characteristics are:
When EL3 is implemented and can use AArch32, defines the Non-secure access permissions to Trace, Advanced SIMD and floating-point functionality. Also includes IMPLEMENTATION DEFINED bits that can define Non-secure access permissions for IMPLEMENTATION DEFINED functionality.
This register is part of the Security registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
In AArch64 state, the NSACR controls are replaced by controls in CPTR_EL3.
Some or all RW fields of this register have defined reset values. These apply whenever the register is accessible. This means they apply when the PE resets into EL3 using AArch32.
NSACR is a 32-bit register.
The NSACR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | NSTRCDIS | 0 | IMPLEMENTATION DEFINED | NSASEDIS | 0 | 0 | 0 | cp11 | cp10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
If EL3 is implemented and is using AArch64 then:
If EL3 is not implemented, then any read of the NSACR from EL2 or EL1 returns a value of 0x00000C00.
Reserved, RES0.
Disables Non-secure System register accesses to all implemented trace registers.
NSTRCDIS | Meaning |
---|---|
0 |
This control has no effect on: |
1 |
Non-secure System register accesses to all implemented trace registers are disabled, meaning: |
The implementation of this field must correspond to the implementation of the CPACR.TRCDIS field:
System register accesses to the trace registers can have side-effects. When a System register access is trapped, any side-effects that are normally associated with the access do not occur before the exception is taken.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.
Reserved, RES0.
IMPLEMENTATION DEFINED.
Disables Non-secure access to the Advanced SIMD functionality.
NSASEDIS | Meaning |
---|---|
0 |
This control has no effect on: |
1 |
Non-secure access to the Advanced SIMD functionality is disabled, meaning: |
The implementation of this field must correspond to the implementation of the CPACR.ASEDIS field:
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.
Reserved, RES0.
The value of this field is ignored. If this field is programmed with a different value to the cp10 field then this field is UNKNOWN on a direct read of the NSACR.
If the implementation does not include Advanced SIMD and floating-point functionality, this field is RES0.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to an architecturally UNKNOWN value.
Enable Non-secure access to the Advanced SIMD and floating-point features. Possible values of the fields are:
cp10 | Meaning |
---|---|
0 |
Advanced SIMD and floating-point features can be accessed only from Secure state. Any attempt to access this functionality from Non-secure state is UNDEFINED. When the PE is in Non-secure state: |
1 |
Advanced SIMD and floating-point features can be accessed from both Security states. |
If Non-secure access to the Advanced SIMD and floating-point functionality is enabled, the CPACR must be checked to determine the level of access that is permitted.
The Advanced SIMD and floating-point features controlled by these fields are:
If the implementation does not include Advanced SIMD and floating-point functionality, this field is RES0.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to an architecturally UNKNOWN value.
Reserved, RES0.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c1, c1, 2 | 000 | 010 | 0001 | 1111 | 0001 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | - | n/a | RW |
x | 0 | 1 | - | RO | RO | RW |
x | 1 | 1 | - | n/a | RO | RW |
This table applies to all instructions that can access this register.
If EL3 is implemented and is using AArch64, any read from or write to NSACR from Secure EL1 is trapped as an exception to EL3.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HSTR_EL2.T1==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T1==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HSTR.T1==1, Non-secure read accesses to this register from EL1 are trapped to Hyp mode.
02/05/2017 15:43
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