ID_ISAR0, Instruction Set Attribute Register 0

The ID_ISAR0 characteristics are:

Purpose

Provides information about the instruction sets implemented by the PE in AArch32 state.

Must be interpreted with ID_ISAR1, ID_ISAR2, ID_ISAR3, ID_ISAR4, and ID_ISAR5.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section G4.14.6.

This register is part of the Identification registers functional group.

Configuration

There is one instance of this register that is used in both Secure and Non-secure states.

AArch32 System register ID_ISAR0 is architecturally mapped to AArch64 System register ID_ISAR0_EL1.

Attributes

ID_ISAR0 is a 32-bit register.

Field descriptions

The ID_ISAR0 bit assignments are:

313029282726252423222120191817161514131211109876543210
0000DivideDebugCoprocCmpBranchBitFieldBitCountSwap

Bits [31:28]

Reserved, RES0.

Divide, bits [27:24]

Indicates the implemented Divide instructions. Defined values are:

DivideMeaning
0000

None implemented.

0001

Adds SDIV and UDIV in the T32 instruction set.

0010

As for 0001, and adds SDIV and UDIV in the A32 instruction set.

All other values are reserved.

In ARMv8-A the only permitted value is 0010.

Debug, bits [23:20]

Indicates the implemented Debug instructions. Defined values are:

DebugMeaning
0000

None implemented.

0001

Adds BKPT.

All other values are reserved.

In ARMv8-A the only permitted value is 0001.

Coproc, bits [19:16]

Indicates the implemented System register access instructions. Defined values are:

CoprocMeaning
0000

None implemented, except for instructions separately attributed by the architecture to provide access to AArch32 System registers and System instructions.

0001

Adds generic CDP, LDC, MCR, MRC, and STC.

0010

As for 0001, and adds generic CDP2, LDC2, MCR2, MRC2, and STC2.

0011

As for 0010, and adds generic MCRR and MRRC.

0100

As for 0011, and adds generic MCRR2 and MRRC2.

All other values are reserved.

In ARMv8-A the only permitted value is 0000.

CmpBranch, bits [15:12]

Indicates the implemented combined Compare and Branch instructions in the T32 instruction set. Defined values are:

CmpBranchMeaning
0000

None implemented.

0001

Adds CBNZ and CBZ.

All other values are reserved.

In ARMv8-A the only permitted value is 0001.

BitField, bits [11:8]

Indicates the implemented BitField instructions. Defined values are:

BitFieldMeaning
0000

None implemented.

0001

Adds BFC, BFI, SBFX, and UBFX.

All other values are reserved.

In ARMv8-A the only permitted value is 0001.

BitCount, bits [7:4]

Indicates the implemented Bit Counting instructions. Defined values are:

BitCountMeaning
0000

None implemented.

0001

Adds CLZ.

All other values are reserved.

In ARMv8-A the only permitted value is 0001.

Swap, bits [3:0]

Indicates the implemented Swap instructions in the A32 instruction set. Defined values are:

SwapMeaning
0000

None implemented.

0001

Adds SWP and SWPB.

All other values are reserved.

In ARMv8-A the only permitted value is 0000.

Accessing the ID_ISAR0

This register can be read using MRC with the following syntax:

MRC <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 0, <Rt>, c0, c2, 0000000000011110010

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RO n/a RO
x01 - RORORO
x11 - n/a RORO

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :




02/05/2017 15:43

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