PRRR, Primary Region Remap Register

The PRRR characteristics are:

Purpose

Controls the top level mapping of the TEX[0], C, and B memory region attributes.

This register is part of the Virtual memory control registers functional group.

Configuration

AArch32 System register PRRR is architecturally mapped to AArch64 System register MAIR_EL1[31:0] when TTBCR.EAE==0.

MAIR0 and PRRR are the same register, with a different view depending on the value of TTBCR.EAE:

When EL3 is using AArch32, write access to PRRR(S) is disabled when the CP15SDISABLE signal is asserted HIGH.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

PRRR is a 32-bit register.

Field descriptions

The PRRR bit assignments are:

When TTBCR.EAE==0:

313029282726252423222120191817161514131211109876543210
NOS7NOS6NOS5NOS4NOS3NOS2NOS1NOS00000NS1NS0DS1DS0TR7TR6TR5TR4TR3TR2TR1TR0

NOS<n>, bit [n+24], for n = 0 to 7

Not Outer Shareable. NOS<n> is the Outer Shareable property for memory attributes n, if the region is mapped as Normal memory that is not Inner Non-cacheable, Outer Non-cacheable, and the appropriate PRRR.{NS0, NS1} field identifies the region as shareable. n is the value of the concatenation of the {TEX[0], C, B} bits from the translation table descriptor. The possible values of each NOS<n> field other than NOS6 are:

NOS<n>Meaning
0

Memory region is Outer Shareable.

1

Memory region is Inner Shareable.

The value of this bit is ignored if the region is:

The meaning of the NOS6 field is IMPLEMENTATION DEFINED.

Bits [23:20]

Reserved, RES0.

NS1, bit [19]

Mapping of S = 1 attribute for Normal memory regions. This field is used in determining the Shareability of a memory region that is mapped to Normal memory and both:

The possible values of this bit are:

NS1Meaning
0

Region is Non-shareable.

1

Region is shareable. The value of the appropriate PRRR.NOS<n> field determines whether the region is Inner Shareable or Outer Shareable.

NS0, bit [18]

Mapping of S = 0 attribute for Normal memory regions. This field is used in determining the Shareability of a memory region that is mapped to Normal memory and both:

The possible values of this bit are:

NS0Meaning
0

Region is Non-shareable.

1

Region is shareable. The value of the appropriate PRRR.NOS<n> field determines whether the region is Inner Shareable or Outer Shareable.

DS1, bit [17]

Mapping of S = 1 attribute for Device memory. In ARMv8, all types of Device memory are Outer Shareable, and therefore this bit is RES1.

DS0, bit [16]

Mapping of S = 0 attribute for Device memory. In ARMv8, all types of Device memory are Outer Shareable, and therefore this bit is RES1.

TR<n>, bits [2n+1:2n], for n = 0 to 7

TR<n> is the primary TEX mapping for memory attributes n, and defines the mapped memory type for a region with attributes n. n is the value of the concatenation of the {TEX[0], C, B} bits from the translation table descriptor. The possible values for each field other than TR6 are:

TR<n>Meaning
00

Device-nGnRnE memory

01

Device-nGnRE memory

10

Normal memory

The value 11 is reserved. The effect of programming a field to 11 is CONSTRAINED UNPREDICTABLE, see 'Unallocated values in fields of AArch32 System registers and translation table entries' in the ARMv8 ARM, section K1.1.11.

The meaning of the TR6 field is IMPLEMENTATION DEFINED.

Accessing the PRRR

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 0, <Rt>, c10, c2, 0000000101011110010

Accessibility

The register is accessible as follows:

Configuration Control Accessibility Instance
E2HTGENSEL0EL1EL2EL3
EL3 not implemented xx0 - RW n/a n/a PRRR
EL3 not implemented x01 - RWRW n/a PRRR
EL3 not implemented x11 - n/a RW n/a PRRR
EL3 using AArch64xx0 - RW n/a n/a PRRR
EL3 using AArch64x01 - RWRW n/a PRRR
EL3 using AArch64x11 - n/a RW n/a PRRR
EL3 using AArch32xx0 - n/a n/a RWPRRR_s
EL3 using AArch32x01 - RWRWRWPRRR_ns
EL3 using AArch32x11 - n/a RWRWPRRR_ns

This table applies to all instructions that can access this register.

When EL3 is using AArch32, write access to PRRR_s is UNDEFINED when the CP15SDISABLE signal is asserted HIGH.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :




02/05/2017 15:43

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