GICD_ITARGETSR<n>, Interrupt Processor Targets Registers, n = 0 - 254

The GICD_ITARGETSR<n> characteristics are:

Purpose

When affinity routing is not enabled, holds the list of target PEs for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority.

This register is part of the GIC Distributor registers functional group.

Usage constraints

This register is accessible as follows:

Security disabledSecureNon-secure
RWRWRW

These registers are used when affinity routing is not enabled. When affinity routing is enabled for the Security state of an interrupt, the target PEs for an interrupt are defined by GICD_IROUTER<n> and the associated byte in GICD_ITARGETSR<n> is RES0. An implementation is permitted to make the byte RAZ/WI in this case.

In a single connected PE implementation, all interrupts target one PE, and these registers are RAZ/WI.

Note

Implementations must ensure that an interrupt that is pending at the time of the write uses either the old value or the new value and must ensure that the interrupt is neither lost nor handled more than once. The effect of the change must be visible in finite time.

Configuration

RW fields in this register reset to architecturally UNKNOWN values.

These registers are available in all configurations of the GIC. When GICD_CTLR.DS==0, these registers are Common.

The number of implemented GICD_ITARGETSR<n> registers is 8*(GICD_TYPER.ITLinesNumber+1). Registers are numbered from 0.

GICD_ITARGETSR0 to GICD_ITARGETSR7 are Banked for each connected PEwith GICR_TYPER.Processor_Number < 8.

Accessing GICD_ITARGETSR0 to GICD_ITARGETSR7 from a PE with GICR_TYPER.Processor_Number > 7 is CONSTRAINED UNPREDICTABLE:

Attributes

GICD_ITARGETSR<n> is a 32-bit register.

Field descriptions

The GICD_ITARGETSR<n> bit assignments are:

313029282726252423222120191817161514131211109876543210
CPU_targets_offset_3BCPU_targets_offset_2BCPU_targets_offset_1BCPU_targets_offset_0B

PEs in the system number from 0, and each bit in a PE targets field refers to the corresponding PE. For example, a value of 0x3 means that the Pending interrupt is sent to PEs 0 and 1. For GICD_ITARGETSR0-GICD_ITARGETSR7, a read of any targets field returns the number of the PE performing the read.

CPU_targets_offset_3B, bits [31:24]

PE targets for an interrupt, at byte offset 3.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

CPU_targets_offset_2B, bits [23:16]

PE targets for an interrupt, at byte offset 2.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

CPU_targets_offset_1B, bits [15:8]

PE targets for an interrupt, at byte offset 1.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

CPU_targets_offset_0B, bits [7:0]

PE targets for an interrupt, at byte offset 0.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

The bits that are set to 1 in the PE targets field determine which PEs are targeted:

Value of PE targets field Interrupt targets
0bxxxxxxx1 CPU interface 0
0bxxxxxx1x CPU interface 1
0bxxxxx1xx CPU interface 2
0bxxxx1xxx CPU interface 3
0bxxx1xxxx CPU interface 4
0bxx1xxxxx CPU interface 5
0bx1xxxxxx CPU interface 6
0b1xxxxxxx CPU interface 7

For interrupt ID m, when DIV and MOD are the integer division and modulo operations:

Software can write to these registers at any time. Any change to a targets field value:

Accessing the GICD_ITARGETSR<n>

GICD_ITARGETSR<n> can be accessed through its memory-mapped interface:

ComponentOffset
GIC Distributor0x0800 + 4n



02/05/2017 15:43

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