The ICC_PMR_EL1 characteristics are:
Provides an interrupt priority filter. Only interrupts with a higher priority than the value in this register are signaled to the PE.
Writes to this register must be high performance and must ensure that no interrupt of lower priority than the written value occurs after the write, without requiring an ISB or an exception boundary.
This register is part of:
AArch64 System register ICC_PMR_EL1 is architecturally mapped to AArch32 System register ICC_PMR.
To allow software to ensure appropriate observability of actions initiated by GIC register accesses, the PE and CPU interface logic must ensure that writes to this register are self-synchronising. This ensures that no interrupts below the written PMR value will be taken after a write to this register is architecturally executed. See Observability of the effects of accesses to the GIC registers, for more information.
ICC_PMR_EL1 is a 32-bit register.
The ICC_PMR_EL1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Priority |
Reserved, RES0.
The priority mask level for the CPU interface. If the priority of an interrupt is higher than the value indicated by this field, the interface signals the interrupt to the PE.
The possible priority field values are as follows:
Implemented priority bits | Possible priority field values | Number of priority levels |
---|---|---|
[7:0] | 0x00-0xFF (0-255), all values | 256 |
[7:1] | 0x00-0xFE (0-254), even values only | 128 |
[7:2] | 0x00-0xFC (0-252), in steps of 4 | 64 |
[7:3] | 0x00-0xF8 (0-248), in steps of 8 | 32 |
[7:4] | 0x00-0xF0 (0-240), in steps of 16 | 16 |
Unimplemented priority bits are RAZ/WI.
When this register has an architecturally-defined reset value, this field resets to 0.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op1 | CRn | CRm | op2 |
---|---|---|---|---|
ICC_PMR_EL1 | 000 | 0100 | 0110 | 000 |
When HCR_EL2.{FMO, IMO} != {0, 0}, execution of this encoding at Non-secure EL1 results in an access to ICV_PMR_EL1.
The register is accessible as follows:
Control | Accessibility | ||||||
---|---|---|---|---|---|---|---|
FMO | IMO | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | x | 0 | - | RW | n/a | RW |
x | x | 1 | 1 | - | n/a | RW | RW |
x | 1 | 0 | 1 | - | ICV_PMR_EL1 | RW | RW |
1 | x | 0 | 1 | - | ICV_PMR_EL1 | RW | RW |
0 | 0 | 0 | 1 | - | RW | RW | RW |
This table applies to all instructions that can access this register.
ICC_PMR_EL1 is only accessible at Non-secure EL1 when HCR_EL2.{FMO, IMO} == {0, 0}.
When HCR_EL2.{FMO, IMO} != {0, 0}, at Non-secure EL1, the instruction encoding used to access ICC_PMR_EL1 results in an access to ICV_PMR_EL1.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_SRE_EL1.SRE==0, accesses to this register from EL1 are trapped to EL1.
If ICC_SRE_EL2.SRE==0, accesses to this register from EL2 are trapped to EL2.
If ICC_SRE_EL3.SRE==0, accesses to this register from EL3 are trapped to EL3.
When SCR_EL3.NS==1 :
If ICH_HCR_EL2.TC==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL3 is implemented and is using AArch64 and SCR_EL3.NS==0 :
If SCR_EL3.FIQ==1, and SCR_EL3.IRQ==1, Secure accesses to this register from EL1 are trapped to EL3.
When EL3 is implemented and is using AArch64 :
When EL3 is implemented and is using AArch64 and SCR_EL3.NS==1 :
02/05/2017 15:43
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