PMPCSR, Program Counter Sample Register

The PMPCSR characteristics are:

Purpose

Holds a sampled instruction address value.

This register is part of the Performance Monitors registers functional group.

Usage constraints

This register is accessible as follows:

OffDLKOSLKSLKDefault
ErrorErrorErrorRORO

Configuration

PMPCSR is in the Core power domain.

Fields in this register reset to architecturally UNKNOWN values. These apply only on a Cold reset. The register is not affected by a Warm reset and is not affected by an External debug reset.

Implemented only if the OPTIONAL PC Sample-based Profiling Extension is implemented and ARMv8.2-PCSample is implemented.

Support for 64-bit atomic reads is IMPLEMENTATION DEFINED. If 64-bit atomic reads are implemented, a 64-bit read of PMPCSR has the same side-effect as a 32-bit read of PMCSR[31:0] followed by a 32-bit read of PMPCSR[63:32], returning the combined value. For example, if the PE is in Debug state then a 64-bit atomic read returns bits[31:0] == 0xFFFFFFFF and bits[63:32] UNKNOWN.

If the OPTIONAL PC Sample-based Profiling Extension is implemented and ARMv8.2-PCSample is not implemented, this register is not implemented and the architecture defines the functionality in EDPCSR.

This register is introduced in ARMv8.2.

Attributes

PMPCSR is a 64-bit register.

Field descriptions

The PMPCSR bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
NSEL00000PC Sample[55:32]
PC Sample[31:0]
313029282726252423222120191817161514131211109876543210

NS, bit [63]

Non-secure state sample. Indicates the Security state that is associated with the most recent PMPCSR sample or, when it is read as a single atomic 64-bit read, the current PMPCSR sample.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

EL, bits [62:61]

Exception level status sample. Indicates the Exception level that is associated with the most recent PMPCSR sample or, when it is read as a single atomic 64-bit read, the current PMPCSR sample.

ELMeaning
00

Sample is from EL0.

01

Sample is from EL1.

10

Sample is from EL2.

11

Sample is from EL3.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bits [60:56]

Reserved, RES0.

PC Sample[55:32], bits [55:32]

Bits[55:32] of the sampled instruction address value. The translation regime that PMPCSR samples can be determined from PMPCSR.{NS,EL}.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

PC Sample[31:0], bits [31:0]

Bits[31:0] of the sampled instruction address value. The translation regime that PMPCSR samples can be determined from PMPCSR.{NS,EL}.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Accessing the PMPCSR

PMPCSR[31:0] can be accessed through the external debug interface:

ComponentOffset
PMU 0x200
PMU 0x220

PMPCSR[63:32] can be accessed through the external debug interface:

ComponentOffset
PMU 0x204
PMU 0x224



02/05/2017 15:43

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