The TLBIALLIS characteristics are:
Invalidate all cached copies of translation table entries from TLBs that are from any level of the translation table walk. The entries that are invalidated are as follows:
The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this instructions.
This System instruction is part of the TLB maintenance instructions functional group.
There are no configuration notes.
TLBIALLIS is a 32-bit System instruction.
TLBIALLIS ignores the value in the register specified by the instruction encoding. Software does not have to write a value to the register before issuing this instruction.
This instruction is executed using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c8, c3, 0 | 000 | 000 | 1000 | 1111 | 0011 |
The instruction is executable as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | WO | n/a | WO |
x | 0 | 1 | - | WO | WO | WO |
x | 1 | 1 | - | n/a | WO | WO |
This table applies to all syntax that can be used to execute this instruction.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when executing this System instruction.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TTLB==1, Non-secure execution of this instruction at EL1 is trapped to EL2.
If HSTR_EL2.T8==1, Non-secure execution of this instruction at EL1 is trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TTLB==1, Non-secure execution of this instruction at EL1 is trapped to EL2.
If HSTR_EL2.T8==1, Non-secure execution of this instruction at EL1 is trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
02/05/2017 15:43
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.