PMUSERENR, Performance Monitors User Enable Register

The PMUSERENR characteristics are:

Purpose

Enables or disables User mode access to the Performance Monitors.

This register is part of the Performance Monitors registers functional group.

Configuration

There is one instance of this register that is used in both Secure and Non-secure states.

AArch32 System register PMUSERENR is architecturally mapped to AArch64 System register PMUSERENR_EL0.

This register is in the Warm reset domain. Some or all RW fields of this register have defined reset values. On a Warm or Cold reset these apply only if the PE resets into an Exception level that is using AArch32. Otherwise, on a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.

Attributes

PMUSERENR is a 32-bit register.

Field descriptions

The PMUSERENR bit assignments are:

313029282726252423222120191817161514131211109876543210
0000000000000000000000000000ERCRSWEN

Bits [31:4]

Reserved, RES0.

ER, bit [3]

Event counter read trap control:

ERMeaning
0

EL0 reads of the PMXEVCNTR and PMEVCNTR<n>, and EL0 read/write access to the PMSELR, are trapped to Undefined mode if PMUSERENR.EN is also 0.

1

This control does not cause any instructions to be trapped.

When this register has an architecturally-defined reset value, this field resets to 0.

CR, bit [2]

Cycle counter read trap control:

CRMeaning
0

EL0 reads of the PMCCNTR are trapped to Undefined mode if PMUSERENR.EN is also 0.

1

This control does not cause any instructions to be trapped.

When this register has an architecturally-defined reset value, this field resets to 0.

SW, bit [1]

Software increment write trap control:

SWMeaning
0

EL0 writes to the PMSWINC are trapped to Undefined mode if PMUSERENR.EN is also 0.

1

This control does not cause any instructions to be trapped.

When this register has an architecturally-defined reset value, this field resets to 0.

EN, bit [0]

Traps EL0 accesses to the Performance Monitors registers to Undefined mode:

ENMeaning
0

EL0 accesses to the Performance Monitors registers are trapped to Undefined mode, unless enabled by one of PMUSERENR.{ER, CR, SW}.

1

This control does not cause any instructions to be trapped. Software can access all PMU registers at EL0.

Note

When this register has an architecturally-defined reset value, this field resets to 0.

Accessing the PMUSERENR

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 0, <Rt>, c9, c14, 0000000100111111110

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0RORW n/a RW
x01RORWRWRW
x11RO n/a RWRW

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :

When EL3 is implemented and is using AArch64 :




02/05/2017 15:43

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