The ID_MMFR1 characteristics are:
Provides information about the implemented memory model and memory management support in AArch32 state.
Must be interpreted with ID_MMFR0, ID_MMFR2, ID_MMFR3, and ID_MMFR4.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section G4.14.6.
This register is part of the Identification registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register ID_MMFR1 is architecturally mapped to AArch64 System register ID_MMFR1_EL1.
ID_MMFR1 is a 32-bit register.
The ID_MMFR1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BPred | L1TstCln | L1Uni | L1Hvd | L1UniSW | L1HvdSW | L1UniVA | L1HvdVA |
Branch Predictor. Indicates branch predictor management requirements. Defined values are:
BPred | Meaning |
---|---|
0000 |
No branch predictor, or no MMU present. Implies a fixed MPU configuration. |
0001 |
Branch predictor requires flushing on: |
0010 |
Branch predictor requires flushing on: |
0011 |
Branch predictor requires flushing only on writing new data to instruction locations. |
0100 |
For execution correctness, branch predictor requires no flushing at any time. |
All other values are reserved.
In ARMv8-A the permitted values are 0010, 0011, or 0100. For values other than 0000 and 0100 the ARM Architecture Reference Manual, or the product documentation, might give more information about the required maintenance.
Level 1 cache Test and Clean. Indicates the supported Level 1 data cache test and clean operations, for Harvard or unified cache implementations. Defined values are:
L1TstCln | Meaning |
---|---|
0000 |
None supported. |
0001 |
Supported Level 1 data cache test and clean operations are:
|
0010 |
As for 0001, and adds:
|
All other values are reserved.
In ARMv8-A the only permitted value is 0000.
Level 1 Unified cache. Indicates the supported entire Level 1 cache maintenance operations for a unified cache implementation. Defined values are:
L1Uni | Meaning |
---|---|
0000 |
None supported. |
0001 |
Supported entire Level 1 cache operations are:
|
0010 |
As for 0001, and adds:
|
All other values are reserved.
In ARMv8-A the only permitted value is 0000.
Level 1 Harvard cache. Indicates the supported entire Level 1 cache maintenance operations for a Harvard cache implementation. Defined values are:
L1Hvd | Meaning |
---|---|
0000 |
None supported. |
0001 |
Supported entire Level 1 cache operations are:
|
0010 |
As for 0001, and adds:
|
0011 |
As for 0010, and adds:
|
All other values are reserved.
In ARMv8-A the only permitted value is 0000.
Level 1 Unified cache by Set/Way. Indicates the supported Level 1 cache line maintenance operations by set/way, for a unified cache implementation. Defined values are:
L1UniSW | Meaning |
---|---|
0000 |
None supported. |
0001 |
Supported Level 1 unified cache line maintenance operations by set/way are:
|
0010 |
As for 0001, and adds:
|
0011 |
As for 0010, and adds:
|
All other values are reserved.
In ARMv8-A the only permitted value is 0000.
Level 1 Harvard cache by Set/Way. Indicates the supported Level 1 cache line maintenance operations by set/way, for a Harvard cache implementation. Defined values are:
L1HvdSW | Meaning |
---|---|
0000 |
None supported. |
0001 |
Supported Level 1 Harvard cache line maintenance operations by set/way are:
|
0010 |
As for 0001, and adds:
|
0011 |
As for 0010, and adds:
|
All other values are reserved.
In ARMv8-A the only permitted value is 0000.
Level 1 Unified cache by Virtual Address. Indicates the supported Level 1 cache line maintenance operations by VA, for a unified cache implementation. Defined values are:
L1UniVA | Meaning |
---|---|
0000 |
None supported. |
0001 |
Supported Level 1 unified cache line maintenance operations by VA are:
|
0010 |
As for 0001, and adds:
|
All other values are reserved.
In ARMv8-A the only permitted value is 0000.
Level 1 Harvard cache by Virtual Address. Indicates the supported Level 1 cache line maintenance operations by VA, for a Harvard cache implementation. Defined values are:
L1HvdVA | Meaning |
---|---|
0000 |
None supported. |
0001 |
Supported Level 1 Harvard cache line maintenance operations by VA are:
|
0010 |
As for 0001, and adds:
|
All other values are reserved.
In ARMv8-A the only permitted value is 0000.
This register can be read using MRC with the following syntax:
MRC <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c0, c1, 5 | 000 | 101 | 0000 | 1111 | 0001 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HSTR_EL2.T0==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HSTR_EL2.T0==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
02/05/2017 15:43
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