The CTIINEN<n> characteristics are:
Enables the signaling of an event on output channels when input trigger event n is received by the CTI.
This register is part of the Cross-Trigger Interface registers functional group.
This register is accessible as follows:
SLK | Default |
---|---|
RO | RW |
CTIINEN<n> is in the Debug power domain. RW fields in this register reset to architecturally UNKNOWN values. These apply only on an External debug reset. The register is not affected by a Warm reset and is not affected by a Cold reset.
If input trigger n is not connected, the behavior of CTIINEN<n> is IMPLEMENTATION DEFINED.
CTIINEN<n> is a 32-bit register.
The CTIINEN<n> bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INEN<x>, bit [x] |
Input trigger <n> to output channel <x> enable.
Bits [31:N] are RAZ/WI. N is the number of ECT channels implemented as defined by the CTIDEVID.NUMCHAN field.
Possible values of this bit are:
INEN<x> | Meaning |
---|---|
0 |
Input trigger <n> will not generate an event on output channel <x>. |
1 |
Input trigger <n> will generate an event on output channel <x>. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
CTIINEN<n> can be accessed through the external debug interface:
Component | Offset |
---|---|
CTI | 0x020 + 4n |
02/05/2017 15:43
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