PMCR_EL0, Performance Monitors Control Register

The PMCR_EL0 characteristics are:

Purpose

Provides details of the Performance Monitors implementation, including the number of counters implemented, and configures and controls the counters.

This register is part of the Performance Monitors registers functional group.

Usage constraints

This register is accessible as follows:

OffDLKOSLKEPMADSLKDefault
ErrorErrorErrorErrorRORW

Configuration

External register PMCR_EL0 bits [6:0] are architecturally mapped to AArch32 System register PMCR[6:0] .

External register PMCR_EL0 bits [6:0] are architecturally mapped to AArch64 System register PMCR_EL0[6:0] .

PMCR_EL0 is in the Core power domain. Some or all RW fields of this register have defined reset values. These apply on a Warm or Cold reset. The register is not affected by an External debug reset.

This register is only partially mapped to the internal PMCR System register. An external agent must use other means to discover the information held in PMCR[31:11], such as accessing PMCFGR and the ID registers.

Attributes

PMCR_EL0 is a 32-bit register.

Field descriptions

The PMCR_EL0 bit assignments are:

313029282726252423222120191817161514131211109876543210
0000000000000000000000000LCDPXDCPE

Bits [31:11]

RAZ/WI. Hardware must implement this field as RAZ/WI. Software must not rely on the register reading as zero, and must use a read-modify-write sequence to write to the register.

Bits [10:7]

Reserved, RES0.

LC, bit [6]

Long cycle counter enable. Determines which PMCCNTR_EL0 bit generates an overflow recorded by PMOVSR[31].

LCMeaning
0

Cycle counter overflow on increment that changes PMCCNTR_EL0[31] from 1 to 0.

1

Cycle counter overflow on increment that changes PMCCNTR_EL0[63] from 1 to 0.

ARM deprecates use of PMCR_EL0.LC = 0.

In an AArch64-only implementation, this field is RES1.

When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to a value that is architecturally UNKNOWN.

DP, bit [5]

Disable cycle counter when event counting is prohibited. The possible values of this bit are:

DPMeaning
0

PMCCNTR_EL0, if enabled, counts when event counting is prohibited.

1

PMCCNTR_EL0 does not count when event counting is prohibited.

Counting events is never prohibited in Non-secure state. However, there are some restrictions on counting events in Secure state. For more information about the interaction between the Performance Monitors and EL3, see 'Interaction with EL3' in the ARMv8 ARM, section D5.5.1.

When EL3 is not implemented, this field is RES0:

Otherwise this field is RW.

When this register has an architecturally-defined reset value, if this field is implemented as an RW field it resets to:

X, bit [4]

Enable export of events in an IMPLEMENTATION DEFINED event stream. The possible values of this bit are:

XMeaning
0

Do not export events.

1

Export events where not prohibited.

This field enables the exporting of events over an event bus to another device, for example to an OPTIONAL trace macrocell. If the implementation does not include such an event bus then this field is RAZ/WI, otherwise it is an RW field.

In an implementation that includes an event bus, no events are exported when counting is prohibited.

This field does not affect the generation of Performance Monitors overflow interrupt requests or signaling to a cross-trigger interface (CTI) that can be implemented as signals exported from the PE.

When this register has an architecturally-defined reset value, if this field is implemented as an RW field it resets to:

D, bit [3]

Clock divider. The possible values of this bit are:

DMeaning
0

When enabled, PMCCNTR_EL0 counts every clock cycle.

1

When enabled, PMCCNTR_EL0 counts once every 64 clock cycles.

In an AArch64-only implementation this field is RES0, otherwise it is an RW field. If PMCR_EL0.LC == 1, this bit is ignored and the cycle counter counts every clock cycle.

ARM deprecates use of PMCR_EL0.D = 1.

When this register has an architecturally-defined reset value, if this field is implemented as an RW field it resets to:

C, bit [2]

Cycle counter reset. This bit is WO. The effects of writing to this bit are:

CMeaning
0

No action.

1

Reset PMCCNTR_EL0 to zero.

This bit is always RAZ.

Resetting PMCCNTR_EL0 does not clear the PMCCNTR_EL0 overflow bit to 0.

P, bit [1]

Event counter reset. This bit is WO. The effects of writing to this bit are:

PMeaning
0

No action.

1

Reset all event counters, not including PMCCNTR_EL0, to zero.

This bit is always RAZ.

Resetting the event counters does not clear any overflow bits to 0.

E, bit [0]

Enable. The possible values of this bit are:

EMeaning
0

All counters, including PMCCNTR_EL0, are disabled.

1

All counters are enabled by PMCNTENSET_EL0.

This bit is RW.

When this register has an architecturally-defined reset value, this field resets to 0.

Accessing the PMCR_EL0

PMCR_EL0 can be accessed through the external debug interface:

ComponentOffset
PMU 0xE04



02/05/2017 15:43

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