GICC_APR<n>, CPU Interface Active Priorities Registers, n = 0 - 3

The GICC_APR<n> characteristics are:

Purpose

Provides information about interrupt active priorities.

This register is part of the GIC physical CPU interface registers functional group.

Usage constraints

This register is accessible as follows:

Security disabledSecureNon-secure
RWRWRW

These registers are used only when System register access is not enabled. When System register access is enabled the following registers provide equivalent functionality:

Configuration

Some or all RW fields of this register have defined reset values.

The contents of these registers are IMPLEMENTATION DEFINED with the one architectural requirement that the value 0x00000000 is consistent with no interrupts being active.

When GICD_CTLR.DS == 0, these registers are Banked, and Non-secure accesses do not affect Secure operation. The Secure copies of these registers hold active priorities for Group 0 interrupts, and the Non-secure copies provide a Non-secure view of the active priorities for Group 1 interrupts.

GICC_APR1 is only implemented in implementations that support 6 or more bits of priority. GICC_APR2 and GICC_APR3 are only implemented in implementations that support 7 bits of priority.

When GICD_CTLR.DS==1, these registers hold the active priorities for Group 0 interrupts, and the active priorities for Group 1 interrupts are held by the GICC_NSAPR<n> registers.

Attributes

GICC_APR<n> is a 32-bit register.

Field descriptions

The GICC_APR<n> bit assignments are:

313029282726252423222120191817161514131211109876543210
IMPLEMENTATION DEFINED

IMPLEMENTATION DEFINED, bits [31:0]

IMPLEMENTATION DEFINED.

When this register has an architecturally-defined reset value, this field resets to 0.

Accessing the GICC_APR<n>

GICC_APR<n> can be accessed through its memory-mapped interface:

ComponentOffset
GIC CPU interface0x00D0 + 4n



02/05/2017 15:43

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