The CNTHCTL characteristics are:
Controls the generation of an event stream from the physical counter, and access from Non-secure EL1 modes to the physical counter and the Non-secure EL1 physical timer.
This register is part of:
AArch32 System register CNTHCTL is architecturally mapped to AArch64 System register CNTHCTL_EL2.
If EL2 is not implemented, this register is RES0 from EL3.
RW fields in this register reset to architecturally UNKNOWN values.
CNTHCTL is a 32-bit register.
The CNTHCTL bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | EVNTI | EVNTDIR | EVNTEN | PL1PCEN | PL1PCTEN |
Reserved, RES0.
Selects which bit (0 to 15) of the counter register CNTPCT is the trigger for the event stream generated from that counter, when that stream is enabled.
Controls which transition of the counter register CNTPCT trigger bit, defined by EVNTI, generates an event when the event stream is enabled:
EVNTDIR | Meaning |
---|---|
0 |
A 0 to 1 transition of the trigger bit triggers an event. |
1 |
A 1 to 0 transition of the trigger bit triggers an event. |
Enables the generation of an event stream from the counter register CNTPCT:
EVNTEN | Meaning |
---|---|
0 |
Disables the event stream. |
1 |
Enables the event stream. |
Traps Non-secure EL0 and EL1 accesses to the physical timer registers to Hyp mode.
PL1PCEN | Meaning |
---|---|
0 |
Non-secure EL0 and EL1 accesses to the CNTP_CTL, CNTP_CVAL, and CNTP_TVAL are trapped to Hyp mode, unless the it is trapped by CNTKCTL.PL0PTEN. |
1 |
This control does not cause any instructions to be trapped. |
If EL3 is implemented and EL2 is not implemented, behavior is as if this bit is 1 other than for the purpose of a direct read.
Traps Non-secure EL0 and EL1 accesses to the physical counter register to Hyp mode.
PL1PCTEN | Meaning |
---|---|
0 |
Non-secure EL0 and EL1 accesses to the CNTPCT are trapped to Hyp mode, unless it is trapped by CNTKCTL.PL0PCTEN. |
1 |
This control does not cause any instructions to be trapped. |
If EL3 is implemented and EL2 is not implemented, behavior is as if this bit is 1 other than for the purpose of a direct read.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 4, <Rt>, c14, c1, 0 | 100 | 000 | 1110 | 1111 | 0001 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | - | n/a | - |
x | 0 | 1 | - | - | RW | RW |
x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
02/05/2017 15:43
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