The DC ZVA characteristics are:
Zero data cache by address. Zeroes a naturally aligned block of N bytes, where the size of N is identified in DCZID_EL0.
This System instruction is part of the Cache maintenance instructions functional group.
There are no configuration notes.
DC ZVA is a 64-bit System instruction.
The DC ZVA input value bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
Virtual address to use | |||||||||||||||||||||||||||||||
Virtual address to use | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Virtual address to use. There is no alignment restriction on the address within the block of N bytes that is used.
This instruction is executed using DC with the following syntax:
DC <dc_op>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<dc_op> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
ZVA | 01 | 011 | 0111 | 0100 | 001 |
When this instruction is executed, it can generate memory faults or watchpoints which are prioritized in the same way as other memory-related faults or watchpoints. If a synchronous data abort fault or a watchpoint is generated, the CM bit in the ESR_ELx.ISS field is not set.
If the memory region being zeroed is any type of Device memory, this instruction can give an alignment fault which is prioritized in the same way as other alignment faults that are determined by the memory type.
This instruction applies to Normal memory regardless of cacheability attributes.
This instruction behaves as a set of Stores to each byte within the block being accessed, and so it:
The instruction is executable as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | WO | WO | n/a | WO |
x | 0 | 1 | WO | WO | WO | WO |
x | 1 | 1 | WO | n/a | WO | WO |
This table applies to all syntax that can be used to execute this instruction.
When EL0 access is disabled (SCTLR_EL1.DZE is set to 0) and HCR_EL2.TDZ is set to 1, execution of this instruction at EL0 is UNDEFINED.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when executing this System instruction.
In both Security states, and not dependent on other configuration bits:
If SCTLR_EL1.DZE==0, execution of this instruction at EL0 is trapped to EL1.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TDZ==1, Non-secure execution of this instruction at EL0 and EL1 is trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TDZ==1, Non-secure execution of this instruction at EL0 and EL1 is trapped to EL2.
02/05/2017 15:43
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