ICC_CTLR_EL1, Interrupt Controller Control Register (EL1)

The ICC_CTLR_EL1 characteristics are:

Purpose

Controls aspects of the behavior of the GIC CPU interface and provides information about the features implemented.

This register is part of:

Configuration

AArch64 System register ICC_CTLR_EL1 (S) is architecturally mapped to AArch32 System register ICC_CTLR (S) .

AArch64 System register ICC_CTLR_EL1 (NS) is architecturally mapped to AArch32 System register ICC_CTLR (NS) .

Attributes

ICC_CTLR_EL1 is a 32-bit register.

Field descriptions

The ICC_CTLR_EL1 bit assignments are:

313029282726252423222120191817161514131211109876543210
0000000000000000A3VSEISIDbitsPRIbits0PMHE0000EOImodeCBPR

Bits [31:16]

Reserved, RES0.

A3V, bit [15]

Affinity 3 Valid. Read-only and writes are ignored. Possible values are:

A3VMeaning
0

The CPU interface logic only supports zero values of Affinity 3 in SGI generation System registers.

1

The CPU interface logic supports non-zero values of Affinity 3 in SGI generation System registers.

If EL3 is implemented, this bit is an alias of ICC_CTLR_EL3.A3V.

SEIS, bit [14]

SEI Support. Read-only and writes are ignored. Indicates whether the CPU interface supports local generation of SEIs:

SEISMeaning
0

The CPU interface logic does not support local generation of SEIs.

1

The CPU interface logic supports local generation of SEIs.

If EL3 is implemented, this bit is an alias of ICC_CTLR_EL3.SEIS.

IDbits, bits [13:11]

Identifier bits. Read-only and writes are ignored. The number of physical interrupt identifier bits supported:

IDbitsMeaning
000

16 bits.

001

24 bits.

All other values are reserved.

If EL3 is implemented, this field is an alias of ICC_CTLR_EL3.IDbits.

PRIbits, bits [10:8]

Priority bits. Read-only and writes are ignored. The number of priority bits implemented, minus one.

An implementation that supports two Security states must implement at least 32 levels of physical priority (5 priority bits).

An implementation that supports only a single Security state must implement at least 16 levels of physical priority (4 priority bits).

Note

This field always returns the number of priority bits implemented, regardless of the Security state of the access or the value of GICD_CTLR.DS.

For physical accesses, this field determines the minimum value of ICC_BPR0_EL1.

If EL3 is implemented, physical accesses return the value from ICC_CTLR_EL3.PRIbits.

If EL3 is not implemented, physical accesses return the value from this field.

Bit [7]

Reserved, RES0.

PMHE, bit [6]

Priority Mask Hint Enable. Controls whether the priority mask register is used as a hint for interrupt distribution:

PMHEMeaning
0

Disables use of ICC_PMR_EL1 as a hint for interrupt distribution.

1

Enables use of ICC_PMR_EL1 as a hint for interrupt distribution.

If EL3 is implemented, this bit is an alias of ICC_CTLR_EL3.PMHE. Whether this bit can be written as part of an access to this register depends on the value of GICD_CTLR.DS:

If EL3 is not implemented, it is IMPLEMENTATION DEFINED whether this bit is read-only or read-write:

Bits [5:2]

Reserved, RES0.

EOImode, bit [1]

EOI mode for the current Security state. Controls whether a write to an End of Interrupt register also deactivates the interrupt:

EOImodeMeaning
0

ICC_EOIR0_EL1 and ICC_EOIR1_EL1 provide both priority drop and interrupt deactivation functionality. Accesses to ICC_DIR_EL1 are UNPREDICTABLE.

1

ICC_EOIR0_EL1 and ICC_EOIR1_EL1 provide priority drop functionality only. ICC_DIR_EL1 provides interrupt deactivation functionality.

The Secure ICC_CTLR_EL1.EOIMode is an alias of ICC_CTLR_EL3.EOImode_EL1S.

The Non-secure ICC_CTLR_EL1.EOIMode is an alias of ICC_CTLR_EL3.EOImode_EL1NS

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

CBPR, bit [0]

Common Binary Point Register. Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 interrupts:

CBPRMeaning
0

ICC_BPR0_EL1 determines the preemption group for Group 0 interrupts only.

ICC_BPR1_EL1 determines the preemption group for Group 1 interrupts.

1

ICC_BPR0_EL1 determines the preemption group for both Group 0 and Group 1 interrupts.

If EL3 is implemented:

If EL3 is not implemented, this bit is read/write.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Accessing the ICC_CTLR_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op1CRnCRmop2
ICC_CTLR_EL100011001100100

When HCR_EL2.{FMO, IMO} != {0, 0}, execution of this encoding at Non-secure EL1 results in an access to ICV_CTLR_EL1.

Accessibility

The register is accessible as follows:

Control Accessibility Instance
FMOIMOTGENSEL0EL1EL2EL3
xx11 - n/a RWRWICC_CTLR_EL1_ns
x101 - ICV_CTLR_EL1 RWRWICC_CTLR_EL1_ns
1x01 - ICV_CTLR_EL1 RWRWICC_CTLR_EL1_ns
0001 - RWRWRWICC_CTLR_EL1_ns
xxx0 - RW n/a RWICC_CTLR_EL1_s

This table applies to all instructions that can access this register.

ICC_CTLR_EL1 is only accessible at Non-secure EL1 when HCR_EL2.{FMO, IMO} == {0, 0}.

Note

When HCR_EL2.{FMO, IMO} != {0, 0}, at Non-secure EL1, the instruction encoding used to access ICC_CTLR_EL1 results in an access to ICV_CTLR_EL1.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When SCR_EL3.NS==1 :

When EL3 is implemented and is using AArch64 and SCR_EL3.NS==0 :

When EL3 is implemented and is using AArch64 :

When EL3 is implemented and is using AArch64 and SCR_EL3.NS==1 :




02/05/2017 15:43

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