ICV_EOIR1_EL1, Interrupt Controller Virtual End Of Interrupt Register 1

The ICV_EOIR1_EL1 characteristics are:

Purpose

A PE writes to this register to inform the CPU interface that it has completed the processing of the specified virtual Group 1 interrupt.

This register is part of:

Configuration

AArch64 System register ICV_EOIR1_EL1 performs the same function as AArch32 System register ICV_EOIR1.

Attributes

ICV_EOIR1_EL1 is a 32-bit register.

Field descriptions

The ICV_EOIR1_EL1 bit assignments are:

313029282726252423222120191817161514131211109876543210
00000000INTID

Bits [31:24]

Reserved, RES0.

INTID, bits [23:0]

The INTID from the corresponding ICV_IAR1_EL1 access.

This field has either 16 or 24 bits implemented. The number of implemented bits can be found in ICV_CTLR_EL1.IDbits. If only 16 bits are implemented, bits [23:16] of this register are RES0.

If the ICV_CTLR.EOImode bit is 0, a write to this register drops the priority for the virtual interrupt, and also deactivates the virtual interrupt.

If the ICV_CTLR.EOImode bit is 1, a write to this register only drops the priority for the virtual interrupt. Software must write to ICV_DIR_EL1 to deactivate the virtual interrupt.

Accessing the ICV_EOIR1_EL1

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op1CRnCRmop2
ICC_EOIR1_EL100011001100001

When HCR_EL2.IMO is set to 0, execution of this encoding at Non-secure EL1 results in an access to ICC_EOIR1_EL1.

Accessibility

The register is accessible as follows:

Control Accessibility
FMOIMOTGENSEL0EL1EL2EL3
xxx0 - ICC_EOIR1_EL1 n/a ICC_EOIR1_EL1
xx11 - n/a ICC_EOIR1_EL1 ICC_EOIR1_EL1
x001 - ICC_EOIR1_EL1 ICC_EOIR1_EL1 ICC_EOIR1_EL1
x101 - WO ICC_EOIR1_EL1 ICC_EOIR1_EL1

This table applies to all instructions that can access this register.

ICV_EOIR1_EL1 is only accessible at Non-secure EL1 when HCR_EL2.IMO is set to 1.

Note

When HCR_EL2.IMO is set to 0, at Non-secure EL1, the instruction encoding used to access ICV_EOIR1_EL1 results in an access to ICC_EOIR1_EL1.

A write to this register must correspond to the most recent valid read by this vPE from a Virtual Interrupt Acknowledge Register, and must correspond to the INTID that was read from ICV_IAR1_EL1, otherwise the system behavior is UNPREDICTABLE. A valid read is a read that returns a valid INTID that is not a special INTID.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When SCR_EL3.NS==1 :




02/05/2017 15:43

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