The ICC_HPPIR0 characteristics are:
Indicates the highest priority pending Group 0 interrupt on the CPU interface.
This register is part of:
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register ICC_HPPIR0 performs the same function as AArch64 System register ICC_HPPIR0_EL1.
ICC_HPPIR0 is a 32-bit register.
The ICC_HPPIR0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | INTID |
Reserved, RES0.
The INTID of the highest priority pending interrupt, if that interrupt is observable at the current Security state and Exception level.
If the highest priority pending interrupt is not observable, this field contains a special INTID to indicate the reason. These special INTIDs can be one of: 1020, 1021, or 1023. See Special INTIDs, for more information.
This field has either 16 or 24 bits implemented. The number of implemented bits can be found in ICC_CTLR.IDbits and ICC_MCTLR.IDbits. If only 16 bits are implemented, bits [23:16] of this register are RES0.
This register can be read using MRC with the following syntax:
MRC <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c12, c8, 2 | 000 | 010 | 1100 | 1111 | 1000 |
When HCR.FMO is set to 1, execution of this encoding at Non-secure EL1 results in an access to ICV_HPPIR0.
The register is accessible as follows:
Control | Accessibility | ||||||
---|---|---|---|---|---|---|---|
FMO | IMO | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | x | 0 | - | RO | n/a | RO |
x | x | 1 | 1 | - | n/a | RO | RO |
0 | x | 0 | 1 | - | RO | RO | RO |
1 | x | 0 | 1 | - | ICV_HPPIR0 | RO | RO |
This table applies to all instructions that can access this register.
ICC_HPPIR0 is only accessible at Non-secure EL1 when HCR.FMO is set to 0.
When HCR.FMO is set to 1, at Non-secure EL1, the instruction encoding used to access ICC_HPPIR0 results in an access to ICV_HPPIR0.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_SRE.SRE==0, read accesses to this register from EL1 are UNDEFINED.
If ICC_HSRE.SRE==0, read accesses to this register from EL2 are UNDEFINED.
If ICC_MSRE.SRE==0, read accesses to this register from EL3 are UNDEFINED.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==0 :
If HSTR_EL2.T12==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T12==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HSTR.T12==1, Non-secure read accesses to this register from EL1 are trapped to Hyp mode.
When SCR_EL3.NS==1 :
If ICH_HCR.TALL0==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If ICH_HCR_EL2.TALL0==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL3 is implemented and is using AArch32 :
If SCR.FIQ==1, and EL3 is implemented and configured to use AArch32, read accesses to this register from EL2 and EL3 modes other than Monitor mode are UNDEFINED.
When EL3 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If SCR.FIQ==1, and HCR.FMO==0, and EL2 is implemented and configured to use AArch32, Non-secure read accesses to this register from EL1 are UNDEFINED.
When EL3 is implemented and is using AArch64 and SCR_EL3.NS==0 :
If SCR_EL3.FIQ==1, and EL3 is implemented and configured to use AArch64, Secure read accesses to this register from EL1 are trapped to EL3.
When EL3 is implemented and is using AArch64 :
If SCR_EL3.FIQ==1, and EL3 is implemented and configured to use AArch64, read accesses to this register from EL2 are trapped to EL3.
When EL3 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If SCR_EL3.FIQ==1, and HCR.FMO==0, and EL3 is implemented and configured to use AArch64 and EL2 is implemented and configured to use AArch32, Non-secure read accesses to this register from EL1 are trapped to EL3.
If SCR_EL3.FIQ==1, and HCR_EL2.FMO==0, and EL2 is implemented and configured to use AArch64, Non-secure read accesses to this register from EL1 are trapped to EL3.
02/05/2017 15:43
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