AT S12E0R: Address Translate Stages 1 and 2 EL0 Read
AT S12E0W: Address Translate Stages 1 and 2 EL0 Write
AT S12E1R: Address Translate Stages 1 and 2 EL1 Read
AT S12E1W: Address Translate Stages 1 and 2 EL1 Write
AT S1E0R: Address Translate Stage 1 EL0 Read
AT S1E0W: Address Translate Stage 1 EL0 Write
AT S1E1R: Address Translate Stage 1 EL1 Read
AT S1E1RP: Address Translate Stage 1 EL1 Read PAN
AT S1E1W: Address Translate Stage 1 EL1 Write
AT S1E1WP: Address Translate Stage 1 EL1 Write PAN
AT S1E2R: Address Translate Stage 1 EL2 Read
AT S1E2W: Address Translate Stage 1 EL2 Write
AT S1E3R: Address Translate Stage 1 EL3 Read
AT S1E3W: Address Translate Stage 1 EL3 Write
DC CISW: Data or unified Cache line Clean and Invalidate by Set/Way
DC CIVAC: Data or unified Cache line Clean and Invalidate by VA to PoC
DC CSW: Data or unified Cache line Clean by Set/Way
DC CVAC: Data or unified Cache line Clean by VA to PoC
DC CVAP: Data or unified Cache line Clean by VA to PoP
DC CVAU: Data or unified Cache line Clean by VA to PoU
DC ISW: Data or unified Cache line Invalidate by Set/Way
DC IVAC: Data or unified Cache line Invalidate by VA to PoC
DC ZVA: Data Cache Zero by VA
IC IALLU: Instruction Cache Invalidate All to PoU
IC IALLUIS: Instruction Cache Invalidate All to PoU, Inner Shareable
IC IVAU: Instruction Cache line Invalidate by VA to PoU
S1_<op1>_<Cn>_<Cm>_<op2>: IMPLEMENTATION DEFINED maintenance instructions
TLBI ALLE1: TLB Invalidate All, EL1
TLBI ALLE1IS: TLB Invalidate All, EL1, Inner Shareable
TLBI ALLE2: TLB Invalidate All, EL2
TLBI ALLE2IS: TLB Invalidate All, EL2, Inner Shareable
TLBI ALLE3: TLB Invalidate All, EL3
TLBI ALLE3IS: TLB Invalidate All, EL3, Inner Shareable
TLBI ASIDE1: TLB Invalidate by ASID, EL1
TLBI ASIDE1IS: TLB Invalidate by ASID, EL1, Inner Shareable
TLBI IPAS2E1: TLB Invalidate by Intermediate Physical Address, Stage 2, EL1
TLBI IPAS2E1IS: TLB Invalidate by Intermediate Physical Address, Stage 2, EL1, Inner Shareable
TLBI IPAS2LE1: TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1
TLBI IPAS2LE1IS: TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Inner Shareable
TLBI VAAE1: TLB Invalidate by VA, All ASID, EL1
TLBI VAAE1IS: TLB Invalidate by VA, All ASID, EL1, Inner Shareable
TLBI VAALE1: TLB Invalidate by VA, All ASID, Last level, EL1
TLBI VAALE1IS: TLB Invalidate by VA, All ASID, EL1, Last Level, Inner Shareable
TLBI VAE1: TLB Invalidate by VA, EL1
TLBI VAE1IS: TLB Invalidate by VA, EL1, Inner Shareable
TLBI VAE2: TLB Invalidate by VA, EL2
TLBI VAE2IS: TLB Invalidate by VA, EL2, Inner Shareable
TLBI VAE3: TLB Invalidate by VA, EL3
TLBI VAE3IS: TLB Invalidate by VA, EL3, Inner Shareable
TLBI VALE1: TLB Invalidate by VA, Last level, EL1
TLBI VALE1IS: TLB Invalidate by VA, Last level, EL1, Inner Shareable
TLBI VALE2: TLB Invalidate by VA, Last level, EL2
TLBI VALE2IS: TLB Invalidate by VA, Last level, EL2, Inner Shareable
TLBI VALE3: TLB Invalidate by VA, Last level, EL3
TLBI VALE3IS: TLB Invalidate by VA, Last level, EL3, Inner Shareable
TLBI VMALLE1: TLB Invalidate by VMID, All at stage 1, EL1
TLBI VMALLE1IS: TLB Invalidate by VMID, All at stage 1, EL1, Inner Shareable
TLBI VMALLS12E1: TLB Invalidate by VMID, All at Stage 1 and 2, EL1
TLBI VMALLS12E1IS: TLB Invalidate by VMID, All at Stage 1 and 2, EL1, Inner Shareable
02/05/2017 15:43
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