The ICC_BPR1 characteristics are:
Defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field. The group priority field determines Group 1 interrupt preemption.
This register is part of:
AArch32 System register ICC_BPR1 (S) is architecturally mapped to AArch64 System register ICC_BPR1_EL1 (S) .
AArch32 System register ICC_BPR1 (NS) is architecturally mapped to AArch64 System register ICC_BPR1_EL1 (NS) .
In GIC implementations supporting two Security states, this register is Banked.
ICC_BPR1 is a 32-bit register.
The ICC_BPR1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | BinaryPoint |
Reserved, RES0.
If the GIC is configured to use separate binary point fields for Group 0 and Group 1 interrupts, the value of this field controls how the 8-bit interrupt priority field is split into a group priority field, that determines interrupt preemption, and a subpriority field. For more information about priorities, see Priority grouping.
Writing 0 to this field will set this field to its reset value, which is IMPLEMENTATION DEFINED and non-zero.
If EL3 is implemented and ICC_MCTLR.CBPR_EL1S is 1:
If EL3 is implemented and ICC_MCTLR.CBPR_EL1NS is 1, Non-secure accesses to this register at EL1 or EL2 behave as follows, depending on the values of HCR.IMO and SCR.IRQ:
HCR.IMO | SCR.IRQ | Behavior |
---|---|---|
0 | 0 | Non-secure EL1 and EL2 reads return ICC_BPR0 + 1 saturated to 0b111. Non-secure EL1 and EL2 writes are ignored. |
0 | 1 | Non-secure EL1 and EL2 accesses trap to EL3. |
1 | 0 | Non-secure EL1 accesses affect virtual interrupts. Non-secure EL2 reads return ICC_BPR0 + 1 saturated to 0b111. Non-secure EL2 writes are ignored. |
1 | 1 | Non-secure EL1 accesses affect virtual interrupts. Non-secure EL2 accesses trap to EL3. |
If EL3 is not implemented and ICC_CTLR.CBPR is 1, Non-secure accesses to this register at EL1 or EL2 behave as follows, depending on the values of HCR.IMO:
HCR.IMO | Behavior |
---|---|
0 | Non-secure EL1 and EL2 reads return ICC_BPR0 + 1 saturated to 0b111. Non-secure EL1 and EL2 writes are ignored. |
1 | Non-secure EL1 accesses affect virtual interrupts. Non-secure EL2 reads return ICC_BPR0 + 1 saturated to 0b111. Non-secure EL2 writes are ignored. |
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c12, c12, 3 | 000 | 011 | 1100 | 1111 | 1100 |
When HCR.IMO is set to 1, execution of this encoding at Non-secure EL1 results in an access to ICV_BPR1.
The register is accessible as follows:
Configuration | Control | Accessibility | Instance | ||||||
---|---|---|---|---|---|---|---|---|---|
FMO | IMO | TGE | NS | EL0 | EL1 | EL2 | EL3 | ||
EL3 not implemented | x | x | x | 0 | - | RW | n/a | n/a | ICC_BPR1 |
EL3 not implemented | x | x | 1 | 1 | - | n/a | RW | n/a | ICC_BPR1 |
EL3 not implemented | x | 0 | 0 | 1 | - | RW | RW | n/a | ICC_BPR1 |
EL3 not implemented | x | 1 | 0 | 1 | - | ICV_BPR1 | RW | n/a | ICC_BPR1 |
EL3 using AArch64 | x | x | 1 | 1 | - | n/a | RW | n/a | ICC_BPR1_ns |
EL3 using AArch64 | x | 0 | 0 | 1 | - | RW | RW | n/a | ICC_BPR1_ns |
EL3 using AArch64 | x | 1 | 0 | 1 | - | ICV_BPR1 | RW | n/a | ICC_BPR1_ns |
EL3 using AArch32 | x | x | 1 | 1 | - | n/a | RW | RW | ICC_BPR1_ns |
EL3 using AArch32 | x | 0 | 0 | 1 | - | RW | RW | RW | ICC_BPR1_ns |
EL3 using AArch32 | x | 1 | 0 | 1 | - | ICV_BPR1 | RW | RW | ICC_BPR1_ns |
EL3 using AArch64 | x | x | x | 0 | - | RW | n/a | n/a | ICC_BPR1_s |
EL3 using AArch32 | x | x | x | 0 | - | - | - | RW | ICC_BPR1_s |
This table applies to all instructions that can access this register.
ICC_BPR1 is only accessible at Non-secure EL1 when HCR.IMO is set to 0.
When HCR.IMO is set to 1, at Non-secure EL1, the instruction encoding used to access ICC_BPR1 results in an access to ICV_BPR1.
When the PE resets into an Exception level that is using AArch32, the reset value is equal to:
Where the minimum value of ICC_BPR0 is IMPLEMENTATION DEFINED.
If EL3 is not implemented:
An attempt to program the binary point field to a value less than the reset value sets the field to the reset value.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_SRE.SRE==0, accesses to this register from EL1 are UNDEFINED.
If ICC_HSRE.SRE==0, accesses to this register from EL2 are UNDEFINED.
If ICC_MSRE.SRE==0, accesses to this register from EL3 are UNDEFINED.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==0 :
If HSTR_EL2.T12==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T12==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HSTR.T12==1, Non-secure accesses to this register from EL1 are trapped to Hyp mode.
When SCR_EL3.NS==1 :
If ICH_HCR.TALL1==1, Non-secure accesses to this register from EL1 are trapped to EL2.
If ICH_HCR_EL2.TALL1==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL3 is implemented and is using AArch32 :
If SCR.IRQ==1, accesses to this register from EL2 and EL3 modes other than Monitor mode are UNDEFINED.
When EL3 is implemented and is using AArch32 and SCR_EL3.NS==1 :
When EL3 is implemented and is using AArch64 and SCR_EL3.NS==0 :
If SCR_EL3.IRQ==1, Secure accesses to this register from EL1 are trapped to EL3.
When EL3 is implemented and is using AArch64 :
If SCR_EL3.IRQ==1, accesses to this register from EL2 are trapped to EL3.
When EL3 is implemented and is using AArch64 and SCR_EL3.NS==1 :
02/05/2017 15:43
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