The RVBAR characteristics are:
If EL3 is not implemented, contains the IMPLEMENTATION DEFINED address that execution starts from after reset when executing in AArch32 state.
This register is part of the Reset management registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
This register is only implemented if the highest Exception level implemented is capable of using AArch32, and is not EL3.
RVBAR is a 32-bit register.
The RVBAR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset Address[31:1] | 1 |
Reset Address[31:1]. Bits [31:1] of the IMPLEMENTATION DEFINED address that execution starts from after reset when executing in 32-bit state.
Reserved, RES1.
This register can be read using MRC with the following syntax:
MRC <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c12, c0, 1 | 000 | 001 | 1100 | 1111 | 0000 |
The register is accessible as follows:
Configuration | Control | Accessibility | |||||
---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | |
EL1 is the highest implemented Exception level | x | x | x | - | RO | n/a | n/a |
EL2 is the highest implemented Exception level | x | 0 | 1 | - | - | RO | n/a |
EL2 is the highest implemented Exception level | x | 1 | 1 | - | n/a | RO | n/a |
EL3 is the highest implemented Exception level | x | x | 0 | - | - | n/a | - |
EL3 is the highest implemented Exception level | x | 0 | 1 | - | - | - | - |
EL3 is the highest implemented Exception level | x | 1 | 1 | - | n/a | - | - |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HSTR_EL2.T12==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T12==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HSTR.T12==1, Non-secure accesses to this register from EL1 are trapped to Hyp mode.
02/05/2017 15:43
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