The VTCR characteristics are:
The control register for stage 2 of the Non-secure PL1&0 translation regime.
This stage of translation always uses the Long-descriptor translation table format.
This register is part of:
AArch32 System register VTCR is architecturally mapped to AArch64 System register VTCR_EL2.
If EL2 is not implemented, this register is RES0 from EL3.
RW fields in this register reset to architecturally UNKNOWN values.
VTCR is a 32-bit register.
The VTCR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 0 | 0 | HWU62 | HWU61 | HWU60 | HWU59 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SH0 | ORGN0 | IRGN0 | SL0 | 0 | S | T0SZ |
Reserved, RES1.
Reserved, RES0.
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[62] of the stage 2 translation table block or level 3 entry.
Defined values are:
HWU62 | Meaning |
---|---|
0 |
The stage 2 translation table entry block or level 3 entry cannot be interpreted by hardware for an IMPLEMENTATION DEFINED purpose. |
1 |
The stage 2 translation table entry block or level 3 entry can be interpreted by hardware for an IMPLEMENTATION DEFINED purpose. |
This bit is RES0 if ARMv8.2-TTPBHA is not implemented.
Reserved, RES0.
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[61] of the stage 2 translation table block or level 3 entry.
Defined values are:
HWU61 | Meaning |
---|---|
0 |
The stage 2 translation table entry block or level 3 entry cannot be interpreted by hardware for an IMPLEMENTATION DEFINED purpose. |
1 |
The stage 2 translation table entry block or level 3 entry can be interpreted by hardware for an IMPLEMENTATION DEFINED purpose. |
This bit is RES0 if ARMv8.2-TTPBHA is not implemented.
Reserved, RES0.
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[60] of the stage 2 translation table block or level 3 entry.
Defined values are:
HWU60 | Meaning |
---|---|
0 |
The stage 2 translation table entry block or level 3 entry cannot be interpreted by hardware for an IMPLEMENTATION DEFINED purpose. |
1 |
The stage 2 translation table entry block or level 3 entry can be interpreted by hardware for an IMPLEMENTATION DEFINED purpose. |
This bit is RES0 if ARMv8.2-TTPBHA is not implemented.
Reserved, RES0.
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[59] of the stage 2 translation table block or level 3 entry.
Defined values are:
HWU59 | Meaning |
---|---|
0 |
The stage 2 translation table entry block or level 3 entry cannot be interpreted by hardware for an IMPLEMENTATION DEFINED purpose. |
1 |
The stage 2 translation table entry block or level 3 entry can be interpreted by hardware for an IMPLEMENTATION DEFINED purpose. |
This bit is RES0 if ARMv8.2-TTPBHA is not implemented.
Reserved, RES0.
Reserved, RES0.
Shareability attribute for memory associated with translation table walks using VTTBR.
SH0 | Meaning |
---|---|
00 |
Non-shareable |
10 |
Outer Shareable |
11 |
Inner Shareable |
Other values are reserved. The effect of programming this field to a Reserved value is that behavior is CONSTRAINED UNPREDICTABLE, as described in 'Unallocated values in fields of AArch32 System registers and translation table entries' in the ARM ARM, section K1.1.11.
Outer cacheability attribute for memory associated with translation table walks using VTTBR.
ORGN0 | Meaning |
---|---|
00 |
Normal memory, Outer Non-cacheable |
01 |
Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable |
10 |
Normal memory, Outer Write-Through Read-Allocate No Write-Allocate Cacheable |
11 |
Normal memory, Outer Write-Back Read-Allocate No Write-Allocate Cacheable |
Inner cacheability attribute for memory associated with translation table walks using VTTBR.
IRGN0 | Meaning |
---|---|
00 |
Normal memory, Inner Non-cacheable |
01 |
Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable |
10 |
Normal memory, Inner Write-Through Read-Allocate No Write-Allocate Cacheable |
11 |
Normal memory, Inner Write-Back Read-Allocate No Write-Allocate Cacheable |
Starting level for translation table walks using VTTBR.
SL0 | Meaning |
---|---|
00 |
Start at level 2 |
01 |
Start at level 1 |
All other values are reserved. If this field is programmed to a reserved value, or to a value that is not consistent with the programming of T0SZ, then a stage 2 level 1 Translation fault is generated.
Reserved, RES0.
Sign extension bit. This bit must be programmed to the value of T0SZ[3]. If it is not, then the behavior is CONSTRAINED UNPREDICTABLE and the stage 2 T0SZ value is treated as an UNKNOWN value, see 'Misprogramming VTCR.S' in the ARM ARM.
The size offset of the memory region addressed by VTTBR. The region size is 2(32-T0SZ) bytes.
This field holds a four-bit signed integer value, meaning it supports values from -8 to 7.
This is different from the other translation control registers, where TnSZ holds a three-bit unsigned integer, supporting values from 0 to 7.
If this field is programmed to a value that is not consistent with the programming of SL0 then a stage 2 level 1 Translation fault is generated.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 4, <Rt>, c2, c1, 2 | 100 | 010 | 0010 | 1111 | 0001 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | - | n/a | - |
x | 0 | 1 | - | - | RW | RW |
x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HSTR_EL2.T2==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T2==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HSTR.T2==1, Non-secure accesses to this register from EL1 are trapped to Hyp mode.
02/05/2017 15:43
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