TCR_EL1, Translation Control Register (EL1)

The TCR_EL1 characteristics are:

Purpose

The control register for stage 1 of the EL1&0 translation regime.

This register is part of the Virtual memory control registers functional group.

Configuration

AArch64 System register TCR_EL1 bits [31:0] are architecturally mapped to AArch32 System register TTBCR.

AArch64 System register TCR_EL1 bits [63:32] are architecturally mapped to AArch32 System register TTBCR2.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

TCR_EL1 is a 64-bit register.

Field descriptions

The TCR_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
000000000NFD1NFD000HWU162HWU161HWU160HWU159HWU062HWU061HWU060HWU059HPD1HPD0HDHATBI1TBI0AS0IPS
TG1SH1ORGN1IRGN1EPD1A1T1SZTG0SH0ORGN0IRGN0EPD00T0SZ
313029282726252423222120191817161514131211109876543210

Any of the bits in TCR_EL1 are permitted to be cached in a TLB.

Bits [63:55]

Reserved, RES0.

NFD1, bit [54]
In ARMv8.2:

Present only if SVE is implemented.

Non-fault translation table walk disable for translations using TTBR1_EL1.

This bit controls whether to perform a translation table walk in response to an SVE non-fault access for an address that is translated using TTBR1_EL1. The affected access types are:

See 'The Scalable Vector Extension (SVE)', in the ARM ARM, chapter A1 for more information.

Defined values are:

NFD1Meaning
0

Perform translation table walks using TTBR1_EL1.

1

A TLB miss on an address that is translated using TTBR1_EL1 due to an SVE non-fault access generates a Translation fault. No translation table walk is performed.

If SVE is not implemented, this field is RES0.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

NFD0, bit [53]
In ARMv8.2:

Present only if SVE is implemented.

Non-fault translation table walk disable for translations using TTBR0_EL1.

This bit controls whether to perform a translation table walk in response to an SVE non-fault access for an address that is translated using TTBR0_EL1. The affected access types are:

See 'The Scalable Vector Extension (SVE)', in the ARM ARM, chapter A1 for more information.

Defined values are:

NFD0Meaning
0

Perform translation table walks using TTBR0_EL1.

1

A TLB miss on an address that is translated using TTBR0_EL1 due to an SVE non-fault access generates a Translation fault. No translation table walk is performed.

If SVE is not implemented, this field is RES0.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

Bits [52:51]

Reserved, RES0.

HWU162, bit [50]
In ARMv8.2:

Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[62] of the stage 1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1 if the TCR_EL1.HPD1 value is 1.

Defined values are:

HWU162Meaning
0

The stage 1 translation table entry block or level 3 bit cannot be interpreted by hardware for an IMPLEMENTATION DEFINED purpose.

1

The stage 1 translation table entry block or level 3 bit can be interpreted by hardware for an IMPLEMENTATION DEFINED purpose if the TCR_EL1.HPD1 value is 1.

This bit is RES0 if ARMv8.2-TTPBHA is not implemented.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

HWU161, bit [49]
In ARMv8.2:

Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[61] of the stage 1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1 if the TCR_EL1.HPD1 value is 1.

Defined values are:

HWU161Meaning
0

The stage 1 translation table entry block or level 3 bit cannot be interpreted by hardware for an IMPLEMENTATION DEFINED purpose.

1

The stage 1 translation table entry block or level 3 bit can be interpreted by hardware for an IMPLEMENTATION DEFINED purpose if the TCR_EL1.HPD1 value is 1.

This bit is RES0 if ARMv8.2-TTPBHA is not implemented.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

HWU160, bit [48]
In ARMv8.2:

Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[60] of the stage 1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1 if the TCR_EL1.HPD1 value is 1.

Defined values are:

HWU160Meaning
0

The stage 1 translation table entry block or level 3 bit cannot be interpreted by hardware for an IMPLEMENTATION DEFINED purpose.

1

The stage 1 translation table entry block or level 3 bit can be interpreted by hardware for an IMPLEMENTATION DEFINED purpose if the TCR_EL1.HPD1 value is 1.

This bit is RES0 if ARMv8.2-TTPBHA is not implemented.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

HWU159, bit [47]
In ARMv8.2:

Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[59] of the stage 1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1 if the TCR_EL1.HPD1 value is 1.

Defined values are:

HWU159Meaning
0

The stage 1 translation table entry block or level 3 bit cannot be interpreted by hardware for an IMPLEMENTATION DEFINED purpose.

1

The stage 1 translation table entry block or level 3 bit can be interpreted by hardware for an IMPLEMENTATION DEFINED purpose if the TCR_EL1.HPD1 value is 1.

This bit is RES0 if ARMv8.2-TTPBHA is not implemented.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

HWU062, bit [46]
In ARMv8.2:

Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[62] of the stage 1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1 if the TCR_EL1.HPD0 value is 1.

Defined values are:

HWU062Meaning
0

The stage 1 translation table entry block or level 3 bit cannot be interpreted by hardware for an IMPLEMENTATION DEFINED purpose.

1

The stage 1 translation table entry block or level 3 bit can be interpreted by hardware for an IMPLEMENTATION DEFINED purpose if the TCR_EL1.HPD0 value is 1.

This bit is RES0 if ARMv8.2-TTPBHA is not implemented.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

HWU061, bit [45]
In ARMv8.2:

Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[61] of the stage 1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1 if the TCR_EL1.HPD0 value is 1.

Defined values are:

HWU061Meaning
0

The stage 1 translation table entry block or level 3 bit cannot be interpreted by hardware for an IMPLEMENTATION DEFINED purpose.

1

The stage 1 translation table entry block or level 3 bit can be interpreted by hardware for an IMPLEMENTATION DEFINED purpose if the TCR_EL1.HPD0 value is 1.

This bit is RES0 if ARMv8.2-TTPBHA is not implemented.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

HWU060, bit [44]
In ARMv8.2:

Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[60] of the stage 1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1 if the TCR_EL1.HPD0 value is 1.

Defined values are:

HWU060Meaning
0

The stage 1 translation table entry block or level 3 bit cannot be interpreted by hardware for an IMPLEMENTATION DEFINED purpose.

1

The stage 1 translation table entry block or level 3 bit can be interpreted by hardware for an IMPLEMENTATION DEFINED purpose if the TCR_EL1.HPD0 value is 1.

This bit is RES0 if ARMv8.2-TTPBHA is not implemented.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

HWU059, bit [43]
In ARMv8.2:

Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[59] of the stage 1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1 if the TCR_EL1.HPD0 value is 1.

Defined values are:

HWU059Meaning
0

The stage 1 translation table entry block or level 3 bit cannot be interpreted by hardware for an IMPLEMENTATION DEFINED purpose.

1

The stage 1 translation table entry block or level 3 bit can be interpreted by hardware for an IMPLEMENTATION DEFINED purpose if the TCR_EL1.HPD0 value is 1.

This bit is RES0 if ARMv8.2-TTPBHA is not implemented.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

HPD1, bit [42]
In ARMv8.2 and ARMv8.1:

Hierarchical Permission Disables. This affects the hierarchical control bits, APTable, PXNTable, and UXNTable, except NSTable, in the translation tables pointed to by TTBR1_EL1.

Defined values are:

HPD1Meaning
0

Hierarchical permissions are enabled.

1

Hierarchical permissions are disabled.

When disabled, the permissions are treated as if the bits are zero.

This bit is RES0 if ARMv8.1-HPD is not implemented.


In ARMv8.0:

Reserved, RES0.

HPD0, bit [41]
In ARMv8.2 and ARMv8.1:

Hierarchical Permission Disables. This affects the hierarchical control bits, APTable, PXNTable, and UXNTable, except NSTable, in the translation tables pointed to by TTBR0_EL1.

Defined values are:

HPD0Meaning
0

Hierarchical permissions are enabled.

1

Hierarchical permissions are disabled.

When disabled, the permissions are treated as if the bits are zero.

This bit is RES0 if ARMv8.1-HPD is not implemented.


In ARMv8.0:

Reserved, RES0.

HD, bit [40]
In ARMv8.2 and ARMv8.1:

Hardware management of dirty state in stage 1 translations from EL0 and EL1.

Defined values are:

HDMeaning
0

Stage 1 hardware management of dirty state disabled.

1

Stage 1 hardware management of dirty state enabled, only if the HA bit is also set to 1.

This bit is RES0 if ARMv8.1-TTHM is not implemented.


In ARMv8.0:

Reserved, RES0.

HA, bit [39]
In ARMv8.2 and ARMv8.1:

Hardware Access flag update in stage 1 translations from EL0 and EL1.

Defined values are:

HAMeaning
0

Stage 1 Access flag update disabled.

1

Stage 1 Access flag update enabled.

This bit is RES0 if ARMv8.1-TTHM is not implemented.


In ARMv8.0:

Reserved, RES0.

TBI1, bit [38]

Top Byte ignored - indicates whether the top byte of an address is used for address match for the TTBR1_EL1 region, or ignored and used for tagged addresses. Defined values are:

TBI1Meaning
0

Top Byte used in the address calculation.

1

Top Byte ignored in the address calculation.

This affects addresses generated in EL0 and EL1 using AArch64 where the address would be translated by tables pointed to by TTBR1_EL1. It has an effect whether the EL1&0 translation regime is enabled or not.

Additionally, this affects changes to the program counter, when TBI1 is 1 and bit [55] of the target address is 1, caused by:

In these cases bits [63:56] of the address are also set to 1 before it is stored in the PC.

TBI0, bit [37]

Top Byte ignored - indicates whether the top byte of an address is used for address match for the TTBR0_EL1 region, or ignored and used for tagged addresses. Defined values are:

TBI0Meaning
0

Top Byte used in the address calculation.

1

Top Byte ignored in the address calculation.

This affects addresses generated in EL0 and EL1 using AArch64 where the address would be translated by tables pointed to by TTBR0_EL1. It has an effect whether the EL1&0 translation regime is enabled or not.

Additionally, this affects changes to the program counter, when TBI0 is 1 and bit [55] of the target address is 0, caused by:

In these cases bits [63:56] of the address are also set to 0 before it is stored in the PC.

AS, bit [36]

ASID Size. Defined values are:

ASMeaning
0

8 bit - the upper 8 bits of TTBR0_EL1 and TTBR1_EL1 are ignored by hardware for every purpose except reading back the register, and are treated as if they are all zeros for when used for allocation and matching entries in the TLB.

1

16 bit - the upper 16 bits of TTBR0_EL1 and TTBR1_EL1 are used for allocation and matching in the TLB.

If the implementation has only 8 bits of ASID, this field is RES0.

Bit [35]

Reserved, RES0.

IPS, bits [34:32]

Intermediate Physical Address Size.

IPSMeaning
000

32 bits, 4GB.

001

36 bits, 64GB.

010

40 bits, 1TB.

011

42 bits, 4TB.

100

44 bits, 16TB.

101

48 bits, 256TB.

110

52 bits, 4PB

Other values are reserved.

The reserved values behave in the same way as the 101 encoding, but software must not rely on this property as the behavior of the reserved values might change in a future revision of the architecture.

The value 110 is permitted only if ARMv8.2-LPA is implemented and the translation granule size is 64KB.

In an implementation that supports 52-bit PAs, if the value of this field is not 110, then bits[51:48] of every translation table base address for the stage of translation controlled by TCR_EL1 are 0000.

TG1, bits [31:30]

Granule size for the TTBR1_EL1.

TG1Meaning
01

16KB

10

4KB

11

64KB

Other values are reserved.

If the value is programmed to either a reserved value, or a size that has not been implemented, then the hardware will treat the field as if it has been programmed to an IMPLEMENTATION DEFINED choice of the sizes that has been implemented for all purposes other than the value read back from this register.

It is IMPLEMENTATION DEFINED whether the value read back is the value programmed or the value that corresponds to the size chosen.

SH1, bits [29:28]

Shareability attribute for memory associated with translation table walks using TTBR1_EL1. Defined values are:

SH1Meaning
00

Non-shareable

10

Outer Shareable

11

Inner Shareable

Other values are reserved. The effect of programming this field to a Reserved value is that behavior is CONSTRAINED UNPREDICTABLE, as described in 'Reserved values in AArch64 System registers and translation table entries' in the ARM ARM, section K1.2.2.

ORGN1, bits [27:26]

Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1.

ORGN1Meaning
00

Normal memory, Outer Non-cacheable

01

Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable

10

Normal memory, Outer Write-Through Read-Allocate No Write-Allocate Cacheable

11

Normal memory, Outer Write-Back Read-Allocate No Write-Allocate Cacheable

IRGN1, bits [25:24]

Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1.

IRGN1Meaning
00

Normal memory, Inner Non-cacheable

01

Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable

10

Normal memory, Inner Write-Through Read-Allocate No Write-Allocate Cacheable

11

Normal memory, Inner Write-Back Read-Allocate No Write-Allocate Cacheable

EPD1, bit [23]

Translation table walk disable for translations using TTBR1_EL1. This bit controls whether a translation table walk is performed on a TLB miss, for an address that is translated using TTBR1_EL1. The encoding of this bit is:

EPD1Meaning
0

Perform translation table walks using TTBR1_EL1.

1

A TLB miss on an address that is translated using TTBR1_EL1 generates a Translation fault. No translation table walk is performed.

A1, bit [22]

Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID. The encoding of this bit is:

A1Meaning
0

TTBR0_EL1.ASID defines the ASID.

1

TTBR1_EL1.ASID defines the ASID.

T1SZ, bits [21:16]

The size offset of the memory region addressed by TTBR1_EL1. The region size is 2(64-T1SZ) bytes.

The maximum and minimum possible values for T1SZ depend on the level of translation table and the memory translation granule size, as described in the AArch64 Virtual Memory System Architecture chapter.

TG0, bits [15:14]

Granule size for the TTBR0_EL1.

TG0Meaning
00

4KB

01

64KB

10

16KB

Other values are reserved.

If the value is programmed to either a reserved value, or a size that has not been implemented, then the hardware will treat the field as if it has been programmed to an IMPLEMENTATION DEFINED choice of the sizes that has been implemented for all purposes other than the value read back from this register.

It is IMPLEMENTATION DEFINED whether the value read back is the value programmed or the value that corresponds to the size chosen.

SH0, bits [13:12]

Shareability attribute for memory associated with translation table walks using TTBR0_EL1.

SH0Meaning
00

Non-shareable

10

Outer Shareable

11

Inner Shareable

Other values are reserved. The effect of programming this field to a Reserved value is that behavior is CONSTRAINED UNPREDICTABLE, as described in 'Reserved values in AArch64 System registers and translation table entries' in the ARM ARM, section K1.2.2.

ORGN0, bits [11:10]

Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1.

ORGN0Meaning
00

Normal memory, Outer Non-cacheable

01

Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable

10

Normal memory, Outer Write-Through Read-Allocate No Write-Allocate Cacheable

11

Normal memory, Outer Write-Back Read-Allocate No Write-Allocate Cacheable

IRGN0, bits [9:8]

Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1.

IRGN0Meaning
00

Normal memory, Inner Non-cacheable

01

Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable

10

Normal memory, Inner Write-Through Read-Allocate No Write-Allocate Cacheable

11

Normal memory, Inner Write-Back Read-Allocate No Write-Allocate Cacheable

EPD0, bit [7]

Translation table walk disable for translations using TTBR0_EL1. This bit controls whether a translation table walk is performed on a TLB miss, for an address that is translated using TTBR0_EL1. The encoding of this bit is:

EPD0Meaning
0

Perform translation table walks using TTBR0_EL1.

1

A TLB miss on an address that is translated using TTBR0_EL1 generates a Translation fault. No translation table walk is performed.

Bit [6]

Reserved, RES0.

T0SZ, bits [5:0]

The size offset of the memory region addressed by TTBR0_EL1. The region size is 2(64-T0SZ) bytes.

The maximum and minimum possible values for T0SZ depend on the level of translation table and the memory translation granule size, as described in the AArch64 Virtual Memory System Architecture chapter.

Accessing the TCR_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
TCR_EL11100000100000010
TCR_EL121110100100000010

Accessibility

The register is accessible as follows:

<systemreg> Control Accessibility
E2HTGENSEL0EL1EL2EL3
TCR_EL1xx0 - RW n/a RW
TCR_EL1001 - RWRWRW
TCR_EL1011 - n/a RWRW
TCR_EL1101 - RW TCR_EL2 RW
TCR_EL1111 - n/a TCR_EL2 RW
TCR_EL12xx0 - - n/a -
TCR_EL12001 - - - -
TCR_EL12011 - n/a - -
TCR_EL12101 - - RWRW
TCR_EL12111 - n/a RWRW

When HCR_EL2.E2H is 1, without explicit synchronization, access from EL3 using the mnemonic TCR_EL1 or TCR_EL12 are not guaranteed to be ordered with respect to accesses using the other mnemonic.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :




02/05/2017 15:43

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