The GICC_BPR characteristics are:
Defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
This register is part of the GIC physical CPU interface registers functional group.
This register is accessible as follows:
Security disabled | Secure | Non-secure |
---|---|---|
RW | RW | RW |
This register is used only when System register access is not enabled. When System register access is enabled this register is RAZ/WI, and the System registers ICC_BPR0_EL1 and ICC_BPR1_EL1 provide equivalent functionality.
Some or all RW fields of this register have defined reset values.
In systems that support two Security states:
In systems that support only one Security state, when GICC_CTLR.CBPR == 0, this register determines only Group 0 interrupt preemption.
When GICC_CTLR.CBPR == 1, this register determines interrupt preemption for both Group 0 and Group 1 interrupts.
GICC_BPR is a 32-bit register.
The GICC_BPR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Binary_Point |
Reserved, RES0.
Controls how the 8-bit interrupt priority field is split into a group priority field, that determines interrupt preemption, and a subpriority field. The following list describes how this field determines the interrupt priority bits assigned to the group priority field:
When this register has an architecturally-defined reset value, this field resets to an architecturally UNKNOWN value.
GICC_BPR can be accessed through its memory-mapped interface:
Component | Offset |
---|---|
GIC CPU interface | 0x0008 |
02/05/2017 15:43
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