The CLIDR_EL1 characteristics are:
Identifies the type of cache, or caches, that are implemented at each level and can be managed using the architected cache maintenance instructions that operate by set/way, up to a maximum of seven levels. Also identifies the Level of Coherence (LoC) and Level of Unification (LoU) for the cache hierarchy.
This register is part of the Identification registers functional group.
AArch64 System register CLIDR_EL1 is architecturally mapped to AArch32 System register CLIDR.
CLIDR_EL1 is a 64-bit register.
The CLIDR_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ICB |
ICB | LoUU | LoC | LoUIS | Ctype7 | Ctype6 | Ctype5 | Ctype4 | Ctype3 | Ctype2 | Ctype1 | |||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Inner cache boundary. This field indicates the boundary for caching Inner Cacheable memory regions.
The possible values are:
ICB | Meaning |
---|---|
000 |
Not disclosed by this mechanism. |
001 |
L1 cache is the highest Inner Cacheable level. |
010 |
L2 cache is the highest Inner Cacheable level. |
011 |
L3 cache is the highest Inner Cacheable level. |
100 |
L4 cache is the highest Inner Cacheable level. |
101 |
L5 cache is the highest Inner Cacheable level. |
110 |
L6 cache is the highest Inner Cacheable level. |
111 |
L7 cache is the highest Inner Cacheable level. |
Level of Unification Uniprocessor for the cache hierarchy.
Level of Coherence for the cache hierarchy.
Level of Unification Inner Shareable for the cache hierarchy.
Cache Type fields. Indicate the type of cache that is implemented and can be managed using the architected cache maintenance instructions that operate by set/way at each level, from Level 1 up to a maximum of seven levels of cache hierarchy. Possible values of each field are:
Ctype<n> | Meaning |
---|---|
000 |
No cache. |
001 |
Instruction cache only. |
010 |
Data cache only. |
011 |
Separate instruction and data caches. |
100 |
Unified cache. |
All other values are reserved.
If software reads the Cache Type fields from Ctype1 upwards, once it has seen a value of 000, no caches that can be managed using the architected cache maintenance instructions that operate by set/way exist at further-out levels of the hierarchy. So, for example, if Ctype3 is the first Cache Type field with a value of 000, the values of Ctype4 to Ctype7 must be ignored.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
CLIDR_EL1 | 11 | 001 | 0000 | 0000 | 001 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TID2==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TID2==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
02/05/2017 15:43
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