ICV_BPR1_EL1, Interrupt Controller Virtual Binary Point Register 1

The ICV_BPR1_EL1 characteristics are:

Purpose

Defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field. The group priority field determines virtual Group 1 interrupt preemption.

This register is part of:

Configuration

AArch64 System register ICV_BPR1_EL1 is architecturally mapped to AArch32 System register ICV_BPR1.

Attributes

ICV_BPR1_EL1 is a 32-bit register.

Field descriptions

The ICV_BPR1_EL1 bit assignments are:

313029282726252423222120191817161514131211109876543210
00000000000000000000000000000BinaryPoint

Bits [31:3]

Reserved, RES0.

BinaryPoint, bits [2:0]

If the GIC is configured to use separate binary point fields for virtual Group 0 and virtual Group 1 interrupts, the value of this field controls how the 8-bit interrupt priority field is split into a group priority field, that determines interrupt preemption, and a subpriority field. This is done as follows:

Binary point value Group priority field Subpriority field Field with binary point
0 - - -
1 [7:1] [0] ggggggg.s
2 [7:2] [1:0] gggggg.ss
3 [7:3] [2:0] ggggg.sss
4 [7:4] [3:0] gggg.ssss
5 [7:5] [4:0] ggg.sssss
6 [7:6] [5:0] gg.ssssss
7 [7] [6:0] g.sssssss

Writing 0 to this field will set this field to its reset value, which is IMPLEMENTATION DEFINED and non-zero.

If ICV_CTLR_EL1.CBPR is set to 1, Non-secure EL1 reads return ICV_BPR0_EL1 + 1 saturated to 0b111. Non-secure EL1 writes are ignored.

Accessing the ICV_BPR1_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op1CRnCRmop2
ICC_BPR1_EL100011001100011

When HCR_EL2.IMO is set to 0, execution of this encoding at Non-secure EL1 results in an access to ICC_BPR1_EL1.

Accessibility

The register is accessible as follows:

Control Accessibility
FMOIMOTGENSEL0EL1EL2EL3
xxx0 - ICC_BPR1_EL1 n/a ICC_BPR1_EL1
xx11 - n/a ICC_BPR1_EL1 ICC_BPR1_EL1
x001 - ICC_BPR1_EL1 ICC_BPR1_EL1 ICC_BPR1_EL1
x101 - RW ICC_BPR1_EL1 ICC_BPR1_EL1

This table applies to all instructions that can access this register.

ICV_BPR1_EL1 is only accessible at Non-secure EL1 when HCR_EL2.IMO is set to 1.

Note

When HCR_EL2.IMO is set to 0, at Non-secure EL1, the instruction encoding used to access ICV_BPR1_EL1 results in an access to ICC_BPR1_EL1.

The reset value is IMPLEMENTATION DEFINED, but is equal to the minimum value of ICV_BPR0_EL1 plus one.

An attempt to program the binary point field to a value less than the reset value sets the field to the reset value.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When SCR_EL3.NS==1 :




02/05/2017 15:43

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