PMCCNTR_EL0, Performance Monitors Cycle Counter

The PMCCNTR_EL0 characteristics are:

Purpose

Holds the value of the processor Cycle Counter, CCNT, that counts processor clock cycles. See 'Time as measured by the Performance Monitors cycle counter' in the ARMv8 ARM, section D5 for more information.

PMCCFILTR_EL0 determines the modes and states in which the PMCCNTR_EL0 can increment.

This register is part of the Performance Monitors registers functional group.

Usage constraints

This register is accessible as follows:

OffDLKOSLKEPMADSLKDefault
ErrorErrorErrorErrorRORW

Configuration

External register PMCCNTR_EL0 is architecturally mapped to AArch64 System register PMCCNTR_EL0.

External register PMCCNTR_EL0 is architecturally mapped to AArch32 System register PMCCNTR.

PMCCNTR_EL0 is in the Core power domain. RW fields in this register reset to architecturally UNKNOWN values. These apply on a Warm or Cold reset. The register is not affected by an External debug reset.

Attributes

PMCCNTR_EL0 is a 64-bit register.

Field descriptions

The PMCCNTR_EL0 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
CCNT
CCNT
313029282726252423222120191817161514131211109876543210

CCNT, bits [63:0]

Cycle count. Depending on the values of PMCR_EL0.{LC,D}, the cycle count increments in one of the following ways:

Writing 1 to PMCR_EL0.C sets this field to 0.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Accessing the PMCCNTR_EL0

PMCCNTR_EL0[31:0] can be accessed through the external debug interface:

ComponentOffset
PMU 0x0F8

PMCCNTR_EL0[63:32] can be accessed through the external debug interface:

ComponentOffset
PMU 0x0FC



02/05/2017 15:43

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