The ID_MMFR4 characteristics are:
Provides information about the implemented memory model and memory management support in AArch32 state.
Must be interpreted with ID_MMFR0, ID_MMFR1, ID_MMFR2, and ID_MMFR3.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section G4.14.6.
This register is part of the Identification registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register ID_MMFR4 is architecturally mapped to AArch64 System register ID_MMFR4_EL1.
In an implementation that does not include ACTLR2 and HACTLR2 this register is RAZ.
ID_MMFR4 is a 32-bit register.
The ID_MMFR4 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | LSM | HPDS | CnP | XNX | AC2 | SpecSEI |
Reserved, RAZ.
Indicates support for LSMAOE and nTLSMD bits in HSCTLR and SCTLR. Defined values are:
LSM | Meaning |
---|---|
0000 |
LSMAOE and nTLSMD bits not supported. |
0001 |
LSMAOE and nTLSMD bits supported. |
All other values are reserved.
In ARMv8.0 and ARMv8.1 the only permitted value is 0000.
From ARMv8.2, the permitted values are 0000 and 0001. This feature is identified by the name ARMv8.2-LSMAOC.
Reserved, RAZ.
Hierarchical permission disables bits in translation tables. Defined values are:
HPDS | Meaning |
---|---|
0000 |
Disabling of hierarchical controls not supported. |
0001 |
Supports disabling of hierarchical controls using the TTBCR2.HPD0, TTBCR2.HPD1, and HTCR.HPD bits. |
0010 |
Supports disabling of hierarchical controls using the TTBCR2.HPD0, TTBCR2.HPD1, and HTCR.HPD bits, and hardware allocation of bits[62:59] of the last level page table descriptor for IMPLEMENTATION DEFINED use. |
All other values are reserved.
In ARMv8.0 and ARMv8.1 the only permitted value is 0000.
From ARMv8.2, the permitted values are 0000, 0001 and 0010. This feature is identified by the name ARMv8.2-AA32HPD.
The encoding 0000 implies that the encoding for TTBCR2 is unallocated.
Reserved, RAZ.
Common not Private translations. Defined values are:
CnP | Meaning |
---|---|
0000 |
Common not Private translations not supported. |
0001 |
Common not Private translations supported. |
All other values are reserved.
In ARMv8.0 and ARMv8.1 the only permitted value is 0000.
From ARMv8.2, the only permitted value is 0001. This feature is identified by the name ARMv8.2-TTCNP.
Reserved, RAZ.
Support for execute never control distinction at stage 2 bit. Defined values are:
XNX | Meaning |
---|---|
0000 |
Distinction between EL0 and EL1 execute permission at stage 2 not supported. |
0001 |
Distinction between EL0 and EL1 execute permission at stage 2 supported. |
All other values are reserved.
In ARMv8.0 and ARMv8.1 the only permitted value is 0000.
From ARMv8.2, the only permitted value is 0001. This feature is identified by the name ARMv8.2-TTS2UXN.
Reserved, RAZ.
Indicates the extension of the ACTLR and HACTLR registers using ACTLR2 and HACTLR2. Defined values are:
AC2 | Meaning |
---|---|
0000 | |
0001 |
All other values are reserved.
In ARMv8.0 and ARMv8.1 the permitted values are 0000 and 0001.
From ARMv8.2, the only permitted value is 0001.
Describes whether the PE can generate SError interrupt exceptions from speculative reads of memory, including speculative instruction fetches. The defined values of this field are:
SpecSEI | Meaning |
---|---|
0000 |
The PE never generates an SError interrupt due to an external abort on a speculative read. |
0001 |
The PE might generate an SError interrupt due to an external abort on a speculative read. |
All other values are reserved.
When the RAS Extension is not implemented, this field is RAZ.
This register can be read using MRC with the following syntax:
MRC <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c0, c2, 6 | 000 | 110 | 0000 | 1111 | 0010 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2 using AArch64.
If HSTR_EL2.T0==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2 using AArch64.
If HSTR_EL2.T0==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
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