The CNTP_TVAL characteristics are:
Holds the timer value for the EL1 physical timer.
This register is part of the Generic Timer registers functional group.
AArch32 System register CNTP_TVAL is architecturally mapped to AArch64 System register CNTP_TVAL_EL0.
RW fields in this register reset to architecturally UNKNOWN values.
CNTP_TVAL is a 32-bit register.
The CNTP_TVAL bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TimerValue |
The TimerValue view of the EL1 physical timer.
On a read of this register:
On a write of this register, CNTP_CVAL is set to (CNTPCT + TimerValue), where TimerValue is treated as a signed 32-bit integer.
When CNTP_CTL.ENABLE is 1, the timer condition is met when (CNTPCT - CNTP_CVAL) is greater than zero. This means that TimerValue acts like a 32-bit downcounter timer. When the timer condition is met:
When CNTP_CTL.ENABLE is 0, the timer condition is not met, but CNTPCT continues to count, so the TimerValue view appears to continue to count down.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c14, c2, 0 | 000 | 000 | 1110 | 1111 | 0010 |
The register is accessible as follows:
Configuration | Control | Accessibility | Instance | |||||
---|---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | ||
EL3 not implemented | x | x | 0 | RW | RW | n/a | n/a | CNTP_TVAL |
EL3 not implemented | 0 | 0 | 1 | RW | RW | RW | n/a | CNTP_TVAL |
EL3 not implemented | 0 | 1 | 1 | RW | n/a | RW | n/a | CNTP_TVAL |
EL3 not implemented | 1 | 0 | 1 | RW | RW | n/a | n/a | CNTP_TVAL |
EL3 not implemented | 1 | 1 | 1 | CNTHP_TVAL | n/a | n/a | n/a | - |
EL3 using AArch64 | x | x | 0 | RW | RW | n/a | n/a | CNTP_TVAL |
EL3 using AArch64 | 0 | 0 | 1 | RW | RW | RW | n/a | CNTP_TVAL |
EL3 using AArch64 | 0 | 1 | 1 | RW | n/a | RW | n/a | CNTP_TVAL |
EL3 using AArch64 | 1 | 0 | 1 | RW | RW | n/a | n/a | CNTP_TVAL |
EL3 using AArch64 | 1 | 1 | 1 | CNTHP_TVAL | n/a | n/a | n/a | - |
EL3 using AArch32 | x | 0 | 1 | RW | RW | RW | RW | CNTP_TVAL_ns |
EL3 using AArch32 | x | 1 | 1 | RW | n/a | RW | RW | CNTP_TVAL_ns |
EL3 using AArch32 | x | x | 0 | RW | n/a | n/a | RW | CNTP_TVAL_s |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When HCR_EL2.E2H==0 :
If CNTKCTL_EL1.EL0PTEN==0, accesses to this register from EL0 are trapped to EL1.
If CNTKCTL.PL0PTEN==0, accesses to this register from EL0 are trapped to Undefined mode.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If CNTHCTL_EL2.EL1PCEN==0, Non-secure accesses to this register from EL1 are trapped to EL2.
If CNTHCTL_EL2.EL1PCEN==0, and CNTKCTL_EL1.EL0PTEN==1, Non-secure accesses to this register from EL0 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If CNTHCTL_EL2.EL1PTEN==0, Non-secure accesses to this register from EL1 are trapped to EL2.
If CNTHCTL_EL2.EL1PTEN==0, and CNTKCTL_EL1.EL0PTEN==1, Non-secure accesses to this register from EL0 are trapped to EL2.
If CNTKCTL_EL1.EL0PTEN==0, Non-secure accesses to this register from EL0 are trapped to EL1.
If CNTKCTL.PL0PTEN==0, Non-secure accesses to this register from EL0 are trapped to Undefined mode.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==1 :
If CNTHCTL_EL2.EL0PTEN==0, Non-secure accesses to this register from EL0 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If CNTHCTL.PL1PCEN==0, Non-secure accesses to this register from EL0 and EL1 are trapped to Hyp mode.
02/05/2017 15:43
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.