PMSWINC_EL0, Performance Monitors Software Increment register

The PMSWINC_EL0 characteristics are:

Purpose

Increments a counter that is configured to count the Software increment event, event 0x00. For more information, see 'SW_INCR' in the ARMv8 ARM, section D5.

This register is part of the Performance Monitors registers functional group.

Usage constraints

This register is accessible as follows:

OffDLKOSLKEPMADSLKDefault
ErrorErrorErrorErrorWIWO

Configuration

External register PMSWINC_EL0 is architecturally mapped to AArch64 System register PMSWINC_EL0.

External register PMSWINC_EL0 is architecturally mapped to AArch32 System register PMSWINC.

PMSWINC_EL0 is in the Core power domain.

Implementation of this register is OPTIONAL.

If this register is implemented, use of it is deprecated.

If 1 is written to bit [n] from the external debug interface, it is CONSTRAINED UNPREDICTABLE whether or not a SW_INCR event is created for counter n. This is consistent with not implementing the register in the external debug interface.

Attributes

PMSWINC_EL0 is a 32-bit register.

Field descriptions

The PMSWINC_EL0 bit assignments are:

313029282726252423222120191817161514131211109876543210
0P<n>, bit [n]

Bit [31]

Reserved, RES0.

P<n>, bit [n], for n = 0 to 30

Event counter software increment bit for PMEVCNTR<n>_EL0.

P<n> is WI if n >= PMCR_EL0.N, the number of implemented counters.

Otherwise, the effects of writing to this bit are:

P<n>Meaning
0

No action. The write to this bit is ignored.

1

It is CONSTRAINED UNPREDICTABLE whether a SW_INCR event is generated for event counter n.

Accessing the PMSWINC_EL0

PMSWINC_EL0 can be accessed through the external debug interface:

ComponentOffset
PMU 0xCA0



02/05/2017 15:43

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