CNTHP_CVAL_EL2, Counter-timer Hypervisor Physical Timer CompareValue register

The CNTHP_CVAL_EL2 characteristics are:

Purpose

Holds the compare value for the EL2 physical timer.

This register is part of:

Configuration

AArch64 System register CNTHP_CVAL_EL2 is architecturally mapped to AArch32 System register CNTHP_CVAL.

If EL2 is not implemented, this register is RES0 from EL3.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

CNTHP_CVAL_EL2 is a 64-bit register.

Field descriptions

The CNTHP_CVAL_EL2 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
CompareValue
CompareValue
313029282726252423222120191817161514131211109876543210

CompareValue, bits [63:0]

Holds the EL2 physical timer CompareValue.

When CNTHP_CTL_EL2.ENABLE is 1, the timer condition is met when (CNTPCT_EL0 - CompareValue) is greater than zero. This means that CompareValue acts like a 64-bit upcounter timer. When the timer condition is met:

When CNTHP_CTL_EL2.ENABLE is 0, the timer condition is not met, but CNTPCT_EL0 continues to count.

Accessing the CNTHP_CVAL_EL2

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
CNTHP_CVAL_EL21110011100010010
CNTP_CVAL_EL01101111100010010

Accessibility

The register is accessible as follows:

<systemreg> Control Accessibility
E2HTGENSEL0EL1EL2EL3
CNTHP_CVAL_EL2xx0 - - n/a RW
CNTHP_CVAL_EL2001 - - RWRW
CNTHP_CVAL_EL2011 - n/a RWRW
CNTHP_CVAL_EL2101 - - RWRW
CNTHP_CVAL_EL2111 - n/a RWRW
CNTP_CVAL_EL0xx0 CNTP_CVAL_EL0 CNTP_CVAL_EL0 n/a CNTP_CVAL_EL0
CNTP_CVAL_EL0001 CNTP_CVAL_EL0 CNTP_CVAL_EL0 CNTP_CVAL_EL0 CNTP_CVAL_EL0
CNTP_CVAL_EL0011 CNTP_CVAL_EL0 n/a CNTP_CVAL_EL0 CNTP_CVAL_EL0
CNTP_CVAL_EL0101 CNTP_CVAL_EL0 CNTP_CVAL_EL0 RWRW
CNTP_CVAL_EL0111RW n/a RWRW

When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic CNTHP_CVAL_EL2 or CNTP_CVAL_EL0 are not guaranteed to be ordered with respect to accesses using the other mnemonic.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==1 :




02/05/2017 15:43

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