The DBGDSCRint characteristics are:
Main control register for the debug implementation. This is an internal, read-only view.
This register is part of the Debug registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
This register is required in all implementations.
DBGDSCRint.{NS, SPNIDdis, SPIDdis, MDBGen, UDCCdis, MOE} are UNKNOWN when the register is accessed at EL0. However, although these values are not accessible at EL0 by instructions that are neither UNPREDICTABLE nor return UNKNOWN values, it is permissible for an implementation to return the values of DBGDSCRext.{NS, SPNIDdis, SPIDdis, MDBGen, UDCCdis, MOE} for these fields at EL0.
It is also permissible for an implementation to return the same values as defined for a read of DBGDSCRint at EL1 or above. (This is the case even if the implementation does not support AArch32 at EL1 or above.)
DBGDSCRint is a 32-bit register.
The DBGDSCRint bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | RXfull | TXfull | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | NS | SPNIDdis | SPIDdis | MDBGen | 0 | 0 | UDCCdis | 0 | 0 | 0 | 0 | 0 | 0 | MOE | 0 | 0 |
Reserved, RES0.
DTRRX full. Read-only view of the equivalent bit in the EDSCR.
DTRTX full. Read-only view of the equivalent bit in the EDSCR.
Reserved, RES0.
Non-secure status.
Read-only view of the equivalent bit in the DBGDSCRext. ARM deprecates use of this field.
Secure privileged non-invasive debug disable.
Read-only view of the equivalent bit in the DBGDSCRext. ARM deprecates use of this field.
Secure privileged invasive debug disable.
Read-only view of the equivalent bit in the DBGDSCRext. ARM deprecates use of this field.
Monitor debug events enable.
Read-only view of the equivalent bit in the DBGDSCRext.
Reserved, RES0.
User mode access to Debug Communications Channel disable.
Read-only view of the equivalent bit in the DBGDSCRext. ARM deprecates use of this field.
Reserved, RES0.
Method of Entry for debug exception. When a debug exception is taken to an Exception level using AArch32, this field is set to indicate the event that caused the exception:
MOE | Meaning |
---|---|
0001 |
Breakpoint |
0011 |
Software breakpoint (BKPT) instruction |
0101 |
Vector catch |
1010 |
Watchpoint |
Read-only view of the equivalent bit in the DBGDSCRext.
Reserved, RES0.
This register can be read using MRC with the following syntax:
MRC <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p14, 0, <Rt>, c0, c1, 0 | 000 | 000 | 0000 | 1110 | 0001 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | RO | RO | n/a | RO |
x | 0 | 1 | RO | RO | RO | RO |
x | 1 | 1 | RO | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If DBGDSCRext.UDCCdis==1, read accesses to this register from EL0 are trapped to Undefined mode.
If MDSCR_EL1.TDCC==1, read accesses to this register from EL0 are trapped to EL1.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TDA==1, Non-secure read accesses to this register from EL0 and EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HDCR.TDA==1, Non-secure read accesses to this register from EL0 and EL1 are trapped to Hyp mode.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TDA==1, read accesses to this register from EL0, EL1, and EL2 are trapped to EL3.
02/05/2017 15:43
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