The CPACR_EL1 characteristics are:
Controls access to trace, SVE, Advanced SIMD and floating-point functionality.
This register is part of the Other system control registers functional group.
AArch64 System register CPACR_EL1 is architecturally mapped to AArch32 System register CPACR.
When HCR_EL2.{E2H, TGE} == {1, 1}, the fields in this register have no effect on execution at EL0 and EL1. In this case, the controls provided by CPTR_EL2 are used.
RW fields in this register reset to architecturally UNKNOWN values.
CPACR_EL1 is a 32-bit register.
The CPACR_EL1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | TTA | 0 | 0 | 0 | 0 | 0 | 0 | FPEN | 0 | 0 | ZEN | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Reserved, RES0.
Traps EL0 and EL1 System register accesses to all implemented trace registers to EL1, or to EL2 when SCR_EL3.NS is 1 and HCR_EL2.TGE is 1, from both Execution states.
TTA | Meaning |
---|---|
0 |
This control does not cause any instructions to be trapped. |
1 |
This control causes EL0 and EL1 System register accesses to all implemented trace registers to be trapped. |
System register accesses to the trace registers can have side-effects. When a System register access is trapped, any side-effects that are normally associated with the access do not occur before the exception is taken.
If System register access to the trace functionality is not implemented, this bit is RES0.
Reserved, RES0.
Traps EL0 and EL1 accesses to the SVE, Advanced SIMD, and floating-point registers to EL1, or to EL2 when SCR_EL3.NS is 1 and HCR_EL2.TGE is 1, from both Execution states, unless SVE is implemented and they are trapped by CPACR_EL1.ZEN.
FPEN | Meaning |
---|---|
00 |
This control causes any instructions at EL0 or EL1 that use the registers associated with SVE, Advanced SIMD and floating-point execution to be trapped. |
01 |
This control causes any instructions at EL0 that use the registers associated with SVE, Advanced SIMD and floating-point execution to be trapped, but does not cause any instruction in EL1 to be trapped. |
10 |
This control causes any instructions at EL0 or EL1 that use the registers associated with SVE, Advanced SIMD and floating-point execution to be trapped. |
11 |
This control does not cause any instructions to be trapped. |
Writes to MVFR0, MVFR1 and MVFR2 from EL1 or higher are CONSTRAINED UNPREDICTABLE and whether these accesses can be trapped by this control depends on implemented CONSTRAINED UNPREDICTABLE behavior.
Reserved, RES0.
Traps SVE instructions and instructions that access SVE System registers at EL0 and EL1 to EL1, or to EL2 when SCR_EL3.NS and HCR_EL2.TGE are both 1. Defined values are:
ZEN | Meaning |
---|---|
00 |
This control causes these instructions executed at EL0 or EL1 to be trapped. |
01 |
This control causes these instructions executed at EL0 to be trapped, but does not cause any instruction in EL1 to be trapped. |
10 |
This control causes these instructions executed at EL0 or EL1 to be trapped. |
11 |
This control does not cause any instruction to be trapped. |
If SVE is not implemented, this field is RES0.
Reserved, RES0.
Reserved, RES0.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
CPACR_EL1 | 11 | 000 | 0001 | 0000 | 010 |
CPACR_EL12 | 11 | 101 | 0001 | 0000 | 010 |
The register is accessible as follows:
<systemreg> | Control | Accessibility | |||||
---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | |
CPACR_EL1 | x | x | 0 | - | RW | n/a | RW |
CPACR_EL1 | 0 | 0 | 1 | - | RW | RW | RW |
CPACR_EL1 | 0 | 1 | 1 | - | n/a | RW | RW |
CPACR_EL1 | 1 | 0 | 1 | - | RW | CPTR_EL2 | RW |
CPACR_EL1 | 1 | 1 | 1 | - | n/a | CPTR_EL2 | RW |
CPACR_EL12 | x | x | 0 | - | - | n/a | - |
CPACR_EL12 | 0 | 0 | 1 | - | - | - | - |
CPACR_EL12 | 0 | 1 | 1 | - | n/a | - | - |
CPACR_EL12 | 1 | 0 | 1 | - | - | RW | RW |
CPACR_EL12 | 1 | 1 | 1 | - | n/a | RW | RW |
When HCR_EL2.E2H is 1, without explicit synchronization, access from EL3 using the mnemonic CPACR_EL1 or CPACR_EL12 are not guaranteed to be ordered with respect to accesses using the other mnemonic.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If CPTR_EL2.TCPAC==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If CPTR_EL2.TCPAC==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL3 is implemented and is using AArch64 :
If CPTR_EL3.TCPAC==1, accesses to this register from EL1 and EL2 are trapped to EL3.
02/05/2017 15:43
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