The PMCID2SR characteristics are:
Contains the sampled value of CONTEXTIDR_EL2, captured on reading PMPCSR[31:0].
This register is part of the Performance Monitors registers functional group.
This register is accessible as follows:
Off | DLK | OSLK | SLK | Default |
---|---|---|---|---|
Error | Error | Error | RO | RO |
PMCID2SR is in the Core power domain.
Fields in this register reset to architecturally UNKNOWN values. These apply only on a Cold reset. The register is not affected by a Warm reset and is not affected by an External debug reset.
Implemented only if the OPTIONAL PC Sample-based Profiling Extension is implemented and ARMv8.2-PCSample is implemented. If the OPTIONAL PC Sample-based Profiling Extension is implemented and ARMv8.2-PCSample is not implemented, this register is not implemented and the architecture defines the functionality in EDCIDSR.
If EL2 is not implemented, this register is RES0.
This register is introduced in ARMv8.2.
PMCID2SR is a 32-bit register.
The PMCID2SR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CONTEXTIDR_EL2 |
Context ID. The value of CONTEXTIDR that is associated with the most recent PMPCSR sample.
Because the value written to PMCID2SR is an indirect read of CONTEXTIDR, therefore it is CONSTRAINED UNPREDICTABLE whether PMCID2SR is set to the original or new value if a read of PMPCSR samples:
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
PMCID2SR can be accessed through the external debug interface:
Component | Offset |
---|---|
PMU | 0x22C |
02/05/2017 15:43
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