The ICH_AP1R<n> characteristics are:
Provides information about Group 1 active priorities for EL2.
This register is part of:
AArch32 System register ICH_AP1R<n> is architecturally mapped to AArch64 System register ICH_AP1R<n>_EL2.
If EL2 is not implemented, this register is RES0 from EL3.
ICH_AP1R<n> is a 32-bit register.
The ICH_AP1R<n> bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
P31 | P30 | P29 | P28 | P27 | P26 | P25 | P24 | P23 | P22 | P21 | P20 | P19 | P18 | P17 | P16 | P15 | P14 | P13 | P12 | P11 | P10 | P9 | P8 | P7 | P6 | P5 | P4 | P3 | P2 | P1 | P0 |
Group 1 interrupt active priorities. Possible values of each bit are:
P<x> | Meaning |
---|---|
0 |
There is no Group 1 interrupt active at the priority corresponding to that bit. |
1 |
There is a Group 1 interrupt active at the priority corresponding to that bit. |
The correspondence between priority levels and bits depends on the number of bits of priority that are implemented.
If 5 bits of priority are implemented (bits [7:3] of priority), then there are 32 priority levels, and the active state of these priority levels are held in ICH_AP1R0 in the bits corresponding to Priority[7:3].
If 6 bits of priority are implemented (bits [7:2] of priority), then there are 64 priority levels, and:
If 7 bits of priority are implemented (bits [7:1] of priority), then there are 128 priority levels, and:
Having the bit corresponding to a priority set to 1 in both ICH_AP0R<n> and ICH_AP1R<n> might result in UNPREDICTABLE behavior of the interrupt prioritization system for virtual interrupts.
When this register has an architecturally-defined reset value, this field resets to 0.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 4, <Rt>, c12, c9, <opc2> | 100 | 0:n<1:0> | 1100 | 1111 | 1001 |
The register is accessible as follows:
Control | Accessibility | ||||||
---|---|---|---|---|---|---|---|
FMO | IMO | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | x | 0 | - | - | n/a | - |
x | x | 0 | 1 | - | - | RW | RW |
x | x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
ICH_AP1R1 is only implemented in implementations that support 6 or more bits of priority. ICH_AP1R2 and ICH_AP1R3 are only implemented in implementations that support 7 bits of priority. Unimplemented registers are UNDEFINED.
Writing to the active priority registers in any order other than the following order will result in UNPREDICTABLE behavior:
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_HSRE.SRE==0, accesses to this register from EL2 are UNDEFINED.
If ICC_MSRE.SRE==0, Non-secure accesses to this register from EL3 are UNDEFINED.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==0 :
If HSTR_EL2.T12==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T12==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HSTR.T12==1, Non-secure accesses to this register from EL1 are trapped to Hyp mode.
02/05/2017 15:43
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