GICR_PENDBASER, Redistributor LPI Pending Table Base Address Register

The GICR_PENDBASER characteristics are:

Purpose

Specifies the base address of the LPI Pending table, and the Shareability and Cacheability of accesses to the LPI Pending table.

This register is part of the GIC Redistributor registers functional group.

Usage constraints

This register is accessible as follows:

Security disabledSecureNon-secure
RWRWRW

Having the GICR_PENDBASER OuterCache, Shareability or InnerCache fields programmed to different values on different Redistributors with GICR_CTLR.EnableLPIs == 1 in the system is UNPREDICTABLE.

Changing GICR_PENDBASER with GICR_CTLR.EnableLPIs == 1 is UNPREDICTABLE.

Configuration

RW fields in this register reset to architecturally UNKNOWN values.

A copy of this register is provided for each Redistributor.

Attributes

GICR_PENDBASER is a 64-bit register.

Field descriptions

The GICR_PENDBASER bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
0PTZ000OuterCache0000Physical_Address
Physical_Address0000ShareabilityInnerCache0000000
313029282726252423222120191817161514131211109876543210

Bit [63]

Reserved, RES0.

PTZ, bit [62]

Pending Table Zero. Indicates to the Redistributor whether the LPI Pending table is zero when GICR_CTLR.EnableLPIs == 1.

This field is WO, and reads as 0.

PTZMeaning
0

The LPI Pending table is not zero, and contains live data.

1

The LPI Pending table is zero. Software must ensure the LPI Pending table is zero before this value is written.

Bits [61:59]

Reserved, RES0.

OuterCache, bits [58:56]

Indicates the Outer Cacheability attributes of accesses to the LPI Pending table. The possible values of this field are:

OuterCacheMeaning
000

Memory type defined in InnerCache field. For Normal memory, Outer Cacheability is the same as Inner Cacheability.

001

Normal Outer Non-cacheable.

010

Normal Outer Cacheable Read-allocate, Write-through.

011

Normal Outer Cacheable Read-allocate, Write-back.

100

Normal Outer Cacheable Write-allocate, Write-through.

101

Normal Outer Cacheable Write-allocate, Write-back.

110

Normal Outer Cacheable Read-allocate, Write-allocate, Write-through.

111

Normal Outer Cacheable Read-allocate, Write-allocate, Write-back.

It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.

When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to a value that is architecturally UNKNOWN.

Bits [55:52]

Reserved, RES0.

Physical_Address, bits [51:16]

Bits [51:16] of the physical address containing the LPI Pending table.

In implementations supporting fewer than 52 bits of physical address, unimplemented upper bits are RES0.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bits [15:12]

Reserved, RES0.

Shareability, bits [11:10]

Indicates the Shareability attributes of accesses to the LPI Pending table. The possible values of this field are:

ShareabilityMeaning
00

Non-shareable.

01

Inner Shareable.

10

Outer Shareable.

11

Reserved. Treated as 00.

It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.

When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to a value that is architecturally UNKNOWN.

InnerCache, bits [9:7]

Indicates the Inner Cacheability attributes of accesses to the LPI Pending table. The possible values of this field are:

InnerCacheMeaning
000

Device-nGnRnE.

001

Normal Inner Non-cacheable.

010

Normal Inner Cacheable Read-allocate, Write-through.

011

Normal Inner Cacheable Read-allocate, Write-back.

100

Normal Inner Cacheable Write-allocate, Write-through.

101

Normal Inner Cacheable Write-allocate, Write-back.

110

Normal Inner Cacheable Read-allocate, Write-allocate, Write-through.

111

Normal Inner Cacheable Read-allocate, Write-allocate, Write-back.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bits [6:0]

Reserved, RES0.

Accessing the GICR_PENDBASER

GICR_PENDBASER can be accessed through its memory-mapped interface:

ComponentFrameOffset
GIC RedistributorRD_base0x0078-0x007C



02/05/2017 15:43

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