The CSSELR_EL1 characteristics are:
Selects the current Cache Size ID Register, CCSIDR_EL1, by specifying the required cache level and the cache type (either instruction or data cache).
This register is part of the Identification registers functional group.
AArch64 System register CSSELR_EL1 is architecturally mapped to AArch32 System register CSSELR.
RW fields in this register reset to architecturally UNKNOWN values.
CSSELR_EL1 is a 32-bit register.
The CSSELR_EL1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Level | InD |
Reserved, RES0.
Cache level of required cache. Permitted values are:
Level | Meaning |
---|---|
000 |
Level 1 cache |
001 |
Level 2 cache |
010 |
Level 3 cache |
011 |
Level 4 cache |
100 |
Level 5 cache |
101 |
Level 6 cache |
110 |
Level 7 cache |
All other values are reserved.
If CSSELR_EL1.Level is programmed to a cache level that is not implemented, then the value for this field on a read of CSSELR is UNKNOWN.
Instruction not Data bit. Permitted values are:
InD | Meaning |
---|---|
0 |
Data or unified cache. |
1 |
Instruction cache. |
If CSSELR_EL1.Level is programmed to a cache level that is not implemented, then the value for this field on a read of CSSELR is UNKNOWN.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
CSSELR_EL1 | 11 | 010 | 0000 | 0000 | 000 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RW | n/a | RW |
x | 0 | 1 | - | RW | RW | RW |
x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TID2==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TID2==1, Non-secure accesses to this register from EL1 are trapped to EL2.
02/05/2017 15:43
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.