The CNTHV_CTL characteristics are:
Provides AArch32 access to the control register for the EL2 virtual timer.
The EL2 virtual timer is implemented by ARMv8.1-VHE. It is only accessible from AArch32 state when EL0 is using AArch32, EL2 is using AArch64, and the value of HCR_EL2.{E2H, TGE} is {1, 1}.
This register is part of the Generic Timer registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register CNTHV_CTL is architecturally mapped to AArch64 System register CNTHV_CTL_EL2.
This register is introduced in ARMv8.1.
CNTHV_CTL is a 32-bit register.
The CNTHV_CTL bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ISTATUS | IMASK | ENABLE |
Reserved, RES0.
The status of the timer. This bit indicates whether the timer condition is met:
ISTATUS | Meaning |
---|---|
0 |
Timer condition is not met. |
1 |
Timer condition is met. |
When the value of the ENABLE bit is 1, ISTATUS indicates whether the timer condition is met. ISTATUS takes no account of the value of the IMASK bit. If the value of ISTATUS is 1 and the value of IMASK is 0 then the timer interrupt is asserted.
When the value of the ENABLE bit is 0, the ISTATUS field is UNKNOWN.
For more information see 'Operation of the CompareValue views of the timers' and 'Operation of the TimerValue views of the timers' in the ARM ARM, chapter D6.
This bit is read-only.
Timer interrupt mask bit. Permitted values are:
IMASK | Meaning |
---|---|
0 |
Timer interrupt is not masked by the IMASK bit. |
1 |
Timer interrupt is masked by the IMASK bit. |
For more information, see the description of the ISTATUS bit.
Enables the timer. Permitted values are:
ENABLE | Meaning |
---|---|
0 |
Timer disabled. |
1 |
Timer enabled. |
Setting this bit to 0 disables the timer output signal, but the timer value accessible from CNTHV_TVAL continues to count down.
Disabling the output signal might be a power-saving option.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c14, c3, 1 | 000 | 001 | 1110 | 1111 | 0011 |
This register is accessed using the encoding for CNTV_CTL.
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | CNTV_CTL | CNTV_CTL | n/a | CNTV_CTL |
0 | 0 | 1 | CNTV_CTL | CNTV_CTL | CNTV_CTL | CNTV_CTL |
0 | 1 | 1 | CNTV_CTL | n/a | CNTV_CTL | CNTV_CTL |
1 | 0 | 1 | CNTV_CTL | CNTV_CTL | n/a | n/a |
1 | 1 | 1 | RW | n/a | n/a | n/a |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==1 :
If CNTHCTL_EL2.EL0VTEN==0, Non-secure accesses to this register from EL0 are trapped to EL2.
02/05/2017 15:43
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