TTBR0_EL3, Translation Table Base Register 0 (EL3)

The TTBR0_EL3 characteristics are:

Purpose

Holds the base address of the translation table for the initial lookup for stage 1 of an address translation in the EL3 translation regime, and other information for this translation regime.

This register is part of the Virtual memory control registers functional group.

Configuration

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

TTBR0_EL3 is a 64-bit register.

Field descriptions

The TTBR0_EL3 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
0000000000000000BADDR
BADDRCnP
313029282726252423222120191817161514131211109876543210

Any of the fields in this register are permitted to be cached in a TLB.

Bits [63:48]

Reserved, RES0.

BADDR, bits [47:1]

Translation table base address, A[47:x] or A[51:x].

Note

In an implementation that includes ARMv8.2-LPA, if the value of TCR_EL3.PS is 110 then:

Note

In an implementation that includes ARMv8.2-LPA a TCR_EL3.PS value of 110, that selects a PA size of 52 bits, is permitted only when using the 64KB translation granule.

When the value of ID_AA64MMFR0_EL1.PARange indicates that the implementation does not support a 52 bit PA size, if a translation table lookup uses this register with the 64KB translation granule when the value of TCR_EL3.PS is 110 and the value of register bits[5:2] is nonzero it is IMPLEMENTATION DEFINED whether an Address size fault is generated, but ARM deprecates not generating an Address size fault.

If the Effective value of TCR_EL3.PS is not 110 then:

Note

This definition applies:

If any TTBR0_EL3[47:0] bit that is defined as RES0 has the value 1 when a translation table walk is performed using TTBR0_EL3, then the translation table base address might be misaligned, with effects that are CONSTRAINED UNPREDICTABLE, and must be one of the following:

The AArch64 Virtual Memory System Architecture chapter describes how x is calculated based on the value of TCR_EL3.T0SZ, the stage of translation, and the translation granule size.

CnP, bit [0]
In ARMv8.2:

Common not Private. In an implementation that includes ARMv8.2-TTCNP, indicates whether each entry that is pointed to by TTBR0_EL3 is a member of a common set that can be used by every PE in the Inner Shareable domain for which the value of TTBR0_EL3.CnP is 1.

CnPMeaning
0

The translation table entries pointed to by TTBR0_EL3, for the current translation regime, are permitted to differ from corresponding entries for TTBR0_EL3 for other PEs in the Inner Shareable domain. This is not affected by the value of TTBR0_EL3.CnP on those other PEs.

1

The translation table entries pointed to by TTBR0_EL3 are the same as the translation table entries for every other PE in the Inner Shareable domain for which the value of TTBR0_EL3.CnP is 1 and the translation table entries are pointed to by TTBR0_EL3.

Note

If the value of the TTBR0_EL3.CnP bit is 1 on multiple PEs in the same Inner Shareable domain and those TTBR0_EL3s do not point to the same translation table entries the results of translations using TTBR0_EL3 are CONSTRAINED UNPREDICTABLE, see 'CONSTRAINED UNPREDICTABLE behaviors due to caching of control or data values' in the ARMv8-A ARM appendix K1.

In an implementation that does not include ARMv8.2-TTCNP this field is RES0.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

Accessing the TTBR0_EL3

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
TTBR0_EL31111000100000000

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - - n/a RW
x01 - - - RW
x11 - n/a - RW

This table applies to all instructions that can access this register.




02/05/2017 15:43

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