The DBGDSAR characteristics are:
In earlier versions of the ARM Architecture, this register defines the offset from the base address defined in DBGDRAR of the physical base address of the debug registers for the PE. ARMv8 deprecates any use of this register.
This register is part of the Debug registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
If EL1 cannot use AArch32 then the implementation of this register is OPTIONAL and deprecated.
DBGDSAR is a 64-bit register that can also be accessed as a 32-bit value. If it is accessed as a 32-bit register, bits [31:0] are read.
The DBGDSAR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Offset |
This register value is RAZ.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
Offset | |||||||||||||||||||||||||||||||
Offset | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
This register value is RAZ.
This register can be read using MRC with the following syntax:
MRC <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p14, 0, <Rt>, c2, c0, 0 | 000 | 000 | 0010 | 1110 | 0000 |
This register can be read using MRRC with the following syntax:
MRRC <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | coproc | CRm |
---|---|---|---|
p14, 0, <Rt>, <Rt2>, c2 | 0000 | 1110 | 0010 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | RO | RO | n/a | RO |
x | 0 | 1 | RO | RO | RO | RO |
x | 1 | 1 | RO | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If DBGDSCRext.UDCCdis==1, read accesses to this register from EL0 are trapped to Undefined mode.
If MDSCR_EL1.TDCC==1, read accesses to this register from EL0 are trapped to EL1.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TDRA==1, Non-secure read accesses to this register from EL0 and EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HDCR.TDRA==1, Non-secure read accesses to this register from EL0 and EL1 are trapped to Hyp mode.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TDA==1, read accesses to this register from EL0, EL1, and EL2 are trapped to EL3.
02/05/2017 15:43
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.