The FPEXC32_EL2 characteristics are:
Allows access to the AArch32 register FPEXC from AArch64 state only. Its value has no effect on execution in AArch64 state.
This register is part of the Floating-point registers functional group.
AArch64 System register FPEXC32_EL2 is architecturally mapped to AArch32 System register FPEXC.
If EL1 cannot use AArch32, this register is UNDEFINED.
If EL2 is not implemented but EL3 is implemented, and EL1 is capable of using AArch32, then this register is not RES0.
RW fields in this register reset to architecturally UNKNOWN values.
FPEXC32_EL2 is a 32-bit register.
The FPEXC32_EL2 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EX | EN | DEX | FP2V | VV | TFV | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | VECITR | IDF | 0 | 0 | IXF | UFF | OFF | DZF | IOF |
Exception bit. In ARMv8, this bit is RAZ/WI.
Enables access to the Advanced SIMD and floating-point functionality from all Exception levels, except that setting this field to 0 does not disable the following:
EN | Meaning |
---|---|
0 |
Accesses to the FPSCR, and any of the SIMD and floating-point registers Q0-Q15, including their views as D0-D31 registers or S0-S31 registers, are UNDEFINED at all Exception levels. |
1 |
This control permits access to the Advanced SIMD and floating-point functionality at all Exception levels. |
Execution of floating-point and Advanced SIMD instructions in AArch32 state can be disabled or trapped by the following controls:
See the descriptions of the controls for more information.
When executing at EL0 using AArch32:
Defined synchronous exception on floating-point execution.
This field identifies whether a synchronous exception generated by the attempted execution of an instruction was generated by an unallocated encoding. The instruction must be in the encoding space that is identified by the pseudocode function ExecutingCP10or11Instr() returning TRUE. This field also indicates whether the FPEXC32_EL2.TFV field is valid.
The meaning of this bit is:
DEX | Meaning |
---|---|
0 |
The exception was generated by the attempted execution of an unallocated instruction in the encoding space that is identified by the pseudocode function ExecutingCP10or11Instr(). If FPEXC32_EL2.TFV is RW then it is invalid and UNKNOWN. If FPEXC32_EL2.{IDF, IXF, UFF, OFF, DZF, IOF} are RW then they are invalid and UNKNOWN. |
1 |
The exception was generated during the execution of an unallocated encoding. FPEXC32_EL2.TFV is valid and indicates the cause of the exception. |
On an exception that sets this bit to 1 the exception-handling routine must clear this bit to 0.
On an implementation that both does not support trapping of floating-point exceptions and implements the AArch32 FPSCR.{Stride, Len} fields as RAZ, this bit is RES0.
FPINST2 instruction valid bit. In ARMv8, this bit is RES0.
VECITR valid bit. In ARMv8, this bit is RES0.
Trapped Fault Valid bit. Valid only when the value of FPEXC.DEX is 1. When valid, it indicates the cause of the exception and therefore whether the FPEXC.{IDF, IXF, UFF, OFF, DZF, IOF} bits are valid.
TFV | Meaning |
---|---|
0 |
The exception was caused by the execution of a floating-point VABS, VADD, VDIV, VFMA, VFMS, VFNMA, VFNMS, VMLA, VMLS, VMOV, VMUL, VNEG, VNMLA, VNMLS, VNMUL, VSQRT, or VSUB instruction when one or both of FPSCR.{Stride, Len} was non-zero. If the FPEXC.{IDF, IXF, UFF, OFF, DZF, IOF} bits are RW then they are invalid and UNKNOWN. |
1 |
FPEXC.{IDF, IXF, UFF, OFF, DZF, IOF} indicate the presence of trapped floating-point exceptions that had occurred at the time of the exception. Bits are set for all trapped exceptions that had occurred at the time of the exception. |
This bit returns a status value and ignores writes.
When the value of FPEXC.DEX is 0 and this bit is RW, this bit is invalid and UNKNOWN.
On an implementation that does not support the trapping of floating-point exceptions this bit is RAZ/WI.
On an implementation that supports the trapping of floating-point exceptions and implements FPSCR.{Stride, Len} as RAZ, this bit is RAO/WI.
Reserved, RES0.
Vector iteration count. In ARMv8, this field is RES1.
Input Denormal trapped exception bit. Valid only when the value of FPEXC.TFV is 1. When valid, it indicates whether an Input Denormal exception occurred while FPSCR.IDE was 1:
IDF | Meaning |
---|---|
0 |
Input denormal exception has not occurred. |
1 |
Input denormal exception has occurred. |
Input Denormal exceptions can occur only when FPSCR.FZ is 1.
This bit must be cleared to 0 by the exception-handling routine.
When the value of FPEXC.TFV is 0 and this bit is RW, this bit is invalid and UNKNOWN.
On an implementation that does not support the trapping of floating-point exceptions this bit is RAZ/WI.
Reserved, RES0.
Inexact trapped exception bit. Valid only when the value of FPEXC.TFV is 1. When valid, it indicates whether an Inexact exception occurred while FPSCR.IXE was 1:
IXF | Meaning |
---|---|
0 |
Inexact exception has not occurred. |
1 |
Inexact exception has occurred. |
This bit must be cleared to 0 by the exception-handling routine.
When the value of FPEXC.TFV is 0 and this bit is RW, this bit is invalid and UNKNOWN.
On an implementation that does not support the trapping of floating-point exceptions this bit is RAZ/WI.
Underflow trapped exception bit. Valid only when the value of FPEXC.TFV is 1. When valid, it indicates whether an Underflow exception occurred while FPSCR.UFE was 1:
UFF | Meaning |
---|---|
0 |
Underflow exception has not occurred. |
1 |
Underflow exception has occurred. |
Underflow trapped exceptions can occur only when FPSCR.FZ is 0.
This bit must be cleared to 0 by the exception-handling routine.
When the value of FPEXC.TFV is 0 and this bit is RW, this bit is invalid and UNKNOWN.
On an implementation that does not support the trapping of floating-point exceptions this bit is RAZ/WI.
Overflow trapped exception bit. Valid only when the value of FPEXC.TFV is 1. When valid, it indicates whether an Overflow exception occurred while FPSCR.OFE was 1:
OFF | Meaning |
---|---|
0 |
Overflow exception has not occurred. |
1 |
Overflow exception has occurred. |
This bit must be cleared to 0 by the exception-handling routine.
When the value of FPEXC.TFV is 0 and this bit is RW, this bit is invalid and UNKNOWN.
On an implementation that does not support the trapping of floating-point exceptions this bit is RAZ/WI.
Divide by Zero trapped exception bit. Valid only when the value of FPEXC.TFV is 1. When valid, it indicates whether a Divide by Zero exception occurred while FPSCR.DZE was 1:
DZF | Meaning |
---|---|
0 |
Divide by Zero exception has not occurred. |
1 |
Divide by Zero exception has occurred. |
This bit must be cleared to 0 by the exception-handling routine.
When the value of FPEXC.TFV is 0 and this bit is RW, this bit is invalid and UNKNOWN.
On an implementation that does not support the trapping of floating-point exceptions this bit is RAZ/WI.
Invalid Operation trapped exception bit. Valid only when the value of FPEXC.TFV is 1. When valid, it indicates whether an Invalid Operation exception occurred while FPSCR.IOE was 1:
IOF | Meaning |
---|---|
0 |
Invalid Operation exception has not occurred. |
1 |
Invalid Operation exception has occurred. |
This bit must be cleared to 0 by the exception-handling routine.
When the value of FPEXC.TFV is 0 and this bit is RW, this bit is invalid and UNKNOWN.
On an implementation that does not support the trapping of floating-point exceptions this bit is RAZ/WI.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
FPEXC32_EL2 | 11 | 100 | 0101 | 0011 | 000 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | - | n/a | RW |
x | 0 | 1 | - | - | RW | RW |
x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If CPTR_EL2.TFP==1, Non-secure accesses to this register from EL2 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If CPTR_EL2.FPEN==00, Non-secure accesses to this register from EL2 are trapped to EL2.
If CPTR_EL2.FPEN==10, Non-secure accesses to this register from EL2 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==1 :
If CPTR_EL2.FPEN==00, Non-secure accesses to this register from EL2 are trapped to EL2.
If CPTR_EL2.FPEN==10, Non-secure accesses to this register from EL2 are trapped to EL2.
When EL3 is implemented and is using AArch64 :
If CPTR_EL3.TFP==1, accesses to this register from EL2 and EL3 are trapped to EL3.
02/05/2017 15:43
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