TTBR0_EL1, Translation Table Base Register 0 (EL1)

The TTBR0_EL1 characteristics are:

Purpose

Holds the base address of the translation table for the initial lookup for stage 1 of the translation of an address from the lower VA range in the EL1&0 translation regime, and other information for this translation regime.

This register is part of the Virtual memory control registers functional group.

Configuration

AArch64 System register TTBR0_EL1 is architecturally mapped to AArch32 System register TTBR0.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

TTBR0_EL1 is a 64-bit register.

Field descriptions

The TTBR0_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
ASIDBADDR
BADDRCnP
313029282726252423222120191817161514131211109876543210

Any of the fields in this register are permitted to be cached in a TLB.

ASID, bits [63:48]

An ASID for the translation table base address. The TCR_EL1.A1 field selects either TTBR0_EL1.ASID or TTBR1_EL1.ASID.

If the implementation has only 8 bits of ASID, then the upper 8 bits of this field are RES0.

BADDR, bits [47:1]

Translation table base address, A[47:x] or A[51:x], bits[47:1].

Note

In an implementation that includes ARMv8.2-LPA, if the value of TCR_EL1.IPS is 110, then:

Note

In an implementation that includes ARMv8.2-LPA a TCR_EL1.IPS value of 110, that selects an IPA size of 52 bits, is permitted only when using the 64KB translation granule.

When the value of ID_AA64MMFR0_EL1.PARange indicates that the implementation does not support a 52 bit PA size, if a translation table lookup uses this register with the 64KB translation granule when the value of TCR_EL1.IPS is 110 and the value of register bits[5:2] is nonzero it is IMPLEMENTATION DEFINED whether an Address size fault is generated, but ARM deprecates not generating an Address size fault.

If the Effective value of TCR_EL1.IPS is not 110 then:

Note

This definition applies:

If any TTBR0_EL1[47:0] bit that is defined as RES0 has the value 1 when a translation table walk is performed using TTBR0_EL1, then the translation table base address might be misaligned, with effects that are CONSTRAINED UNPREDICTABLE, and must be one of the following:

The AArch64 Virtual Memory System Architecture chapter describes how x is calculated based on the value of TCR_EL1.T0SZ, the stage of translation, and the translation granule size.

CnP, bit [0]
In ARMv8.2:

Common not Private. In an implementation that includes ARMv8.2-TTCNP, indicates whether each entry that is pointed to by TTBR0_EL1 is a member of a common set that can be used by every PE in the Inner Shareable domain for which the value of TTBR0_EL1.CnP is 1.

CnPMeaning
0

The translation table entries pointed to by TTBR0_EL1, for the current translation regime and ASID, are permitted to differ from corresponding entries for TTBR0_EL1 for other PEs in the Inner Shareable domain. This is not affected by:

  • The value of TTBR0_EL1.CnP on those other PEs.
  • The value of the current ASID or, in Non-secure state, the value of the current VMID.
1

The translation table entries pointed to by TTBR0_EL1 are the same as the translation table entries for every other PE in the Inner Shareable domain for which the value of TTBR0_EL1.CnP is 1 and all of the following apply:

  • The translation table entries are pointed to by TTBR0_EL1.
  • The translation tables relate to the same translation regime.
  • The ASID is the same as the current ASID.
  • In Non-secure state, the VMID is the same as the current VMID.

When a TLB combines entries from stage 1 translation and stage 2 translation into a single entry, that entry can only be shared between different PEs if the value of the CnP bit is 1 for both stage 1 and stage 2.

Note

If the value of the TTBR0_EL1.CnP bit is 1 on multiple PEs in the same Inner Shareable domain and those TTBR0_EL1s do not point to the same translation table entries when the other conditions specified for the case when the value of CnP is 1 apply, then the results of translations are CONSTRAINED UNPREDICTABLE, see 'CONSTRAINED UNPREDICTABLE behaviors due to caching of control or data values' in the ARMv8-A ARM appendix K1.

In an implementation that does not include ARMv8.2-TTCNP this field is RES0.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

Accessing the TTBR0_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
TTBR0_EL11100000100000000
TTBR0_EL121110100100000000

Accessibility

The register is accessible as follows:

<systemreg> Control Accessibility
E2HTGENSEL0EL1EL2EL3
TTBR0_EL1xx0 - RW n/a RW
TTBR0_EL1001 - RWRWRW
TTBR0_EL1011 - n/a RWRW
TTBR0_EL1101 - RW TTBR0_EL2 RW
TTBR0_EL1111 - n/a TTBR0_EL2 RW
TTBR0_EL12xx0 - - n/a -
TTBR0_EL12001 - - - -
TTBR0_EL12011 - n/a - -
TTBR0_EL12101 - - RWRW
TTBR0_EL12111 - n/a RWRW

When HCR_EL2.E2H is 1, without explicit synchronization, access from EL3 using the mnemonic TTBR0_EL1 or TTBR0_EL12 are not guaranteed to be ordered with respect to accesses using the other mnemonic.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :




02/05/2017 15:43

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