The GICD_ICFGR<n> characteristics are:
Determines whether the corresponding interrupt is edge-triggered or level-sensitive.
This register is part of the GIC Distributor registers functional group.
This register is accessible as follows:
Security disabled | Secure | Non-secure |
---|---|---|
RW | RW | RW |
Some or all RW fields of this register have defined reset values.
These registers are available in all GIC configurations. If the GIC implementation supports two Security states, these registers are Common.
GICD_ICFGR1 is Banked for each connected PE with GICR_TYPER.Processor_Number < 8.
Accessing GICD_ICFGR1 from a PE with GICR_TYPER.Processor_Number > 7 is CONSTRAINED UNPREDICTABLE:
For SGIs and PPIs:
For each supported PPI, it is IMPLEMENTATION DEFINED whether software can program the corresponding Int_config field.
For SGIs, Int_config fields are RO, meaning that GICD_ICFGR0 is RO.
Software must disable an interrupt before the value of the corresponding programmable Int_config field is changed. GIC behavior is otherwise UNPREDICTABLE.
Changing the interrupt configuration between level-sensitive and edge-triggered (in either direction) at a time when there is a pending interrupt will leave the interrupt in an UNKNOWN pending state.
Fields corresponding to unimplemented interrupts are RAZ/WI.
GICD_ICFGR<n> is a 32-bit register.
The GICD_ICFGR<n> bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Int_config<x>, bits [2x+1:2x], for x = 0 to 15 |
Indicates whether the interrupt with ID 16n + x is level-sensitive or edge-triggered.
Int_config[0] (bit [2x]) is RES0.
Possible values of Int_config[1] (bit [2x+1]) are:
Int_config<x> | Meaning |
---|---|
0 |
Corresponding interrupt is level-sensitive. |
1 |
Corresponding interrupt is edge-triggered. |
For SGIs, Int_config[1] is RAO/WI.
For SPIs and PPIs, Int_config[1] is programmable unless the implementation supports two Security states and the bit corresponds to a Group 0 or Secure Group 1 interrupt, in which case the bit is RAZ/WI to Non-secure accesses.
When this register has an architecturally-defined reset value, this field resets to an architecturally UNKNOWN value.
GICD_ICFGR<n> can be accessed through its memory-mapped interface:
Component | Offset |
---|---|
GIC Distributor | 0x0C00 + 4n |
02/05/2017 15:43
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