The CTIDEVARCH characteristics are:
Identifies the programmers' model architecture of the CTI component.
This register is part of the Cross-Trigger Interface registers functional group.
This register is accessible as follows:
SLK | Default |
---|---|
RO | RO |
CTIDEVARCH is in the Debug power domain.
Implementation of this register is OPTIONAL.
CTIDEVARCH is a 32-bit register.
The CTIDEVARCH bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ARCHITECT | PRESENT | REVISION | ARCHID |
Defines the architecture of the component. For CTI, this is ARM Limited.
Bits [31:28] are the JEP106 continuation code, 0x4.
Bits [27:21] are the JEP106 ID code, 0x3B.
When set to 1, indicates that the DEVARCH is present.
This field is 1 in ARMv8.
Defines the architecture revision. For architectures defined by ARM this is the minor revision.
For CTI, the revision defined by ARMv8 is 0x0.
All other values are reserved.
Defines this part to be an ARMv8 debug component. For architectures defined by ARM this is further subdivided.
For CTI:
This corresponds to CTI architecture version CTIv2.
CTIDEVARCH can be accessed through the external debug interface:
Component | Offset |
---|---|
CTI | 0xFBC |
02/05/2017 15:43
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