ICH_MISR, Interrupt Controller Maintenance Interrupt State Register

The ICH_MISR characteristics are:

Purpose

Indicates which maintenance interrupts are asserted.

This register is part of:

Configuration

AArch32 System register ICH_MISR is architecturally mapped to AArch64 System register ICH_MISR_EL2.

If EL2 is not implemented, this register is RES0 from EL3.

Attributes

ICH_MISR is a 32-bit register.

Field descriptions

The ICH_MISR bit assignments are:

313029282726252423222120191817161514131211109876543210
000000000000000000000000VGrp1DVGrp1EVGrp0DVGrp0ENPLRENPUEOI

Bits [31:8]

Reserved, RES0.

VGrp1D, bit [7]

vPE Group 1 Disabled.

VGrp1DMeaning
0

vPE Group 1 Disabled maintenance interrupt not asserted.

1

vPE Group 1 Disabled maintenance interrupt asserted.

This maintenance interrupt is asserted when ICH_HCR.VGrp1DIE==1 and ICH_VMCR.VMGrp1En==0.

When this register has an architecturally-defined reset value, this field resets to 0.

VGrp1E, bit [6]

vPE Group 1 Enabled.

VGrp1EMeaning
0

vPE Group 1 Enabled maintenance interrupt not asserted.

1

vPE Group 1 Enabled maintenance interrupt asserted.

This maintenance interrupt is asserted when ICH_HCR.VGrp1EIE==1 and ICH_VMCR.VMGrp1En==1.

When this register has an architecturally-defined reset value, this field resets to 0.

VGrp0D, bit [5]

vPE Group 0 Disabled.

VGrp0DMeaning
0

vPE Group 0 Disabled maintenance interrupt not asserted.

1

vPE Group 0 Disabled maintenance interrupt asserted.

This maintenance interrupt is asserted when ICH_HCR.VGrp0DIE==1 and ICH_VMCR.VMGrp0En==0.

When this register has an architecturally-defined reset value, this field resets to 0.

VGrp0E, bit [4]

vPE Group 0 Enabled.

VGrp0EMeaning
0

vPE Group 0 Enabled maintenance interrupt not asserted.

1

vPE Group 0 Enabled maintenance interrupt asserted.

This maintenance interrupt is asserted when ICH_HCR.VGrp0EIE==1 and ICH_VMCR.VMGrp0En==1.

When this register has an architecturally-defined reset value, this field resets to 0.

NP, bit [3]

No Pending.

NPMeaning
0

No Pending maintenance interrupt not asserted.

1

No Pending maintenance interrupt asserted.

This maintenance interrupt is asserted when ICH_HCR.NPIE==1 and no List register is in pending state.

When this register has an architecturally-defined reset value, this field resets to 0.

LRENP, bit [2]

List Register Entry Not Present.

LRENPMeaning
0

List Register Entry Not Present maintenance interrupt not asserted.

1

List Register Entry Not Present maintenance interrupt asserted.

This maintenance interrupt is asserted when ICH_HCR.LRENPIE==1 and ICH_HCR.EOIcount is non-zero.

When this register has an architecturally-defined reset value, this field resets to 0.

U, bit [1]

Underflow.

UMeaning
0

Underflow maintenance interrupt not asserted.

1

Underflow maintenance interrupt asserted.

This maintenance interrupt is asserted when ICH_HCR.UIE==1 and zero or one of the List register entries are marked as a valid interrupt, that is, if the corresponding ICH_LRC<n>.State bits do not equal 0x0.

When this register has an architecturally-defined reset value, this field resets to 0.

EOI, bit [0]

End Of Interrupt.

EOIMeaning
0

End Of Interrupt maintenance interrupt not asserted.

1

End Of Interrupt maintenance interrupt asserted.

This maintenance interrupt is asserted when at least one bit in ICH_EISR is 1.

When this register has an architecturally-defined reset value, this field resets to 0.

Accessing the ICH_MISR

This register can be read using MRC with the following syntax:

MRC <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 4, <Rt>, c12, c11, 2100010110011111011

Accessibility

The register is accessible as follows:

Control Accessibility
TGENSEL0EL1EL2EL3
x0 - - n/a -
01 - - RORO
11 - n/a RORO

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :




02/05/2017 15:43

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