ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0

The ID_AA64ISAR0_EL1 characteristics are:

Purpose

Provides information about the instructions implemented in AArch64 state.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.

This register is part of the Identification registers functional group.

Configuration

There are no configuration notes.

Attributes

ID_AA64ISAR0_EL1 is a 64-bit register.

Field descriptions

The ID_AA64ISAR0_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
00000000000000000000000000000000
RDM0000AtomicCRC32SHA2SHA1AES0000
313029282726252423222120191817161514131211109876543210

Bits [63:32]

Reserved, RES0.

RDM, bits [31:28]
In ARMv8.2 and ARMv8.1:

SQRDMLAH and SQRDMLSH instructions implemented in AArch64 state. Defined values are:

RDMMeaning
0000

No SQRDMLAH and SQRDMLSH instructions implemented.

0001

SQRDMLAH and SQRDMLSH instructions implemented.

All other values are reserved.

In ARMv8.0 the only permitted value is 0000.

From ARMv8.1 the only permitted value is 0001. This feature is identified by the name ARMv8.1-RDMA.


In ARMv8.0:

Reserved, RES0.

Bits [27:24]

Reserved, RES0.

Atomic, bits [23:20]
In ARMv8.2 and ARMv8.1:

Atomic instructions implemented in AArch64 state. Defined values are:

AtomicMeaning
0000

No Atomic instructions implemented.

0010

LDADD, LDCLR, LDEOR, LDSET, LDSMAX, LDSMIN, LDUMAX, LDUMIN, CAS, CASP, and SWP instructions implemented.

All other values are reserved.

In ARMv8.0 the only permitted value is 0000.

From ARMv8.1 the only permitted value is 0010. This feature is identified by the name ARMv8.1-LSE.


In ARMv8.0:

Reserved, RES0.

CRC32, bits [19:16]

CRC32 instructions implemented in AArch64 state. Defined values are:

CRC32Meaning
0000

No CRC32 instructions implemented.

0001

CRC32B, CRC32H, CRC32W, CRC32X, CRC32CB, CRC32CH, CRC32CW, and CRC32CX instructions implemented.

All other values are reserved.

In ARMv8.0 the permitted values are 0000 and 0001.

From ARMv8.1 the only permitted value is 0001.

SHA2, bits [15:12]

SHA2 instructions implemented in AArch64 state. Defined values are:

SHA2Meaning
0000

No SHA2 instructions implemented.

0001

SHA256H, SHA256H2, SHA256SU0, and SHA256SU1 instructions implemented.

All other values are reserved.

SHA1, bits [11:8]

SHA1 instructions implemented in AArch64 state. Defined values are:

SHA1Meaning
0000

No SHA1 instructions implemented.

0001

SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0, and SHA1SU1 instructions implemented.

All other values are reserved.

AES, bits [7:4]

AES instructions implemented in AArch64 state. Defined values are:

AESMeaning
0000

No AES instructions implemented.

0001

AESE, AESD, AESMC, and AESIMC instructions implemented.

0010

As for 0001, plus PMULL/PMULL2 instructions operating on 64-bit data quantities.

All other values are reserved.

Bits [3:0]

Reserved, RES0.

Accessing the ID_AA64ISAR0_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
ID_AA64ISAR0_EL11100000000110000

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RO n/a RO
x01 - RORORO
x11 - n/a RORO

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :




02/05/2017 15:43

Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.