The TTBR0_EL2 characteristics are:
When HCR_EL2.E2H is 0, holds the base address of the translation table for the initial lookup for stage 1 of an address translation in the EL2 translation regime, and other information for this translation regime.
When HCR_EL2.E2H is 1, holds the base address of the translation table for the initial lookup for stage 1 of the translation of an address from the lower VA range in the EL2&0 translation regime, and other information for this translation regime.
This register is part of:
AArch64 System register TTBR0_EL2 is architecturally mapped to AArch32 System register HTTBR.
If EL2 is not implemented, this register is RES0 from EL3.
RW fields in this register reset to architecturally UNKNOWN values.
TTBR0_EL2 is a 64-bit register.
The TTBR0_EL2 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
ASID | BADDR | ||||||||||||||||||||||||||||||
BADDR | CnP | ||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Any of the fields in this register are permitted to be cached in a TLB.
When HCR_EL2.E2H is 0, this field is RES0.
When HCR_EL2.E2H is 1, it holds an ASID for the translation table base address. The TCR_EL2.A1 field selects either TTBR0_EL2.ASID or TTBR1_EL2.ASID.
If the implementation has only 8 bits of ASID, then the upper 8 bits of this field are RES0.
Reserved, RES0.
Translation table base address, A[47:x] or A[51:x], bits[47:1].
In an implementation that includes ARMv8.2-LPA, if the value of TCR_EL2.{I}PS is 110, then:
In an implementation that includes ARMv8.2-LPA:
When the value of ID_AA64MMFR0_EL1.PARange indicates that the implementation does not support a 52 bit PA size, if a translation table lookup uses this register with the 64KB translation granule when the value of TCR_EL2.{I}PS is 110 and the value of register bits[5:2] is nonzero it is IMPLEMENTATION DEFINED whether an Address size fault is generated, but ARM deprecates not generating an Address size fault.
If the Effective value of TCR_EL2.{I}PS is not 110 then:
This definition applies:
If any TTBR0_EL2[47:0] bit that is defined as RES0 has the value 1 when a translation table walk is performed using TTBR0_EL2, then the translation table base address might be misaligned, with effects that are CONSTRAINED UNPREDICTABLE, and must be one of the following:
The AArch64 Virtual Memory System Architecture chapter describes how x is calculated based on the value of TCR_EL2.T0SZ, the stage of translation, and the translation granule size.
Common not Private. In an implementation that includes ARMv8.2-TTCNP, indicates whether each entry that is pointed to by TTBR0_EL2 is a member of a common set that can be used by every PE in the Inner Shareable domain for which the value of TTBR0_EL2.CnP is 1.
CnP | Meaning |
---|---|
0 |
The translation table entries pointed to by TTBR0_EL2 for the current translation regime, and ASID if applicable, are permitted to differ from corresponding entries for TTBR0_EL2 for other PEs in the Inner Shareable domain. This is not affected by:
|
1 |
The translation table entries pointed to by TTBR0_EL2 are the same as the translation table entries for every other PE in the Inner Shareable domain for which the value of TTBR0_EL2.CnP is 1 and all of the following apply:
|
If the value of the TTBR0_EL2.CnP bit is 1 on multiple PEs in the same Inner Shareable domain and those TTBR0_EL2s do not point to the same translation table entries when the other conditions specified for the case when the value of CnP is 1 apply, then the results of translations are CONSTRAINED UNPREDICTABLE, see 'CONSTRAINED UNPREDICTABLE behaviors due to caching of control or data values' in the ARMv8-A ARM appendix K1.
In an implementation that does not include ARMv8.2-TTCNP this field is RES0.
Reserved, RES0.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
TTBR0_EL2 | 11 | 100 | 0010 | 0000 | 000 |
TTBR0_EL1 | 11 | 000 | 0010 | 0000 | 000 |
The register is accessible as follows:
<systemreg> | Control | Accessibility | |||||
---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | |
TTBR0_EL2 | x | x | 0 | - | - | n/a | RW |
TTBR0_EL2 | 0 | 0 | 1 | - | - | RW | RW |
TTBR0_EL2 | 0 | 1 | 1 | - | n/a | RW | RW |
TTBR0_EL2 | 1 | 0 | 1 | - | - | RW | RW |
TTBR0_EL2 | 1 | 1 | 1 | - | n/a | RW | RW |
TTBR0_EL1 | x | x | 0 | - | TTBR0_EL1 | n/a | TTBR0_EL1 |
TTBR0_EL1 | 0 | 0 | 1 | - | TTBR0_EL1 | TTBR0_EL1 | TTBR0_EL1 |
TTBR0_EL1 | 0 | 1 | 1 | - | n/a | TTBR0_EL1 | TTBR0_EL1 |
TTBR0_EL1 | 1 | 0 | 1 | - | TTBR0_EL1 | RW | TTBR0_EL1 |
TTBR0_EL1 | 1 | 1 | 1 | - | n/a | RW | TTBR0_EL1 |
When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic TTBR0_EL2 or TTBR0_EL1 are not guaranteed to be ordered with respect to accesses using the other mnemonic.
02/05/2017 15:43
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