The ICH_VMCR_EL2 characteristics are:
Enables the hypervisor to save and restore the virtual machine view of the GIC state.
This register is part of:
AArch64 System register ICH_VMCR_EL2 is architecturally mapped to AArch32 System register ICH_VMCR.
If EL2 is not implemented, this register is RES0 from EL3.
ICH_VMCR_EL2 is a 32-bit register.
The ICH_VMCR_EL2 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VPMR | VBPR0 | VBPR1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | VEOIM | 0 | 0 | 0 | 0 | VCBPR | VFIQEn | VAckCtl | VENG1 | VENG0 |
Virtual Priority Mask. The priority mask level for the virtual CPU interface. If the priority of a pending virtual interrupt is higher than the value indicated by this field, the interface signals the virtual interrupt to the PE.
This field is an alias of ICV_PMR_EL1.Priority.
Virtual Binary Point Register, Group 0. Defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field. The group priority field determines Group 0 interrupt preemption, and also determines Group 1 interrupt preemption if ICH_VMCR_EL2.VCBPR == 1.
This field is an alias of ICV_BPR0_EL1.BinaryPoint.
The minimum value of this field is determined by ICH_VTR_EL2.PREbits. An attempt to program the binary point field to a value less than the minimum value sets the field to the minimum value.
Virtual Binary Point Register, Group 1. Defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field. The group priority field determines Group 1 interrupt preemption if ICH_VMCR_EL2.VCBPR == 0.
This field is an alias of ICV_BPR1_EL1.BinaryPoint.
Reserved, RES0.
Virtual EOI mode. Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt:
VEOIM | Meaning |
---|---|
0 |
ICV_EOIR0_EL1 and ICV_EOIR1_EL1 provide both priority drop and interrupt deactivation functionality. Accesses to ICV_DIR_EL1 are UNPREDICTABLE. |
1 |
ICV_EOIR0_EL1 and ICV_EOIR1_EL1 provide priority drop functionality only. ICV_DIR_EL1 provides interrupt deactivation functionality. |
This bit is an alias of ICV_CTLR_EL1.EOImode.
Reserved, RES0.
Virtual Common Binary Point Register. Possible values of this bit are:
VCBPR | Meaning |
---|---|
0 |
ICV_BPR0_EL1 determines the preemption group for virtual Group 0 interrupts only. ICV_BPR1_EL1 determines the preemption group for virtual Group 1 interrupts. |
1 |
ICV_BPR0_EL1 determines the preemption group for both virtual Group 0 and virtual Group 1 interrupts. Reads of ICV_BPR1_EL1 return ICV_BPR0_EL1 plus one, saturated to 0b111. Writes to ICV_BPR1_EL1 are ignored. |
This field is an alias of ICV_CTLR_EL1.CBPR.
Virtual FIQ enable. Possible values of this bit are:
VFIQEn | Meaning |
---|---|
0 |
Group 0 virtual interrupts are presented as virtual IRQs. |
1 |
Group 0 virtual interrupts are presented as virtual FIQs. |
This bit is an alias of GICV_CTLR.FIQEn.
In implementations where the Non-secure copy of ICC_SRE_EL1.SRE is always 1, this bit is RES1.
Virtual AckCtl. Possible values of this bit are:
VAckCtl | Meaning |
---|---|
0 |
If the highest priority pending interrupt is Group 1, a read of GICV_IAR or GICV_HPPIR returns an INTID of 1022. |
1 |
If the highest priority pending interrupt is Group 1, a read of GICV_IAR or GICV_HPPIR returns the INTID of the corresponding interrupt. |
This bit is an alias of GICV_CTLR.AckCtl.
This field is supported for backwards compatibility with GICv2. ARM deprecates the use of this field.
In implementations where the Non-secure copy of ICC_SRE_EL1.SRE is always 1, this bit is RES0.
Virtual Group 1 interrupt enable. Possible values of this bit are:
VENG1 | Meaning |
---|---|
0 |
Virtual Group 1 interrupts are disabled. |
1 |
Virtual Group 1 interrupts are enabled. |
This bit is an alias of ICV_IGRPEN1_EL1.Enable.
Virtual Group 0 interrupt enable. Possible values of this bit are:
VENG0 | Meaning |
---|---|
0 |
Virtual Group 0 interrupts are disabled. |
1 |
Virtual Group 0 interrupts are enabled. |
This bit is an alias of ICV_IGRPEN0_EL1.Enable.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op1 | CRn | CRm | op2 |
---|---|---|---|---|
ICH_VMCR_EL2 | 100 | 1100 | 1011 | 111 |
The register is accessible as follows:
Control | Accessibility | ||||
---|---|---|---|---|---|
TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | 0 | - | - | n/a | RW |
0 | 1 | - | - | RW | RW |
1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
When EL2 is using System register access, EL1 using either System register or memory-mapped access must be supported.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_SRE_EL2.SRE==0, accesses to this register from EL2 are trapped to EL2.
If ICC_SRE_EL3.SRE==0, accesses to this register from EL3 are trapped to EL3.
02/05/2017 15:43
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