CNTSR, Counter Status Register

The CNTSR characteristics are:

Purpose

Provides counter frequency status information.

This register is part of the Generic Timer registers functional group.

Usage constraints

This register is accessible as follows:

Default
RO

In a system that supports Secure and Non-secure memory maps the CNTControlBase frame, that includes this register, is implemented only in the Secure memory map.

Configuration

The power domain of CNTSR is IMPLEMENTATION DEFINED.

Some or all fields in this register have defined reset values. These apply only on a reset of the reset domain in which the register is implemented. The register is not affected by a reset of any other reset domain. For more information see 'Power and reset domains for the system level implementation of the Generic Timer' in Chapter I1 of the ARMv8 ARM.

Attributes

CNTSR is a 32-bit register.

Field descriptions

The CNTSR bit assignments are:

313029282726252423222120191817161514131211109876543210
FCACK000000DBGH0

FCACK, bits [31:8]

Frequency change acknowledge. Indicates the currently selected entry in the Frequency modes table, see 'The Frequency modes table' in Chapter I1 of the ARMv8 ARM.

When this register has an architecturally-defined reset value, this field resets to 0.

Bits [7:2]

Reserved, RES0.

DBGH, bit [1]

Indicates whether the counter is halted because the Halt-on-Debug signal is asserted:

DBGHMeaning
0

Counter is not halted.

1

Counter is halted.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bit [0]

Reserved, RES0.

Accessing the CNTSR

CNTSR can be accessed through its memory-mapped interface:

ComponentFrameOffset
TimerCNTControlBase 0x004



02/05/2017 15:43

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