IFSR, Instruction Fault Status Register

The IFSR characteristics are:

Purpose

Holds status information about the last instruction fault.

This register is part of the Exception and fault handling registers functional group.

Configuration

AArch32 System register IFSR is architecturally mapped to AArch64 System register IFSR32_EL2.

The current translation table format determines which format of the register is used.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

IFSR is a 32-bit register.

Field descriptions

The IFSR bit assignments are:

When TTBCR.EAE==0:

313029282726252423222120191817161514131211109876543210
000000000000000FnV000ExT0FS[4]LPAE00000FS[3:0]

Bits [31:17]

Reserved, RES0.

FnV, bit [16]

FAR not Valid, for a Synchronous external abort other than a Synchronous external abort on a translation table walk.

FnVMeaning
0

IFAR is valid.

1

IFAR is not valid, and holds an UNKNOWN value.

This field is only valid for a Synchronous external abort other than a Synchronous external abort on a translation table walk. It is RES0 for all other Prefetch Abort exceptions.

Bits [15:13]

Reserved, RES0.

ExT, bit [12]

External abort type. This bit can be used to provide an IMPLEMENTATION DEFINED classification of external aborts.

In an implementation that does not provide any classification of external aborts, this bit is RES0.

For aborts other than external aborts this bit always returns 0.

Bit [11]

Reserved, RES0.

FS[4], bit [10]

See FS[3:0], bits [3:0] for description of the FS field.

LPAE, bit [9]

On taking a Data Abort exception, this bit is set as follows:

LPAEMeaning
0

Using the Short-descriptor translation table formats.

1

Using the Long-descriptor translation table formats.

Hardware does not interpret this bit to determine the behavior of the memory system, and therefore software can set this bit to 0 or 1 without affecting operation.

Bits [8:4]

Reserved, RES0.

FS[3:0], bits [3:0]

Fault status bits. Interpreted with bit [10]. Possible values of FS[4:0] are:

FSMeaning
00001

PC alignment fault

00010

Debug exception

00011

Access flag fault, level 1

00101

Translation fault, level 1

00110

Access flag fault, level 2

00111

Translation fault, level 2

01000

Synchronous external abort, not on translation table walk

01001

Domain fault, level 1

01011

Domain fault, level 2

01100

Synchronous external abort, on translation table walk, level 1

01101

Permission fault, level 1

01110

Synchronous external abort, on translation table walk, level 2

01111

Permission fault, level 2

10000

TLB conflict abort

10100

IMPLEMENTATION DEFINED fault (Lockdown fault)

11001

Synchronous parity or ECC error on memory access, not on translation table walk

11100

Synchronous parity or ECC error on translation table walk, level 1

11110

Synchronous parity or ECC error on translation table walk, level 2

All other values are reserved.

When the RAS Extension is implemented, 11001, 11100, and 11110, are reserved.

For more information about the lookup level associated with a fault, see 'The level associated with MMU faults on a Short-descriptor translation table lookup' in the ARMv8 ARM.

When TTBCR.EAE==1:

313029282726252423222120191817161514131211109876543210
000000000000000FnV000ExT00LPAE000STATUS

Bits [31:17]

Reserved, RES0.

FnV, bit [16]

FAR not Valid, for a Synchronous external abort other than a Synchronous external abort on a translation table walk.

FnVMeaning
0

IFAR is valid.

1

IFAR is not valid, and holds an UNKNOWN value.

This field is only valid for a Synchronous external abort other than a Synchronous external abort on a translation table walk. It is RES0 for all other Prefetch Abort exceptions.

Bits [15:13]

Reserved, RES0.

ExT, bit [12]

External abort type. This bit can be used to provide an IMPLEMENTATION DEFINED classification of external aborts.

In an implementation that does not provide any classification of external aborts, this bit is RES0.

For aborts other than external aborts this bit always returns 0.

Bits [11:10]

Reserved, RES0.

LPAE, bit [9]

On taking a Data Abort exception, this bit is set as follows:

LPAEMeaning
0

Using the Short-descriptor translation table formats.

1

Using the Long-descriptor translation table formats.

Hardware does not interpret this bit to determine the behavior of the memory system, and therefore software can set this bit to 0 or 1 without affecting operation.

Bits [8:6]

Reserved, RES0.

STATUS, bits [5:0]

Fault status bits. Possible values of this field are:

STATUSMeaning
000000

Address size fault in TTBR0 or TTBR1

000001

Address size fault, level 1

000010

Address size fault, level 2

000011

Address size fault, level 3

000101

Translation fault, level 1

000110

Translation fault, level 2

000111

Translation fault, level 3

001001

Access flag fault, level 1

001010

Access flag fault, level 2

001011

Access flag fault, level 3

001101

Permission fault, level 1

001110

Permission fault, level 2

001111

Permission fault, level 3

010000

Synchronous external abort, not on translation table walk

010101

Synchronous external abort, on translation table walk, level 1

010110

Synchronous external abort, on translation table walk, level 2

010111

Synchronous external abort, on translation table walk, level 3

011000

Synchronous parity or ECC error on memory access, not on translation table walk

011101

Synchronous parity or ECC error on memory access on translation table walk, level 1

011110

Synchronous parity or ECC error on memory access on translation table walk, level 2

011111

Synchronous parity or ECC error on memory access on translation table walk, level 3

100001

PC alignment fault

100010

Debug exception

110000

TLB conflict abort

All other values are reserved.

When the RAS Extension is implemented, 011000, 011101, 011110, and 011111, are reserved.

For more information about the lookup level associated with a fault, see 'The level associated with MMU faults on a Long-descriptor translation table lookup' in the ARMv8 ARM.

Accessing the IFSR

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 0, <Rt>, c5, c0, 1000001010111110000

Accessibility

The register is accessible as follows:

Configuration Control Accessibility Instance
E2HTGENSEL0EL1EL2EL3
EL3 not implemented xx0 - RW n/a n/a IFSR
EL3 not implemented x01 - RWRW n/a IFSR
EL3 not implemented x11 - n/a RW n/a IFSR
EL3 using AArch64xx0 - RW n/a n/a IFSR
EL3 using AArch64x01 - RWRW n/a IFSR
EL3 using AArch64x11 - n/a RW n/a IFSR
EL3 using AArch32xx0 - n/a n/a RWIFSR_s
EL3 using AArch32x01 - RWRWRWIFSR_ns
EL3 using AArch32x11 - n/a RWRWIFSR_ns

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :




02/05/2017 15:43

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