The CPACR characteristics are:
Controls access to trace, and to Advanced SIMD and floating-point functionality from EL0, EL1, and EL3.
In an implementation that includes EL2, the CPACR has no effect on instructions executed at EL2.
This register is part of the Other system control registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register CPACR is architecturally mapped to AArch64 System register CPACR_EL1.
Bits in the NSACR control Non-secure access to the CPACR fields. See the field descriptions for more information.
In the register field descriptions, controls are described as applying at specified Privilege levels. This is because, in Secure state, a PL1 control:
See 'Security state, Exception levels, and AArch32 execution privilege' in the ARMv8 ARM, section G1.7.
Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch32. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.
CPACR is a 32-bit register.
The CPACR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ASEDIS | 0 | 0 | TRCDIS | 0 | 0 | 0 | 0 | cp11 | cp10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Disables PL0 and PL1 execution of Advanced SIMD instructions.
ASEDIS | Meaning |
---|---|
0 |
This control permits execution of Advanced SIMD instructions at PL0 and PL1. |
1 |
All instruction encodings that are Advanced SIMD instruction encodings, but are not also floating-point instruction encodings, are UNDEFINED at PL0 and PL1. |
If the implementation does not include Advanced SIMD and floating-point functionality, this field is RES0. Otherwise, it is IMPLEMENTATION DEFINED whether this field is implemented as a RW field. If it is not implemented as a RW field, it is RAZ/WI.
If EL3 is implemented and is using AArch32, and the value of NSACR.NSASEDIS is 1, this field behaves as RAO/WI in Non-secure state, regardless of its actual value. This applies even if the field is implemented as RAZ/WI.
For the list of instructions affected by this field, see 'Controls of Advanced SIMD operation that do not apply to floating-point operation' in the ARMv8 ARM, section E1.
See the description of CPACR.cp10 for a list of other controls that can disable or trap execution of Advanced SIMD instructions in AArch32 state.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.
Reserved, RES0.
Traps PL0 and PL1 System register accesses to all implemented trace registers to Undefined mode.
TRCDIS | Meaning |
---|---|
0 |
This control has no effect on PL0 and PL1 System register accesses to trace registers. |
1 |
PL0 and PL1 System register accesses to all implemented trace registers are trapped to Undefined mode. |
If the implementation does not include a trace macrocell, or does not include a System register interface to the trace macrocell registers, this field is RES0. Otherwise, it is IMPLEMENTATION DEFINED whether this field is implemented as a RW field. If it is not implemented as a RW field, it is RAZ/WI.
If EL3 is implemented and is using AArch32, and the value of NSACR.NSTRCDIS is 1, this field behaves as RAO/WI in Non-secure state, regardless of its actual value. This applies even if the field is implemented as RAZ/WI.
System register accesses to the trace registers can have side-effects. When a System register access is trapped, any side-effects that are normally associated with the access do not occur before the exception is taken.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to a value that is architecturally UNKNOWN.
Reserved, RES0.
The value of this field is ignored. If this field is programmed with a different value to the cp10 field then this field is UNKNOWN on a direct read of the CPACR.
If the implementation does not include Advanced SIMD and floating-point functionality, this field is RES0.
In Non-secure state, if EL3 is implemented and is using AArch32, when the value of NSACR.cp10 is 0, this field behaves as RAZ/WI, regardless of its actual value.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.
Defines the access rights for the floating-point and Advanced SIMD functionality. Possible values of the field are:
cp10 | Meaning |
---|---|
00 |
PL0 and PL1 accesses to floating-point and Advanced SIMD registers or instructions are UNDEFINED. |
01 |
PL0 accesses to floating-point and Advanced SIMD registers or instructions are UNDEFINED. |
10 |
Reserved. The effect of programming this field to this value is CONSTRAINED UNPREDICTABLE. See 'Unallocated values in fields of AArch32 System registers and translation table entries' in the ARMv8 ARM, section J1.1.11. |
11 |
This control permits full access to the floating-point and Advanced SIMD functionality from PL0 and PL1. |
The floating-point and Advanced SIMD features controlled by these fields are:
The CPACR has no effect on floating-point and Advanced SIMD accesses from PL2. These can be disabled by the HCPTR.TCP10 field.
If the implementation does not include Advanced SIMD and floating-point functionality, this field is RES0.
In Non-secure state, if EL3 is implemented and is using AArch32, when the value of NSACR.cp10 is 0, this field behaves as RAZ/WI, regardless of its actual value.
Execution of floating-point and Advanced SIMD instructions in AArch32 state can be disabled or trapped by the following controls:
See the descriptions of the controls for more information.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.
Reserved, RES0.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c1, c0, 2 | 000 | 010 | 0001 | 1111 | 0000 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RW | n/a | RW |
x | 0 | 1 | - | RW | RW | RW |
x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If CPTR_EL2.TCPAC==1, Non-secure accesses to this register from EL1 are trapped to EL2.
If HSTR_EL2.T1==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If CPTR_EL2.TCPAC==1, Non-secure accesses to this register from EL1 are trapped to EL2.
If HSTR_EL2.T1==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HCPTR.TCPAC==1, Non-secure accesses to this register from EL1 are trapped to Hyp mode.
If HSTR.T1==1, Non-secure accesses to this register from EL1 are trapped to Hyp mode.
When EL3 is implemented and is using AArch64 :
If CPTR_EL3.TCPAC==1, accesses to this register from EL1 and EL2 are trapped to EL3.
02/05/2017 15:43
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