DCZID_EL0, Data Cache Zero ID register

The DCZID_EL0 characteristics are:

Purpose

Indicates the block size that is written with byte values of 0 by the DC ZVA (Data Cache Zero by Address) system instruction.

This register is part of the Identification registers functional group.

Configuration

There are no configuration notes.

Attributes

DCZID_EL0 is a 32-bit register.

Field descriptions

The DCZID_EL0 bit assignments are:

313029282726252423222120191817161514131211109876543210
000000000000000000000000000DZPBS

Bits [31:5]

Reserved, RES0.

DZP, bit [4]

Data Zero prohibited. Permitted values are:

DZPMeaning
0

DC ZVA instruction is permitted.

1

DC ZVA instruction is prohibited.

The value read from this field is governed by the access state and the values of the HCR_EL2.TDZ and SCTLR_EL1.DZE bits.

BS, bits [3:0]

Log2 of the block size in words. The maximum size supported is 2KB (value == 9).

Accessing the DCZID_EL0

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
DCZID_EL01101100000000111

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0RORO n/a RO
x01RORORORO
x11RO n/a RORO

This table applies to all instructions that can access this register.




02/05/2017 15:43

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