PMINTENCLR_EL1, Performance Monitors Interrupt Enable Clear register

The PMINTENCLR_EL1 characteristics are:

Purpose

Disables the generation of interrupt requests on overflows from the Cycle Count Register, PMCCNTR_EL0, and the event counters PMEVCNTR<n>_EL0. Reading the register shows which overflow interrupt requests are enabled.

This register is part of the Performance Monitors registers functional group.

Usage constraints

This register is accessible as follows:

OffDLKOSLKEPMADSLKDefault
ErrorErrorErrorErrorRORW

Configuration

External register PMINTENCLR_EL1 is architecturally mapped to AArch64 System register PMINTENCLR_EL1.

External register PMINTENCLR_EL1 is architecturally mapped to AArch32 System register PMINTENCLR.

PMINTENCLR_EL1 is in the Core power domain. RW fields in this register reset to architecturally UNKNOWN values. These apply on a Warm or Cold reset. The register is not affected by an External debug reset.

Attributes

PMINTENCLR_EL1 is a 32-bit register.

Field descriptions

The PMINTENCLR_EL1 bit assignments are:

313029282726252423222120191817161514131211109876543210
CP<n>, bit [n]

C, bit [31]

PMCCNTR_EL0 overflow interrupt request disable bit. Possible values are:

CMeaning
0

When read, means the cycle counter overflow interrupt request is disabled. When written, has no effect.

1

When read, means the cycle counter overflow interrupt request is enabled. When written, disables the cycle count overflow interrupt request.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

P<n>, bit [n], for n = 0 to 30

Event counter overflow interrupt request disable bit for PMEVCNTR<n>_EL0.

Bits [30:N] are RAZ/WI. N is the value in PMCFGR.N.

Possible values are:

P<n>Meaning
0

When read, means that the PMEVCNTR<n>_EL0 event counter interrupt request is disabled. When written, has no effect.

1

When read, means that the PMEVCNTR<n>_EL0 event counter interrupt request is enabled. When written, disables the PMEVCNTR<n>_EL0 interrupt request.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Accessing the PMINTENCLR_EL1

PMINTENCLR_EL1 can be accessed through the external debug interface:

ComponentOffset
PMU 0xC60



02/05/2017 15:43

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