DACR32_EL2, Domain Access Control Register

The DACR32_EL2 characteristics are:

Purpose

Allows access to the AArch32 DACR register from AArch64 state only. Its value has no effect on execution in AArch64 state.

This register is part of the Virtual memory control registers functional group.

Configuration

AArch64 System register DACR32_EL2 is architecturally mapped to AArch32 System register DACR.

If EL1 does not support AArch32, this register is UNDEFINED.

If EL2 is not implemented but EL3 is implemented, and EL1 is capable of using AArch32, then this register is not RES0.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

DACR32_EL2 is a 32-bit register.

Field descriptions

The DACR32_EL2 bit assignments are:

313029282726252423222120191817161514131211109876543210
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

D<n>, bits [2n+1:2n], for n = 0 to 15

Domain n access permission, where n = 0 to 15. Permitted values are:

D<n>Meaning
00

No access. Any access to the domain generates a Domain fault.

01

Client. Accesses are checked against the permission bits in the translation tables.

11

Manager. Accesses are not checked against the permission bits in the translation tables.

The value 10 is reserved.

Accessing the DACR32_EL2

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
DACR32_EL21110000110000000

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - - n/a RW
x01 - - RWRW
x11 - n/a RWRW

This table applies to all instructions that can access this register.




02/05/2017 15:43

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