The APSR characteristics are:
Hold program status and control information.
This register is part of the Process state registers functional group.
The APSR can be read using the MRS instruction and written using the MSR (immediate) or MSR (register) instructions. For more details on the instruction syntax, see 'PSTATE and banked register access instructions' in the ARMv8 ARM, section F1.5.
There are no traps or enables affecting this register.
There is one instance of this register that is used in both Secure and Non-secure states.
APSR is a 32-bit register.
The APSR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
N | Z | C | V | Q | 0 | 0 | 0 | 0 | 0 | 0 | 0 | GE | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
Negative condition flag. Set to bit[31] of the result of the last flag-setting instruction. If the result is regarded as a two's complement signed integer, then N is set to 1 if the result was negative, and N is set to 0 if the result was positive or zero.
Zero condition flag. Set to 1 if the result of the last flag-setting instruction was zero, and to 0 otherwise. A result of zero often indicates an equal result from a comparison.
Carry condition flag. Set to 1 if the last flag-setting instruction resulted in a carry condition, for example an unsigned overflow on an addition.
Overflow condition flag. Set to 1 if the last flag-setting instruction resulted in an overflow condition, for example a signed overflow on an addition.
Cumulative saturation bit. Set to 1 to indicate that overflow or saturation occurred in some instructions.
Reserved, RES0.
Greater than or Equal flags, for parallel addition and subtraction.
Reserved, RES0.
Reserved, RES1.
Reserved, RES0.
02/05/2017 15:43
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