The ICC_SRE_EL1 characteristics are:
Controls whether the System register interface or the memory-mapped interface to the GIC CPU interface is used for EL1.
This register is part of:
AArch64 System register ICC_SRE_EL1 (S) is architecturally mapped to AArch32 System register ICC_SRE (S) .
AArch64 System register ICC_SRE_EL1 (NS) is architecturally mapped to AArch32 System register ICC_SRE (NS) .
ICC_SRE_EL1 is a 32-bit register.
The ICC_SRE_EL1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DIB | DFB | SRE |
Reserved, RES0.
Disable IRQ bypass.
DIB | Meaning |
---|---|
0 |
IRQ bypass enabled. |
1 |
IRQ bypass disabled. |
If EL3 is implemented and GICD_CTLR.DS == 0, this field is a read-only alias of ICC_SRE_EL3.DIB.
If EL3 is implemented and GICD_CTLR.DS == 1, and EL2 is not implemented, this field is a read-write alias of ICC_SRE_EL3.DIB.
If EL3 is not implemented or GICD_CTLR.DS == 1, and EL2 is implemented, this field is a read-only alias of ICC_SRE_EL2.DIB.
In systems that do not support IRQ bypass, this field is RAO/WI.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.
Disable FIQ bypass.
DFB | Meaning |
---|---|
0 |
FIQ bypass enabled. |
1 |
FIQ bypass disabled. |
If EL3 is implemented and GICD_CTLR.DS == 0, this field is a read-only alias of ICC_SRE_EL3.DFB.
If EL3 is implemented and GICD_CTLR.DS == 1, and EL2 is not implemented, this field is a read-write alias of ICC_SRE_EL3.DFB.
If EL3 is not implemented or GICD_CTLR.DS == 1, and EL2 is implemented, this field is a read-only alias of ICC_SRE_EL2.DFB.
In systems that do not support FIQ bypass, this field is RAO/WI.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.
System Register Enable.
SRE | Meaning |
---|---|
0 |
The memory-mapped interface must be used. Access at EL1 to any ICC_* System register other than ICC_SRE_EL1 is trapped to EL1. |
1 |
The System register interface for the current Security state is enabled. |
If software changes this bit from 1 to 0 in the Secure instance of this register, the results are UNPREDICTABLE.
If an implementation supports only a System register interface to the GIC CPU interface, this bit is RAO/WI.
If EL3 is implemented and ICC_SRE_EL3.SRE==0 the Secure copy of this bit is RAZ/WI.
If EL2 is implemented and ICC_SRE_EL2.SRE==0 the Non-secure copy of this bit is RAZ/WI.
If EL3 is implemented and ICC_SRE_EL3.SRE==0 the Non-secure copy of this bit is RAZ/WI.
GICv3 implementations that do not require GICv2 compatibility might choose to make this bit RAO/WI. The following options are supported:
A VM using only virtual interrupts might still use memory-mapped access if the Non-secure copy of ICC_SRE_EL1.SRE is not RAO/WI.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op1 | CRn | CRm | op2 |
---|---|---|---|---|
ICC_SRE_EL1 | 000 | 1100 | 1100 | 101 |
The register is accessible as follows:
Control | Accessibility | Instance | ||||
---|---|---|---|---|---|---|
TGE | NS | EL0 | EL1 | EL2 | EL3 | |
x | 0 | - | RW | n/a | RW | ICC_SRE_EL1_s |
0 | 1 | - | RW | RW | RW | ICC_SRE_EL1_ns |
1 | 1 | - | n/a | RW | RW | ICC_SRE_EL1_ns |
This table applies to all instructions that can access this register.
Execution with ICC_SRE_EL1.SRE set to 0 might make some System registers UNKNOWN.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_SRE_EL3.Enable==0, and EL3 is implemented, accesses to this register from EL1 and EL2 are trapped to EL3.
When SCR_EL3.NS==1 :
If ICC_SRE_EL2.Enable==0, and EL2 is implemented, Non-secure accesses to this register from EL1 are trapped to EL2.
02/05/2017 15:43
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