The GICV_CTLR characteristics are:
Controls the behavior of virtual interrupts.
This register corresponds to the physical CPU interface register GICC_CTLR.
This register is part of the GIC virtual CPU interface registers functional group.
This register is accessible as follows:
Security disabled | Secure | Non-secure |
---|---|---|
RW | RW | RW |
This register is used only when System register access is not enabled. When System register access is enabled:
RW fields in this register reset to architecturally UNKNOWN values.
This register is available when a GIC implementation supports interrupt virtualization.
GICV_CTLR is a 32-bit register.
The GICV_CTLR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | EOImode | 0 | 0 | 0 | 0 | CBPR | FIQEn | AckCtl | EnableGrp1 | EnableGrp0 |
Reserved, RES0.
Controls the behavior associated with the GICV_EOIR, GICV_AEOIR, and GICV_DIR registers:
EOImode | Meaning |
---|---|
0 |
Writes to GICV_EOIR and GICV_AEOIR perform priority drop and deactivate interrupt operations simultaneously. Behavior on a write to GICV_DIR is UNPREDICTABLE. When it has completed processing the interrupt, the virtual machine writes to GICV_EOIR or GICV_AEOIR to deactivate the interrupt. The write updates the List registers and causes the virtual CPU interface to signal the interrupt completion to the physical Distributor. |
1 |
Writes to GICV_EOIR and GICV_AEOIR perform priority drop operation only. Writes to GICV_DIR perform deactivate interrupt operation only. At some point during interrupt processing, the virtual machine writes to GICV_EOIR or GICV_AEOIR. This write drops the priority of the virtual interrupt by updating its entry in the List registers. When it has completed processing the interrupt, the virtual machine writes to GICV_DIR to deactivate the interrupt. The write updates the List registers and causes the virtual CPU interface to signal the interrupt completion to the Distributor. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Reserved, RES0.
Controls whether GICV_BPR affects both Group 0 and Group 1 interrupts:
CBPR | Meaning |
---|---|
0 |
GICV_BPR affects Group 0 virtual interrupts only. GICV_ABPR affects Group 1 virtual interrupts only. |
1 |
GICV_BPR affects both Group 0 and Group 1 virtual interrupts. |
See Priority grouping for more information.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
FIQ Enable. Controls whether Group 0 virtual interrupts are presented as virtual FIQs:
FIQEn | Meaning |
---|---|
0 |
Group 0 virtual interrupts are presented as virtual IRQs. |
1 |
Group 0 virtual interrupts are presented as virtual FIQs. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
ARM deprecates use of this bit. ARM strongly recommends that software is written to operate with this bit always cleared to 0.
Acknowledge control. When the highest priority interrupt is Group 1, determines whether GICV_IAR causes the CPU interface to acknowledge the interrupt or returns the spurious identifier 1022, and whether GICV_HPPIR returns the interrupt ID or the special identifier 1022.
AckCtl | Meaning |
---|---|
0 |
If the highest priority pending interrupt is Group 1, a read of GICV_IAR or GICV_HPPIR returns an interrupt ID of 1022. |
1 |
If the highest priority pending interrupt is Group 1, a read of GICV_IAR or GICV_HPPIR returns the interrupt ID of the corresponding interrupt. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Enables the signaling of Group 1 virtual interrupts by the virtual CPU interface to the virtual machine:
EnableGrp1 | Meaning |
---|---|
0 |
Signaling of Group 1 interrupts is disabled. |
1 |
Signaling of Group 1 interrupts is enabled. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Enables the signaling of Group 0 virtual interrupts by the virtual CPU interface to the virtual machine:
EnableGrp0 | Meaning |
---|---|
0 |
Signaling of Group 0 interrupts is disabled. |
1 |
Signaling of Group 0 interrupts is enabled. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
GICV_CTLR can be accessed through its memory-mapped interface:
Component | Offset |
---|---|
GIC Virtual CPU interface | 0x0000 |
02/05/2017 15:43
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