AT S12E1W, Address Translate Stages 1 and 2 EL1 Write

The AT S12E1W characteristics are:

Purpose

Performs stage 1 and 2 address translation, with permissions as if writing to the given virtual address, using the following translation regime:

This System instruction is part of the Address translation instructions functional group.

Configuration

There are no configuration notes.

Attributes

AT S12E1W is a 64-bit System instruction.

Field descriptions

The AT S12E1W input value bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
Input address for translation
Input address for translation
313029282726252423222120191817161514131211109876543210

Bits [63:0]

Input address for translation. The resulting address can be read from the PAR_EL1.

If the address translation instructions are targeting a translation regime that is using AArch32, and so has a VA of only 32 bits, then VA[63:32] is RES0.

Executing the AT S12E1W instruction

This instruction is executed using AT with the following syntax:

AT <at_op>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<at_op> op0op1CRnCRmop2
S12E1W0110001111000101

Accessibility

The instruction is executable as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - - n/a WO
001 - - WOWO
011 - n/a WOWO
101 - - WOWO
111 - n/a WOWO

This table applies to all syntax that can be used to execute this instruction.

If EL2 is not implemented, or stage 2 translation is disabled, or the instruction is executed at EL3 when the value of SCR_EL3.NS is 0, this instruction executes as AT S1E1W.




02/05/2017 15:43

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