The MVFR2_EL1 characteristics are:
Describes the features provided by the AArch32 Advanced SIMD and Floating-point implementation.
Must be interpreted with MVFR0_EL1 and MVFR1_EL1.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.
This register is part of:
AArch64 System register MVFR2_EL1 is architecturally mapped to AArch32 System register MVFR2.
In an implementation where at least one Exception level supports execution in AArch32 state, but there is no support for Advanced SIMD and floating-point operation, this register is RAZ.
In an AArch64-only implementation, this register is UNKNOWN.
MVFR2_EL1 is a 32-bit register.
The MVFR2_EL1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | FPMisc | SIMDMisc |
Reserved, RES0.
Indicates whether the floating-point implementation provides support for miscellaneous VFP features.
FPMisc | Meaning |
---|---|
0000 |
Not implemented, or no support for miscellaneous features. |
0001 |
Support for Floating-point selection. |
0010 |
As 0001, and Floating-point Conversion to Integer with Directed Rounding modes. |
0011 |
As 0010, and Floating-point Round to Integer Floating-point. |
0100 |
As 0011, and Floating-point MaxNum and MinNum. |
All other values are reserved.
In ARMv8-A the permitted values are 0000 and 0100.
Indicates whether the Advanced SIMD implementation provides support for miscellaneous Advanced SIMD features.
SIMDMisc | Meaning |
---|---|
0000 |
Not implemented, or no support for miscellaneous features. |
0001 |
Floating-point Conversion to Integer with Directed Rounding modes. |
0010 |
As 0001, and Floating-point Round to Integer Floating-point. |
0011 |
As 0010, and Floating-point MaxNum and MinNum. |
All other values are reserved.
In ARMv8-A the permitted values are 0000 and 0011.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
MVFR2_EL1 | 11 | 000 | 0000 | 0011 | 010 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
02/05/2017 15:43
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