The MVFR0 characteristics are:
Describes the features provided by the AArch32 Advanced SIMD and Floating-point implementation.
Must be interpreted with MVFR1 and MVFR2.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section G4.14.6.
This register is part of:
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register MVFR0 is architecturally mapped to AArch64 System register MVFR0_EL1.
Implemented only if the implementation includes Advanced SIMD and floating-point instructions.
MVFR0 is a 32-bit register.
The MVFR0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FPRound | FPShVec | FPSqrt | FPDivide | FPTrap | FPDP | FPSP | SIMDReg |
Floating-Point Rounding modes. Indicates whether the floating-point implementation provides support for rounding modes. Defined values are:
FPRound | Meaning |
---|---|
0000 |
Not implemented, or only Round to Nearest mode supported, except that Round towards Zero mode is supported for VCVT instructions that always use that rounding mode regardless of the FPSCR setting. |
0001 |
All rounding modes supported. |
All other values are reserved.
In ARMv8-A the permitted values are 0000 and 0001.
Short Vectors. Indicates whether the floating-point implementation provides support for the use of short vectors. Defined values are:
FPShVec | Meaning |
---|---|
0000 |
Short vectors not supported. |
0001 |
Short vector operation supported. |
All other values are reserved.
In ARMv8-A the only permitted value is 0000.
Square Root. Indicates whether the floating-point implementation provides support for the ARMv6 VFP square root operations. Defined values are:
FPSqrt | Meaning |
---|---|
0000 |
Not supported in hardware. |
0001 |
Supported. |
All other values are reserved.
In ARMv8-A the permitted values are 0000 and 0001.
The VSQRT.F32 instruction also requires the single-precision floating-point attribute, bits [7:4], and the VSQRT.F64 instruction also requires the double-precision floating-point attribute, bits [11:8].
Indicates whether the floating-point implementation provides support for VFP divide operations. Defined values are:
FPDivide | Meaning |
---|---|
0000 |
Not supported in hardware. |
0001 |
Supported. |
All other values are reserved.
In ARMv8-A the permitted values are 0000 and 0001.
The VDIV.F32 instruction also requires the single-precision floating-point attribute, bits [7:4], and the VDIV.F64 instruction also requires the double-precision floating-point attribute, bits [11:8].
Floating Point Exception Trapping. Indicates whether the floating-point implementation provides support for exception trapping. Defined values are:
FPTrap | Meaning |
---|---|
0000 |
Not supported. |
0001 |
Supported. |
All other values are reserved.
A value of 0001 indicates that, when the corresponding trap is enabled, a floating-point exception generates an exception.
Double Precision. Indicates whether the floating-point implementation provides support for double-precision operations. Defined values are:
FPDP | Meaning |
---|---|
0000 |
Not supported in hardware. |
0001 |
Supported, VFPv2. |
0010 |
Supported, VFPv3, VFPv4, or ARMv8. VFPv3 and ARMv8 add an instruction to load a double-precision floating-point constant, and conversions between double-precision and fixed-point values. |
All other values are reserved.
In ARMv8-A the permitted values are 0000 and 0010.
A value of 0b0001 or 0b0010 indicates support for all VFP double-precision instructions in the supported version of VFP, except that, in addition to this field being nonzero:
Single Precision. Indicates whether the floating-point implementation provides support for single-precision operations. Defined values are:
FPSP | Meaning |
---|---|
0000 |
Not supported in hardware. |
0001 |
Supported, VFPv2. |
0010 |
Supported, VFPv3 or VFPv4. VFPv3 adds an instruction to load a single-precision floating-point constant, and conversions between single-precision and fixed-point values. |
All other values are reserved.
In ARMv8-A the permitted values are 0000 and 0010.
A value of 0b0001 or 0b0010 indicates support for all VFP single-precision instructions in the supported version of VFP, except that, in addition to this field being nonzero:
Advanced SIMD registers. Indicates whether the Advanced SIMD and floating-point implementation provides support for the Advanced SIMD and floating-point register bank. Defined values are:
SIMDReg | Meaning |
---|---|
0000 |
The implementation has no Advanced SIMD and floating-point support. |
0001 |
The implementation includes floating-point support with 16 x 64-bit registers. |
0010 |
The implementation includes Advanced SIMD and floating-point support with 32 x 64-bit registers. |
All other values are reserved.
In ARMv8-A the permitted values are 0000 and 0010.
This register can be read using VMRS with the following syntax:
VMRS <Rt>, <spec_reg>
This syntax uses the following encoding in the System instruction encoding space:
<spec_reg> | reg |
---|---|
MVFR0 | 0111 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When HCR_EL2.E2H==0 :
If CPACR.cp10==00, read accesses to this register from PL1 are UNDEFINED.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If CPTR_EL2.TFP==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If CPTR_EL2.FPEN==00, Non-secure read accesses to this register from EL1 are trapped to EL2.
If CPTR_EL2.FPEN==10, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HCPTR.TCP10==1, Non-secure read accesses to this register from EL1 are trapped to Hyp mode.
If HCPTR.TCP10==1, Non-secure read accesses to this register from EL2 are UNDEFINED.
If HCR.TID3==1, Non-secure read accesses to this register from EL1 are trapped to Hyp mode.
When EL3 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If NSACR.cp10==0, Non-secure read accesses to this register from EL1 and EL2 are UNDEFINED.
When EL3 is implemented and is using AArch64 :
If CPTR_EL3.TFP==1, read accesses to this register from EL1 and EL2 are trapped to EL3.
02/05/2017 15:43
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