AMAIR0, Auxiliary Memory Attribute Indirection Register 0

The AMAIR0 characteristics are:

Purpose

When using the Long-descriptor format translation tables for stage 1 translations, provides IMPLEMENTATION DEFINED memory attributes for the memory regions specified by MAIR0.

This register is part of:

Configuration

AArch32 System register AMAIR0 is architecturally mapped to AArch64 System register AMAIR_EL1[31:0] .

When EL3 is using AArch32, write access to AMAIR0(S) is disabled when the CP15SDISABLE signal is asserted HIGH.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

AMAIR0 is a 32-bit register.

Field descriptions

The AMAIR0 bit assignments are:

313029282726252423222120191817161514131211109876543210
IMPLEMENTATION DEFINED

This register is RES0 in the following cases:

If EL3 is implemented and is using AArch32:

Any IMPLEMENTATION DEFINED memory attributes are additional qualifiers for the memory locations and must not change the architected behavior specified by MAIR0 and MAIR1.

In a typical implementation, AMAIR0 and AMAIR1 split into eight one-byte fields, corresponding to the MAIRn.Attr<n> fields, but the architecture does not require them to do so.

IMPLEMENTATION DEFINED, bits [31:0]

IMPLEMENTATION DEFINED.

Accessing the AMAIR0

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 0, <Rt>, c10, c3, 0000000101011110011

Accessibility

The register is accessible as follows:

Configuration Control Accessibility Instance
E2HTGENSEL0EL1EL2EL3
EL3 not implemented xx0 - RW n/a n/a AMAIR0
EL3 not implemented x01 - RWRW n/a AMAIR0
EL3 not implemented x11 - n/a RW n/a AMAIR0
EL3 using AArch64xx0 - RW n/a n/a AMAIR0
EL3 using AArch64x01 - RWRW n/a AMAIR0
EL3 using AArch64x11 - n/a RW n/a AMAIR0
EL3 using AArch32x01 - RWRWRWAMAIR0_ns
EL3 using AArch32x11 - n/a RWRWAMAIR0_ns
EL3 using AArch32xx0 - n/a n/a RWAMAIR0_s

This table applies to all instructions that can access this register.

When EL3 is using AArch32, write access to AMAIR0_s is UNDEFINED when the CP15SDISABLE signal is asserted HIGH.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :




02/05/2017 15:43

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