DBGWVR<n>_EL1, Debug Watchpoint Value Registers, n = 0 - 15

The DBGWVR<n>_EL1 characteristics are:

Purpose

Holds a data address value for use in watchpoint matching. Forms watchpoint n together with control register DBGWCR<n>_EL1.

This register is part of the Debug registers functional group.

Usage constraints

This register is accessible as follows:

OffDLKOSLKEDADSLKDefault
ErrorErrorErrorErrorRORW

Configuration

External register DBGWVR<n>_EL1 is architecturally mapped to AArch64 System register DBGWVR<n>_EL1.

External register DBGWVR<n>_EL1 bits [31:0] are architecturally mapped to AArch32 System register DBGWVR<n>.

DBGWVR<n>_EL1 is in the Core power domain. RW fields in this register reset to architecturally UNKNOWN values. These apply only on a Cold reset. The register is not affected by a Warm reset and is not affected by an External debug reset.

If breakpoint n is not implemented then this register is unallocated.

Attributes

DBGWVR<n>_EL1 is a 64-bit register.

Field descriptions

The DBGWVR<n>_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RESS[14:4]VA[52:49]VA[48:2]
VA[48:2]00
313029282726252423222120191817161514131211109876543210

RESS[14:4], bits [63:53]

Reserved, Sign extended. Hardware and software must treat this field as RES0 if the most significant bit of VA is 0 or RES0, and as RES1 if the most significant bit of VA is 1.

Hardware always ignores the value of these bits and it is IMPLEMENTATION DEFINED whether:

VA[52:49], bits [52:49]
In ARMv8.2:

Extension to VA[48:2]. See VA[48:2] for more details.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.


In ARMv8.1 and ARMv8.0:

Extension to RESS[14:4]. See RESS[14:4] for more details.

VA[48:2], bits [48:2]

Bits[48:2] of the address value for comparison.

When ARMv8.2-LVA is implemented, and 52-bit addresses and a 64KB translation granule are in use, VA[52:49] forms the upper part of the address value. Otherwise, VA[52:49] are RESS.

ARM deprecates setting DBGWVR<n>_EL1[2] == 1.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bits [1:0]

Reserved, RES0.

Accessing the DBGWVR<n>_EL1

DBGWVR<n>_EL1[31:0] can be accessed through the external debug interface:

ComponentOffset
Debug0x800 + 16n

DBGWVR<n>_EL1[63:32] can be accessed through the external debug interface:

ComponentOffset
Debug0x804 + 16n



02/05/2017 15:43

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