ICC_IGRPEN1_EL1, Interrupt Controller Interrupt Group 1 Enable register

The ICC_IGRPEN1_EL1 characteristics are:

Purpose

Controls whether Group 1 interrupts are enabled for the current Security state.

This register is part of:

Configuration

AArch64 System register ICC_IGRPEN1_EL1 (S) is architecturally mapped to AArch32 System register ICC_IGRPEN1 (S) .

AArch64 System register ICC_IGRPEN1_EL1 (NS) is architecturally mapped to AArch32 System register ICC_IGRPEN1 (NS) .

Attributes

ICC_IGRPEN1_EL1 is a 32-bit register.

Field descriptions

The ICC_IGRPEN1_EL1 bit assignments are:

313029282726252423222120191817161514131211109876543210
0000000000000000000000000000000Enable

Bits [31:1]

Reserved, RES0.

Enable, bit [0]

Enables Group 1 interrupts for the current Security state.

EnableMeaning
0

Group 1 interrupts are disabled for the current Security state.

1

Group 1 interrupts are enabled for the current Security state.

Virtual accesses to this register update ICH_VMCR_EL2.VENG1.

If EL3 is present:

If the highest priority pending interrupt for that PE is a Group 1 interrupt using 1 of N model, then the interrupt will target another PE as a result of the Enable bit changing from 1 to 0.

When this register has an architecturally-defined reset value, this field resets to 0.

Accessing the ICC_IGRPEN1_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op1CRnCRmop2
ICC_IGRPEN1_EL100011001100111

When HCR_EL2.IMO is set to 1, execution of this encoding at Non-secure EL1 results in an access to ICV_IGRPEN1_EL1.

Accessibility

The register is accessible as follows:

Control Accessibility Instance
FMOIMOTGENSEL0EL1EL2EL3
xxx0 - RW n/a RWICC_IGRPEN1_EL1_s
xx11 - n/a RWRWICC_IGRPEN1_EL1_ns
x001 - RWRWRWICC_IGRPEN1_EL1_ns
x101 - ICV_IGRPEN1_EL1 RWRWICC_IGRPEN1_EL1_ns

This table applies to all instructions that can access this register.

ICC_IGRPEN1_EL1 is only accessible at Non-secure EL1 when HCR_EL2.IMO is set to 0.

Note

When HCR_EL2.IMO is set to 1, at Non-secure EL1, the instruction encoding used to access ICC_IGRPEN1_EL1 results in an access to ICV_IGRPEN1_EL1.

If EL3 is present and this register is accessed at EL3, the copy of this register appropriate to the current setting of SCR_EL3.NS is accessed.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When SCR_EL3.NS==1 :

When EL3 is implemented and is using AArch64 and SCR_EL3.NS==0 :

When EL3 is implemented and is using AArch64 :

When EL3 is implemented and is using AArch64 and SCR_EL3.NS==1 :




02/05/2017 15:43

Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.