The PMCCFILTR_EL0 characteristics are:
Determines the modes in which the Cycle Counter, PMCCNTR_EL0, increments.
This register is part of the Performance Monitors registers functional group.
AArch64 System register PMCCFILTR_EL0 is architecturally mapped to AArch32 System register PMCCFILTR.
AArch64 System register PMCCFILTR_EL0 is architecturally mapped to External register PMCCFILTR_EL0.
This register is in the Warm reset domain. On a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.
PMCCFILTR_EL0 is a 32-bit register.
The PMCCFILTR_EL0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
P | U | NSK | NSU | NSH | M | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Privileged filtering bit. Controls counting in EL1. If EL3 is implemented, then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are:
P | Meaning |
---|---|
0 |
Count cycles in EL1. |
1 |
Do not count cycles in EL1. |
User filtering bit. Controls counting in EL0. If EL3 is implemented, then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are:
U | Meaning |
---|---|
0 |
Count cycles in EL0. |
1 |
Do not count cycles in EL0. |
Non-secure EL1 (kernel) modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented, this bit is RES0.
If the value of this bit is equal to the value of P, cycles in Non-secure EL1 are counted.
Otherwise, cycles in Non-secure EL1 are not counted.
Non-secure EL0 (Unprivileged) filtering. Controls counting in Non-secure EL0. If EL3 is not implemented, this bit is RES0.
If the value of this bit is equal to the value of U, cycles in Non-secure EL0 are counted.
Otherwise, cycles in Non-secure EL0 are not counted.
Non-secure EL2 (Hypervisor) filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented, this bit is RES0.
NSH | Meaning |
---|---|
0 |
Do not count cycles in EL2. |
1 |
Count cycles in EL2. |
Secure EL3 filtering bit. If EL3 is not implemented, this bit is RES0.
If the value of this bit is equal to the value of P, cycles in Secure EL3 are counted.
Otherwise, cycles in Secure EL3 are not counted.
Most applications can ignore this field and set its value to 0.
This field is not visible in the AArch32 PMCCFILTR System register.
Reserved, RES0.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
PMCCFILTR_EL0 | 11 | 011 | 1110 | 1111 | 111 |
PMCCFILTR_EL0 can also be accessed by using PMXEVTYPER_EL0 with PMSELR_EL0.SEL set to 0b11111.
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | RW | RW | n/a | RW |
x | 0 | 1 | RW | RW | RW | RW |
x | 1 | 1 | RW | n/a | RW | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If PMUSERENR_EL0.EN==0, accesses to this register from EL0 are trapped to EL1.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TPM==1, Non-secure accesses to this register from EL0 and EL1 are trapped to EL2.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TPM==1, accesses to this register from EL0, EL1, and EL2 are trapped to EL3.
02/05/2017 15:43
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