PMPIDR3, Performance Monitors Peripheral Identification Register 3

The PMPIDR3 characteristics are:

Purpose

Provides information to identify a Performance Monitor component.

For more information see 'About the Peripheral identification scheme' in the ARMv8 ARM, section H8 (About the External Debug Registers).

This register is part of the Performance Monitors registers functional group.

Usage constraints

This register is accessible as follows:

SLKDefault
RORO

Configuration

PMPIDR3 is in the Debug power domain.

Implementation of this register is OPTIONAL.

This register is required for CoreSight compliance.

Attributes

PMPIDR3 is a 32-bit register.

Field descriptions

The PMPIDR3 bit assignments are:

313029282726252423222120191817161514131211109876543210
000000000000000000000000REVANDCMOD

Bits [31:8]

Reserved, RES0.

REVAND, bits [7:4]

Part minor revision. Parts using PMPIDR2.REVISION as an extension to the Part number must use this field as a major revision number.

CMOD, bits [3:0]

Customer modified. Indicates someone other than the Designer has modified the component.

Accessing the PMPIDR3

PMPIDR3 can be accessed through the external debug interface:

ComponentOffset
PMU 0xFEC



02/05/2017 15:43

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