The CNTPCT characteristics are:
Holds the 64-bit physical count value.
This register is part of the Generic Timer registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register CNTPCT is architecturally mapped to AArch64 System register CNTPCT_EL0.
CNTPCT is a 64-bit register.
The CNTPCT bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
Physical count value | |||||||||||||||||||||||||||||||
Physical count value | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Physical count value.
This register can be read using MRRC with the following syntax:
MRRC <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | coproc | CRm |
---|---|---|---|
p15, 0, <Rt>, <Rt2>, c14 | 0000 | 1111 | 1110 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | RO | RO | n/a | RO |
x | 0 | 1 | RO | RO | RO | RO |
x | 1 | 1 | RO | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When HCR_EL2.E2H==0 :
If CNTKCTL_EL1.EL0PCTEN==0, read accesses to this register from EL0 are trapped to EL1.
If CNTKCTL.PL0PCTEN==0, read accesses to this register from EL0 are trapped to Undefined mode.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If CNTHCTL_EL2.EL1PCTEN==0, Non-secure read accesses to this register from EL1 are trapped to EL2.
If CNTHCTL_EL2.EL1PCTEN==0, and CNTKCTL_EL1.EL0PCTEN==1, Non-secure read accesses to this register from EL0 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If CNTHCTL_EL2.EL1PCTEN==0, Non-secure read accesses to this register from EL1 are trapped to EL2.
If CNTHCTL_EL2.EL1PCTEN==0, and CNTKCTL_EL1.EL0PCTEN==1, Non-secure read accesses to this register from EL0 are trapped to EL2.
If CNTKCTL_EL1.EL0PCTEN==0, Non-secure read accesses to this register from EL0 are trapped to EL1.
If CNTKCTL.PL0PCTEN==0, Non-secure read accesses to this register from EL0 are trapped to Undefined mode.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==1 :
If CNTHCTL_EL2.EL0PCTEN==0, Non-secure read accesses to this register from EL0 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If CNTHCTL.PL1PCTEN==0, Non-secure read accesses to this register from EL0 and EL1 are trapped to Hyp mode.
02/05/2017 15:43
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