MAIR_EL2, Memory Attribute Indirection Register (EL2)

The MAIR_EL2 characteristics are:

Purpose

Provides the memory attribute encodings corresponding to the possible AttrIndx values in a Long-descriptor format translation table entry for stage 1 translations at EL2.

This register is part of:

Configuration

AArch64 System register MAIR_EL2 bits [31:0] are architecturally mapped to AArch32 System register HMAIR0.

AArch64 System register MAIR_EL2 bits [63:32] are architecturally mapped to AArch32 System register HMAIR1.

If EL2 is not implemented, this register is RES0 from EL3.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

MAIR_EL2 is a 64-bit register.

Field descriptions

The MAIR_EL2 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
Attr7Attr6Attr5Attr4
Attr3Attr2Attr1Attr0
313029282726252423222120191817161514131211109876543210

MAIR_EL2 is permitted to be cached in a TLB.

Attr<n>, bits [8n+7:8n], for n = 0 to 7

The memory attribute encoding for an AttrIndx[2:0] entry in a Long descriptor format translation table entry, where AttrIndx[2:0] gives the value of <n> in Attr<n>.

Bits [7:4] are encoded as follows:

Attr<n>[7:4] Meaning
0000 Device memory. See encoding of Attr<n>[3:0] for the type of Device memory.
00RW, RW not 00 Normal memory, Outer Write-Through Transient
0100 Normal memory, Outer Non-cacheable
01RW, RW not 00 Normal memory, Outer Write-Back Transient
10RW Normal memory, Outer Write-Through Non-transient
11RW Normal memory, Outer Write-Back Non-transient

R = Outer Read-Allocate policy, W = Outer Write-Allocate policy.

The meaning of bits [3:0] depends on the value of bits [7:4]:

Attr<n>[3:0] Meaning when Attr<n>[7:4] is 0000 Meaning when Attr<n>[7:4] is not 0000
0000 Device-nGnRnE memory UNPREDICTABLE
00RW, RW not 00 UNPREDICTABLE Normal memory, Inner Write-Through Transient
0100 Device-nGnRE memory Normal memory, Inner Non-cacheable
01RW, RW not 00 UNPREDICTABLE Normal memory, Inner Write-Back Transient
1000 Device-nGRE memory Normal memory, Inner Write-Through Non-transient (RW=00)
10RW, RW not 00 UNPREDICTABLE Normal memory, Inner Write-Through Non-transient
1100 Device-GRE memory Normal memory, Inner Write-Back Non-transient (RW=00)
11RW, RW not 00 UNPREDICTABLE Normal memory, Inner Write-Back Non-transient

R = Inner Read-Allocate policy, W = Inner Write-Allocate policy.

The R and W bits in some Attr<n> fields have the following meanings:

R or W Meaning
0 No Allocate
1 Allocate

Accessing the MAIR_EL2

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
MAIR_EL21110010100010000
MAIR_EL11100010100010000

Accessibility

The register is accessible as follows:

<systemreg> Control Accessibility
E2HTGENSEL0EL1EL2EL3
MAIR_EL2xx0 - - n/a RW
MAIR_EL2001 - - RWRW
MAIR_EL2011 - n/a RWRW
MAIR_EL2101 - - RWRW
MAIR_EL2111 - n/a RWRW
MAIR_EL1xx0 - MAIR_EL1 n/a MAIR_EL1
MAIR_EL1001 - MAIR_EL1 MAIR_EL1 MAIR_EL1
MAIR_EL1011 - n/a MAIR_EL1 MAIR_EL1
MAIR_EL1101 - MAIR_EL1 RW MAIR_EL1
MAIR_EL1111 - n/a RW MAIR_EL1

When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic MAIR_EL2 or MAIR_EL1 are not guaranteed to be ordered with respect to accesses using the other mnemonic.




02/05/2017 15:43

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