GICH_ELRSR, Empty List Register Status Register

The GICH_ELRSR characteristics are:

Purpose

Indicates which List registers contain valid interrupts.

This register is part of the GIC virtualised guest interface control registers functional group.

Usage constraints

This register is accessible as follows:

Security disabledSecureNon-secure
RORORO

This register is used only when System register access is not enabled. When System register access is enabled:

Bits corresponding to unimplemented List registers are RES0.

Configuration

Some or all RW fields of this register have defined reset values.

This register is available when the GIC implementation supports interrupt virtualization.

Attributes

GICH_ELRSR is a 32-bit register.

Field descriptions

The GICH_ELRSR bit assignments are:

313029282726252423222120191817161514131211109876543210
0000000000000000Status<n>, bit [n], for n = 0 to 15

Bits [31:16]

Reserved, RES0.

Status<n>, bit [n], for n = 0 to 15

Status bit for List register <n>:

Status<n>Meaning
0

GICH_LR<n>, if implemented, contains a valid interrupt. Using this List register can result in overwriting a valid interrupt.

1

GICH_LR<n> does not contain a valid interrupt. The List register is empty and can be used without overwriting a valid interrupt or losing an EOI maintenance interrupt.

For any GICH_LR<n> register, the corresponding status bit is set to 1 if GICH_LR<n>.State is 0b00 and either:

When this register has an architecturally-defined reset value, this field resets to 1.

Accessing the GICH_ELRSR

GICH_ELRSR can be accessed through its memory-mapped interface:

ComponentOffset
GIC Virtual interface control 0x0030



02/05/2017 15:43

Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.