The GICD_CLRSPI_SR characteristics are:
Removes the pending state from a valid SPI.
A write to this register changes the state of a pending SPI to inactive, and the state of an active and pending SPI to active.
This register is part of the GIC Distributor registers functional group.
This register is accessible as follows:
Security disabled | Secure | Non-secure |
---|---|---|
WI | WO | WI |
Writes to this register have no effect if:
16-bit accesses to bits [15:0] of this register must be supported.
If GICD_TYPER.MBIS == 0, this register is reserved.
When GICD_CTLR.DS==1, this register is WI.
GICD_CLRSPI_SR is a 32-bit register.
The GICD_CLRSPI_SR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | INTID |
Reserved, RES0.
The INTID of the SPI.
The function of this register depends on whether the targeted SPI is configured to be an edge-triggered or level-sensitive interrupt:
GICD_CLRSPI_SR can be accessed through its memory-mapped interface:
Component | Offset |
---|---|
GIC Distributor | 0x0058 |
02/05/2017 15:43
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