HSR, Hyp Syndrome Register

The HSR characteristics are:

Purpose

Holds syndrome information for an exception taken to Hyp mode.

This register is part of:

Configuration

AArch32 System register HSR is architecturally mapped to AArch64 System register ESR_EL2.

If EL2 is not implemented, this register is RES0 from EL3.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

HSR is a 32-bit register.

Field descriptions

The HSR bit assignments are:

313029282726252423222120191817161514131211109876543210
ECILISS

Execution in any Non-secure PE mode other than Hyp mode makes this register UNKNOWN.

When an UNPREDICTABLE instruction is treated as UNDEFINED, and the exception is taken to EL2, the value of HSR is UNKNOWN. The value written to HSR must be consistent with a value that could be created as a result of an exception from the same Exception level that generated the exception as a result of a situation that is not UNPREDICTABLE at that Exception level, in order to avoid the possibility of a privilege violation.

EC, bits [31:26]

Exception Class. Indicates the reason for the exception that this register holds information about. Possible values of this field are:

ECMeaningISS
000000

Unknown reason.

Exceptions with an unknown reason
000001

Trapped WFI or WFE instruction execution.

Conditional WFE and WFI instructions that fail their condition code check do not cause an exception.

Exception from a WFI or WFE instruction
000011

Trapped MCR or MRC access with (coproc==1111) that is not reported using EC 0b000000.

Exception from an MCR or MRC access
000100

Trapped MCRR or MRRC access with (coproc==1111) that is not reported using EC 0b000000.

Exception from an MCRR or MRRC access
000101

Trapped MCR or MRC access with (coproc==1110).

Exception from an MCR or MRC access
000110

Trapped LDC or STC access.

The only architected uses of these instructions are:

Exception from an LDC or STC instruction
000111

Access to Advanced SIMD or floating-point functionality trapped by a HCPTR.{TASE, TCP10} control.

Excludes exceptions generated because Advanced SIMD and floating-point are not implemented. These are reported with EC value 0b000000.

Exception from an access to SIMD or floating-point functionality, resulting from HCPTR
001000

Trapped VMRS access, from ID group trap, that is not reported using EC 0b000111.

Exception from an MCR or MRC access
001100

Trapped MRRC access with (coproc==1110).

Exception from an MCRR or MRRC access
001110

Illegal exception return to AArch32 state.

Exception from an Illegal state or PC alignment fault
010001

Exception on SVC instruction execution in AArch32 state routed to EL2.

Exception from HVC or SVC instruction execution
010010

HVC instruction execution in AArch32 state, when HVC is not disabled.

Exception from HVC or SVC instruction execution
010011

Trapped execution of SMC instruction in AArch32 state.

Exception from SMC instruction execution
100000

Prefetch Abort from a lower Exception level.

Exception from a Prefetch Abort
100001

Prefetch Abort taken without a change in Exception level.

Exception from a Prefetch Abort
100010

PC alignment fault exception.

Exception from an Illegal state or PC alignment fault
100100

Data Abort from a lower Exception level.

Exception from a Data Abort
100101

Data Abort taken without a change in Exception level.

Exception from a Data Abort

All other EC values are reserved by ARM, and:

The effect of programming this field to a reserved value is that behavior is CONSTRAINED UNPREDICTABLE, as described in 'Reserved values in System and memory-mapped registers and translation table entries' in the ARM ARM, section K1.2.2.

IL, bit [25]

Instruction length bit. Indicates the size of the instruction that has been trapped to Hyp mode. When this bit is valid, possible values of this bit are:

ILMeaning
0

16-bit instruction trapped.

1

32-bit instruction trapped.

This field is RES1 and not valid for the following cases:

Note

This is a change from the behavior in ARMv7, where the IL field is UNK/SBZP for the corresponding cases.

The IL field is not valid and is UNKNOWN on an exception from a PC alignment fault.

ISS, bits [24:0]

Instruction Specific Syndrome. Architecturally, this field can be defined independently for each defined Exception class. However, in practice, some ISS encodings are used for more than one Exception class.

Exceptions with an unknown reason

This is the layout of the ISS field for exceptions with the following EC values:

2423222120191817161514131211109876543210
0000000000000000000000000

Bits [24:0]

Reserved, RES0.

This EC code is used for all exceptions that are not covered by any other EC value. This includes exceptions that are generated in the following situations:

Note

An exception is generated only if the CONSTRAINED UNPREDICTABLE behavior of the instruction is that it is UNDEFINED, see 'MSR/MRS Banked registers' in the ARMv8 ARM, section K1.1.29 (CONSTRAINED UNPREDICTABLE behavior of EL2 features).

'Undefined Instruction exception, when HCR.TGE is set to 1' in the ARMv8 ARM, section G1 (The AArch32 System Level Programmers' Model), describes the configuration settings for a trap that returns an HSR.EC value of 0b000000.

Exception from a WFI or WFE instruction

This is the layout of the ISS field for exceptions with the following EC values:

2423222120191817161514131211109876543210
CVCOND0000000000000000000TI

CV, bit [24]

Condition code valid. Possible values of this bit are:

CVMeaning
0

The COND field is not valid.

1

The COND field is valid.

When an A32 instruction is trapped, CV is set to 1.

When a T32 instruction is trapped, it is IMPLEMENTATION DEFINED whether CV is set to 1 or set to 0. See the description of the COND field for more information.

COND, bits [23:20]

The condition code for the trapped instruction.

When an A32 instruction is trapped, CV is set to 1 and:

A conditional A32 instruction that is known to pass its condition code check can be presented either:

When a T32 instruction is trapped, it is IMPLEMENTATION DEFINED whether:

For an implementation that, for both A32 and T32 instructions, takes an exception on a trapped conditional instruction only if the instruction passes its condition code check, these definitions mean that when CV is set to 1 it is IMPLEMENTATION DEFINED whether the COND field is set to 0b1110, or to the value of any condition that applied to the instruction.

Bits [19:1]

Reserved, RES0.

TI, bit [0]

Trapped instruction. Possible values of this bit are:

TIMeaning
0

WFI trapped.

1

WFE trapped.

'Trapping use of the WFI and WFE instructions' in the ARMv8 ARM, section G1 (The AArch32 System Level Programmers' Model), describes the configuration settings for this trap.

Exception from an MCR or MRC access

This is the layout of the ISS field for exceptions with the following EC values:

2423222120191817161514131211109876543210
CVCONDOpc2Opc1CRn0RtCRmDirection

CV, bit [24]

Condition code valid. Possible values of this bit are:

CVMeaning
0

The COND field is not valid.

1

The COND field is valid.

When an A32 instruction is trapped, CV is set to 1.

When a T32 instruction is trapped, it is IMPLEMENTATION DEFINED whether CV is set to 1 or set to 0. See the description of the COND field for more information.

COND, bits [23:20]

The condition code for the trapped instruction.

When an A32 instruction is trapped, CV is set to 1 and:

A conditional A32 instruction that is known to pass its condition code check can be presented either:

When a T32 instruction is trapped, it is IMPLEMENTATION DEFINED whether:

For an implementation that, for both A32 and T32 instructions, takes an exception on a trapped conditional instruction only if the instruction passes its condition code check, these definitions mean that when CV is set to 1 it is IMPLEMENTATION DEFINED whether the COND field is set to 0b1110, or to the value of any condition that applied to the instruction.

Opc2, bits [19:17]

The Opc2 value from the issued instruction.

For a trapped VMRS access, holds the value 0b000.

Opc1, bits [16:14]

The Opc1 value from the issued instruction.

For a trapped VMRS access, holds the value 0b111.

CRn, bits [13:10]

The CRn value from the issued instruction.

For a trapped VMRS access, holds the reg field from the VMRS instruction encoding.

Bit [9]

Reserved, RES0.

Rt, bits [8:5]

The Rt value from the issued instruction, the general-purpose register used for the transfer.

CRm, bits [4:1]

The CRm value from the issued instruction.

For a trapped VMRS access, holds the value 0b0000.

Direction, bit [0]

Indicates the direction of the trapped instruction. The possible values of this bit are:

DirectionMeaning
0

Write to System register space. MCR instruction.

1

Read from System register space. MRC or VMRS instruction.

The following sections describe configuration settings for traps that are reported using EC value 0b000011:

The following sections describe configuration settings for traps that are reported using EC value 0b000101:

The following sections describes configuration settings for traps that are reported using EC value 0b001000:

Exception from an MCRR or MRRC access

This is the layout of the ISS field for exceptions with the following EC values:

2423222120191817161514131211109876543210
CVCONDOpc100Rt20RtCRmDirection

CV, bit [24]

Condition code valid. Possible values of this bit are:

CVMeaning
0

The COND field is not valid.

1

The COND field is valid.

When an A32 instruction is trapped, CV is set to 1.

When a T32 instruction is trapped, it is IMPLEMENTATION DEFINED whether CV is set to 1 or set to 0. See the description of the COND field for more information.

COND, bits [23:20]

The condition code for the trapped instruction.

When an A32 instruction is trapped, CV is set to 1 and:

A conditional A32 instruction that is known to pass its condition code check can be presented either:

When a T32 instruction is trapped, it is IMPLEMENTATION DEFINED whether:

For an implementation that, for both A32 and T32 instructions, takes an exception on a trapped conditional instruction only if the instruction passes its condition code check, these definitions mean that when CV is set to 1 it is IMPLEMENTATION DEFINED whether the COND field is set to 0b1110, or to the value of any condition that applied to the instruction.

Opc1, bits [19:16]

The Opc1 value from the issued instruction.

Bits [15:14]

Reserved, RES0.

Rt2, bits [13:10]

The Rt2 value from the issued instruction, the second general-purpose register used for the transfer.

Bit [9]

Reserved, RES0.

Rt, bits [8:5]

The Rt value from the issued instruction, the first general-purpose register used for the transfer.

CRm, bits [4:1]

The CRm value from the issued instruction.

Direction, bit [0]

Indicates the direction of the trapped instruction. The possible values of this bit are:

DirectionMeaning
0

Write to System register space. MCRR instruction.

1

Read from System register space. MRRC instruction.

The following sections describe configuration settings for traps that are reported using EC value 0b000100:

The following sections describe configuration settings for traps that are reported using EC value 0b001100:

Exception from an LDC or STC instruction

This is the layout of the ISS field for exceptions with the following EC values:

2423222120191817161514131211109876543210
CVCONDimm8000RnOffsetAMDirection

CV, bit [24]

Condition code valid. Possible values of this bit are:

CVMeaning
0

The COND field is not valid.

1

The COND field is valid.

When an A32 instruction is trapped, CV is set to 1.

When a T32 instruction is trapped, it is IMPLEMENTATION DEFINED whether CV is set to 1 or set to 0. See the description of the COND field for more information.

COND, bits [23:20]

The condition code for the trapped instruction.

When an A32 instruction is trapped, CV is set to 1 and:

A conditional A32 instruction that is known to pass its condition code check can be presented either:

When a T32 instruction is trapped, it is IMPLEMENTATION DEFINED whether:

For an implementation that, for both A32 and T32 instructions, takes an exception on a trapped conditional instruction only if the instruction passes its condition code check, these definitions mean that when CV is set to 1 it is IMPLEMENTATION DEFINED whether the COND field is set to 0b1110, or to the value of any condition that applied to the instruction.

imm8, bits [19:12]

The immediate value from the issued instruction.

Bits [11:9]

Reserved, RES0.

Rn, bits [8:5]

The Rn value from the issued instruction. Valid only when AM[2] is 0, indicating an immediate form of the LDC or STC instruction.

When AM[2] is 1, indicating a literal form of the LDC or STC instruction, this field is UNKNOWN.

Offset, bit [4]

Indicates whether the offset is added or subtracted:

OffsetMeaning
0

Subtract offset.

1

Add offset.

This bit corresponds to the U bit in the instruction encoding.

AM, bits [3:1]

Addressing mode. The permitted values of this field are:

AMMeaning
000

Immediate unindexed.

001

Immediate post-indexed.

010

Immediate offset.

011

Immediate pre-indexed.

100

Literal unindexed.

LDC instruction in A32 instruction set only.

For a trapped STC instruction or a trapped T32 LDC instruction this encoding is reserved.

110

Literal offset.

LDC instruction only.

For a trapped STC instruction, this encoding is reserved.

The values 0b101 and 0b111 are reserved. The effect of programming this field to a reserved value is that behavior is CONSTRAINED UNPREDICTABLE, as described in 'Unallocated values in fields of AArch32 System registers and translation table entries' in the ARM ARM, section K1.1.11.

Bit [2] in this subfield indicates the instruction form, immediate or literal.

Bits [1:0] in this subfield correspond to the bits {P, W} in the instruction encoding.

Direction, bit [0]

Indicates the direction of the trapped instruction. The possible values of this bit are:

DirectionMeaning
0

Write to memory. STC instruction.

1

Read from memory. LDC instruction.

'Trapping general Non-secure System register accesses to debug registers' in the ARMv8 ARM, section G1 describes the configuration settings for the trap that is reported using EC value 0b000110.

Exception from an access to SIMD or floating-point functionality, resulting from HCPTR

This is the layout of the ISS field for exceptions with the following EC values:

2423222120191817161514131211109876543210
CVCOND00000000000000TA0coproc

Excludes exceptions that occur because Advanced SIMD and floating-point functionality is not implemented, or because the value of HCR.TGE or HCR_EL2.TGE is 1. These are reported with EC value 0b000000.

CV, bit [24]

Condition code valid. Possible values of this bit are:

CVMeaning
0

The COND field is not valid.

1

The COND field is valid.

When an A32 instruction is trapped, CV is set to 1.

When a T32 instruction is trapped, it is IMPLEMENTATION DEFINED whether CV is set to 1 or set to 0. See the description of the COND field for more information.

COND, bits [23:20]

The condition code for the trapped instruction.

When an A32 instruction is trapped, CV is set to 1 and:

A conditional A32 instruction that is known to pass its condition code check can be presented either:

When a T32 instruction is trapped, it is IMPLEMENTATION DEFINED whether:

For an implementation that, for both A32 and T32 instructions, takes an exception on a trapped conditional instruction only if the instruction passes its condition code check, these definitions mean that when CV is set to 1 it is IMPLEMENTATION DEFINED whether the COND field is set to 0b1110, or to the value of any condition that applied to the instruction.

Bits [19:6]

Reserved, RES0.

TA, bit [5]

Indicates trapped use of Advanced SIMD functionality. The possible values of this bit are:

TAMeaning
0

Exception was not caused by trapped use of Advanced SIMD functionality.

1

Exception was caused by trapped use of Advanced SIMD functionality.

Any use of an Advanced SIMD instruction that is not also a floating-point instruction that is trapped to Hyp mode because of a trap configured in the HCPTR sets this bit to 1.

For a list of these instructions, see 'Controls of Advanced SIMD operation that do not apply to floating-point operation' in the ARMv8 ARM, section E1.

Bit [4]

Reserved, RES0.

coproc, bits [3:0]

When the TA field returns the value 1, this field returns the value 1010, otherwise this field is RES0.

The following sections describe the configuration settings for the traps that are reported using EC value 0b000111:

Exception from HVC or SVC instruction execution

This is the layout of the ISS field for exceptions with the following EC values:

2423222120191817161514131211109876543210
000000000imm16

Bits [24:16]

Reserved, RES0.

imm16, bits [15:0]

The value of the immediate field from the HVC or SVC instruction.

For an HVC instruction, this is the value of the imm16 field of the issued instruction.

For an SVC instruction:

The HVC instruction is unconditional, and a conditional SVC instruction generates an exception only if it passes its condition code check. Therefore, the syndrome information for these exceptions does not require conditionality information.

'Supervisor Call exception, when HCR.TGE is set to 1' in the ARMv8 ARM, section G1 (The AArch32 System Level Programmers' Model), describes the configuration settings for the trap reported with EC value 0b010001.

Exception from SMC instruction execution

This is the layout of the ISS field for exceptions with the following EC values:

2423222120191817161514131211109876543210
CVCONDCCKNOWNPASS0000000000000000000

CV, bit [24]

Condition code valid. Possible values of this bit are:

CVMeaning
0

The COND field is not valid.

1

The COND field is valid.

When an A32 instruction is trapped, CV is set to 1.

When a T32 instruction is trapped, it is IMPLEMENTATION DEFINED whether CV is set to 1 or set to 0. See the description of the COND field for more information.

This field is only valid if CCKNOWNPASS is 1, otherwise it is RES0.

COND, bits [23:20]

The condition code for the trapped instruction.

When an A32 instruction is trapped, CV is set to 1 and:

A conditional A32 instruction that is known to pass its condition code check can be presented either:

When a T32 instruction is trapped, it is IMPLEMENTATION DEFINED whether:

For an implementation that, for both A32 and T32 instructions, takes an exception on a trapped conditional instruction only if the instruction passes its condition code check, these definitions mean that when CV is set to 1 it is IMPLEMENTATION DEFINED whether the COND field is set to 0b1110, or to the value of any condition that applied to the instruction.

This field is only valid if CCKNOWNPASS is 1, otherwise it is RES0.

CCKNOWNPASS, bit [19]

Indicates whether the instruction might have failed its condition code check.

CCKNOWNPASSMeaning
0

The instruction was unconditional, or was conditional and passed its condition code check.

1

The instruction was conditional, and might have failed its condition code check.

Bits [18:0]

Reserved, RES0.

'Traps to Hyp mode of Non-secure PL1 execution of SMC instructions' in the ARMv8 ARM, section G1 (The AArch32 System Level Programmers' Model), describes the configuration settings for this trap, for instructions executed in Non-secure PL1 modes.

Exception from a Prefetch Abort

This is the layout of the ISS field for exceptions with the following EC values:

2423222120191817161514131211109876543210
00000000000000FnVEA0S1PTW0IFSC

Bits [24:11]

Reserved, RES0.

FnV, bit [10]

FAR not Valid, for a Synchronous external abort other than a Synchronous external abort on a translation table walk.

FnVMeaning
0

HIFAR is valid.

1

HIFAR is not valid, and holds an UNKNOWN value.

This field is only valid if the IFSC code is 010000. It is RES0 for all other aborts.

EA, bit [9]

External abort type. This bit can provide an IMPLEMENTATION DEFINED classification of External aborts.

For any abort other than an External abort this bit returns a value of 0.

Bit [8]

Reserved, RES0.

S1PTW, bit [7]

For a stage 2 fault, indicates whether the fault was a stage 2 fault on an access made for a stage 1 translation table walk:

S1PTWMeaning
0

Fault not on a stage 2 translation for a stage 1 translation table walk.

1

Fault on the stage 2 translation of an access for a stage 1 translation table walk.

For any abort other than a stage 2 fault this bit is RES0.

Bit [6]

Reserved, RES0.

IFSC, bits [5:0]

Instruction Fault Status Code. Possible values of this field are:

IFSCMeaning
000000

Address size fault, translation table base register

000001

Address size fault, level 1

000010

Address size fault, level 2

000011

Address size fault, level 3

000101

Translation fault, level 1

000110

Translation fault, level 2

000111

Translation fault, level 3

001001

Access flag fault, level 1

001010

Access flag fault, level 2

001011

Access flag fault, level 3

001101

Permission fault, level 1

001110

Permission fault, level 2

001111

Permission fault, level 3

010000

Synchronous external abort, not on translation table walk

011000

Synchronous parity or ECC error on memory access, not on translation table walk

010101

Synchronous external abort, on translation table walk, level 1

010110

Synchronous external abort, on translation table walk, level 2

010111

Synchronous external abort, on translation table walk, level 3

011101

Synchronous parity or ECC error on memory access on translation table walk, level 1

011110

Synchronous parity or ECC error on memory access on translation table walk, level 2

011111

Synchronous parity or ECC error on memory access on translation table walk, level 3

100010

Debug exception, only when the EC value is 0b100001

110000

TLB conflict abort

All other values are reserved.

When the RAS Extension is implemented, 011000, 011101, 011110, and 011111, are reserved.

Note

ARMv8.2 requires the implementation of the RAS Extension.

For more information about the lookup level associated with a fault, see 'The level associated with MMU faults on a Long-descriptor translation table lookup' in the ARMv8 ARM.

The following sections describe cases where Prefetch Abort exceptions can be routed to Hyp mode, generating exceptions that are reported in the HSR with EC value 0b100000:

Exception from an Illegal state or PC alignment fault

This is the layout of the ISS field for exceptions with the following EC values:

2423222120191817161514131211109876543210
0000000000000000000000000

Bits [24:0]

Reserved, RES0.

For more information about the Illegal state exception, see:

For more information about the PC alignment fault exception, see 'Branching to an unaligned PC' in the ARMv8 ARM, appendix A.

Exception from a Data Abort

This is the layout of the ISS field for exceptions with the following EC values:

2423222120191817161514131211109876543210
ISVSASSSE0SRT0AR00AETFnVEACMS1PTWWnRDFSC

ISV, bit [24]

Instruction syndrome valid. Indicates whether the syndrome information in ISS[23:14] is valid.

ISVMeaning
0

No valid instruction syndrome. ISS[23:14] are RES0.

1

ISS[23:14] hold a valid instruction syndrome.

This bit is 0 for all faults except Data Aborts generated by stage 2 address translations for which all the following apply to the instruction that generated the Data Abort exception:

For these cases, ISV is UNKNOWN if the exception was generated in Debug state in memory access mode, as described in 'Data Aborts in Memory access mode' in the ARMv8 ARM, section H4.3.2 (Memory access mode), and otherwise indicates whether ISS[23:14] hold a valid syndrome.

Note

In the A32 instruction set, LDR*T and STR*T instructions always perform register writeback and therefore never return a valid instruction syndrome.

When the RAS Extension is implemented, ISV is 0 for any Synchronous external abort.

ISV is set to 0 on a stage 2 abort on a stage 1 translation table walk.

When the RAS Extension is not implemented, it is IMPLEMENTATION DEFINED whether ISV is set to 1 or 0 on a Synchronous external abort on a stage 2 translation table walk.

SAS, bits [23:22]

Syndrome Access Size. When ISV is 1, indicates the size of the access attempted by the faulting operation.

SASMeaning
00

Byte

01

Halfword

10

Word

11

Doubleword

This field is UNKNOWN when the value of ISV is UNKNOWN.

This field is RES0 when the value of ISV is 0.

SSE, bit [21]

Syndrome Sign Extend. When ISV is 1, for a byte, halfword, or word load operation, indicates whether the data item must be sign extended. For these cases, the possible values of this bit are:

SSEMeaning
0

Sign-extension not required.

1

Data item must be sign-extended.

For all other operations this bit is 0.

This field is UNKNOWN when the value of ISV is UNKNOWN.

This field is RES0 when the value of ISV is 0.

Bit [20]

Reserved, RES0.

SRT, bits [19:16]

Syndrome Register transfer. When ISV is 1, the register number of the Rt operand of the faulting instruction.

This field is UNKNOWN when the value of ISV is UNKNOWN.

This field is RES0 when the value of ISV is 0.

Bit [15]

Reserved, RES0.

AR, bit [14]

Acquire/Release. When ISV is 1, the possible values of this bit are:

ARMeaning
0

Instruction did not have acquire/release semantics.

1

Instruction did have acquire/release semantics.

This field is UNKNOWN when the value of ISV is UNKNOWN.

This field is RES0 when the value of ISV is 0.

Bits [13:12]

Reserved, RES0.

AET, bit [11]

Asynchronous Error Type.

When the RAS Extension is implemented and the value returned in the DFSC field is 010001, describes the state of the PE after taking the SError interrupt exception. The possible values of this field are:

AETMeaning
00

Uncontainable error (UC) or uncategorized.

01

Unrecoverable error (UEU).

10

Restartable error (UEO) or Corrected error (CE).

11

Recoverable error (UER).

On a synchronous Data Abort, this field is RES0.

If multiple errors are taken as a single SError interrupt exception, the overall state of the PE is reported. For example, if both a Recoverable and Unrecoverable error occurred, the state is Unrecoverable.

Note

Software can use this information to determine what recovery might be possible. The recovery software must also examine any implemented fault records to determine the location and extent of the error.

When the RAS Extension is not implemented, or when DFSC is not 010001:

Note

ARMv8.2 requires the implementation of the RAS Extension.

FnV, bit [10]

FAR not Valid, for a Synchronous external abort other than a Synchronous external abort on a translation table walk.

FnVMeaning
0

HDFAR is valid.

1

HDFAR is not valid, and holds an UNKNOWN value.

When the RAS Extension is not implemented, this field is valid only if DFSC is 010000. It is RES0 for all other aborts.

When the RAS Extension is implemented:

Note

ARMv8.2 requires the implementation of the RAS Extension.

EA, bit [9]

External abort type. This bit can provide an IMPLEMENTATION DEFINED classification of External aborts.

For any abort other than an External abort this bit returns a value of 0.

CM, bit [8]

Cache maintenance. For a synchronous fault, identifies fault that comes from a cache maintenance or address translation instruction. For synchronous faults, the possible values of this bit are:

CMMeaning
0

Fault not generated by a cache maintenance or address translation instruction.

1

Fault generated by a cache maintenance or address translation instruction.

For an asynchronous Data Abort exception, this bit is 0.

S1PTW, bit [7]

For a stage 2 fault, indicates whether the fault was a stage 2 fault on an access made for a stage 1 translation table walk:

S1PTWMeaning
0

Fault not on a stage 2 translation for a stage 1 translation table walk.

1

Fault on the stage 2 translation of an access for a stage 1 translation table walk.

For any abort other than a stage 2 fault this bit is RES0.

WnR, bit [6]

Write not Read. Indicates whether a synchronous abort was caused by a write instruction or a read instruction. The possible values of this bit are:

WnRMeaning
0

Abort caused by a read instruction.

1

Abort caused by a write instruction.

For faults on cache maintenance and address translation instructions, this bit always returns a value of 1.

On an asynchronous Data Abort:

Note

ARMv8.2 requires the implementation of the RAS Extension.

DFSC, bits [5:0]

Data Fault Status Code. Possible values of this field are:

DFSCMeaning
000000

Address size fault, translation table base register

000001

Address size fault, level 1

000010

Address size fault, level 2

000011

Address size fault, level 3

000101

Translation fault, level 1

000110

Translation fault, level 2

000111

Translation fault, level 3

001001

Access flag fault, level 1

001010

Access flag fault, level 2

001011

Access flag fault, level 3

001101

Permission fault, level 1

001110

Permission fault, level 2

001111

Permission fault, level 3

010000

Synchronous external abort, not on translation table walk

011000

Synchronous parity or ECC error on memory access, not on translation table walk

010001

SError interrupt

011001

SError interrupt from a parity or ECC error on memory access

010101

Synchronous external abort, on translation table walk, level 1

010110

Synchronous external abort, on translation table walk, level 2

010111

Synchronous external abort, on translation table walk, level 3

011101

Synchronous parity or ECC error on memory access on translation table walk, level 1

011110

Synchronous parity or ECC error on memory access on translation table walk, level 2

011111

Synchronous parity or ECC error on memory access on translation table walk, level 3

100001

Alignment fault

100010

Debug exception, only when the EC value is 0b100100

110000

TLB conflict abort

110100

IMPLEMENTATION DEFINED fault (Lockdown)

110101

IMPLEMENTATION DEFINED fault (Unsupported Exclusive access)

All other values are reserved.

When the RAS Extension is implemented, 011000, 011001, 011101, 011110, and 011111, are reserved.

For more information about the lookup level associated with a fault, see 'The level associated with MMU faults on a Long-descriptor translation table lookup' in the ARMv8 ARM.

The following describe cases where Data Abort exceptions can be routed to Hyp mode, generating exceptions that are reported in the HSR with EC value 0b100100:

The following describe cases that can cause a Data Abort exception that is taken to Hyp mode, and reported in the HSR with EC value of 0b100000 or 0b100100:

Accessing the HSR

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 4, <Rt>, c5, c2, 0100000010111110010

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - - n/a -
x01 - - RWRW
x11 - n/a RWRW

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :




02/05/2017 15:43

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