ICC_BPR1_EL1, Interrupt Controller Binary Point Register 1

The ICC_BPR1_EL1 characteristics are:

Purpose

Defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field. The group priority field determines Group 1 interrupt preemption.

This register is part of:

Configuration

AArch64 System register ICC_BPR1_EL1 (S) is architecturally mapped to AArch32 System register ICC_BPR1 (S) .

AArch64 System register ICC_BPR1_EL1 (NS) is architecturally mapped to AArch32 System register ICC_BPR1 (NS) .

Virtual accesses to this register update ICH_VMCR_EL2.VBPR1.

Attributes

ICC_BPR1_EL1 is a 32-bit register.

Field descriptions

The ICC_BPR1_EL1 bit assignments are:

313029282726252423222120191817161514131211109876543210
00000000000000000000000000000BinaryPoint

Bits [31:3]

Reserved, RES0.

BinaryPoint, bits [2:0]

If the GIC is configured to use separate binary point fields for Group 0 and Group 1 interrupts, the value of this field controls how the 8-bit interrupt priority field is split into a group priority field, that determines interrupt preemption, and a subpriority field. For more information about priorities, see Priority grouping.

The minimum value of the Non-secure copy of this register is the minimum value of ICC_BPR0_EL1 + 1. The minimum value of the Secure copy of this register is the minimum value of ICC_BPR0_EL1.

If EL3 is implemented and ICC_CTLR_EL3.CBPR_EL1S is 1:

If EL3 is implemented and ICC_CTLR_EL3.CBPR_EL1NS is 1, Non-secure accesses to this register at EL1 or EL2 behave as follows, depending on the values of HCR_EL2.IMO and SCR_EL3.IRQ:

HCR_EL2.IMO SCR_EL3.IRQ Behavior
0 0 Non-secure EL1 and EL2 reads return ICC_BPR0_EL1 + 1 saturated to 0b111. Non-secure EL1 and EL2 writes are ignored.
0 1 Non-secure EL1 and EL2 accesses trap to EL3.
1 0 Non-secure EL1 accesses affect virtual interrupts. Non-secure EL2 reads return ICC_BPR0_EL1 + 1 saturated to 0b111. Non-secure EL2 writes are ignored.
1 1 Non-secure EL1 accesses affect virtual interrupts. Non-secure EL2 accesses trap to EL3.

If EL3 is not implemented and ICC_CTLR_EL1.CBPR is 1, Non-secure accesses to this register at EL1 or EL2 behave as follows, depending on the values of HCR_EL2.IMO:

HCR_EL2.IMO Behavior
0 Non-secure EL1 and EL2 reads return ICC_BPR0_EL1 + 1 saturated to 0b111. Non-secure EL1 and EL2 writes are ignored.
1 Non-secure EL1 accesses affect virtual interrupts. Non-secure EL2 reads return ICC_BPR0_EL1 + 1 saturated to 0b111. Non-secure EL2 writes are ignored.

Accessing the ICC_BPR1_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op1CRnCRmop2
ICC_BPR1_EL100011001100011

When HCR_EL2.IMO is set to 1, execution of this encoding at Non-secure EL1 results in an access to ICV_BPR1_EL1.

Accessibility

The register is accessible as follows:

Control Accessibility Instance
FMOIMOTGENSEL0EL1EL2EL3
xxx0 - RW n/a RWICC_BPR1_EL1_s
xx11 - n/a RWRWICC_BPR1_EL1_ns
x001 - RWRWRWICC_BPR1_EL1_ns
x101 - ICV_BPR1_EL1 RWRWICC_BPR1_EL1_ns

This table applies to all instructions that can access this register.

ICC_BPR1_EL1 is only accessible at Non-secure EL1 when HCR_EL2.IMO is set to 0.

Note

When HCR_EL2.IMO is set to 1, at Non-secure EL1, the instruction encoding used to access ICC_BPR1_EL1 results in an access to ICV_BPR1_EL1.

On a reset, the binary point field is UNKNOWN.

An attempt to program the binary point field to a value less than the minimum value sets the field to the minimum value.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When SCR_EL3.NS==1 :

When EL3 is implemented and is using AArch64 and SCR_EL3.NS==0 :

When EL3 is implemented and is using AArch64 :

When EL3 is implemented and is using AArch64 and SCR_EL3.NS==1 :




02/05/2017 15:43

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