ICV_IGRPEN0_EL1, Interrupt Controller Virtual Interrupt Group 0 Enable register

The ICV_IGRPEN0_EL1 characteristics are:

Purpose

Controls whether virtual Group 0 interrupts are enabled or not.

This register is part of:

Configuration

AArch64 System register ICV_IGRPEN0_EL1 is architecturally mapped to AArch32 System register ICV_IGRPEN0.

Attributes

ICV_IGRPEN0_EL1 is a 32-bit register.

Field descriptions

The ICV_IGRPEN0_EL1 bit assignments are:

313029282726252423222120191817161514131211109876543210
0000000000000000000000000000000Enable

Bits [31:1]

Reserved, RES0.

Enable, bit [0]

Enables virtual Group 0 interrupts.

EnableMeaning
0

Virtual Group 0 interrupts are disabled.

1

Virtual Group 0 interrupts are enabled.

When this register has an architecturally-defined reset value, this field resets to 0.

Accessing the ICV_IGRPEN0_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op1CRnCRmop2
ICC_IGRPEN0_EL100011001100110

When HCR_EL2.FMO is set to 0, execution of this encoding at Non-secure EL1 results in an access to ICC_IGRPEN0_EL1.

Accessibility

The register is accessible as follows:

Control Accessibility
FMOIMOTGENSEL0EL1EL2EL3
xxx0 - ICC_IGRPEN0_EL1 n/a ICC_IGRPEN0_EL1
xx11 - n/a ICC_IGRPEN0_EL1 ICC_IGRPEN0_EL1
0x01 - ICC_IGRPEN0_EL1 ICC_IGRPEN0_EL1 ICC_IGRPEN0_EL1
1x01 - RW ICC_IGRPEN0_EL1 ICC_IGRPEN0_EL1

This table applies to all instructions that can access this register.

ICV_IGRPEN0_EL1 is only accessible at Non-secure EL1 when HCR_EL2.FMO is set to 1.

Note

When HCR_EL2.FMO is set to 0, at Non-secure EL1, the instruction encoding used to access ICV_IGRPEN0_EL1 results in an access to ICC_IGRPEN0_EL1.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When SCR_EL3.NS==1 :




02/05/2017 15:43

Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.