The SPSR_EL2 characteristics are:
Holds the saved process state when an exception is taken to EL2.
This register is part of the Special-purpose registers functional group.
AArch64 System register SPSR_EL2 is architecturally mapped to AArch32 System register SPSR_hyp.
SPSR_EL2 is a 32-bit register.
The SPSR_EL2 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
N | Z | C | V | Q | IT[1:0] | J | 0 | PAN | SS | IL | GE | IT[7:2] | E | A | I | F | T | M[4] | M[3:0] |
An exception return from EL2 using AArch64 makes SPSR_EL2 become UNKNOWN.
Set to the value of CPSR.N on taking an exception to Hyp mode, and copied to CPSR.N on executing an exception return operation in Hyp mode.
Set to the value of CPSR.Z on taking an exception to Hyp mode, and copied to CPSR.Z on executing an exception return operation in Hyp mode.
Set to the value of CPSR.C on taking an exception to Hyp mode, and copied to CPSR.C on executing an exception return operation in Hyp mode.
Set to the value of CPSR.V on taking an exception to Hyp mode, and copied to CPSR.V on executing an exception return operation in Hyp mode.
Cumulative saturation bit. Set to 1 to indicate that overflow or saturation occurred in some instructions.
IT block state bits for the T32 IT (If-Then) instruction. See IT[7:2] for explanation of this field.
RES0.
In previous versions of the architecture, the {J, T} bits determined the AArch32 Instruction set state. ARMv8 does not support either Jazelle state or T32EE state, and the T bit determines the Instruction set state.
Reserved, RES0.
When ARMv8.1-PAN is implemented, set to the value of CPSR.PAN on taking an exception to Hyp mode, and copied to CPSR.PAN on executing an exception return operation in Hyp mode.
When ARMv8.1-PAN is not implemented, this bit is RES0.
Reserved, RES0.
Software step. Shows the value of PSTATE.SS immediately before the exception was taken.
Illegal Execution state bit. Shows the value of PSTATE.IL immediately before the exception was taken.
Greater than or Equal flags, for parallel addition and subtraction.
IT block state bits for the T32 IT (If-Then) instruction. This field must be interpreted in two parts.
The IT field is 0b00000000 when no IT block is active.
Endianness state bit. Controls the load and store endianness for data accesses:
E | Meaning |
---|---|
0 |
Little-endian operation |
1 |
Big-endian operation. |
Instruction fetches ignore this bit.
When the reset value of the SCTLR.EE bit is defined by a configuration input signal, that value also applies to the CPSR.E bit on reset, and therefore applies to software execution from reset.
If an implementation does not provide Big-endian support, this bit is RES0. If it does not provide Little-endian support, this bit is RES1.
If an implementation provides Big-endian support but only at EL0, this bit is RES0 for an exception return to any Exception level other than EL0.
Likewise, if it provides Little-endian support only at EL0, this bit is RES1 for an exception return to any Exception level other than EL0.
SError interrupt mask bit. The possible values of this bit are:
A | Meaning |
---|---|
0 |
Exception not masked. |
1 |
Exception masked. |
IRQ mask bit. The possible values of this bit are:
I | Meaning |
---|---|
0 |
Exception not masked. |
1 |
Exception masked. |
FIQ mask bit. The possible values of this bit are:
F | Meaning |
---|---|
0 |
Exception not masked. |
1 |
Exception masked. |
T32 Instruction set state bit. Determines the AArch32 instruction set state that the exception was taken from. Possible values of this bit are:
T | Meaning |
---|---|
0 |
Taken from A32 state. |
1 |
Taken from T32 state. |
Execution state that the exception was taken from. Possible values of this bit are:
M[4] | Meaning |
---|---|
1 |
Exception taken from AArch32. |
AArch32 mode that an exception was taken from. The possible values are:
M[3:0] | Mode |
---|---|
0b0000 | User |
0b0001 | FIQ |
0b0010 | IRQ |
0b0011 | Supervisor |
0b0111 | Abort |
0b1010 | Hyp |
0b1011 | Undefined |
0b1111 | System |
Other values are reserved. The effect of programming this field to a Reserved value is that behavior is CONSTRAINED UNPREDICTABLE, as described in 'Reserved values in AArch64 System registers and translation table entries' in the ARM ARM, section K1.2.2.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
N | Z | C | V | 0 | 0 | 0 | 0 | UAO | PAN | SS | IL | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | D | A | I | F | 0 | M[4] | M[3:0] |
An exception return from EL2 using AArch64 makes SPSR_EL2 become UNKNOWN.
Set to the value of the N condition flag on taking an exception to EL2, and copied to the N condition flag on executing an exception return operation in EL2.
Set to the value of the Z condition flag on taking an exception to EL2, and copied to the Z condition flag on executing an exception return operation in EL2.
Set to the value of the C condition flag on taking an exception to EL2, and copied to the C condition flag on executing an exception return operation in EL2.
Set to the value of the V condition flag on taking an exception to EL2, and copied to the V condition flag on executing an exception return operation in EL2.
Reserved, RES0.
When ARMv8.2-UAO is implemented, set to the value of PSTATE.UAO on taking an exception to EL2, and copied to PSTATE.UAO on executing an exception return operation in EL2.
When ARMv8.2-UAO is not implemented, this bit is RES0.
Reserved, RES0.
When ARMv8.1-PAN is implemented, set to the value of PSTATE.PAN on taking an exception to EL2, and copied to PSTATE.PAN on executing an exception return operation in EL2.
When ARMv8.1-PAN is not implemented, this bit is RES0.
Reserved, RES0.
Software step. Shows the value of PSTATE.SS immediately before the exception was taken.
Illegal Execution state bit. Shows the value of PSTATE.IL immediately before the exception was taken.
Reserved, RES0.
Process state D mask. The possible values of this bit are:
D | Meaning |
---|---|
0 |
Watchpoint, Breakpoint, and Software Step exceptions targeted at the current Exception level are not masked. |
1 |
Watchpoint, Breakpoint, and Software Step exceptions targeted at the current Exception level are masked. |
When the target Exception level of the debug exception is higher than the current Exception level, the exception is not masked by this bit.
SError interrupt mask bit. The possible values of this bit are:
A | Meaning |
---|---|
0 |
Exception not masked. |
1 |
Exception masked. |
IRQ mask bit. The possible values of this bit are:
I | Meaning |
---|---|
0 |
Exception not masked. |
1 |
Exception masked. |
FIQ mask bit. The possible values of this bit are:
F | Meaning |
---|---|
0 |
Exception not masked. |
1 |
Exception masked. |
Reserved, RES0.
Execution state that the exception was taken from. Possible values of this bit are:
M[4] | Meaning |
---|---|
0 |
Exception taken from AArch64. |
AArch64 state (Exception level and selected SP) that an exception was taken from. The possible values are:
M[3:0] | State |
---|---|
0b0000 | EL0t |
0b0100 | EL1t |
0b0101 | EL1h |
0b1000 | EL2t |
0b1001 | EL2h |
Other values are reserved, and returning to an Exception level that is using AArch64 with a reserved value in this field is treated as an illegal exception return.
The bits in this field are interpreted as follows:
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
SPSR_EL2 | 11 | 100 | 0100 | 0000 | 000 |
SPSR_EL1 | 11 | 000 | 0100 | 0000 | 000 |
The register is accessible as follows:
<systemreg> | Control | Accessibility | |||||
---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | |
SPSR_EL2 | x | x | 0 | - | - | n/a | RW |
SPSR_EL2 | 0 | 0 | 1 | - | - | RW | RW |
SPSR_EL2 | 0 | 1 | 1 | - | n/a | RW | RW |
SPSR_EL2 | 1 | 0 | 1 | - | - | RW | RW |
SPSR_EL2 | 1 | 1 | 1 | - | n/a | RW | RW |
SPSR_EL1 | x | x | 0 | - | SPSR_EL1 | n/a | SPSR_EL1 |
SPSR_EL1 | 0 | 0 | 1 | - | SPSR_EL1 | SPSR_EL1 | SPSR_EL1 |
SPSR_EL1 | 0 | 1 | 1 | - | n/a | SPSR_EL1 | SPSR_EL1 |
SPSR_EL1 | 1 | 0 | 1 | - | SPSR_EL1 | RW | SPSR_EL1 |
SPSR_EL1 | 1 | 1 | 1 | - | n/a | RW | SPSR_EL1 |
When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic SPSR_EL2 or SPSR_EL1 are not guaranteed to be ordered with respect to accesses using the other mnemonic.
02/05/2017 15:43
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