ICC_IGRPEN1, Interrupt Controller Interrupt Group 1 Enable register

The ICC_IGRPEN1 characteristics are:

Purpose

Controls whether Group 1 interrupts are enabled for the current Security state.

This register is part of:

Configuration

AArch32 System register ICC_IGRPEN1 (S) is architecturally mapped to AArch64 System register ICC_IGRPEN1_EL1 (S) .

AArch32 System register ICC_IGRPEN1 (NS) is architecturally mapped to AArch64 System register ICC_IGRPEN1_EL1 (NS) .

Attributes

ICC_IGRPEN1 is a 32-bit register.

Field descriptions

The ICC_IGRPEN1 bit assignments are:

313029282726252423222120191817161514131211109876543210
0000000000000000000000000000000Enable

Bits [31:1]

Reserved, RES0.

Enable, bit [0]

Enables Group 1 interrupts for the current Security state.

EnableMeaning
0

Group 1 interrupts are disabled for the current Security state.

1

Group 1 interrupts are enabled for the current Security state.

Virtual accesses to this register update ICH_VMCR.VENG1.

If EL3 is present:

When this register has an architecturally-defined reset value, this field resets to 0.

Accessing the ICC_IGRPEN1

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 0, <Rt>, c12, c12, 7000111110011111100
p15, 0, <Rt>, c12, c12, 7000111110011111100

When HCR.IMO is set to 1, execution of this encoding at Non-secure EL1 results in an access to ICV_IGRPEN1.

Accessibility

The register is accessible as follows:

<syntax> Configuration Control Accessibility Instance
FMOIMOTGENSEL0EL1EL2EL3
p15, 0, <Rt>, c12, c12, 7 EL3 not implemented xxx0 - RW n/a n/a ICC_IGRPEN1
p15, 0, <Rt>, c12, c12, 7 EL3 not implemented xx11 - n/a RW n/a ICC_IGRPEN1
p15, 0, <Rt>, c12, c12, 7 EL3 not implemented x001 - RWRW n/a ICC_IGRPEN1
p15, 0, <Rt>, c12, c12, 7 EL3 not implemented x101 - ICV_IGRPEN1 RW n/a ICC_IGRPEN1
p15, 0, <Rt>, c12, c12, 7 EL3 using AArch64xx11 - n/a RW n/a ICC_IGRPEN1_ns
p15, 0, <Rt>, c12, c12, 7 EL3 using AArch64x001 - RWRW n/a ICC_IGRPEN1_ns
p15, 0, <Rt>, c12, c12, 7 EL3 using AArch64x101 - ICV_IGRPEN1 RW n/a ICC_IGRPEN1_ns
p15, 0, <Rt>, c12, c12, 7 EL3 using AArch32xx11 - n/a RWRWICC_IGRPEN1_ns
p15, 0, <Rt>, c12, c12, 7 EL3 using AArch32x001 - RWRWRWICC_IGRPEN1_ns
p15, 0, <Rt>, c12, c12, 7 EL3 using AArch32x101 - ICV_IGRPEN1 RWRWICC_IGRPEN1_ns
p15, 0, <Rt>, c12, c12, 7 EL3 using AArch64xxx0 - RW n/a n/a ICC_IGRPEN1_s
p15, 0, <Rt>, c12, c12, 7 EL3 using AArch32xxx0 - - - RWICC_IGRPEN1_s

ICC_IGRPEN1 is only accessible at Non-secure EL1 when HCR.IMO is set to 0.

Note

When HCR.IMO is set to 1, at Non-secure EL1, the instruction encoding used to access ICC_IGRPEN1 results in an access to ICV_IGRPEN1.

The lowest Exception level at which this register can be accessed is governed by the Exception level to which IRQ is routed. This routing depends on SCR.IRQ, SCR.NS and HCR.IMO.

If an interrupt is pending within the CPU interface when Enable becomes 0, the interrupt must be released to allow the Distributor to forward the interrupt to a different PE.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :

When SCR_EL3.NS==1 :

When EL3 is implemented and is using AArch32 :

When EL3 is implemented and is using AArch32 and SCR_EL3.NS==1 :

When EL3 is implemented and is using AArch64 and SCR_EL3.NS==0 :

When EL3 is implemented and is using AArch64 :

When EL3 is implemented and is using AArch64 and SCR_EL3.NS==1 :




02/05/2017 15:43

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