The ICC_EOIR1 characteristics are:
A PE writes to this register to inform the CPU interface that it has completed the processing of the specified Group 1 interrupt.
This register is part of:
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register ICC_EOIR1 performs the same function as AArch64 System register ICC_EOIR1_EL1.
ICC_EOIR1 is a 32-bit register.
The ICC_EOIR1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | INTID |
Reserved, RES0.
The INTID from the corresponding ICC_IAR1 access.
This field has either 16 or 24 bits implemented. The number of implemented bits can be found in ICC_CTLR.IDbits and ICC_MCTLR.IDbits. If only 16 bits are implemented, bits [23:16] of this register are RES0.
If the EOImode bit for the current Exception level and Security state is 0, a write to this register drops the priority for the interrupt, and also deactivates the interrupt.
If the EOImode bit for the current Exception level and Security state is 1, a write to this register only drops the priority for the interrupt. Software must write to ICC_DIR to deactivate the interrupt.
The appropriate EOImode bit varies as follows:
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c12, c12, 1 | 000 | 001 | 1100 | 1111 | 1100 |
When HCR.IMO is set to 1, execution of this encoding at Non-secure EL1 results in an access to ICV_EOIR1.
The register is accessible as follows:
Control | Accessibility | ||||||
---|---|---|---|---|---|---|---|
FMO | IMO | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | x | 0 | - | WO | n/a | WO |
x | x | 1 | 1 | - | n/a | WO | WO |
x | 0 | 0 | 1 | - | WO | WO | WO |
x | 1 | 0 | 1 | - | ICV_EOIR1 | WO | WO |
This table applies to all instructions that can access this register.
ICC_EOIR1 is only accessible at Non-secure EL1 when HCR.IMO is set to 0.
When HCR.IMO is set to 1, at Non-secure EL1, the instruction encoding used to access ICC_EOIR1 results in an access to ICV_EOIR1.
A write to this register must correspond to the most recent valid read by this PE from an Interrupt Acknowledge Register, and must correspond to the INTID that was read from ICC_IAR1, otherwise the system behavior is UNPREDICTABLE. A valid read is a read that returns a valid INTID that is not a special INTID.
A write of a Special INTID is ignored. See Special INTIDs, for more information.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_SRE.SRE==0, write accesses to this register from EL1 are UNDEFINED.
If ICC_HSRE.SRE==0, write accesses to this register from EL2 are UNDEFINED.
If ICC_MSRE.SRE==0, write accesses to this register from EL3 are UNDEFINED.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==0 :
If HSTR_EL2.T12==1, Non-secure write accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T12==1, Non-secure write accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HSTR.T12==1, Non-secure write accesses to this register from EL1 are trapped to Hyp mode.
When SCR_EL3.NS==1 :
If ICH_HCR.TALL1==1, Non-secure write accesses to this register from EL1 are trapped to EL2.
If ICH_HCR_EL2.TALL1==1, Non-secure write accesses to this register from EL1 are trapped to EL2.
When EL3 is implemented and is using AArch32 :
If SCR.IRQ==1, write accesses to this register from EL2 and EL3 modes other than Monitor mode are UNDEFINED.
When EL3 is implemented and is using AArch32 and SCR_EL3.NS==1 :
When EL3 is implemented and is using AArch64 and SCR_EL3.NS==0 :
If SCR_EL3.IRQ==1, Secure write accesses to this register from EL1 are trapped to EL3.
When EL3 is implemented and is using AArch64 :
If SCR_EL3.IRQ==1, write accesses to this register from EL2 are trapped to EL3.
When EL3 is implemented and is using AArch64 and SCR_EL3.NS==1 :
02/05/2017 15:43
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