The EDECR characteristics are:
Controls Halting debug events.
This register is part of the Debug registers functional group.
This register is accessible as follows:
SLK | Default |
---|---|
RO | RW |
EDECR is in the Debug power domain. Some or all RW fields of this register have defined reset values. These apply only on an External debug reset. The register is not affected by a Warm reset and is not affected by a Cold reset.
EDECR is a 32-bit register.
The EDECR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SS | RCE | OSUCE |
Reserved, RES0.
Halting step enable. Possible values of this field are:
SS | Meaning |
---|---|
0 |
Halting step debug event disabled. |
1 |
Halting step debug event enabled. |
If the value of EDECR.SS is changed when the PE is in Non-debug state, behavior is CONSTRAINED UNPREDICTABLE as described in 'Changing the value of EDECR.SS when not in Debug state' in the ARM ARM, section H3.2.5.
When this register has an architecturally-defined reset value, this field resets to 0.
Reset Catch enable. Possible values of this field are:
RCE | Meaning |
---|---|
0 |
Reset Catch debug event disabled. |
1 |
Reset Catch debug event enabled. |
When this register has an architecturally-defined reset value, this field resets to 0.
OS Unlock Catch enabled. Possible values of this field are:
OSUCE | Meaning |
---|---|
0 |
OS Unlock Catch debug event disabled. |
1 |
OS Unlock Catch debug event enabled. |
When this register has an architecturally-defined reset value, this field resets to 0.
EDECR can be accessed through the external debug interface:
Component | Offset |
---|---|
Debug | 0x024 |
02/05/2017 15:43
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