The EDDFR characteristics are:
Provides top level information about the debug system.
Debuggers must use EDDEVARCH to determine the Debug architecture version.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.
This register is part of the Identification registers functional group.
This register is accessible as follows:
Off | DLK | Default |
---|---|---|
IMP DEF | IMP DEF | RO |
It is IMPLEMENTATION DEFINED whether EDDFR is implemented in the Core power domain or in the Debug power domain.
EDDFR is a 64-bit register.
The EDDFR bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
CTX_CMPs | 0 | 0 | 0 | 0 | WRPs | 0 | 0 | 0 | 0 | BRPs | PMUVer | TraceVer | UNKNOWN | ||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Number of breakpoints that are context-aware, minus 1. These are the highest numbered breakpoints.
In an ARMv8-A implementation that supports AArch64 state in at least one Exception level, this field returns the value of ID_AA64DFR0_EL1.CTX_CMPs.
Reserved, RES0.
Number of watchpoints, minus 1. The value of 0b0000 is reserved.
In an ARMv8-A implementation that supports AArch64 state in at least one Exception level, this field returns the value of ID_AA64DFR0_EL1.WRPs.
Reserved, RES0.
Number of breakpoints, minus 1. The value of 0b0000 is reserved.
In an ARMv8-A implementation that supports AArch64 state in at least one Exception level, this field returns the value of ID_AA64DFR0_EL1.BRPs.
Performance Monitors Extension version. Indicates whether System register interface to Performance Monitors extension is implemented. Defined values are:
PMUVer | Meaning |
---|---|
0000 |
Performance Monitors Extension System registers not implemented. |
0001 |
Performance Monitors Extension System registers implemented, PMUv3. |
0100 |
Performance Monitors Extension System registers implemented, PMUv3, with a 16-bit evtCount field, and if EL2 is implemented, the addition of the MDCR_EL2.HPMD bit. |
1111 |
IMPLEMENTATION DEFINED form of performance monitors supported, PMUv3 not supported. |
All other values are reserved.
In ARMv8.0 the permitted values are 0b0000, 0b0001 and 0b1111.
From ARMv8.1 the permitted values are 0b0000, 0b0100 and 0b1111.
In an ARMv8-A implementation that supports AArch64 state in at least one Exception level, this field returns the value of ID_AA64DFR0_EL1.PMUVer.
Trace support. Indicates whether System register interface to a trace macrocell is implemented. Defined values are:
TraceVer | Meaning |
---|---|
0000 |
Trace macrocell System registers not implemented. |
0001 |
Trace macrocell System registers implemented. |
All other values are reserved.
A value of 0b0000 only indicates that no System register interface to a trace macrocell is implemented. A trace macrocell might nevertheless be implemented without a System register interface.
In an ARMv8-A implementation that supports AArch64 state in at least one Exception level, this field returns the value of ID_AA64DFR0_EL1.TraceVer.
Reserved, UNKNOWN.
EDDFR[31:0] can be accessed through the external debug interface:
Component | Offset |
---|---|
Debug | 0xD28 |
EDDFR[63:32] can be accessed through the external debug interface:
Component | Offset |
---|---|
Debug | 0xD2C |
02/05/2017 15:43
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