The CNTNSAR characteristics are:
Provides the highest-level control of whether frames CNTBaseN and CNTEL0BaseN are accessible by Non-secure accesses.
This register is part of the Generic Timer registers functional group.
This register is accessible as follows:
Default |
---|
RW |
In a system that recognizes two Security states, this register is only accessible by Secure accesses.
The power domain of CNTNSAR is IMPLEMENTATION DEFINED.
On a reset of the reset domain in which it is implemented, RW fields in this register reset to UNKNOWN values. The register is not affected by a reset of any other reset domain. For more information see 'Power and reset domains for the system level implementation of the Generic Timer' in Chapter I1 of the ARMv8 ARM.
CNTNSAR is a 32-bit register.
The CNTNSAR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | NS7 | NS6 | NS5 | NS4 | NS3 | NS2 | NS1 | NS0 |
Reserved, RES0.
Non-secure access to frame n. The possible values of this bit are:
NS<n> | Meaning |
---|---|
0 |
Secure access only. Behaves as RES0 to Non-secure accesses. |
1 |
Secure and Non-secure accesses permitted. |
This bit also determines whether, in the CNTCTLBase frame, CNTACR<n> and CNTVOFF<n> are accessible to Non-secure accesses.
If frame CNTBase<n>:
CNTNSAR can be accessed through its memory-mapped interface:
Component | Frame | Offset |
---|---|---|
Timer | CNTCTLBase | 0x004 |
02/05/2017 15:43
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