ICH_MISR_EL2, Interrupt Controller Maintenance Interrupt State Register

The ICH_MISR_EL2 characteristics are:

Purpose

Indicates which maintenance interrupts are asserted.

This register is part of:

Configuration

AArch64 System register ICH_MISR_EL2 is architecturally mapped to AArch32 System register ICH_MISR.

If EL2 is not implemented, this register is RES0 from EL3.

Attributes

ICH_MISR_EL2 is a 32-bit register.

Field descriptions

The ICH_MISR_EL2 bit assignments are:

313029282726252423222120191817161514131211109876543210
000000000000000000000000VGrp1DVGrp1EVGrp0DVGrp0ENPLRENPUEOI

Bits [31:8]

Reserved, RES0.

VGrp1D, bit [7]

vPE Group 1 Disabled.

VGrp1DMeaning
0

vPE Group 1 Disabled maintenance interrupt not asserted.

1

vPE Group 1 Disabled maintenance interrupt asserted.

This maintenance interrupt is asserted when ICH_HCR_EL2.VGrp1DIE==1 and ICH_VMCR_EL2.VENG1==is 0.

When this register has an architecturally-defined reset value, this field resets to 0.

VGrp1E, bit [6]

vPE Group 1 Enabled.

VGrp1EMeaning
0

vPE Group 1 Enabled maintenance interrupt not asserted.

1

vPE Group 1 Enabled maintenance interrupt asserted.

This maintenance interrupt is asserted when ICH_HCR_EL2.VGrp1EIE==1 and ICH_VMCR_EL2.VENG1==is 1.

When this register has an architecturally-defined reset value, this field resets to 0.

VGrp0D, bit [5]

vPE Group 0 Disabled.

VGrp0DMeaning
0

vPE Group 0 Disabled maintenance interrupt not asserted.

1

vPE Group 0 Disabled maintenance interrupt asserted.

This maintenance interrupt is asserted when ICH_HCR_EL2.VGrp0DIE==1 and ICH_VMCR_EL2.VENG0==0.

When this register has an architecturally-defined reset value, this field resets to 0.

VGrp0E, bit [4]

vPE Group 0 Enabled.

VGrp0EMeaning
0

vPE Group 0 Enabled maintenance interrupt not asserted.

1

vPE Group 0 Enabled maintenance interrupt asserted.

This maintenance interrupt is asserted when ICH_HCR_EL2.VGrp0EIE==1 and ICH_VMCR_EL2.VENG0==1.

When this register has an architecturally-defined reset value, this field resets to 0.

NP, bit [3]

No Pending.

NPMeaning
0

No Pending maintenance interrupt not asserted.

1

No Pending maintenance interrupt asserted.

This maintenance interrupt is asserted when ICH_HCR_EL2.NPIE==1 and no List register is in pending state.

When this register has an architecturally-defined reset value, this field resets to 0.

LRENP, bit [2]

List Register Entry Not Present.

LRENPMeaning
0

List Register Entry Not Present maintenance interrupt not asserted.

1

List Register Entry Not Present maintenance interrupt asserted.

This maintenance interrupt is asserted when ICH_HCR_EL2.LRENPIE==1 and ICH_HCR_EL2.EOIcount is non-zero.

When this register has an architecturally-defined reset value, this field resets to 0.

U, bit [1]

Underflow.

UMeaning
0

Underflow maintenance interrupt not asserted.

1

Underflow maintenance interrupt asserted.

This maintenance interrupt is asserted when ICH_HCR_EL2.UIE==1 and zero or one of the List register entries are marked as a valid interrupt, that is, if the corresponding ICH_LR<n>_EL2.State bits do not equal 0x0.

When this register has an architecturally-defined reset value, this field resets to 0.

EOI, bit [0]

End Of Interrupt.

EOIMeaning
0

End Of Interrupt maintenance interrupt not asserted.

1

End Of Interrupt maintenance interrupt asserted.

This maintenance interrupt is asserted when at least one bit in ICH_EISR_EL2 is 1.

When this register has an architecturally-defined reset value, this field resets to 0.

The U and NP bits do not include the status of any pending/active VSET packets because these bits control generation of interrupts that allow software management of the contents of the List Registers (which are not affected by VSET packets).

Accessing the ICH_MISR_EL2

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op1CRnCRmop2
ICH_MISR_EL210011001011010

Accessibility

The register is accessible as follows:

Control Accessibility
TGENSEL0EL1EL2EL3
x0 - - n/a RO
01 - - RORO
11 - n/a RORO

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:




02/05/2017 15:43

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