GICR_SYNCR, Redistributor Synchronize Register

The GICR_SYNCR characteristics are:

Purpose

Indicates completion of physical Redistributor operations.

This register is part of the GIC Redistributor registers functional group.

Usage constraints

This register is accessible as follows:

Security disabledSecureNon-secure
RORORO

Optionally, when this register is accessed, an implementation might wait until all operations are complete before returning a value, in which case GICR_SYNCR.Busy is always 0.

This register is mandatory in an implementation that supports LPIs and does not include an ITS. The functionality is IMPLEMENTATION DEFINED in an implementation that does include an ITS.

Configuration

A copy of this register is provided for each Redistributor.

Attributes

GICR_SYNCR is a 32-bit register.

Field descriptions

The GICR_SYNCR bit assignments are:

313029282726252423222120191817161514131211109876543210
0000000000000000000000000000000Busy

Bits [31:1]

Reserved, RES0.

Busy, bit [0]

Indicates completion of any Redistributor operations as follows:

BusyMeaning
0

No operations are in progress.

1

A write is in progress to one or more of the following registers:

This field also indicates completion of any operations initiated by writes to GICR_PENDBASER or GICR_PROPBASER.

Accessing the GICR_SYNCR

GICR_SYNCR can be accessed through its memory-mapped interface:

ComponentFrameOffset
GIC RedistributorRD_base0x00C0-0x00C4



02/05/2017 15:43

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