The JOSCR characteristics are:
A Jazelle register, which provides operating system control of the Jazelle Extension.
This register is part of the Legacy feature registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
JOSCR is a 32-bit register.
The JOSCR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
RAZ/WI at EL1, EL2, and EL3. It is IMPLEMENTATION DEFINED whether this field is RAZ/WI or UNDEFINED at EL0.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p14, 7, <Rt>, c1, c0, 0 | 111 | 000 | 0001 | 1110 | 0000 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | implementation defined | RW | n/a | RW |
x | 0 | 1 | implementation defined | RW | RW | RW |
x | 1 | 1 | implementation defined | n/a | RW | RW |
This table applies to all instructions that can access this register.
For accesses from EL0 it is IMPLEMENTATION DEFINED whether the register is RW or UNDEFINED.
02/05/2017 15:43
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