VBAR_EL2, Vector Base Address Register (EL2)

The VBAR_EL2 characteristics are:

Purpose

Holds the vector base address for any exception that is taken to EL2.

This register is part of:

Configuration

AArch64 System register VBAR_EL2 bits [31:0] are architecturally mapped to AArch32 System register HVBAR.

If EL2 is not implemented, this register is RES0 from EL3.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

VBAR_EL2 is a 64-bit register.

Field descriptions

The VBAR_EL2 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
Vector Base Address
Vector Base Address00000000000
313029282726252423222120191817161514131211109876543210

Bits [63:11]

Vector Base Address. Base address of the exception vectors for exceptions taken to EL2.

If the implementation does not support ARMv8.2-LVA, then:

If the implementation supports ARMv8.2-LVA, then:

Bits [10:0]

Reserved, RES0.

Accessing the VBAR_EL2

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
VBAR_EL21110011000000000
VBAR_EL11100011000000000

Accessibility

The register is accessible as follows:

<systemreg> Control Accessibility
E2HTGENSEL0EL1EL2EL3
VBAR_EL2xx0 - - n/a RW
VBAR_EL2001 - - RWRW
VBAR_EL2011 - n/a RWRW
VBAR_EL2101 - - RWRW
VBAR_EL2111 - n/a RWRW
VBAR_EL1xx0 - VBAR_EL1 n/a VBAR_EL1
VBAR_EL1001 - VBAR_EL1 VBAR_EL1 VBAR_EL1
VBAR_EL1011 - n/a VBAR_EL1 VBAR_EL1
VBAR_EL1101 - VBAR_EL1 RW VBAR_EL1
VBAR_EL1111 - n/a RW VBAR_EL1

When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic VBAR_EL2 or VBAR_EL1 are not guaranteed to be ordered with respect to accesses using the other mnemonic.




02/05/2017 15:43

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