ID_MMFR1_EL1, AArch32 Memory Model Feature Register 1

The ID_MMFR1_EL1 characteristics are:

Purpose

Provides information about the implemented memory model and memory management support in AArch32 state.

Must be interpreted with ID_MMFR0_EL1, ID_MMFR2_EL1, ID_MMFR3_EL1, and ID_MMFR4_EL1.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.

This register is part of the Identification registers functional group.

Configuration

AArch64 System register ID_MMFR1_EL1 is architecturally mapped to AArch32 System register ID_MMFR1.

In an implementation that supports only AArch64 state, this register is UNKNOWN.

Attributes

ID_MMFR1_EL1 is a 32-bit register.

Field descriptions

The ID_MMFR1_EL1 bit assignments are:

313029282726252423222120191817161514131211109876543210
BPredL1TstClnL1UniL1HvdL1UniSWL1HvdSWL1UniVAL1HvdVA

BPred, bits [31:28]

Branch Predictor. Indicates branch predictor management requirements. Defined values are:

BPredMeaning
0000

No branch predictor, or no MMU present. Implies a fixed MPU configuration.

0001

Branch predictor requires flushing on:

  • Enabling or disabling a stage of address translation.
  • Writing new data to instruction locations.
  • Writing new mappings to the translation tables.
  • Changes to the TTBR0, TTBR1, or TTBCR registers.
  • Changes to the ContextID or ASID, or to the FCSE ProcessID if this is supported.
0010

Branch predictor requires flushing on:

  • Enabling or disabling a stage of address translation.
  • Writing new data to instruction locations.
  • Writing new mappings to the translation tables.
  • Any change to the TTBR0, TTBR1, or TTBCR registers without a change to the corresponding ContextID or ASID, or FCSE ProcessID if this is supported.
0011

Branch predictor requires flushing only on writing new data to instruction locations.

0100

For execution correctness, branch predictor requires no flushing at any time.

All other values are reserved.

In ARMv8-A the permitted values are 0010, 0011, or 0100. For values other than 0000 and 0100 the ARM Architecture Reference Manual, or the product documentation, might give more information about the required maintenance.

L1TstCln, bits [27:24]

Level 1 cache Test and Clean. Indicates the supported Level 1 data cache test and clean operations, for Harvard or unified cache implementations. Defined values are:

L1TstClnMeaning
0000

None supported.

0001

Supported Level 1 data cache test and clean operations are:

  • Test and clean data cache.
0010

As for 0001, and adds:

  • Test, clean, and invalidate data cache.

All other values are reserved.

In ARMv8-A the only permitted value is 0000.

L1Uni, bits [23:20]

Level 1 Unified cache. Indicates the supported entire Level 1 cache maintenance operations for a unified cache implementation. Defined values are:

L1UniMeaning
0000

None supported.

0001

Supported entire Level 1 cache operations are:

  • Invalidate cache, including branch predictor if appropriate.
  • Invalidate branch predictor, if appropriate.
0010

As for 0001, and adds:

  • Clean cache, using a recursive model that uses the cache dirty status bit.
  • Clean and invalidate cache, using a recursive model that uses the cache dirty status bit.

All other values are reserved.

In ARMv8-A the only permitted value is 0000.

L1Hvd, bits [19:16]

Level 1 Harvard cache. Indicates the supported entire Level 1 cache maintenance operations for a Harvard cache implementation. Defined values are:

L1HvdMeaning
0000

None supported.

0001

Supported entire Level 1 cache operations are:

  • Invalidate instruction cache, including branch predictor if appropriate.
  • Invalidate branch predictor, if appropriate.
0010

As for 0001, and adds:

  • Invalidate data cache.
  • Invalidate data cache and instruction cache, including branch predictor if appropriate.
0011

As for 0010, and adds:

  • Clean data cache, using a recursive model that uses the cache dirty status bit.
  • Clean and invalidate data cache, using a recursive model that uses the cache dirty status bit.

All other values are reserved.

In ARMv8-A the only permitted value is 0000.

L1UniSW, bits [15:12]

Level 1 Unified cache by Set/Way. Indicates the supported Level 1 cache line maintenance operations by set/way, for a unified cache implementation. Defined values are:

L1UniSWMeaning
0000

None supported.

0001

Supported Level 1 unified cache line maintenance operations by set/way are:

  • Clean cache line by set/way.
0010

As for 0001, and adds:

  • Clean and invalidate cache line by set/way.
0011

As for 0010, and adds:

  • Invalidate cache line by set/way.

All other values are reserved.

In ARMv8-A the only permitted value is 0000.

L1HvdSW, bits [11:8]

Level 1 Harvard cache by Set/Way. Indicates the supported Level 1 cache line maintenance operations by set/way, for a Harvard cache implementation. Defined values are:

L1HvdSWMeaning
0000

None supported.

0001

Supported Level 1 Harvard cache line maintenance operations by set/way are:

  • Clean data cache line by set/way.
  • Clean and invalidate data cache line by set/way.
0010

As for 0001, and adds:

  • Invalidate data cache line by set/way.
0011

As for 0010, and adds:

  • Invalidate instruction cache line by set/way.

All other values are reserved.

In ARMv8-A the only permitted value is 0000.

L1UniVA, bits [7:4]

Level 1 Unified cache by Virtual Address. Indicates the supported Level 1 cache line maintenance operations by VA, for a unified cache implementation. Defined values are:

L1UniVAMeaning
0000

None supported.

0001

Supported Level 1 unified cache line maintenance operations by VA are:

  • Clean cache line by VA.
  • Invalidate cache line by VA.
  • Clean and invalidate cache line by VA.
0010

As for 0001, and adds:

  • Invalidate branch predictor by VA, if branch predictor is implemented.

All other values are reserved.

In ARMv8-A the only permitted value is 0000.

L1HvdVA, bits [3:0]

Level 1 Harvard cache by Virtual Address. Indicates the supported Level 1 cache line maintenance operations by VA, for a Harvard cache implementation. Defined values are:

L1HvdVAMeaning
0000

None supported.

0001

Supported Level 1 Harvard cache line maintenance operations by VA are:

  • Clean data cache line by VA.
  • Invalidate data cache line by VA.
  • Clean and invalidate data cache line by VA.
  • Clean instruction cache line by VA.
0010

As for 0001, and adds:

  • Invalidate branch predictor by VA, if branch predictor is implemented.

All other values are reserved.

In ARMv8-A the only permitted value is 0000.

Accessing the ID_MMFR1_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
ID_MMFR1_EL11100000000001101

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RO n/a RO
x01 - RORORO
x11 - n/a RORO

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :




02/05/2017 15:43

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