The MDSCR_EL1 characteristics are:
Main control register for the debug implementation.
This register is part of the Debug registers functional group.
AArch64 System register MDSCR_EL1 is architecturally mapped to AArch32 System register DBGDSCRext.
This register is in the Warm reset domain. Some or all RW fields of this register have defined reset values. On a Warm or Cold reset these apply only if the PE resets into an Exception level that is using AArch64. Otherwise, on a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.
MDSCR_EL1 is a 32-bit register.
The MDSCR_EL1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | RXfull | TXfull | 0 | RXO | TXU | 0 | 0 | INTdis | TDA | 0 | SC2 | 0 | 0 | 0 | MDE | HDE | KDE | TDCC | 0 | 0 | 0 | 0 | 0 | ERR | 0 | 0 | 0 | 0 | 0 | SS |
Reserved, RES0.
Used for save/restore of EDSCR.RXfull.
When OSLSR_EL1.OSLK == 0 (the OS lock is unlocked), this bit is RO, and software must treat it as UNK/SBZP.
When OSLSR_EL1.OSLK == 1 (the OS lock is locked), this bit is RW and holds the value of EDSCR.RXfull.
Reads and writes of this bit are indirect accesses to EDSCR.RXfull.
The architected behavior of this field determines the value it returns after a reset.
Used for save/restore of EDSCR.TXfull.
When OSLSR_EL1.OSLK == 0 (the OS lock is unlocked), this bit is RO, and software must treat it as UNK/SBZP.
When OSLSR_EL1.OSLK == 1 (the OS lock is locked), this bit is RW and holds the value of EDSCR.TXfull.
Reads and writes of this bit are indirect accesses to EDSCR.TXfull.
The architected behavior of this field determines the value it returns after a reset.
Reserved, RES0.
Used for save/restore of EDSCR.RXO.
When OSLSR_EL1.OSLK == 0 (the OS lock is unlocked), this bit is RO, and software must treat it as UNK/SBZP.
When OSLSR_EL1.OSLK == 1 (the OS lock is locked), this bit is RW and holds the value of EDSCR.RXO.
Reads and writes of this bit are indirect accesses to EDSCR.RXO.
The architected behavior of this field determines the value it returns after a reset.
Used for save/restore of EDSCR.TXU.
When OSLSR_EL1.OSLK == 0 (the OS lock is unlocked), this bit is RO, and software must treat it as UNK/SBZP.
When OSLSR_EL1.OSLK == 1 (the OS lock is locked), this bit is RW and holds the value of EDSCR.TXU.
Reads and writes of this bit are indirect accesses to EDSCR.TXU.
The architected behavior of this field determines the value it returns after a reset.
Reserved, RES0.
Used for save/restore of EDSCR.INTdis.
When OSLSR_EL1.OSLK == 0 (the OS lock is unlocked), this field is RO, and software must treat it as UNK/SBZP.
When OSLSR_EL1.OSLK == 1 (the OS lock is locked), this field is RW and holds the value of EDSCR.INTdis.
Reads and writes of this field are indirect accesses to EDSCR.INTdis.
The architected behavior of this field determines the value it returns after a reset.
Used for save/restore of EDSCR.TDA.
When OSLSR_EL1.OSLK == 0 (the OS lock is unlocked), this bit is RO, and software must treat it as UNK/SBZP.
When OSLSR_EL1.OSLK == 1 (the OS lock is locked), this bit is RW and holds the value of EDSCR.TDA.
Reads and writes of this bit are indirect accesses to EDSCR.TDA.
The architected behavior of this field determines the value it returns after a reset.
Reserved, RES0.
Reserved, RES0.
Used for save/restore of EDSCR.SC2.
When OSLSR_EL1.OSLK == 0 (the OS lock is unlocked), this bit is RO, and software must treat it as UNK/SBZP.
When OSLSR_EL1.OSLK == 1 (the OS lock is locked), this bit is RW and holds the value of EDSCR.SC2.
Reads and writes of this bit are indirect accesses to EDSCR.SC2.
If the PC Sample-based Profiling Extension is not implemented, then this field is RES0.
RAZ/WI. Hardware must implement this field as RAZ/WI. Software must not rely on the register reading as zero, and must use a read-modify-write sequence to write to the register.
Monitor debug events. Enable Breakpoint, Watchpoint, and Vector Catch exceptions.
MDE | Meaning |
---|---|
0 |
Breakpoint, Watchpoint, and Vector Catch exceptions disabled. |
1 |
Breakpoint, Watchpoint, and Vector Catch exceptions enabled. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Used for save/restore of EDSCR.HDE.
When OSLSR_EL1.OSLK == 0 (the OS lock is unlocked), this bit is RO, and software must treat it as UNK/SBZP.
When OSLSR_EL1.OSLK == 1 (the OS lock is locked), this bit is RW and holds the value of EDSCR.HDE.
Reads and writes of this bit are indirect accesses to EDSCR.HDE.
The architected behavior of this field determines the value it returns after a reset.
Local (kernel) debug enable. If ELD is using AArch64, enable debug exceptions within ELD. Permitted values are:
KDE | Meaning |
---|---|
0 |
Debug exceptions, other than Breakpoint Instruction exceptions, disabled within ELD. |
1 |
All debug exceptions enabled within ELD. |
RES0 if ELD is using AArch32.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Traps EL0 accesses to the DCC registers to EL1, from both Execution states:
TDCC | Meaning |
---|---|
0 |
This control does not cause any instructions to be trapped. |
1 |
EL0 using AArch64: EL0 accesses to the MDCCSR_EL0, DBGDTR_EL0, DBGDTRTX_EL0, and DBGDTRRX_EL0 registers are trapped to EL1. EL0 using AArch32: EL0 accesses to the DBGDSCRint, DBGDTRRXint, DBGDTRTXint, DBGDIDR, DBGDSAR, and DBGDRAR registers are trapped to EL1. |
All accesses to these AArch32 registers are trapped, including LDC and STC accesses to DBGDTRTXint and DBGDTRRXint, and MRRC accesses to DBGDSAR and DBGDRAR.
Traps of AArch32 accesses to the DBGDTRRXint and DBGDTRTXint are ignored in Debug state.
Traps of AArch64 accesses to DBGDTR_EL0, DBGDTRRX_EL0, and DBGDTRTX_EL0 are ignored in Debug state.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Reserved, RES0.
Used for save/restore of EDSCR.ERR.
When OSLSR_EL1.OSLK == 0 (the OS lock is unlocked), this bit is RO, and software must treat it as UNK/SBZP.
When OSLSR_EL1.OSLK == 1 (the OS lock is locked), this bit is RW and holds the value of EDSCR.ERR.
Reads and writes of this bit are indirect accesses to EDSCR.ERR.
The architected behavior of this field determines the value it returns after a reset.
Reserved, RES0.
Software step control bit. If ELD is using AArch64, enable Software step. Permitted values are:
SS | Meaning |
---|---|
0 |
Software step disabled |
1 |
Software step enabled. |
RES0 if ELD is using AArch32.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
MDSCR_EL1 | 10 | 000 | 0000 | 0010 | 010 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RW | n/a | RW |
x | 0 | 1 | - | RW | RW | RW |
x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
Individual fields within this register might have restricted accessibility when OSLSR_EL1.OSLK == 0 (the OS lock is unlocked.) See the field descriptions for more detail.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TDA==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TDA==1, accesses to this register from EL1 and EL2 are trapped to EL3.
02/05/2017 15:43
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