The DBGDRAR characteristics are:
Defines the base physical address of a 4KB-aligned memory-mapped debug component, usually a ROM table that locates and describes the memory-mapped debug components in the system. ARMv8 deprecates any use of this register.
This register is part of the Debug registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register DBGDRAR is architecturally mapped to AArch64 System register MDRAR_EL1.
If EL1 cannot use AArch32 then the implementation of this register is OPTIONAL and deprecated.
DBGDRAR is a 64-bit register that can also be accessed as a 32-bit value. If it is accessed as a 32-bit register, bits [31:0] are read.
The DBGDRAR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ROMADDR[31:12] | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Valid |
Bits[31:12] of the ROM table physical address. Bits [11:0] of the address are zero.
In an implementation that includes EL3, ROMADDR is an address in Non-secure memory. It is IMPLEMENTATION DEFINED whether the ROM table is also accessible in Secure memory.
Reserved, RES0.
This field indicates whether the ROM Table address is valid. The permitted values of this field are:
Valid | Meaning |
---|---|
00 |
ROM Table address is not valid. Software must ignore ROMADDR. |
11 |
ROM Table address is valid. |
Other values are reserved.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ROMADDR[47:12] | |||||||||||||||
ROMADDR[47:12] | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Valid | ||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Bits[47:12] of the ROM table physical address.
If the physical address size in bits (PAsize) is less than 48 then the register bits corresponding to ROMADDR [47:PAsize] are RES0.
Bits [11:0] of the ROM table physical address are zero.
ARM strongly recommends that bits ROMADDR[(PAsize-1):32] are zero in any system that supports AArch32 at the highest implemented Exception level.
In an implementation that includes EL3, ROMADDR is an address in Non-secure memory. It is IMPLEMENTATION DEFINED whether the ROM table is also accessible in Secure memory.
Reserved, RES0.
This field indicates whether the ROM Table address is valid. The permitted values of this field are:
Valid | Meaning |
---|---|
00 |
ROM Table address is not valid. Software must ignore ROMADDR. |
11 |
ROM Table address is valid. |
Other values are reserved.
This register can be read using MRC with the following syntax:
MRC <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p14, 0, <Rt>, c1, c0, 0 | 000 | 000 | 0001 | 1110 | 0000 |
This register can be read using MRRC with the following syntax:
MRRC <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | coproc | CRm |
---|---|---|---|
p14, 0, <Rt>, <Rt2>, c1 | 0000 | 1110 | 0001 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | RO | RO | n/a | RO |
x | 0 | 1 | RO | RO | RO | RO |
x | 1 | 1 | RO | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If DBGDSCRext.UDCCdis==1, read accesses to this register from EL0 are trapped to Undefined mode.
If MDSCR_EL1.TDCC==1, read accesses to this register from EL0 are trapped to EL1.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TDRA==1, Non-secure read accesses to this register from EL0 and EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HDCR.TDRA==1, Non-secure read accesses to this register from EL0 and EL1 are trapped to Hyp mode.
02/05/2017 15:43
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