The AFSR0_EL2 characteristics are:
Provides additional IMPLEMENTATION DEFINED fault status information for exceptions taken to EL2.
This register is part of:
AArch64 System register AFSR0_EL2 is architecturally mapped to AArch32 System register HADFSR.
If EL2 is not implemented, this register is RES0 from EL3.
RW fields in this register reset to architecturally UNKNOWN values.
AFSR0_EL2 is a 32-bit register.
The AFSR0_EL2 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED |
IMPLEMENTATION DEFINED.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
AFSR0_EL2 | 11 | 100 | 0101 | 0001 | 000 |
AFSR0_EL1 | 11 | 000 | 0101 | 0001 | 000 |
The register is accessible as follows:
<systemreg> | Control | Accessibility | |||||
---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | |
AFSR0_EL2 | x | x | 0 | - | - | n/a | RW |
AFSR0_EL2 | 0 | 0 | 1 | - | - | RW | RW |
AFSR0_EL2 | 0 | 1 | 1 | - | n/a | RW | RW |
AFSR0_EL2 | 1 | 0 | 1 | - | - | RW | RW |
AFSR0_EL2 | 1 | 1 | 1 | - | n/a | RW | RW |
AFSR0_EL1 | x | x | 0 | - | AFSR0_EL1 | n/a | AFSR0_EL1 |
AFSR0_EL1 | 0 | 0 | 1 | - | AFSR0_EL1 | AFSR0_EL1 | AFSR0_EL1 |
AFSR0_EL1 | 0 | 1 | 1 | - | n/a | AFSR0_EL1 | AFSR0_EL1 |
AFSR0_EL1 | 1 | 0 | 1 | - | AFSR0_EL1 | RW | AFSR0_EL1 |
AFSR0_EL1 | 1 | 1 | 1 | - | n/a | RW | AFSR0_EL1 |
When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic AFSR0_EL2 or AFSR0_EL1 are not guaranteed to be ordered with respect to accesses using the other mnemonic.
02/05/2017 15:43
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