The ICV_IGRPEN0 characteristics are:
Controls whether virtual Group 0 interrupts are enabled or not.
This register is part of:
AArch32 System register ICV_IGRPEN0 is architecturally mapped to AArch64 System register ICV_IGRPEN0_EL1.
ICV_IGRPEN0 is a 32-bit register.
The ICV_IGRPEN0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Enable |
Reserved, RES0.
Enables virtual Group 0 interrupts.
Enable | Meaning |
---|---|
0 |
Virtual Group 0 interrupts are disabled. |
1 |
Virtual Group 0 interrupts are enabled. |
When this register has an architecturally-defined reset value, this field resets to 0.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c12, c12, 6 | 000 | 110 | 1100 | 1111 | 1100 |
p15, 0, <Rt>, c12, c12, 6 | 000 | 110 | 1100 | 1111 | 1100 |
When HCR.FMO is set to 0, execution of this encoding at Non-secure EL1 results in an access to ICC_IGRPEN0.
The register is accessible as follows:
<syntax> | Control | Accessibility | ||||||
---|---|---|---|---|---|---|---|---|
FMO | IMO | TGE | NS | EL0 | EL1 | EL2 | EL3 | |
p15, 0, <Rt>, c12, c12, 6 | x | x | x | 0 | - | ICC_IGRPEN0 | n/a | ICC_IGRPEN0 |
p15, 0, <Rt>, c12, c12, 6 | x | x | 1 | 1 | - | n/a | ICC_IGRPEN0 | ICC_IGRPEN0 |
p15, 0, <Rt>, c12, c12, 6 | 0 | x | 0 | 1 | - | ICC_IGRPEN0 | ICC_IGRPEN0 | ICC_IGRPEN0 |
p15, 0, <Rt>, c12, c12, 6 | 1 | x | 0 | 1 | - | RW | ICC_IGRPEN0 | ICC_IGRPEN0 |
ICV_IGRPEN0 is only accessible at Non-secure EL1 when HCR.FMO is set to 1.
When HCR.FMO is set to 0, at Non-secure EL1, the instruction encoding used to access ICV_IGRPEN0 results in an access to ICC_IGRPEN0.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_SRE.SRE==0, Non-secure accesses to this register from EL1 are UNDEFINED.
If ICC_SRE_EL1.SRE==0, Non-secure accesses to this register from EL1 are trapped to EL1.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==0 :
If HSTR_EL2.T12==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && .E2H==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T12==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HSTR.T12==1, Non-secure accesses to this register from EL1 are trapped to Hyp mode.
When SCR_EL3.NS==1 :
If ICH_HCR.TALL0==1, Non-secure accesses to this register from EL1 are trapped to EL2.
If ICH_HCR_EL2.TALL0==1, Non-secure accesses to this register from EL1 are trapped to EL2.
02/05/2017 15:43
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