The AMAIR_EL1 characteristics are:
Provides IMPLEMENTATION DEFINED memory attributes for the memory regions specified by MAIR_EL1.
This register is part of:
AArch64 System register AMAIR_EL1 bits [31:0] are architecturally mapped to AArch32 System register AMAIR0.
AArch64 System register AMAIR_EL1 bits [63:32] are architecturally mapped to AArch32 System register AMAIR1.
RW fields in this register reset to architecturally UNKNOWN values.
AMAIR_EL1 is a 64-bit register.
The AMAIR_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AMAIR_EL1 is permitted to be cached in a TLB.
IMPLEMENTATION DEFINED.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
AMAIR_EL1 | 11 | 000 | 1010 | 0011 | 000 |
AMAIR_EL12 | 11 | 101 | 1010 | 0011 | 000 |
The register is accessible as follows:
<systemreg> | Control | Accessibility | |||||
---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | |
AMAIR_EL1 | x | x | 0 | - | RW | n/a | RW |
AMAIR_EL1 | 0 | 0 | 1 | - | RW | RW | RW |
AMAIR_EL1 | 0 | 1 | 1 | - | n/a | RW | RW |
AMAIR_EL1 | 1 | 0 | 1 | - | RW | AMAIR_EL2 | RW |
AMAIR_EL1 | 1 | 1 | 1 | - | n/a | AMAIR_EL2 | RW |
AMAIR_EL12 | x | x | 0 | - | - | n/a | - |
AMAIR_EL12 | 0 | 0 | 1 | - | - | - | - |
AMAIR_EL12 | 0 | 1 | 1 | - | n/a | - | - |
AMAIR_EL12 | 1 | 0 | 1 | - | - | RW | RW |
AMAIR_EL12 | 1 | 1 | 1 | - | n/a | RW | RW |
When HCR_EL2.E2H is 1, without explicit synchronization, access from EL3 using the mnemonic AMAIR_EL1 or AMAIR_EL12 are not guaranteed to be ordered with respect to accesses using the other mnemonic.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TRVM==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HCR_EL2.TVM==1, Non-secure write accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
02/05/2017 15:43
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.