The EDCIDR3 characteristics are:
Provides information to identify an external debug component.
For more information see 'About the Component identification scheme' in the ARMv8 ARM, section H8 (About the External Debug Registers).
This register is part of the Debug registers functional group.
This register is accessible as follows:
Default |
---|
RO |
EDCIDR3 is in the Debug power domain.
Implementation of this register is OPTIONAL.
This register is required for CoreSight compliance.
EDCIDR3 is a 32-bit register.
The EDCIDR3 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | PRMBL_3 |
Reserved, RES0.
Preamble. Must read as 0xB1.
EDCIDR3 can be accessed through the external debug interface:
Component | Offset |
---|---|
Debug | 0xFFC |
02/05/2017 15:43
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.