The GICR_NSACR characteristics are:
Enables Secure software to permit Non-secure software to create SGIs targeting the PE connected to this Redistributor by writing to ICC_SGI1R_EL1, ICC_ASGI1R_EL1 or ICC_SGI0R_EL1.
See Forwarding an SGI to a target PE for more information.
This register is part of the GIC Redistributor registers functional group.
This register is accessible as follows:
Security disabled | Secure | Non-secure |
---|---|---|
RW | RW | RW |
When GICD_CTLR.DS == 1, this register is RAZ/WI.
When GICD_CTLR.DS == 0, this register is Secure, and is RAZ/WI to Non-secure accesses.
This register is used when affinity routing is enabled. When affinity routing is not enabled for the Security state of the interrupt, GICD_NSACR<n> with n=0 provides equivalent functionality.
This register does not support PPIs.
RW fields in this register reset to architecturally UNKNOWN values.
For a description on when a write to ICC_SGI0R_EL1, ICC_SGI1R_EL1 or ICC_ASGI1R_EL1 is permitted to generate an interrupt see Use of control registers for SGI forwarding.
GICR_NSACR is a 32-bit register.
The GICR_NSACR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NS_access<x>, bits [2x+1:2x], for x = 0 to 15 |
Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1, as defined from GICR_IGROUPR0 and GICR_IGRPMODR0. A field is provided for each SGI. The possible values of each 2-bit field are:
NS_access<x> | Meaning |
---|---|
00 |
Non-secure writes are not permitted to generate Secure Group 0 SGIs or Secure Group 1 SGIs. |
01 |
Non-secure writes are permitted to generate a Secure Group 0 SGI. |
10 |
As 0b01, but additionally Non-secure writes to are permitted to generate a Secure Group 1 SGI. |
11 |
Reserved. If the field is programmed to the reserved value, then the hardware will treat the field as if it has been programmed to an IMPLEMENTATION DEFINED choice of the valid values. However, to maintain the principle that as the value increases additional accesses are permitted ARM strongly recommends that implementations treat this value as 10. It is IMPLEMENTATION DEFINED whether the value read back is the value programmed or the valid value chosen. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
GICR_NSACR can be accessed through its memory-mapped interface:
Component | Frame | Offset |
---|---|---|
GIC Redistributor | SGI_base | 0x0E00 |
02/05/2017 15:43
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