RVBAR_EL1, Reset Vector Base Address Register (if EL2 and EL3 not implemented)

The RVBAR_EL1 characteristics are:

Purpose

If EL1 is the highest Exception level implemented, contains the IMPLEMENTATION DEFINED address that execution starts from after reset when executing in AArch64 state.

This register is part of the Reset management registers functional group.

Configuration

Only implemented if the highest Exception level implemented is EL1.

Attributes

RVBAR_EL1 is a 64-bit register.

Field descriptions

The RVBAR_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
Reset Address
Reset Address
313029282726252423222120191817161514131211109876543210

Bits [63:0]

Reset Address. The IMPLEMENTATION DEFINED address that execution starts from after reset when executing in 64-bit state. Bits[1:0] of this register are 00, as this address must be aligned, and the address must be within the physical address size supported by the PE.

Accessing the RVBAR_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
RVBAR_EL11100011000000001

Accessibility

The register is accessible as follows:

Configuration Control Accessibility
E2HTGENSEL0EL1EL2EL3
EL1 is the highest implemented Exception levelxxx - RO n/a n/a

This table applies to all instructions that can access this register.

When EL1 is not the highest implemented Exception level, the encoding for this register is UNDEFINED.




02/05/2017 15:43

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