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The SCTLR_EL3 characteristics are:
Provides top level control of the system, including its memory system, at EL3.
This register is part of the Other system control registers functional group.
Some or all RW fields of this register have defined reset values. These apply only if the PE resets into EL3 using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.
SCTLR_EL3 is a 32-bit register.
The SCTLR_EL3 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EnIA | EnIB | 1 | 1 | EnDA | 0 | EE | 0 | 1 | 1 | IESB | 0 | WXN | 1 | 0 | 1 | 0 | 0 | EnDB | I | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | SA | C | A | M |
Controls enabling of pointer authentication (using the APIAKey_EL1 key) of instruction addresses in the EL3 translation regime.
Possible values of this bit are:
EnIA | Meaning |
---|---|
0 | Pointer authentication (using the APIAKey_EL1 key) of instruction addresses is not enabled. |
1 | Pointer authentication (using the APIAKey_EL1 key) of instruction addresses is enabled. |
This field controls the behavior of the AddPACIA and AuthIA pseudocode functions. Specifically, when the field is 1, AddPACIA returns a copy of a pointer to which a pointer authentication code has been added, and AuthIA returns an authenticated copy of a pointer. When the field is 0, both of these functions are NOP.
Reserved, RES0.
Controls enabling of pointer authentication (using the APIBKey_EL1 key) of instruction addresses in the EL3 translation regime.
Possible values of this bit are:
EnIB | Meaning |
---|---|
0 | Pointer authentication (using the APIBKey_EL1 key) of instruction addresses is not enabled. |
1 | Pointer authentication (using the APIBKey_EL1 key) of instruction addresses is enabled. |
This field controls the behavior of the AddPACIB and AuthIB pseudocode functions. Specifically, when the field is 1, AddPACIB returns a copy of a pointer to which a pointer authentication code has been added, and AuthIB returns an authenticated copy of a pointer. When the field is 0, both of these functions are NOP.
Reserved, RES0.
Reserved, RES1.
Controls enabling of pointer authentication (using the APDAKey_EL1 key) of instruction addresses in the EL3 translation regime.
Possible values of this bit are:
EnDA | Meaning |
---|---|
0 | Pointer authentication (using the APDAKey_EL1 key) of instruction addresses is not enabled. |
1 | Pointer authentication (using the APDAKey_EL1 key) of instruction addresses is enabled. |
This field controls the behavior of the AddPACDA and AuthDA pseudocode functions. Specifically, when the field is 1, AddPACDA returns a copy of a pointer to which a pointer authentication code has been added, and AuthDA returns an authenticated copy of a pointer. When the field is 0, both of these functions are NOP.
Reserved, RES0.
Reserved, RES0.
Endianness of data accesses at EL3, and stage 1 translation table walks in the EL3 translation regime.
The possible values of this bit are:
EE | Meaning |
---|---|
0 | Explicit data accesses at EL3, and stage 1 translation table walks in the EL3 translation regime are little-endian. |
1 | Explicit data accesses at EL3, and stage 1 translation table walks in the EL3 translation regime are big-endian. |
If an implementation does not provide Big-endian support at Exception Levels higher than EL0, this bit is RES0.
If an implementation does not provide Little-endian support at Exception Levels higher than EL0, this bit is RES1.
The EE bit is permitted to be cached in a TLB.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to an IMPLEMENTATION DEFINED value.
Reserved, RES0.
Reserved, RES1.
Implicit error synchronization event enable. Possible values are:
IESB | Meaning |
---|---|
0 | Disabled. |
1 | An implicit error synchronization event is added:
|
When the PE is in Debug state, the effect of this field is CONSTRAINED UNPREDICTABLE, and its Effective value might be 0 or 1 regardless of the value of the field. If the Effective value of the field is 1, then an implicit error synchronization event operation is added after each DCPSx instruction taken to EL3 and before each DRPS instruction executed at EL3, in addition to the other cases where it is added.
This field is part of ARMv8.2-IESB.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Reserved, RES0.
Reserved, RES0.
Write permission implies XN (Execute-never). For the EL3 translation regime, this bit can force all memory regions that are writable to be treated as XN. The possible values of this bit are:
WXN | Meaning |
---|---|
0 | This control has no effect on memory access permissions. |
1 | Any region that is writable in the EL3 translation regime is forced to XN for accesses from software executing at EL3. |
The WXN bit is permitted to be cached in a TLB.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Reserved, RES1.
Reserved, RES0.
Reserved, RES1.
Reserved, RES0.
Controls enabling of pointer authentication (using the APDBKey_EL1 key) of instruction addresses in the EL3 translation regime.
Possible values of this bit are:
EnDB | Meaning |
---|---|
0 | Pointer authentication (using the APDBKey_EL1 key) of instruction addresses is not enabled. |
1 | Pointer authentication (using the APDBKey_EL1 key) of instruction addresses is enabled. |
This field controls the behavior of the AddPACDB and AuthDB pseudocode functions. Specifically, when the field is 1, AddPACDB returns a copy of a pointer to which a pointer authentication code has been added, and AuthDB returns an authenticated copy of a pointer. When the field is 0, both of these functions are NOP.
Reserved, RES0.
Instruction access Cacheability control, for accesses at EL3:
I | Meaning |
---|---|
0 | All instruction access to Normal memory from EL3 are Non-cacheable for all levels of instruction and unified cache. If the value of SCTLR_EL3.M is 0, instruction accesses from stage 1 of the EL3 translation regime are to Normal, Outer Shareable, Inner Non-cacheable, Outer Non-cacheable memory. |
1 | This control has no effect on the Cacheability of instruction access to Normal memory from EL3. If the value of SCTLR_EL3.M is 0, instruction accesses from stage 1 of the EL3 translation regime are to Normal, Outer Shareable, Inner Write-Through, Outer Write-Through memory. |
This bit has no effect on the EL1&0, EL2, or EL2&0 translation regimes.
When this register has an architecturally-defined reset value, this field resets to 0.
Reserved, RES1.
Reserved, RES0.
Reserved, RES1.
SP Alignment check enable. When set to 1, if a load or store instruction executed at EL3 uses the SP as the base address and the SP is not aligned to a 16-byte boundary, then a SP alignment fault exception is generated. For more information, see 'SP alignment checking' in the ARMv8 ARM, section D1 (The AArch64 System Level Programmers' Model).
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Cacheability control, for data accesses.
C | Meaning |
---|---|
0 | All data access to Normal memory from EL3, and all Normal memory accesses to the EL3 translation tables, are Non-cacheable for all levels of data and unified cache. |
1 | This control has no effect on the Cacheability of:
|
This bit has no effect on the EL1&0, EL2, or EL2&0 translation regimes.
When this register has an architecturally-defined reset value, this field resets to 0.
Alignment check enable. This is the enable bit for Alignment fault checking at EL3:
A | Meaning |
---|---|
0 | Alignment fault checking disabled when executing at EL3. Instructions that load or store one or more registers, other than load/store exclusive and load-acquire/store-release, do not check that the address being accessed is aligned to the size of the data element(s) being accessed. |
1 | Alignment fault checking enabled when executing at EL3. All instructions that load or store one or more registers have an alignment check that the address being accessed is aligned to the size of the data element(s) being accessed. If this check fails it causes an Alignment fault, which is taken as a Data Abort exception. |
Load/store exclusive and load-acquire/store-release instructions have an alignment check regardless of the value of the A bit.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
MMU enable for EL3 stage 1 address translation. Possible values of this bit are:
M | Meaning |
---|---|
0 | EL3 stage 1 address translation disabled. See the SCTLR_EL3.I field for the behavior of instruction accesses to Normal memory. |
1 | EL3 stage 1 address translation enabled. |
When this register has an architecturally-defined reset value, this field resets to 0.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
SCTLR_EL3 | 11 | 110 | 0001 | 0000 | 000 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | - | n/a | RW |
x | 0 | 1 | - | - | - | RW |
x | 1 | 1 | - | n/a | - | RW |
This table applies to all instructions that can access this register.
28/0907/2017 0816:2440
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