The NMRR characteristics are:
Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in the PRRR.
Used in conjunction with the PRRR.
This register is part of the Virtual memory control registers functional group.
AArch32 System register NMRR is architecturally mapped to AArch64 System register MAIR_EL1[63:32] when TTBCR.EAE==0.
MAIR1 and NMRR are the same register, with a different view depending on the value of TTBCR.EAE:
When EL3 is using AArch32, write access to NMRR(S) is disabled when the CP15SDISABLE signal is asserted HIGH.
RW fields in this register reset to architecturally UNKNOWN values.
NMRR is a 32-bit register.
The NMRR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OR7 | OR6 | OR5 | OR4 | OR3 | OR2 | OR1 | OR0 | IR7 | IR6 | IR5 | IR4 | IR3 | IR2 | IR1 | IR0 |
Outer Cacheable property mapping for memory attributes n, if the region is mapped as Normal memory by the PRRR.TR<n> entry. n is the value of the TEX[0], C, and B bits concatenated. The possible values of this field are:
OR<n> | Meaning |
---|---|
00 |
Region is Non-cacheable. |
01 |
Region is Write-Back, Write-Allocate. |
10 |
Region is Write-Through, no Write-Allocate. |
11 |
Region is Write-Back, no Write-Allocate. |
The meaning of the field with n = 6 is IMPLEMENTATION DEFINED and might differ from the meaning given here. This is because the meaning of the attribute combination {TEX[0] = 1, C = 1, B = 0} is IMPLEMENTATION DEFINED.
Inner Cacheable property mapping for memory attributes n, if the region is mapped as Normal memory by the PRRR.TR<n> entry. n is the value of the TEX[0], C, and B bits concatenated. The possible values of this field are:
IR<n> | Meaning |
---|---|
00 |
Region is Non-cacheable. |
01 |
Region is Write-Back, Write-Allocate. |
10 |
Region is Write-Through, no Write-Allocate. |
11 |
Region is Write-Back, no Write-Allocate. |
The meaning of the field with n = 6 is IMPLEMENTATION DEFINED and might differ from the meaning given here. This is because the meaning of the attribute combination {TEX[0] = 1, C = 1, B = 0} is IMPLEMENTATION DEFINED.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c10, c2, 1 | 000 | 001 | 1010 | 1111 | 0010 |
The register is accessible as follows:
Configuration | Control | Accessibility | Instance | |||||
---|---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | ||
EL3 using AArch32 | x | x | 0 | - | n/a | n/a | RW | NMRR_s |
EL3 not implemented | x | x | 0 | - | RW | n/a | n/a | NMRR |
EL3 not implemented | x | 0 | 1 | - | RW | RW | n/a | NMRR |
EL3 not implemented | x | 1 | 1 | - | n/a | RW | n/a | NMRR |
EL3 using AArch64 | x | x | 0 | - | RW | n/a | n/a | NMRR |
EL3 using AArch64 | x | 0 | 1 | - | RW | RW | n/a | NMRR |
EL3 using AArch64 | x | 1 | 1 | - | n/a | RW | n/a | NMRR |
EL3 using AArch32 | x | 0 | 1 | - | RW | RW | RW | NMRR_ns |
EL3 using AArch32 | x | 1 | 1 | - | n/a | RW | RW | NMRR_ns |
This table applies to all instructions that can access this register.
When EL3 is using AArch32, write access to NMRR_s is UNDEFINED when the CP15SDISABLE signal is asserted HIGH.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TVM==1, Non-secure write accesses to this register from EL1 are trapped to EL2.
If HCR_EL2.TRVM==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HSTR_EL2.T10==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TVM==1, Non-secure write accesses to this register from EL1 are trapped to EL2.
If HCR_EL2.TRVM==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HSTR_EL2.T10==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
28/09/2017 08:24
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