The ID_AA64ISAR1_EL1 characteristics are:
Provides information about the features and instructions implemented in AArch64 state.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.
This register is part of the Identification registers functional group.
There are no configuration notes.
ID_AA64ISAR1_EL1 is a 64-bit register.
The ID_AA64ISAR1_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
GPI | GPA | LRCPC | FCMA | JSCVT | API | APA | DPB | ||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Indicates whether an IMPLEMENTATION DEFINED algorithm is implemented in the PE for generic code authentication, in AArch64 state. Defined values are:
GPI | Meaning |
---|---|
0000 |
Generic Authentication using an IMPLEMENTATION DEFINED algorithm is not implemented. |
0001 |
Generic Authentication using an IMPLEMENTATION DEFINED algorithm is implemented. This involves the PACGA instruction. |
All other values are reserved.
Reserved, RES0.
Indicates whether QARMA or Architected algorithm is implemented in the PE for generic code authentication, in AArch64 state. Defined values are:
GPA | Meaning |
---|---|
0000 |
Generic Authentication using an Architected algorithm is not implemented. |
0001 |
Generic Authentication using the QARMA algorithm is implemented. This involves the PACGA instruction. |
All other values are reserved.
Reserved, RES0.
Indicates support for weaker release consistency, RCpc based model. Defined values are:
LRCPC | Meaning |
---|---|
0000 |
The LDAPRB, LDAPRH and LDAPR instructions are not implemented. |
0001 |
The LDAPRB, LDAPRH and LDAPR instructions are implemented. |
All other values are reserved.
In ARMv8.0, ARMv8.1 and ARMv8.2 the only permitted value is 0000.
From ARMv8.3 the only permitted value is 0001. This feature is identified as ARMv8.3-RCPC.
Reserved, RES0.
Indicates support for complex number addition and multiplication where numbers are stored in vectors. Defined values are:
FCMA | Meaning |
---|---|
0000 |
The FCMLA and FCADD instructions are not implemented. |
0001 |
The FCMLA and FCADD instructions are implemented. |
All other values are reserved.
In ARMv8.0, ARMv8.1 and ARMv8.2 the only permitted value is 0000.
From ARMv8.3 the only permitted value is 0001. This feature is identified as ARMv8.3-CompNum.
Reserved, RES0.
Indicates support for javascript conversion from double precision floating point values to integers in AArch64 state. Defined values are:
JSCVT | Meaning |
---|---|
0000 |
The FJCVTZS instruction is not implemented. |
0001 |
The FJCVTZS instruction is implemented. |
All other values are reserved.
In ARMv8.0, ARMv8.1 and ARMv8.2 the only permitted value is 0000.
From ARMv8.3 the only permitted value is 0001. This feature is identified as ARMv8.3-JSConv.
Reserved, RES0.
Indicates whether an IMPLEMENTATION DEFINED algorithm is implemented in the PE for address authentication, in AArch64 state. Defined values are:
API | Meaning |
---|---|
0000 |
Address Authentication using an IMPLEMENTATION DEFINED algorithm is not implemented. |
0001 |
Address Authentication using an IMPLEMENTATION DEFINED algorithm is implemented. This involves all Pointer Authentication instructions other than the PACGA instruction. |
All other values are reserved.
Reserved, RES0.
Indicates whether QARMA or Architected algorithm is implemented in the PE for address authentication, in AArch64 state. Defined values are:
APA | Meaning |
---|---|
0000 |
Address Authentication using an Architected algorithm is not implemented. |
0001 |
Address Authentication using the QARMA algorithm is implemented. This involves all Pointer Authentication instructions other than the PACGA instruction. |
All other values are reserved.
Reserved, RES0.
Indicates support for the DC CVAP instruction in AArch64 state. Defined values are:
DPB | Meaning |
---|---|
0000 |
DC CVAP not supported. |
0001 |
DC CVAP supported. |
All other values are reserved.
ARMv8.2-DCPoP implements the functionality identified by the value 0001.
From ARMv8.2 the only permitted value is 0001.
Reserved, RES0.
If API == 0000 and APA == 0000, then:
If API == 0000 and APA == 0000 and GPI == 0000 and GPA == 0000, then:
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
ID_AA64ISAR1_EL1 | 11 | 000 | 0000 | 0110 | 001 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
28/09/2017 08:24
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