ICH_HCR_EL2, Interrupt Controller Hyp Control Register

The ICH_HCR_EL2 characteristics are:

Purpose

Controls the environment for VMs.

This register is part of:

Configuration

AArch64 System register ICH_HCR_EL2 is architecturally mapped to AArch32 System register ICH_HCR.

If EL2 is not implemented, this register is RES0 from EL3.

Attributes

ICH_HCR_EL2 is a 32-bit register.

Field descriptions

The ICH_HCR_EL2 bit assignments are:

313029282726252423222120191817161514131211109876543210
EOIcount000000000000TDIRTSEITALL1TALL0TC00VGrp1DIEVGrp1EIEVGrp0DIEVGrp0EIENPIELRENPIEUIEEn

EOIcount, bits [31:27]

This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation. That is either:

This allows software to manage more active interrupts than there are implemented List Registers.

It is CONSTRAINED UNPREDICTABLE whether a virtual write to EOIR that does not clear a bit in the Active Priorities registers (ICH_AP0R<n>_EL2/ICH_AP1R<n>_EL2) increments EOIcount. Permitted behaviors are:

When this register has an architecturally-defined reset value, this field resets to 0.

Bits [26:15]

Reserved, RES0.

TDIR, bit [14]

Trap Non-secure EL1 writes to ICC_DIR_EL1 and ICV_DIR_EL1.

TDIRMeaning
0

Non-secure EL1 writes of ICC_DIR_EL1 and ICV_DIR_EL1 are not trapped to EL2, unless trapped by other mechanisms.

1

Non-secure EL1 writes of ICC_DIR_EL1 and ICV_DIR_EL1 are trapped to EL2.

Support for this bit is OPTIONAL, with support indicated by ICH_VTR_EL2.

If the implementation does not support this trap, this bit is RES0.

ARM deprecates not including this trap bit.

When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.

TSEI, bit [13]

Trap all locally generated SEIs. This bit allows the hypervisor to intercept locally generated SEIs that would otherwise be taken at Non-secure EL1.

TSEIMeaning
0

Locally generated SEIs do not cause a trap to EL2.

1

Locally generated SEIs trap to EL2.

If ICH_VTR_EL2.SEIS is 0, this bit is RES0.

When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.

TALL1, bit [12]

Trap all Non-secure EL1 accesses to ICC_* and ICV_* System registers for Group 1 interrupts to EL2.

TALL1Meaning
0

Non-Secure EL1 accesses to ICC_* and ICV_* registers for Group 1 interrupts proceed as normal.

1

Non-secure EL1 accesses to ICC_* and ICV_* registers for Group 1 interrupts trap to EL2.

When this register has an architecturally-defined reset value, this field resets to 0.

TALL0, bit [11]

Trap all Non-secure EL1 accesses to ICC_* and ICV_* System registers for Group 0 interrupts to EL2.

TALL0Meaning
0

Non-Secure EL1 accesses to ICC_* and ICV_* registers for Group 0 interrupts proceed as normal.

1

Non-secure EL1 accesses to ICC_* and ICV_* registers for Group 0 interrupts trap to EL2.

When this register has an architecturally-defined reset value, this field resets to 0.

TC, bit [10]

Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2.

TCMeaning
0

Non-secure EL1 accesses to common registers proceed as normal.

1

Non-secure EL1 accesses to common registers trap to EL2.

This affects accesses to ICC_SGI0R_EL1, ICC_SGI1R_EL1, ICC_ASGI1R_EL1, ICC_CTLR_EL1, ICC_DIR_EL1, ICC_PMR_EL1, ICC_RPR_EL1, ICV_CTLR_EL1, ICV_DIR_EL1, ICV_PMR_EL1, and ICV_RPR_EL1.

When this register has an architecturally-defined reset value, this field resets to 0.

Bits [9:8]

Reserved, RES0.

VGrp1DIE, bit [7]

VM Group 1 Disabled Interrupt Enable. Enables the signaling of a maintenance interrupt while signaling of Group 1 interrupts from the virtual CPU interface to the connected vPE is disabled:

VGrp1DIEMeaning
0

Maintenance interrupt disabled.

1

Maintenance interrupt signaled when ICH_VMCR_EL2.VENG1 is 0.

When this register has an architecturally-defined reset value, this field resets to 0.

VGrp1EIE, bit [6]

VM Group 1 Enabled Interrupt Enable. Enables the signaling of a maintenance interrupt while signaling of Group 1 interrupts from the virtual CPU interface to the connected vPE is enabled:

VGrp1EIEMeaning
0

Maintenance interrupt disabled.

1

Maintenance interrupt signaled when ICH_VMCR_EL2.VENG1 is 1.

When this register has an architecturally-defined reset value, this field resets to 0.

VGrp0DIE, bit [5]

VM Group 0 Disabled Interrupt Enable. Enables the signaling of a maintenance interrupt while signaling of Group 0 interrupts from the virtual CPU interface to the connected vPE is disabled:

VGrp0DIEMeaning
0

Maintenance interrupt disabled.

1

Maintenance interrupt signaled when ICH_VMCR_EL2.VENG0 is 0.

When this register has an architecturally-defined reset value, this field resets to 0.

VGrp0EIE, bit [4]

VM Group 0 Enabled Interrupt Enable. Enables the signaling of a maintenance interrupt while signaling of Group 0 interrupts from the virtual CPU interface to the connected vPE is enabled:

VGrp0EIEMeaning
0

Maintenance interrupt disabled.

1

Maintenance interrupt signaled when ICH_VMCR_EL2.VENG0 is 1.

When this register has an architecturally-defined reset value, this field resets to 0.

NPIE, bit [3]

No Pending Interrupt Enable. Enables the signaling of a maintenance interrupt when there are no List registers with the State field set to 0b01 (pending):

NPIEMeaning
0

Maintenance interrupt disabled.

1

Maintenance interrupt signaled while the List registers contain no interrupts in the pending state.

When this register has an architecturally-defined reset value, this field resets to 0.

LRENPIE, bit [2]

List Register Entry Not Present Interrupt Enable. Enables the signaling of a maintenance interrupt while the virtual CPU interface does not have a corresponding valid List register entry for an EOI request:

LRENPIEMeaning
0

Maintenance interrupt disabled.

1

Maintenance interrupt is asserted while the EOIcount field is not 0.

When this register has an architecturally-defined reset value, this field resets to 0.

UIE, bit [1]

Underflow Interrupt Enable. Enables the signaling of a maintenance interrupt when the List registers are empty, or hold only one valid entry:

UIEMeaning
0

Maintenance interrupt disabled.

1

Maintenance interrupt is asserted if none, or only one, of the List register entries is marked as a valid interrupt.

When this register has an architecturally-defined reset value, this field resets to 0.

En, bit [0]

Enable. Global enable bit for the virtual CPU interface:

EnMeaning
0

Virtual CPU interface operation disabled.

1

Virtual CPU interface operation enabled.

When this field is set to 0:

When this register has an architecturally-defined reset value, this field resets to 0.

Accessing the ICH_HCR_EL2

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
ICH_HCR_EL21110011001011000

Accessibility

The register is accessible as follows:

Control Accessibility
TGENSEL0EL1EL2EL3
x0 - - n/a RW
01 - - RWRW
11 - n/a RWRW

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.TGE==0 :




28/09/2017 08:24

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