GICH_EISR, End Interrupt Status Register

The GICH_EISR characteristics are:

Purpose

Indicates which List registers have outstanding EOI maintenance interrupts.

This register is part of the GIC virtualised guest interface control registers functional group.

Usage constraints

This register is accessible as follows:

Security disabledSecureNon-secure
RORORO

This register is used only when System register access is not enabled. When System register access is enabled:

Bits corresponding to unimplemented List registers are RAZ.

Configuration

RW fields in this register reset to architecturally UNKNOWN values.

This register is available when the GIC implementation supports interrupt virtualization.

Attributes

GICH_EISR is a 32-bit register.

Field descriptions

The GICH_EISR bit assignments are:

313029282726252423222120191817161514131211109876543210
0000000000000000Status<n>, bit [n], for n = 0 to 15

Bits [31:16]

Reserved, RES0.

Status<n>, bit [n], for n = 0 to 15

EOI maintenance interrupt status for List register <n>:

Status<n>Meaning
0

GICH_LR<n> does not have an EOI maintenance interrupt.

1

GICH_LR<n> has an EOI maintenance interrupt that has not been handled.

For any GICH_LR<n> register, the corresponding status bit is set to 1 if all of the following are true:

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Accessing the GICH_EISR

GICH_EISR can be accessed through its memory-mapped interface:

ComponentOffset
GIC Virtual interface control 0x0020



28/09/2017 08:24

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