AT S1E3W, Address Translate Stage 1 EL3 Write

The AT S1E3W characteristics are:

Purpose

Performs stage 1 address translation as defined for EL3, with permissions as if writing to the given virtual address.

This System instruction is part of the Address translation instructions functional group.

Configuration

There are no configuration notes.

Attributes

AT S1E3W is a 64-bit System instruction.

Field descriptions

The AT S1E3W input value bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
Input address for translation
Input address for translation
313029282726252423222120191817161514131211109876543210

Bits [63:0]

Input address for translation. The resulting address can be read from the PAR_EL1.

If the address translation instructions are targeting a translation regime that is using AArch32, and so has a VA of only 32 bits, then VA[63:32] is RES0.

Executing the AT S1E3W instruction

This instruction is executed using AT with the following syntax:

AT <at_op>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<at_op> op0op1CRnCRmop2
S1E3W0111001111000001

Accessibility

The instruction is executable as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - - n/a WO
001 - - - WO
011 - n/a - WO
101 - - - WO
111 - n/a - WO

This table applies to all syntax that can be used to execute this instruction.




28/09/2017 08:24

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