MIDR_EL1, Main ID Register

The MIDR_EL1 characteristics are:

Purpose

Provides identification information for the PE, including an implementer code for the device and a device ID number.

This register is part of the Identification registers functional group.

Configuration

AArch64 System register MIDR_EL1 is architecturally mapped to AArch32 System register MIDR.

AArch64 System register MIDR_EL1 is architecturally mapped to External register MIDR_EL1.

Attributes

MIDR_EL1 is a 32-bit register.

Field descriptions

The MIDR_EL1 bit assignments are:

313029282726252423222120191817161514131211109876543210
ImplementerVariantArchitecturePartNumRevision

Implementer, bits [31:24]

The Implementer code. This field must hold an implementer code that has been assigned by ARM. Assigned codes include the following:

Hex representation ASCII representation Implementer
0x41 A ARM Limited
0x42 B Broadcom Corporation
0x43 C Cavium Inc.
0x44 D Digital Equipment Corporation
0x49 I Infineon Technologies AG
0x4D M Motorola or Freescale Semiconductor Inc.
0x4E N NVIDIA Corporation
0x50 P Applied Micro Circuits Corporation
0x51 Q Qualcomm Inc.
0x56 V Marvell International Ltd.
0x69 i Intel Corporation

ARM can assign codes that are not published in this manual. All values not assigned by ARM are reserved and must not be used.

Variant, bits [23:20]

An IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product.

Architecture, bits [19:16]

The permitted values of this field are:

ArchitectureMeaning
0001

ARMv4

0010

ARMv4T

0011

ARMv5 (obsolete)

0100

ARMv5T

0101

ARMv5TE

0110

ARMv5TEJ

0111

ARMv6

1111

Architectural features are individually identified in the ID_* registers, see 'ID registers' in the ARMv8 ARM, section K12.3.3.

All other values are reserved.

PartNum, bits [15:4]

An IMPLEMENTATION DEFINED primary part number for the device.

On processors implemented by ARM, if the top four bits of the primary part number are 0x0 or 0x7, the variant and architecture are encoded differently.

Revision, bits [3:0]

An IMPLEMENTATION DEFINED revision number for the device.

Accessing the MIDR_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
MIDR_EL11100000000000000

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RO n/a RO
x01 - RORORO
x11 - n/a RORO

This table applies to all instructions that can access this register.




28/09/2017 08:24

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