PMSIDR_EL1, Sampling Profiling ID Register

The PMSIDR_EL1 characteristics are:

Purpose

Describes the Statistical Profiling implementation to software

This register is part of the Statistical Profiling Extension registers functional group.

Configuration

Present only if the Statistical Profiling Extension is implemented. Direct reads of PMSIDR_EL1 are UNDEFINED otherwise.

Attributes

PMSIDR_EL1 is a 64-bit register.

Field descriptions

The PMSIDR_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
00000000000000000000000000000000
000000000000CountSizeMaxSizeInterval00ERndLDSArchInstFLFTFE
313029282726252423222120191817161514131211109876543210

Bits [63:20]

Reserved, RES0.

Bits [7:6]

Reserved, RES0.

CountSize, bits [19:16]

Defines the size of the counters

CountSizeMeaning
0b0010

12-bit saturating counters

All other values are reserved. Reserved values might be defined in a future version of the architecture.

MaxSize, bits [15:12]

Defines the largest size for a single record, rounded up to a power-of-two. If this is the same as the minimum alignment (PMBIDR_EL1.Align), then each record is exactly this size

MaxSizeMeaning
0b0100

16 bytes

0b0101

32 bytes

0b0110

64 bytes

0b0111

128 bytes

0b1000

256 bytes

0b1001

512 bytes

0b1010

1024 bytes

0b1011

2KB

All other values are reserved. Reserved values might be defined in a future version of the architecture.

Interval, bits [11:8]

Recommended minimum sampling interval. This provides guidance from the implementer to the smallest minimum sampling interval, N.

IntervalMeaning
0b0000

256

0b0010

512

0b0011

768

0b0100

1,024

0b0101

1,536

0b0110

2,048

0b0111

3,072

0b1000

4,096

All other values are reserved. Reserved values might be defined in a future version of the architecture.

ERnd, bit [5]

Defines how the random number generator is used in determining the interval between samples, when enabled by PMSIRR_EL1.RND.

ERndMeaning
0b0

The random number is added at the start of the interval, and the sample is taken and a new interval started when the combined interval expires.

0b1

The random number is added and the new interval started after the interval programmed in PMSIRR_EL1.INTERVAL expires, and the sample is taken when the random interval expires.

LDS, bit [4]

Data source indicator for sampled load instructions

LDSMeaning
0b0

Loaded data source not implemented

0b1

Loaded data source implemented

ArchInst, bit [3]

Architectural instruction profiling

ArchInstMeaning
0b0

Micro-op sampling implemented

0b1

Architecture instruction sampling implemented

FL, bit [2]

Filtering by latency. This bit is RAO.

FT, bit [1]

Filtering by operation type. This bit is RAO.

FE, bit [0]

Filtering by events. This bit is RAO.

Accessing the PMSIDR_EL1

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> CRnop0op1op2CRm
PMSIDR_EL11001110001111001

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RW n/a RW
x01 - RWRWRW
x11 - n/a RWRW

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.




12/09/2017 18:03

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