TLBI VALE2IS, TLB Invalidate by VA, Last level, EL2, Inner Shareable

The TLBI VALE2IS characteristics are:

Purpose

If EL2 is implemented, invalidate cached copies of translation table entries from TLBs that meet all the following requirements:

The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this instructions.

This System instruction is part of the TLB maintenance instructions functional group.

Configuration

There are no configuration notes.

Attributes

TLBI VALE2IS is a 64-bit System instruction.

Field descriptions

The TLBI VALE2IS input value bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
00000000000000000000VA[55:12]
VA[55:12]
313029282726252423222120191817161514131211109876543210

Bits [63:44]

Reserved, RES0.

VA[55:12], bits [43:0]

Bits[55:12] of the virtual address to match. Any appropriate TLB entries that match the ASID value (if appropriate) and VA will be affected by this operation.

If the TLB maintenance instructions are targeting a translation regime that is using AArch32, and so has a VA of only 32 bits, then the software must treat bits[55:32] as RES0.

The treatment of the low-order bits of this field depends on the translation granule size, as follows:

Executing the TLBI VALE2IS instruction

This instruction is executed using TLBI with the following syntax:

TLBI <tlbi_op>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<tlbi_op> op0op1CRnCRmop2
VALE2IS0110010000011101

Accessibility

The instruction is executable as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - - n/a -
001 - - WOWO
011 - n/a WOWO
101 - - WOWO
111 - n/a WOWO

This table applies to all syntax that can be used to execute this instruction.

If EL2 is not implemented, or SCR_EL3.NS is 0, this instruction is UNDEFINED.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when executing this System instruction.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :




28/09/2017 08:24

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