The ID_AA64MMFR2_EL1 characteristics are:
Provides information about the implemented memory model and memory management support in AArch64 state.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.
This register is part of the Identification registers functional group.
This register is introduced in ARMv8.2.
ID_AA64MMFR2_EL1 is a 64-bit register.
The ID_AA64MMFR2_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | NV | CCIDX | VARange | IESB | LSM | UAO | CnP | |||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
If EL2 is implemented, indicates support for the use of Nested Virtualization. Defined values are:
NV | Meaning |
---|---|
0000 |
Nested Virtualization is not supported. |
0001 |
The HCR_EL2.NV, HCR_EL2.NV1, HCR_EL2.AT bits are implemented. |
All other values are reserved.
In ARMv8.2 the only permitted value is 0000.
From ARMv8.3 the permitted values are:
Reserved, RES0.
Support for the use of revised CCSIDR_EL1 register format. Defined values are:
CCIDX | Meaning |
---|---|
0000 |
32-bit format implemented for all levels of the CCSIDR_EL1. |
0001 |
64-bit format implemented for all levels of the CCSIDR_EL1. |
All other values are reserved.
From ARMv8.3, the permitted values are 0000 and 0001. This feature is identified by the name ARMv8.3-CCIDX.
Reserved, RES0.
Indicates support for a larger virtual address. Defined values are:
VARange | Meaning |
---|---|
0000 |
VMSAv8-64 supports 48-bit VAs. |
0001 |
VMSAv8-64 supports 52-bit VAs when using the 64KB translation granule. The other translation granules support 48-bit VAs. |
All other values are reserved.
ARMv8.2-LVA implements the functionality identified by the value 0001.
Indicates support for the IESB bit in the SCTLR_ELx registers. Defined values are:
IESB | Meaning |
---|---|
0000 |
IESB bit in the SCTLR_ELx registers is not supported. |
0001 |
IESB bit in the SCTLR_ELx registers is supported. |
All other values are reserved.
ARMv8.2-IESB implements the functionality identified by the value 0001.
From ARMv8.2 the only permitted value is 0001.
Indicates support for LSMAOE and nTLSMD bits in SCTLR_EL1 and SCTLR_EL2. Defined values are:
LSM | Meaning |
---|---|
0000 |
LSMAOE and nTLSMD bits not supported. |
0001 |
LSMAOE and nTLSMD bits supported. |
All other values are reserved.
ARMv8.2-LSMAOC implements the functionality identified by the value 0001.
User Access Override. Defined values are:
UAO | Meaning |
---|---|
0000 |
UAO not supported. |
0001 |
UAO supported. |
All other values are reserved.
ARMv8.2-UAO implements the functionality identified by the value 0001.
From ARMv8.2 the only permitted value is 0001.
Common not Private translations. Defined values are:
CnP | Meaning |
---|---|
0000 |
Common not Private translations not supported. |
0001 |
Common not Private translations supported. |
All other values are reserved.
ARMv8.2-TTCNP implements the functionality identified by the value 0001.
From ARMv8.2, the only permitted value is 0001.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
ID_AA64MMFR2_EL1 | 11 | 000 | 0000 | 0111 | 010 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
28/09/2017 08:24
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