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The PMSCR_EL2 characteristics are:
Provides EL2 controls for Statistical Profiling
This register is part of the Statistical Profiling Extension registers functional group.
Present only if the Statistical Profiling Extension is implemented. Direct reads and writes of PMSCR_EL2 are UNDEFINED otherwise
PMSCR_EL2 is a 64-bit register.
The PMSCR_EL2 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | PCT | TS | PA | CX | 0 | E2SPE | E0HSPE |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Reserved, RES0.
Physical Timestamp
If timestamp sampling is enabled, determines which counter is collected
PCT | Meaning |
---|---|
0b0 | Virtual counter, CNTVCT_EL0, is collected |
0b1 | Physical counter, CNTPCT_EL0, is collected |
If MDCR_EL2.E2PB != 0b00, this bit is combined with PMSCR_EL1.PCT to determine which counter is collected.
This bit is ignored by the PE when in Secure state. If EL2 is not implemented, the PE behaves as if this bit is set to 1, other than for a direct read of the register.
Timestamp Enable
TS | Meaning |
---|---|
0b0 | Timestamp sampling disabled |
0b1 | Timestamp sampling enabled |
This bit is ignored by the PE when in Non-secure state and MDCR_EL2.E2PB != 0b00, or in Secure state.
Physical Address Sample Enable
PA | Meaning |
---|---|
0b0 | Physical addresses are not collected |
0b1 | Physical addresses are collected |
If MDCR_EL2.E2PB != 0b00, this bit is combined with PMSCR_EL1.PA to determine which address is collected.
This bit is ignored by the PE when in Secure state. If EL2 is not implemented, the PE behaves as if this bit is set to 1, other than a direct read of the register.
CONTEXTIDR_EL2 Sample Enable
CX | Meaning |
---|---|
0b0 | CONTEXTIDR_EL2 is not collected |
0b1 | CONTEXTIDR_EL2 is collected |
This bit is ignored by the PE when in Secure state.
EL2 Statistical Profiling Enable
E2SPE | Meaning |
---|---|
0b0 | Sampling disabled at EL2 |
0b1 | Sampling enabled at EL2 |
This bit is RES0 if MDCR_EL2.E2PB != 0b00. This bit is ignored by the PE when in Secure state.
EL0 Statistical Profiling Enable
E0HSPE | Meaning |
---|---|
0b0 | Sampling disabled at EL0 |
0b1 | Sampling enabled at EL0 |
This bit is RES0 if MDCR_EL2.E2PB != 0b00.
This bit is ignored by the PE when in Non-secure state and HCR_EL2.TGE == 0, or in Secure state.
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | CRn | op0 | op1 | op2 | CRm |
---|---|---|---|---|---|
PMSCR_EL2 | 1100 | 11 | 100 | 000 | 0000 |
PMSCR_EL1 | 1100 | 11 | 000 | 000 | 0000 |
The register is accessible as follows:
<systemreg> | Control | Accessibility | |||||
---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | |
PMSCR_EL2 | x | x | 0 | - | - | n/a | RW |
PMSCR_EL2 | 0 | 0 | 1 | - | - | RW | RW |
PMSCR_EL2 | 0 | 1 | 1 | - | n/a | RW | RW |
PMSCR_EL2 | 1 | 0 | 1 | - | - | RW | RW |
PMSCR_EL2 | 1 | 1 | 1 | - | n/a | RW | RW |
PMSCR_EL1 | x | x | 0 | - | PMSCR_EL1 | n/a | PMSCR_EL1 |
PMSCR_EL1 | 0 | 0 | 1 | - | PMSCR_EL1 | PMSCR_EL1 | PMSCR_EL1 |
PMSCR_EL1 | 0 | 1 | 1 | - | n/a | PMSCR_EL1 | PMSCR_EL1 |
PMSCR_EL1 | 1 | 0 | 1 | - | PMSCR_EL1 | RW | PMSCR_EL1 |
PMSCR_EL1 | 1 | 1 | 1 | - | n/a | RW | PMSCR_EL1 |
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
If AArch64-MDCR_EL3.NSPB != 0b11, then access from EL2 traps to EL3
12/09/2017 18:03
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no old file | htmldiff from-SysReg_v83A_xml-00bet4 | (new) SysReg_v83A_xml-00bet5 |