ADFSR, Auxiliary Data Fault Status Register

The ADFSR characteristics are:

Purpose

Provides additional IMPLEMENTATION DEFINED fault status information for Data Abort exceptions taken to EL1 modes, and EL3 modes when EL3 is implemented and is using AArch32.

This register is part of:

Configuration

AArch32 System register ADFSR is architecturally mapped to AArch64 System register AFSR0_EL1.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

ADFSR is a 32-bit register.

Field descriptions

The ADFSR bit assignments are:

313029282726252423222120191817161514131211109876543210
IMPLEMENTATION DEFINED

IMPLEMENTATION DEFINED, bits [31:0]

IMPLEMENTATION DEFINED.

Accessing the ADFSR

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 0, <Rt>, c5, c1, 0000000010111110001

Accessibility

The register is accessible as follows:

Configuration Control Accessibility Instance
E2HTGENSEL0EL1EL2EL3
EL3 not implemented xx0 - RW n/a n/a ADFSR
EL3 not implemented x01 - RWRW n/a ADFSR
EL3 not implemented x11 - n/a RW n/a ADFSR
EL3 using AArch64xx0 - RW n/a n/a ADFSR
EL3 using AArch64x01 - RWRW n/a ADFSR
EL3 using AArch64x11 - n/a RW n/a ADFSR
EL3 using AArch32xx0 - n/a n/a RWADFSR_s
EL3 using AArch32x01 - RWRWRWADFSR_ns
EL3 using AArch32x11 - n/a RWRWADFSR_ns

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :




28/09/2017 08:24

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