CPTR_EL2, Architectural Feature Trap Register (EL2)

The CPTR_EL2 characteristics are:

Purpose

Controls:

This register is part of the Virtualization registers functional group.

Configuration

AArch64 System register CPTR_EL2 is architecturally mapped to AArch32 System register HCPTR.

If EL2 is not implemented, this register is RES0 from EL3.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

CPTR_EL2 is a 32-bit register.

Field descriptions

The CPTR_EL2 bit assignments are:

When HCR_EL2.E2H == 0:

313029282726252423222120191817161514131211109876543210
TCPAC0000000000TTA000000110TFP1TZ11111111

This format applies in all ARMv8.0 implementations.

TCPAC, bit [31]

Traps Non-secure EL1 accesses to CPACR_EL1 or CPACR to EL2, from both Execution states.

TCPACMeaning
0

This control does not cause any instructions to be trapped.

1

Non-secure EL1 accesses to CPACR_EL1 and CPACR are trapped to EL2.

Note

CPACR_EL1 and CPACR are not accessible at EL0.

Bits [30:21]

Reserved, RES0.

TTA, bit [20]

Traps Non-secure System register accesses to all implemented trace registers to EL2, from both Execution states.

TTAMeaning
0

This control does not cause any instructions to be trapped.

1

Any attempt at EL2, or Non-secure EL0 or EL1, to execute a System register access to an implemented trace register is trapped to EL2, unless it is trapped by CPACR.NSTRCDIS or CPACR_EL1.TTA.

Note

System register accesses to the trace registers can have side-effects. When a System register access is trapped, any side-effects that are normally associated with the access do not occur before the exception is taken.

If System register access to the trace functionality is not supported, this bit is RES0.

Bits [19:14]

Reserved, RES0.

Bits [13:12]

Reserved, RES1.

Bit [11]

Reserved, RES0.

TFP, bit [10]

Traps Non-secure accesses to SVE, Advanced SIMD and floating-point functionality to EL2, from both Execution states.

TFPMeaning
0

This control does not cause any instructions to be trapped.

1

Any attempt at EL2, or Non-secure EL0 or EL1, to execute an instruction that uses the registers associated with SVE, Advanced SIMD and floating-point execution is trapped to EL2, subject to the exception prioritization rules, unless it is trapped by CPTR_EL2.TZ.

Bit [9]

Reserved, RES1.

TZ, bit [8]
In ARMv8.3 and ARMv8.2:

Present only if SVE is implemented.

Traps Non-secure execution at EL2, EL1, or EL0 of SVE instructions and instructions that access SVE System registers to EL2. Defined values are:

TZMeaning
0

This control does not cause any instruction to be trapped.

1

This control causes these instructions to be trapped, subject to the exception prioritization rules.

If SVE is not implemented, this field is RES1.


In ARMv8.1 and ARMv8.0:

Reserved, RES1.

Bits [7:0]

Reserved, RES1.

When HCR_EL2.E2H == 1:

313029282726252423222120191817161514131211109876543210
TCPAC00TTA000000FPEN00ZEN0000000000000000

TCPAC, bit [31]

When HCR_EL2.TGE is 0, traps Non-secure EL1 accesses to CPACR_EL1 and CPACR to EL2, from both Execution states.

TCPACMeaning
0

This control does not cause any instructions to be trapped.

1

Non-secure EL1 accesses to CPACR_EL1 and CPACR are trapped to EL2.

When HCR_EL2.TGE is 1, this control does not cause any instructions to be trapped.

Note

CPACR_EL1 and CPACR are not accessible at EL0.

Bits [30:29]

Reserved, RES0.

TTA, bit [28]

Traps Non-secure System register accesses to all implemented trace registers to EL2, from both Execution states.

TTAMeaning
0

This control does not cause any instructions to be trapped.

1

Any attempt at EL2, or Non-secure EL0 or EL1, to execute a System register access to an implemented trace register is trapped to EL2, unless HCR_EL2.TGE is 0 and it is trapped by CPACR.NSTRCDIS or CPACR_EL1.TTA.

When HCR_EL2.TGE is 1, any attempt at EL2, or Non-secure EL0, to execute a System register access to an implemented trace register is trapped to EL2.

Note

System register accesses to the trace registers can have side-effects. When a System register access is trapped, any side-effects that are normally associated with the access do not occur before the exception is taken.

If System register access to the trace functionality is not supported, this bit is RES0.

Bits [27:22]

Reserved, RES0.

FPEN, bits [21:20]

Traps EL2, Non-secure EL0 and, when HCR_EL2.TGE is 0, Non-secure EL1 accesses to the SVE, Advanced SIMD and floating-point registers to EL2, from both Execution states.

FPENMeaning
00

This control causes any instructions at Non-secure EL0, EL1, or EL2 that use the registers associated with SVE, Advanced SIMD and floating-point execution to be trapped, subject to the exception prioritization rules, unless they are trapped by CPTR_EL2.ZEN.

01

When HCR_EL2.TGE is 0, this control does not cause any instructions to be trapped.

When HCR_EL2.TGE is 1, this control causes instructions at Non-secure EL0 that use the registers associated with SVE, Advanced SIMD and floating-point execution to be trapped, unless they are trapped by CPTR_EL2.ZEN, but does not cause any instruction at EL2 to be trapped.

10

This control causes any instructions at Non-secure EL0, EL1, or EL2 that use the registers associated with SVE, Advanced SIMD and floating-point execution to be trapped, subject to the exception prioritization rules, unless they are trapped by CPTR_EL2.ZEN.

11

This control does not cause any instructions to be trapped.

Writes to MVFR0, MVFR1, and MVFR2 from EL1 or higher are CONSTRAINED UNPREDICTABLE and whether these accesses can be trapped by this control depends on implemented CONSTRAINED UNPREDICTABLE behavior.

Note

Bits [19:18]

Reserved, RES0.

ZEN, bits [17:16]
In ARMv8.3 and ARMv8.2:

Present only if SVE is implemented.

Traps Non-secure execution at EL2, EL1, and EL0 of SVE instructions or instructions that access SVE System registers to EL2.

Defined values are:

ZENMeaning
00

This control causes Non-secure execution at EL2, EL1, and EL0 of these instructions to be trapped, subject to the exception prioritization rules.

01

When HCR_EL2.TGE is 0, this control does not cause any instruction to be trapped.

When HCR_EL2.TGE is 1, this control causes these instructions executed at Non-secure EL0 to be trapped, but does not cause any instruction at EL2 to be trapped.

10

This control causes Non-secure execution at EL2, EL1, and EL0 of these instructions to be trapped, subject to the exception prioritization rules.

11

This control does not cause any instruction to be trapped.

If SVE is not implemented, this field is RES0.


In ARMv8.1:

Reserved, RES0.

Bits [15:0]

Reserved, RES0.

Accessing the CPTR_EL2

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
CPTR_EL21110000010001010
CPACR_EL11100000010000010

Accessibility

The register is accessible as follows:

<systemreg> Control Accessibility
E2HTGENSEL0EL1EL2EL3
CPTR_EL2xx0 - - n/a RW
CPTR_EL2001 - - RWRW
CPTR_EL2011 - n/a RWRW
CPTR_EL2101 - - RWRW
CPTR_EL2111 - n/a RWRW
CPACR_EL1xx0 - CPACR_EL1 n/a CPACR_EL1
CPACR_EL1001 - CPACR_EL1 CPACR_EL1 CPACR_EL1
CPACR_EL1011 - n/a CPACR_EL1 CPACR_EL1
CPACR_EL1101 - CPACR_EL1 RW CPACR_EL1
CPACR_EL1111 - n/a RW CPACR_EL1

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL3 is implemented and is using AArch64 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :




28/09/2017 08:24

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