PMSCR_EL2, Statistical Profiling Control Register (EL2)

The PMSCR_EL2 characteristics are:

Purpose

Provides EL2 controls for Statistical Profiling

This register is part of the Statistical Profiling Extension registers functional group.

Configuration

Present only if the Statistical Profiling Extension is implemented. Direct reads and writes of PMSCR_EL2 are UNDEFINED otherwise

Attributes

PMSCR_EL2 is a 64-bit register.

Field descriptions

The PMSCR_EL2 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
00000000000000000000000000000000
0000000000000000000000000PCTTSPACX0E2SPEE0HSPE
313029282726252423222120191817161514131211109876543210

Bits [63:7]

Reserved, RES0.

Bit [2]

Reserved, RES0.

PCT, bit [6]

Physical Timestamp

If timestamp sampling is enabled, determines which counter is collected

PCTMeaning
0b0

Virtual counter, CNTVCT_EL0, is collected

0b1

Physical counter, CNTPCT_EL0, is collected

If MDCR_EL2.E2PB != 0b00, this bit is combined with PMSCR_EL1.PCT to determine which counter is collected.

This bit is ignored by the PE when in Secure state. If EL2 is not implemented, the PE behaves as if this bit is set to 1, other than for a direct read of the register.

TS, bit [5]

Timestamp Enable

TSMeaning
0b0

Timestamp sampling disabled

0b1

Timestamp sampling enabled

This bit is ignored by the PE when in Non-secure state and MDCR_EL2.E2PB != 0b00, or in Secure state.

PA, bit [4]

Physical Address Sample Enable

PAMeaning
0b0

Physical addresses are not collected

0b1

Physical addresses are collected

If MDCR_EL2.E2PB != 0b00, this bit is combined with PMSCR_EL1.PA to determine which address is collected.

This bit is ignored by the PE when in Secure state. If EL2 is not implemented, the PE behaves as if this bit is set to 1, other than a direct read of the register.

CX, bit [3]

CONTEXTIDR_EL2 Sample Enable

CXMeaning
0b0

CONTEXTIDR_EL2 is not collected

0b1

CONTEXTIDR_EL2 is collected

This bit is ignored by the PE when in Secure state.

E2SPE, bit [1]

EL2 Statistical Profiling Enable

E2SPEMeaning
0b0

Sampling disabled at EL2

0b1

Sampling enabled at EL2

This bit is RES0 if MDCR_EL2.E2PB != 0b00. This bit is ignored by the PE when in Secure state.

E0HSPE, bit [0]

EL0 Statistical Profiling Enable

E0HSPEMeaning
0b0

Sampling disabled at EL0

0b1

Sampling enabled at EL0

This bit is RES0 if MDCR_EL2.E2PB != 0b00.

This bit is ignored by the PE when in Non-secure state and HCR_EL2.TGE == 0, or in Secure state.

Accessing the PMSCR_EL2

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> CRnop0op1op2CRm
PMSCR_EL21100111000000000
PMSCR_EL11100110000000000

Accessibility

The register is accessible as follows:

<systemreg> Control Accessibility
E2HTGENSEL0EL1EL2EL3
PMSCR_EL2xx0 - - n/a RW
PMSCR_EL2001 - - RWRW
PMSCR_EL2011 - n/a RWRW
PMSCR_EL2101 - - RWRW
PMSCR_EL2111 - n/a RWRW
PMSCR_EL1xx0 - PMSCR_EL1 n/a PMSCR_EL1
PMSCR_EL1001 - PMSCR_EL1PMSCR_EL1PMSCR_EL1
PMSCR_EL1011 - n/a PMSCR_EL1PMSCR_EL1
PMSCR_EL1101 - PMSCR_EL1RWPMSCR_EL1
PMSCR_EL1111 - n/a RWPMSCR_EL1

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.




12/09/2017 18:03

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