The TLBIMVALIS characteristics are:
Invalidate all cached copies of translation table entries from TLBs that meet the following requirements:
From the entries that match these requirement, the entries that are invalidated are required for the following translation regime:
The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this instructions.
This System instruction is part of the TLB maintenance instructions functional group.
This System instruction is not implemented in architecture versions before ARMv8.
TLBIMVALIS is a 32-bit System instruction.
The TLBIMVALIS input value bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VA | 0 | 0 | 0 | 0 | ASID |
Virtual address to match. Any TLB entries that match the ASID value and VA value will be affected by this operation.
Reserved, RES0.
ASID value to match. Any TLB entries that match the ASID value and VA value will be affected by this operation.
Global TLB entries that match the VA value will be affected by this operation, regardless of the value of the ASID field.
This instruction is executed using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c8, c3, 5 | 000 | 101 | 1000 | 1111 | 0011 |
The instruction is executable as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | WO | n/a | WO |
x | 0 | 1 | - | WO | WO | WO |
x | 1 | 1 | - | n/a | WO | WO |
This table applies to all syntax that can be used to execute this instruction.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when executing this System instruction.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TTLB==1, Non-secure execution of this instruction at EL1 is trapped to EL2.
If HSTR_EL2.T8==1, Non-secure execution of this instruction at EL1 is trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TTLB==1, Non-secure execution of this instruction at EL1 is trapped to EL2.
If HSTR_EL2.T8==1, Non-secure execution of this instruction at EL1 is trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
28/09/2017 08:24
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