DBGWCR<n>_EL1, Debug Watchpoint Control Registers, n = 0 - 15

The DBGWCR<n>_EL1 characteristics are:

Purpose

Holds control information for a watchpoint. Forms watchpoint n together with value register DBGWVR<n>_EL1.

This register is part of the Debug registers functional group.

Usage constraints

This register is accessible as follows:

OffDLKOSLKEDADSLKDefault
ErrorErrorErrorErrorRORW

Configuration

External register DBGWCR<n>_EL1 is architecturally mapped to AArch64 System register DBGWCR<n>_EL1.

External register DBGWCR<n>_EL1 is architecturally mapped to AArch32 System register DBGWCR<n>.

DBGWCR<n>_EL1 is in the Core power domain. RW fields in this register reset to architecturally UNKNOWN values. These apply only on a Cold reset. The register is not affected by a Warm reset and is not affected by an External debug reset.

If breakpoint n is not implemented then this register is unallocated.

Attributes

DBGWCR<n>_EL1 is a 32-bit register.

Field descriptions

The DBGWCR<n>_EL1 bit assignments are:

313029282726252423222120191817161514131211109876543210
000MASK000WTLBNSSCHMCBASLSCPACE

When the E field is zero, all the other fields in the register are ignored.

Bits [31:29]

Reserved, RES0.

MASK, bits [28:24]

Address mask. Only objects up to 2GB can be watched using a single mask.

MASKMeaning
00000

No mask.

00001

Reserved.

00010

Reserved.

If programmed with a reserved value, a watchpoint must behave as if either:

Software must not rely on this property because the behavior of reserved values might change in a future revision of the architecture.

Other values mask the corresponding number of address bits, from 0b00011 masking 3 address bits (0x00000007 mask for address) to 0b11111 masking 31 address bits (0x7FFFFFFF mask for address).

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bits [23:21]

Reserved, RES0.

WT, bit [20]

Watchpoint type. Possible values are:

WTMeaning
0

Unlinked data address match.

1

Linked data address match.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

LBN, bits [19:16]

Linked breakpoint number. For Linked data address watchpoints, this specifies the index of the Context-matching breakpoint linked to.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

SSC, bits [15:14]

Security state control. Determines the Security states under which a Watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the HMC and PAC fields.

For more information on the operation of the SSC, HMC, and PAC fields, see 'Execution conditions for which a watchpoint generates Watchpoint exceptions' in the ARMv8 ARM, section D2 (AArch64 Self-hosted Debug).

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

HMC, bit [13]

Higher mode control. Determines the debug perspective for deciding when a Watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and PAC fields.

For more information on the operation of the SSC, HMC, and PAC fields, see 'Execution conditions for which a watchpoint generates Watchpoint exceptions' in the ARMv8 ARM, section D2 (AArch64 Self-hosted Debug).

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

BAS, bits [12:5]

Byte address select. Each bit of this field selects whether a byte from within the word or double-word addressed by DBGWVR<n>_EL1 is being watched.

BAS Description
xxxxxxx1 Match byte at DBGWVR<n>_EL1
xxxxxx1x Match byte at DBGWVR<n>_EL1+1
xxxxx1xx Match byte at DBGWVR<n>_EL1+2
xxxx1xxx Match byte at DBGWVR<n>_EL1+3

In cases where DBGWVR<n>_EL1 addresses a double-word:

BAS Description, if DBGWVR<n>_EL1[2] == 0
xxx1xxxx Match byte at DBGWVR<n>_EL1+4
xx1xxxxx Match byte at DBGWVR<n>_EL1+5
x1xxxxxx Match byte at DBGWVR<n>_EL1+6
1xxxxxxx Match byte at DBGWVR<n>_EL1+7

If DBGWVR<n>_EL1[2] == 1, only BAS[3:0] is used. ARM deprecates setting DBGWVR<n>_EL1[2] == 1.

The valid values for BAS are non-zero binary number all of whose set bits are contiguous. All other values are reserved and must not be used by software. See 'Reserved DBGWCR<n>.BAS values' in the ARMv8 ARM, section G2 (AArch32 Self-hosted Debug).

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

LSC, bits [4:3]

Load/store control. This field enables watchpoint matching on the type of access being made. Possible values of this field are:

LSCMeaning
01

Match instructions that load from a watchpointed address.

10

Match instructions that store to a watchpointed address.

11

Match instructions that load from or store to a watchpointed address.

All other values are reserved, but must behave as if the watchpoint is disabled. Software must not rely on this property as the behavior of reserved values might change in a future revision of the architecture.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

PAC, bits [2:1]

Privilege of access control. Determines the Exception level or levels at which a Watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and HMC fields.

For more information on the operation of the SSC, HMC, and PAC fields, see 'Execution conditions for which a watchpoint generates Watchpoint exceptions' in the ARMv8 ARM, section D2 (AArch64 Self-hosted Debug).

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

E, bit [0]

Enable watchpoint n. Possible values are:

EMeaning
0

Watchpoint disabled.

1

Watchpoint enabled.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Accessing the DBGWCR<n>_EL1

DBGWCR<n>_EL1 can be accessed through the external debug interface:

ComponentOffset
Debug0x808 + 16n



28/09/2017 08:24

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