GICR_VPENDBASER, Virtual Redistributor LPI Pending Table Base Address Register

The GICR_VPENDBASER characteristics are:

Purpose

Specifies the base address of the memory that holds the virtual LPI Pending table for the currently scheduled virtual machine.

This register is part of the GIC Redistributor registers functional group.

Usage constraints

This register is accessible as follows:

Security disabledSecureNon-secure
RWRWRW

The effect of a write to this register is not guaranteed to be visible throughout the affinity hierarchy, as indicated by GICR_CTLR.RWP == 0.

Configuration

Some or all RW fields of this register have defined reset values.

This register is provided only in GICv4 implementations.

Attributes

GICR_VPENDBASER is a 64-bit register.

Field descriptions

The GICR_VPENDBASER bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
ValidIDAIPendingLastDirty0OuterCache0000Physical_Address
Physical_Address0000ShareabilityInnerCache0000000
313029282726252423222120191817161514131211109876543210

Valid, bit [63]

This bit controls whether the virtual LPI Pending table is valid:

ValidMeaning
0

The virtual LPI Pending table is not valid. No vPE is scheduled.

1

The virtual LPI Pending table is valid. A vPE is scheduled.

Setting GICR_VPENDBASER.Valid == 1 when the associated CPU interface does not implement GICv4 is UNPREDICTABLE.

Note

Software can determine whether a PE supports GICv3 or GICv4 by reading ID_AA64PFR0_EL1.

Writing a new value to any bit of GICR_VPENDBASER, other than GICR_VPENDBASER.Valid, when GICR_VPENDBASER.Valid==1 is UNPREDICTABLE.

When this register has an architecturally-defined reset value, this field resets to 0.

IDAI, bit [62]

Implementation Defined Area Invalid. Indicates whether the IMPLEMENTATION DEFINED area in the virtual LPI Pending table is valid:

IDAIMeaning
0

The IMPLEMENTATION DEFINED area is valid.

1

The IMPLEMENTATION DEFINED area is invalid and all pending interrupt information is held in the architecturally defined part of the virtual LPI Pending table.

For more information, see LPI Pending tables and Virtual LPI Configuration tables and virtual LPI Pending tables.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

PendingLast, bit [61]

Indicates whether there are pending and enabled interrupts for the last scheduled vPE.

This value is set by the implementation when GICR_VPENDBASER.Valid has been written from 1 to 0 and is otherwise UNKNOWN.

PendingLastMeaning
0

There are no pending and enabled interrupts for the last scheduled vPE.

1

There is at least one pending interrupt for the last scheduled vPE. It is IMPLEMENTATION DEFINED whether this bit is set when the only pending interrupts for the last scheduled vPE are not enabled.

ARM deprecates setting PendingLast to 1 when the only pending interrupts for the last scheduled virtual machine are not enabled.

When the GICR_VPENDBASER.Valid bit is written from 0 to 1, then the state of this bit indicates to the hardware whether the virtual LPI Pending table contains no pending interrupts:

When this register has an architecturally-defined reset value, this field resets to 0.

Dirty, bit [60]

Read-only. Indicates whether there are any virtual LPIs for the last scheduled vPE that have not completed. This field is used only when GICR_VPENDBASER.Valid==0, and is otherwise UNKNOWN:

DirtyMeaning
0

There are no uncompleted virtual LPIs for the last scheduled vPE.

1

There is at least one uncompleted virtual LPI for the last scheduled vPE.

Note

When GICR_VPENDBASER.Valid == 0, the Redistributor must ensure any outstanding pending virtual interrupts are cleared from the CPU interface.

Writing to GICR_VPENDBASER when GICR_VPENDBASER.Dirty==1 is UNPREDICTABLE.

When this register has an architecturally-defined reset value, this field resets to 0.

Bit [59]

Reserved, RES0.

OuterCache, bits [58:56]

Indicates the Outer Cacheability attributes of accesses to virtual LPI Pending tables of vPEs targeting this Redistributor. The possible values of this field are:

OuterCacheMeaning
000

Memory type defined in InnerCache field. For Normal memory, Outer Cacheability is the same as Inner Cacheability.

001

Normal Outer Non-cacheable.

010

Normal Outer Cacheable Read-allocate, Write-through.

011

Normal Outer Cacheable Read-allocate, Write-back.

100

Normal Outer Cacheable Write-allocate, Write-through.

101

Normal Outer Cacheable Write-allocate, Write-back.

110

Normal Outer Cacheable Read-allocate, Write-allocate, Write-through.

111

Normal Outer Cacheable Read-allocate, Write-allocate, Write-back.

It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.

The Cacheability, Outer Cacheability and Shareability fields are used for accesses to the virtual LPI Pending table of resident and non-resident vPEs.

If the OuterCacheabilty attribute of the virtual LPI Pending tables that are associated with vPEs targeting the same Redistributor are different, behavior is UNPREDICTABLE.

When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to a value that is architecturally UNKNOWN.

Bits [55:52]

Reserved, RES0.

Physical_Address, bits [51:16]

Bits [51:16] of the physical address containing the virtual LPI Pending table.

In implementations supporting fewer than 52 bits of physical address, unimplemented upper bits are RES0.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bits [15:12]

Reserved, RES0.

Shareability, bits [11:10]

Indicates the Shareability attributes of accesses to the virtual LPI Pending table. The possible values of this field are:

ShareabilityMeaning
00

Non-shareable.

01

Inner Shareable.

10

Outer Shareable.

11

Reserved. Treated as 00.

It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.

The Cacheability, Outer Cacheability and Shareability fields are used for accesses to the virtual LPI Pending table of resident and non-resident vPEs.

If the Shareability attribute of the virtual LPI Pending tables that are associated with vPEs targeting the same Redistributor are different, behavior is UNPREDICTABLE.

When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to a value that is architecturally UNKNOWN.

InnerCache, bits [9:7]

Indicates the Inner Cacheability attributes of accesses to the virtual LPI Pending table. The possible values of this field are:

InnerCacheMeaning
000

Device-nGnRnE.

001

Normal Inner Non-cacheable.

010

Normal Inner Cacheable Read-allocate, Write-through.

011

Normal Inner Cacheable Read-allocate, Write-back.

100

Normal Inner Cacheable Write-allocate, Write-through.

101

Normal Inner Cacheable Write-allocate, Write-back.

110

Normal Inner Cacheable Read-allocate, Write-allocate, Write-through.

111

Normal Inner Cacheable Read-allocate, Write-allocate, Write-back.

The Cacheability, Outer Cacheability and Shareability fields are used for accesses to the virtual LPI Pending table of resident and non-resident vPEs.

If the InnerCacheabilty attribute of the virtual LPI Pending tables that are associated with vPEs targeting the same Redistributor are different, behavior is UNPREDICTABLE.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bits [6:0]

Reserved, RES0.

Accessing the GICR_VPENDBASER

GICR_VPENDBASER can be accessed through its memory-mapped interface:

ComponentFrameOffset
GIC RedistributorVLPI_base0x0078-0x007C



28/09/2017 08:24

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