HTCR, Hyp Translation Control Register

The HTCR characteristics are:

Purpose

The control register for stage 1 of the EL2 translation regime.

Note

This stage of translation always uses the Long-descriptor translation table format.

This register is part of:

Configuration

AArch32 System register HTCR is architecturally mapped to AArch64 System register TCR_EL2.

If EL2 is not implemented, this register is RES0 from EL3.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

HTCR is a 32-bit register.

Field descriptions

The HTCR bit assignments are:

313029282726252423222120191817161514131211109876543210
1IMP DEF0HWU62HWU61HWU60HWU59HPD1000000000SH0ORGN0IRGN000000T0SZ

Bit [31]

Reserved, RES1.

IMP DEF, bit [30]

IMPLEMENTATION DEFINED.

Bit [29]

Reserved, RES0.

HWU62, bit [28]
In ARMv8.3 and ARMv8.2:

Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[62] of the stage 1 translation table Block or Page entry.

Defined values are:

HWU62Meaning
0

Bit[62] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose.

1

Bit[62] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of HTCR.HPD is 1.

This bit is RES0 if ARMv8.2-TTPBHA is not implemented.

The Effective value of this field is 0 if the value of HTCR.HPD is 0.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

HWU61, bit [27]
In ARMv8.3 and ARMv8.2:

Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[61] of the stage 1 translation table Block or Page entry.

Defined values are:

HWU61Meaning
0

Bit[61] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose.

1

Bit[61] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of HTCR.HPD is 1.

This bit is RES0 if ARMv8.2-TTPBHA is not implemented.

The Effective value of this field is 0 if the value of HTCR.HPD is 0.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

HWU60, bit [26]
In ARMv8.3 and ARMv8.2:

Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[60] of the stage 1 translation table Block or Page entry.

Defined values are:

HWU60Meaning
0

Bit[60] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose.

1

Bit[60] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of HTCR.HPD is 1.

This bit is RES0 if ARMv8.2-TTPBHA is not implemented.

The Effective value of this field is 0 if the value of HTCR.HPD is 0.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

HWU59, bit [25]
In ARMv8.3 and ARMv8.2:

Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[59] of the stage 1 translation table Block or Page entry.

Defined values are:

HWU59Meaning
0

Bit[59] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose.

1

Bit[59] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of HTCR.HPD is 1.

This bit is RES0 if ARMv8.2-TTPBHA is not implemented.

The Effective value of this field is 0 if the value of HTCR.HPD is 0.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

HPD, bit [24]
In ARMv8.3 and ARMv8.2:

Hierarchical Permission Disables. This affects the hierarchical control bits, APTable, XNTable, and PXNTable, in the PL2 translation regime.

Defined values are:

HPDMeaning
0

Hierarchical permissions are enabled.

1

Hierarchical permissions are disabled.

When disabled, the permissions are treated as if the bits are zero.

This bit is RES0 if ARMv8.2-AA32HPD is not implemented.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

Bit [23]

Reserved, RES1.

Bits [22:14]

Reserved, RES0.

SH0, bits [13:12]

Shareability attribute for memory associated with translation table walks using HTTBR.

SH0Meaning
00

Non-shareable

10

Outer Shareable

11

Inner Shareable

Other values are reserved. The effect of programming this field to a Reserved value is that behavior is CONSTRAINED UNPREDICTABLE, as described in 'Unallocated values in fields of AArch32 System registers and translation table entries' in the ARM ARM, section K1.1.11.

ORGN0, bits [11:10]

Outer cacheability attribute for memory associated with translation table walks using HTTBR.

ORGN0Meaning
00

Normal memory, Outer Non-cacheable

01

Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable

10

Normal memory, Outer Write-Through Read-Allocate No Write-Allocate Cacheable

11

Normal memory, Outer Write-Back Read-Allocate No Write-Allocate Cacheable

IRGN0, bits [9:8]

Inner cacheability attribute for memory associated with translation table walks using HTTBR.

IRGN0Meaning
00

Normal memory, Inner Non-cacheable

01

Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable

10

Normal memory, Inner Write-Through Read-Allocate No Write-Allocate Cacheable

11

Normal memory, Inner Write-Back Read-Allocate No Write-Allocate Cacheable

Bits [7:3]

Reserved, RES0.

T0SZ, bits [2:0]

The size offset of the memory region addressed by HTTBR. The region size is 2(32-T0SZ) bytes.

Accessing the HTCR

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 4, <Rt>, c2, c0, 2100010001011110000

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - - n/a -
x01 - - RWRW
x11 - n/a RWRW

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :




28/09/2017 08:24

Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.