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The PMSWINC characteristics are:
Increments a counter that is configured to count the Software increment event, event 0x00. For more information, see 'SW_INCR' in the ARMv8 ARM, section D5.
This register is part of the Performance Monitors registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register PMSWINC is architecturally mapped to AArch64 System register PMSWINC_EL0.
AArch32 System register PMSWINC is architecturally mapped to External register PMSWINC_EL0.
PMSWINC is a 32-bit register.
The PMSWINC bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | P<n>, bit [n] |
Reserved, RES0.
Event counter software increment bit for PMEVCNTR<n>.
Bits [30:N] are WI.
When EL2 is implemented, in Non-secure EL1 and EL0, N is the value in MDCR_EL2.HPMN if EL2 is using AArch64 or in HDCR.HPMN if EL2 is using AArch32. Otherwise, N is the value in PMCR.N.
The effects of writing to this bit are:
P<n> | Meaning |
---|---|
0 | No action. The write to this bit is ignored. |
1 | If PMEVCNTR<n> is enabled and configured to count the software increment event, increments PMEVCNTR<n> by 1. If PMEVCNTR<n> is disabled, or not configured to count the software increment event, the write to this bit is ignored. |
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c9, c12, 4 | 000 | 100 | 1001 | 1111 | 1100 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | WO | WO | n/a | WO |
x | 0 | 1 | WO | WO | WO | WO |
x | 1 | 1 | WO | n/a | WO | WO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If PMUSERENR.EN==0, and PMUSERENR.SW==0, write accesses to this register from EL0 are trapped to Undefined mode.
If PMUSERENR_EL0.EN==0, and PMUSERENR_EL0.SW==0, write accesses to this register from EL0 are trapped to EL1.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HSTR_EL2.T9==1, Non-secure write accesses to this register from EL0 and EL1 are trapped to EL2.
If HSTR_EL2.T9==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TPM==1, Non-secure write accesses to this register from EL0 and EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T9==1, Non-secure write accesses to this register from EL0 and EL1 are trapped to EL2.
If HSTR_EL2.T9==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HDCR.TPM==1, Non-secure write accesses to this register from EL0 and EL1 are trapped to Hyp mode.
If HSTR.T9==1, Non-secure write accesses to this register from EL0 and EL1 are trapped to Hyp mode.
If HSTR.T9==1, Non-secure accesses to this register from EL1 are trapped to Hyp mode.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TPM==1, write accesses to this register from EL0, EL1, and EL2 are trapped to EL3.
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