The HSTR_EL2 characteristics are:
Controls trapping to EL2 of Non-secure EL1 or lower AArch32 accesses to the System register in the coproc == 1111 encoding space, by the CRn value used to access the register using MCR or MRC instruction. When the register is accessible using an MCRR or MRRC instruction, this is the CRm value used to access the register.
This register is part of the Virtualization registers functional group.
AArch64 System register HSTR_EL2 is architecturally mapped to AArch32 System register HSTR.
If EL2 is not implemented, this register is RES0 from EL3.
If no Exception level can use AArch32, then this register is RES0.
RW fields in this register reset to architecturally UNKNOWN values.
HSTR_EL2 is a 32-bit register.
The HSTR_EL2 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | T15 | T14 | T13 | T12 | T11 | T10 | T9 | T8 | T7 | T6 | T5 | T4 | T3 | T2 | T1 | T0 |
Reserved, RES0.
Fields T14 and T4 are RES0.
The remaining fields control whether Non-secure EL0 and EL1 accesses, using MCR, MRC, MCRR, and MRRC instructions, to the System registers in the coproc == 1111 encoding space are trapped to EL2:
T<n> | Meaning |
---|---|
0 |
This control has no effect on Non-secure EL0 or EL1 accesses to System registers. |
1 |
Any Non-secure EL1 MCR or MRC access with coproc == 1111 and CRn == <n> is trapped to EL2. A Non-secure EL0 MCR or MRC access with these values is trapped to EL2 only if the access is not UNDEFINED when the value of this field is 0. Any Non-secure EL1 MCRR or MRRC access with coproc == 1111 and CRm == <n> is trapped to EL2. A Non-secure EL0 MCRR or MRRC access with these values is trapped to EL2 only if the access is not UNDEFINED when the value of this field is 0. |
For example, when HSTR_EL2.T7 is 1, for instructions executed at Non-secure EL1:
When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 0 for all purposes other than a direct read of the value of this bit.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
HSTR_EL2 | 11 | 100 | 0001 | 0001 | 011 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | - | n/a | RW |
0 | 0 | 1 | - | - | RW | RW |
0 | 1 | 1 | - | n/a | RW | RW |
1 | 0 | 1 | - | - | RW | RW |
1 | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.NV==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.NV==1, Non-secure accesses to this register from EL1 are trapped to EL2.
28/09/2017 08:24
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