The ICC_SRE_EL2 characteristics are:
Controls whether the System register interface or the memory-mapped interface to the GIC CPU interface is used for EL2.
This register is part of:
AArch64 System register ICC_SRE_EL2 is architecturally mapped to AArch32 System register ICC_HSRE.
If EL2 is not implemented, this register is RES0 from EL3.
ICC_SRE_EL2 is a 32-bit register.
The ICC_SRE_EL2 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Enable | DIB | DFB | SRE |
Reserved, RES0.
Enable. Enables lower Exception level access to ICC_SRE_EL1.
Enable | Meaning |
---|---|
0 |
Non-secure EL1 accesses to ICC_SRE_EL1 trap to EL2. |
1 |
Non-secure EL1 accesses to ICC_SRE_EL1 do not trap to EL2. |
If ICC_SRE_EL2.SRE is RAO/WI, an implementation is permitted to make the Enable bit RAO/WI.
If ICC_SRE_EL2.SRE is 0, the Enable bit behaves as 1 for all purposes other than reading the value of the bit.
Disable IRQ bypass.
DIB | Meaning |
---|---|
0 |
IRQ bypass enabled. |
1 |
IRQ bypass disabled. |
If EL3 is implemented and GICD_CTLR.DS is 0, this field is a read-only alias of ICC_SRE_EL3.DIB.
If EL3 is implemented and GICD_CTLR.DS is 1, this field is a read-write alias of ICC_SRE_EL3.DIB.
In systems that do not support IRQ bypass, this bit is RAO/WI.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.
Disable FIQ bypass.
DFB | Meaning |
---|---|
0 |
FIQ bypass enabled. |
1 |
FIQ bypass disabled. |
If EL3 is implemented and GICD_CTLR.DS is 0, this field is a read-only alias of ICC_SRE_EL3.DFB.
If EL3 is implemented and GICD_CTLR.DS is 1, this field is a read-write alias of ICC_SRE_EL3.DFB.
In systems that do not support FIQ bypass, this bit is RAO/WI.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.
System Register Enable.
SRE | Meaning |
---|---|
0 |
The memory-mapped interface must be used. Access at EL2 to any ICH_* or ICC_* register other than ICC_SRE_EL1 or ICC_SRE_EL2, is trapped to EL2. |
1 |
The System register interface to the ICH_* registers and the EL1 and EL2 ICC_* registers is enabled for EL2. |
If software changes this bit from 1 to 0, the results are UNPREDICTABLE.
If an implementation supports only a System register interface to the GIC CPU interface, this bit is RAO/WI.
If EL3 is implemented and ICC_SRE_EL3.SRE==0 this bit is RAZ/WI. If ICC_SRE_EL3.SRE is changed from zero to one, this bit becomes UNKNOWN.
GICv3 implementations that do not require GICv2 compatibility might choose to make this bit RAO/WI, but this is only allowed if ICC_SRE_EL3.SRE is also RAO/WI.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
ICC_SRE_EL2 | 11 | 100 | 1100 | 1001 | 101 |
The register is accessible as follows:
Control | Accessibility | ||||
---|---|---|---|---|---|
TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | 0 | - | - | n/a | - |
0 | 1 | - | - | RW | RW |
1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
Execution with ICC_SRE_EL2.SRE set to 0 might make some System registers UNKNOWN.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_SRE_EL3.Enable==0, accesses to this register from EL2 are trapped to EL3.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If HCR_EL2.NV==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.TGE==0 :
If HCR_EL2.NV==1, Non-secure accesses to this register from EL1 are trapped to EL2.
28/09/2017 08:24
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