000
|
000
|
0000
|
1110
|
0000
|
DBGDIDR
|
Debug ID Register
|
1110 | 000 | 0000 | 0000 | 000 | DBGDIDR | Debug ID Register |
111
|
000
|
0000
|
1110
|
0000
|
JIDR
|
Jazelle ID Register
|
1110 | 000 | 0000 | 0000 | 010 | DBGDTRRXext | Debug OS Lock Data Transfer Register, Receive, External View |
000
|
010
|
0000
|
1110
|
0000
|
DBGDTRRXext
|
Debug OS Lock Data Transfer Register, Receive, External View
|
1110 | 000 | 0000 | 0001 | 000 | DBGDSCRint | Debug Status and Control Register, Internal View |
000
|
000
|
0001
|
1110
|
0000
|
DBGDRAR
|
Debug ROM Address Register
|
1110 | 000 | 0000 | 0010 | 000 | DBGDCCINT | DCC Interrupt Enable Register |
111
|
000
|
0001
|
1110
|
0000
|
JOSCR
|
Jazelle OS Control Register
|
1110 | 000 | 0000 | 0010 | 010 | DBGDSCRext | Debug Status and Control Register, External View |
000
|
100
|
0001
|
1110
|
0000
|
DBGOSLAR
|
Debug OS Lock Access Register
|
1110 | 000 | 0000 | 0011 | 010 | DBGDTRTXext | Debug OS Lock Data Transfer Register, Transmit |
000
|
000
|
0010
|
1110
|
0000
|
DBGDSAR
|
Debug Self Address Register
|
1110 | 000 | 0000 | 0101 | 000 | DBGDTRRXint | Debug Data Transfer Register, Receive |
111
|
000
|
0010
|
1110
|
0000
|
JMCR
|
Jazelle Main Configuration Register
|
1110 | 000 | 0000 | 0101 | 000 | DBGDTRTXint | Debug Data Transfer Register, Transmit |
000
|
111
|
0111
|
1110
|
0000
|
DBGDEVID2
|
Debug Device ID register 2
|
1110 | 000 | 0000 | 0110 | 000 | DBGWFAR | Debug Watchpoint Fault Address Register |
000
|
000
|
0000
|
1111
|
0000
|
MIDR
|
Main ID Register
|
1110 | 000 | 0000 | 0110 | 010 | DBGOSECCR | Debug OS Lock Exception Catch Control Register |
0011110
|
000
|
0000
|
11110111
|
0000000
|
CCSIDR
DBGVCR |
CurrentDebug CacheVector Size IDCatch Register
|
0101110
|
000
|
0000
|
1111xxxx
|
0000100
|
CSSELR
DBGBVR<n> |
CacheDebug SizeBreakpoint SelectionValue RegisterRegisters
|
1001110
|
000
|
0000
|
1111xxxx
|
0000101
|
VPIDR
DBGBCR<n> |
VirtualizationDebug ProcessorBreakpoint IDControl RegisterRegisters
|
000
|
001
|
0000
|
1111
|
0000
|
CTR
|
Cache Type Register
|
1110 | 000 | 0000 | xxxx | 110 | DBGWVR<n> | Debug Watchpoint Value Registers |
0011110
|
001000
|
0000
|
1111xxxx
|
0000111
|
CLIDR
DBGWCR<n> |
CacheDebug LevelWatchpoint IDControl RegisterRegisters
|
000
|
010
|
0000
|
1111
|
0000
|
TCMTR
|
TCM Type Register
|
1110 | 000 | 0001 | 0000 | 000 | DBGDRAR | Debug ROM Address Register |
001
|
010
|
0000
|
1111
|
0000
|
CCSIDR2
|
Current Cache Size ID Register 2
|
1110 | 000 | 0001 | 0000 | 100 | DBGOSLAR | Debug OS Lock Access Register |
000
|
011
|
0000
|
1111
|
0000
|
TLBTR
|
TLB Type Register
|
1110 | 000 | 0001 | 0001 | 100 | DBGOSLSR | Debug OS Lock Status Register |
000
|
101
|
0000
|
1111
|
0000
|
MPIDR
|
Multiprocessor Affinity Register
|
1110 | 000 | 0001 | 0011 | 100 | DBGOSDLR | Debug OS Double Lock Register |
100
|
101
|
0000
|
1111
|
0000
|
VMPIDR
|
Virtualization Multiprocessor ID Register
|
1110 | 000 | 0001 | 0100 | 100 | DBGPRCR | Debug Power Control Register |
000
|
110
|
0000
|
1111
|
0000
|
REVIDR
|
Revision ID Register
|
1110 | 000 | 0001 | xxxx | 001 | DBGBXVR<n> | Debug Breakpoint Extended Value Registers |
001
|
111
|
0000
|
1111
|
0000
|
AIDR
|
Auxiliary ID Register
|
1110 | 000 | 0010 | 0000 | 000 | DBGDSAR | Debug Self Address Register |
000
|
000
|
0001
|
1111
|
0000
|
SCTLR
|
System Control Register
|
1110 | 000 | 0111 | 0000 | 111 | DBGDEVID2 | Debug Device ID register 2 |
100
|
000
|
0001
|
1111
|
0000
|
HSCTLR
|
Hyp System Control Register
|
1110 | 000 | 0111 | 0001 | 111 | DBGDEVID1 | Debug Device ID register 1 |
000
|
001
|
0001
|
1111
|
0000
|
ACTLR
|
Auxiliary Control Register
|
1110 | 000 | 0111 | 0010 | 111 | DBGDEVID | Debug Device ID register 0 |
1001110
|
001000
|
00010111
|
11111000
|
0000110
|
HACTLR
DBGCLAIMSET |
HypDebug AuxiliaryClaim ControlTag RegisterSet register
|
000
|
010
|
0001
|
1111
|
0000
|
CPACR
|
Architectural Feature Access Control Register
|
1110 | 000 | 0111 | 1001 | 110 | DBGCLAIMCLR | Debug Claim Tag Clear register |
000
|
011
|
0001
|
1111
|
0000
|
ACTLR2
|
Auxiliary Control Register 2
|
1110 | 000 | 0111 | 1110 | 110 | DBGAUTHSTATUS | Debug Authentication Status register |
100
|
011
|
0001
|
1111
|
0000
|
HACTLR2
|
Hyp Auxiliary Control Register 2
|
1110 | 111 | 0000 | 0000 | 000 | JIDR | Jazelle ID Register |
000
|
000
|
0010
|
1111
|
0000
|
TTBR0
|
Translation Table Base Register 0
|
1110 | 111 | 0001 | 0000 | 000 | JOSCR | Jazelle OS Control Register |
000
|
001
|
0010
|
1111
|
0000
|
TTBR1
|
Translation Table Base Register 1
|
1110 | 111 | 0010 | 0000 | 000 | JMCR | Jazelle Main Configuration Register |
000
|
010
|
0010
|
1111
|
0000
|
TTBCR
|
Translation Table Base Control Register
|
1111 | 000 | 0000 | 0000 | 000 | MIDR | Main ID Register |
100
|
010
|
0010
|
1111
|
0000
|
HTCR
|
Hyp Translation Control Register
|
1111 | 000 | 0000 | 0000 | 001 | CTR | Cache Type Register |
000
|
011
|
0010
|
1111
|
0000
|
TTBCR2
|
Translation Table Base Control Register 2
|
1111 | 000 | 0000 | 0000 | 010 | TCMTR | TCM Type Register |
000
|
000
|
0011
|
1111
|
0000
|
DACR
|
Domain Access Control Register
|
1111 | 000 | 0000 | 0000 | 011 | TLBTR | TLB Type Register |
000
|
000
|
0101
|
1111
|
0000
|
DFSR
|
Data Fault Status Register
|
1111 | 000 | 0000 | 0000 | 101 | MPIDR | Multiprocessor Affinity Register |
000
|
001
|
0101
|
1111
|
0000
|
IFSR
|
Instruction Fault Status Register
|
1111 | 000 | 0000 | 0000 | 110 | REVIDR | Revision ID Register |
000
|
000
|
0110
|
1111
|
0000
|
DFAR
|
Data Fault Address Register
|
1111 | 000 | 0000 | 0001 | 000 | ID_PFR0 | Processor Feature Register 0 |
100
|
000
|
0110
|
1111
|
0000
|
HDFAR
|
Hyp Data Fault Address Register
|
1111 | 000 | 0000 | 0001 | 001 | ID_PFR1 | Processor Feature Register 1 |
000
|
010
|
0110
|
1111
|
0000
|
IFAR
|
Instruction Fault Address Register
|
1111 | 000 | 0000 | 0001 | 010 | ID_DFR0 | Debug Feature Register 0 |
100
|
010
|
0110
|
1111
|
0000
|
HIFAR
|
Hyp Instruction Fault Address Register
|
1111 | 000 | 0000 | 0001 | 011 | ID_AFR0 | Auxiliary Feature Register 0 |
100
|
100
|
0110
|
1111
|
0000
|
HPFAR
|
Hyp IPA Fault Address Register
|
1111 | 000 | 0000 | 0001 | 100 | ID_MMFR0 | Memory Model Feature Register 0 |
100
|
001
|
1000
|
1111
|
0000
|
TLBIIPAS2IS
|
TLB Invalidate by Intermediate Physical Address, Stage 2, Inner Shareable
|
1111 | 000 | 0000 | 0001 | 101 | ID_MMFR1 | Memory Model Feature Register 1 |
100
|
101
|
1000
|
1111
|
0000
|
TLBIIPAS2LIS
|
TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, Inner Shareable
|
1111 | 000 | 0000 | 0001 | 110 | ID_MMFR2 | Memory Model Feature Register 2 |
000
|
000
|
1100
|
1111
|
0000
|
VBAR
|
Vector Base Address Register
|
1111 | 000 | 0000 | 0001 | 111 | ID_MMFR3 | Memory Model Feature Register 3 |
100
|
000
|
1100
|
1111
|
0000
|
HVBAR
|
Hyp Vector Base Address Register
|
1111 | 000 | 0000 | 0010 | 000 | ID_ISAR0 | Instruction Set Attribute Register 0 |
000
|
001
|
1100
|
1111
|
0000
|
MVBAR
|
Monitor Vector Base Address Register
|
1111 | 000 | 0000 | 0010 | 001 | ID_ISAR1 | Instruction Set Attribute Register 1 |
000
|
001
|
1100
|
1111
|
0000
|
RVBAR
|
Reset Vector Base Address Register
|
1111 | 000 | 0000 | 0010 | 010 | ID_ISAR2 | Instruction Set Attribute Register 2 |
000
|
010
|
1100
|
1111
|
0000
|
RMR
|
Reset Management Register
|
1111 | 000 | 0000 | 0010 | 011 | ID_ISAR3 | Instruction Set Attribute Register 3 |
100
|
010
|
1100
|
1111
|
0000
|
HRMR
|
Hyp Reset Management Register
|
1111 | 000 | 0000 | 0010 | 100 | ID_ISAR4 | Instruction Set Attribute Register 4 |
000
|
000
|
1101
|
1111
|
0000
|
FCSEIDR
|
FCSE Process ID register
|
1111 | 000 | 0000 | 0010 | 101 | ID_ISAR5 | Instruction Set Attribute Register 5 |
000
|
001
|
1101
|
1111
|
0000
|
CONTEXTIDR
|
Context ID Register
|
1111 | 000 | 0000 | 0010 | 110 | ID_MMFR4 | Memory Model Feature Register 4 |
000
|
010
|
1101
|
1111
|
0000
|
TPIDRURW
|
PL0 Read/Write Software Thread ID Register
|
1111 | 000 | 0000 | 0010 | 111 | ID_ISAR6 | Instruction Set Attribute Register 6 |
100
|
010
|
1101
|
1111
|
0000
|
HTPIDR
|
Hyp Software Thread ID Register
|
1111 | 000 | 0001 | 0000 | 000 | SCTLR | System Control Register |
000
|
011
|
1101
|
1111
|
0000
|
TPIDRURO
|
PL0 Read-Only Software Thread ID Register
|
1111 | 000 | 0001 | 0000 | 001 | ACTLR | Auxiliary Control Register |
000
|
100
|
1101
|
1111
|
0000
|
TPIDRPRW
|
PL1 Software Thread ID Register
|
1111 | 000 | 0001 | 0000 | 010 | CPACR | Architectural Feature Access Control Register |
000
|
000
|
1110
|
1111
|
0000
|
CNTFRQ
|
Counter-timer Frequency register
|
1111 | 000 | 0001 | 0000 | 011 | ACTLR2 | Auxiliary Control Register 2 |
000
|
000
|
0000
|
1110
|
0001
|
DBGDSCRint
|
Debug Status and Control Register, Internal View
|
1111 | 000 | 0001 | 0001 | 000 | SCR | Secure Configuration Register |
000
|
100
|
0001
|
1110
|
0001
|
DBGOSLSR
|
Debug OS Lock Status Register
|
1111 | 000 | 0001 | 0001 | 001 | SDER | Secure Debug Enable Register |
000
|
111
|
0111
|
1110
|
0001
|
DBGDEVID1
|
Debug Device ID register 1
|
1111 | 000 | 0001 | 0001 | 010 | NSACR | Non-Secure Access Control Register |
000
|
000
|
0000
|
1111
|
0001
|
ID_PFR0
|
Processor Feature Register 0
|
1111 | 000 | 0001 | 0011 | 001 | SDCR | Secure Debug Control Register |
000
|
001
|
0000
|
1111
|
0001
|
ID_PFR1
|
Processor Feature Register 1
|
1111 | 000 | 0010 | 0000 | 000 | TTBR0 | Translation Table Base Register 0 |
000
|
010
|
0000
|
1111
|
0001
|
ID_DFR0
|
Debug Feature Register 0
|
1111 | 000 | 0010 | 0000 | 001 | TTBR1 | Translation Table Base Register 1 |
000
|
011
|
0000
|
1111
|
0001
|
ID_AFR0
|
Auxiliary Feature Register 0
|
1111 | 000 | 0010 | 0000 | 010 | TTBCR | Translation Table Base Control Register |
000
|
100
|
0000
|
1111
|
0001
|
ID_MMFR0
|
Memory Model Feature Register 0
|
1111 | 000 | 0010 | 0000 | 011 | TTBCR2 | Translation Table Base Control Register 2 |
000
|
101
|
0000
|
1111
|
0001
|
ID_MMFR1
|
Memory Model Feature Register 1
|
1111 | 000 | 0011 | 0000 | 000 | DACR | Domain Access Control Register |
000
|
110
|
0000
|
1111
|
0001
|
ID_MMFR2
|
Memory Model Feature Register 2
|
1111 | 000 | 0100 | 0110 | 000 | ICC_PMR | Interrupt Controller Interrupt Priority Mask Register |
000
|
111
|
0000
|
1111
|
0001
|
ID_MMFR3
|
Memory Model Feature Register 3
|
1111 | 000 | 0100 | 0110 | 000 | ICV_PMR | Interrupt Controller Virtual Interrupt Priority Mask Register |
000
|
000
|
0001
|
1111
|
0001
|
SCR
|
Secure Configuration Register
|
1111 | 000 | 0101 | 0000 | 000 | DFSR | Data Fault Status Register |
1001111
|
000
|
00010101
|
11110000
|
0001001
|
HCR
IFSR |
HypInstruction ConfigurationFault Status Register
|
000
|
001
|
0001
|
1111
|
0001
|
SDER
|
Secure Debug Enable Register
|
1111 | 000 | 0101 | 0001 | 000 | ADFSR | Auxiliary Data Fault Status Register |
100
|
001
|
0001
|
1111
|
0001
|
HDCR
|
Hyp Debug Control Register
|
1111 | 000 | 0101 | 0001 | 001 | AIFSR | Auxiliary Instruction Fault Status Register |
000
|
010
|
0001
|
1111
|
0001
|
NSACR
|
Non-Secure Access Control Register
|
1111 | 000 | 0110 | 0000 | 000 | DFAR | Data Fault Address Register |
100
|
010
|
0001
|
1111
|
0001
|
HCPTR
|
Hyp Architectural Feature Trap Register
|
1111 | 000 | 0110 | 0000 | 010 | IFAR | Instruction Fault Address Register |
100
|
011
|
0001
|
1111
|
0001
|
HSTR
|
Hyp System Trap Register
|
1111 | 000 | 0111 | 0001 | 000 | ICIALLUIS | Instruction Cache Invalidate All to PoU, Inner Shareable |
100
|
100
|
0001
|
1111
|
0001
|
HCR2
|
Hyp Configuration Register 2
|
1111 | 000 | 0111 | 0001 | 110 | BPIALLIS | Branch Predictor Invalidate All, Inner Shareable |
100
|
111
|
0001
|
1111
|
0001
|
HACR
|
Hyp Auxiliary Configuration Register
|
1111 | 000 | 0111 | 0100 | 000 | PAR | Physical Address Register |
100
|
010
|
0010
|
1111
|
0001
|
VTCR
|
Virtualization Translation Control Register
|
1111 | 000 | 0111 | 0101 | 000 | ICIALLU | Instruction Cache Invalidate All to PoU |
000
|
000
|
0101
|
1111
|
0001
|
ADFSR
|
Auxiliary Data Fault Status Register
|
1111 | 000 | 0111 | 0101 | 001 | ICIMVAU | Instruction Cache line Invalidate by VA to PoU |
100
|
000
|
0101
|
1111
|
0001
|
HADFSR
|
Hyp Auxiliary Data Fault Status Register
|
1111 | 000 | 0111 | 0101 | 100 | CP15ISB | Instruction Synchronization Barrier System instruction |
000
|
001
|
0101
|
1111
|
0001
|
AIFSR
|
Auxiliary Instruction Fault Status Register
|
1111 | 000 | 0111 | 0101 | 110 | BPIALL | Branch Predictor Invalidate All |
100
|
001
|
0101
|
1111
|
0001
|
HAIFSR
|
Hyp Auxiliary Instruction Fault Status Register
|
1111 | 000 | 0111 | 0101 | 111 | BPIMVA | Branch Predictor Invalidate by VA |
000
|
000
|
0111
|
1111
|
0001
|
ICIALLUIS
|
Instruction Cache Invalidate All to PoU, Inner Shareable
|
1111 | 000 | 0111 | 0110 | 001 | DCIMVAC | Data Cache line Invalidate by VA to PoC |
000
|
110
|
0111
|
1111
|
0001
|
BPIALLIS
|
Branch Predictor Invalidate All, Inner Shareable
|
1111 | 000 | 0111 | 0110 | 010 | DCISW | Data Cache line Invalidate by Set/Way |
000
|
000
|
1100
|
1111
|
0001
|
ISR
|
Interrupt Status Register
|
1111 | 000 | 0111 | 1000 | 000 | ATS1CPR | Address Translate Stage 1 Current state PL1 Read |
000
|
000
|
1110
|
1111
|
0001
|
CNTKCTL
|
Counter-timer Kernel Control register
|
1111 | 000 | 0111 | 1000 | 001 | ATS1CPW | Address Translate Stage 1 Current state PL1 Write |
1001111
|
000
|
11100111
|
11111000
|
0001010
|
CNTHCTL
ATS1CUR |
Counter-timerAddress HypTranslate ControlStage register1 Current state Unprivileged Read
|
000
|
000
|
0000
|
1110
|
0010
|
DBGDCCINT
|
DCC Interrupt Enable Register
|
1111 | 000 | 0111 | 1000 | 011 | ATS1CUW | Address Translate Stage 1 Current state Unprivileged Write |
000
|
010
|
0000
|
1110
|
0010
|
DBGDSCRext
|
Debug Status and Control Register, External View
|
1111 | 000 | 0111 | 1000 | 100 | ATS12NSOPR | Address Translate Stages 1 and 2 Non-secure Only PL1 Read |
000
|
111
|
0111
|
1110
|
0010
|
DBGDEVID
|
Debug Device ID register 0
|
1111 | 000 | 0111 | 1000 | 101 | ATS12NSOPW | Address Translate Stages 1 and 2 Non-secure Only PL1 Write |
000
|
000
|
0000
|
1111
|
0010
|
ID_ISAR0
|
Instruction Set Attribute Register 0
|
1111 | 000 | 0111 | 1000 | 110 | ATS12NSOUR | Address Translate Stages 1 and 2 Non-secure Only Unprivileged Read |
000
|
001
|
0000
|
1111
|
0010
|
ID_ISAR1
|
Instruction Set Attribute Register 1
|
1111 | 000 | 0111 | 1000 | 111 | ATS12NSOUW | Address Translate Stages 1 and 2 Non-secure Only Unprivileged Write |
000
|
010
|
0000
|
1111
|
0010
|
ID_ISAR2
|
Instruction Set Attribute Register 2
|
1111 | 000 | 0111 | 1001 | 000 | ATS1CPRP | Address Translate Stage 1 Current state PL1 Read PAN |
000
|
011
|
0000
|
1111
|
0010
|
ID_ISAR3
|
Instruction Set Attribute Register 3
|
1111 | 000 | 0111 | 1001 | 001 | ATS1CPWP | Address Translate Stage 1 Current state PL1 Write PAN |
000
|
100
|
0000
|
1111
|
0010
|
ID_ISAR4
|
Instruction Set Attribute Register 4
|
1111 | 000 | 0111 | 1010 | 001 | DCCMVAC | Data Cache line Clean by VA to PoC |
000
|
101
|
0000
|
1111
|
0010
|
ID_ISAR5
|
Instruction Set Attribute Register 5
|
1111 | 000 | 0111 | 1010 | 010 | DCCSW | Data Cache line Clean by Set/Way |
000
|
110
|
0000
|
1111
|
0010
|
ID_MMFR4
|
Memory Model Feature Register 4
|
1111 | 000 | 0111 | 1010 | 100 | CP15DSB | Data Synchronization Barrier System instruction |
000
|
111
|
0000
|
1111
|
0010
|
ID_ISAR6
|
Instruction Set Attribute Register 6
|
1111 | 000 | 0111 | 1010 | 101 | CP15DMB | Data Memory Barrier System instruction |
1001111
|
000
|
01010111
|
11111011
|
0010001
|
HSR
DCCMVAU |
HypData SyndromeCache Registerline Clean by VA to PoU
|
000
|
000
|
1010
|
1111
|
0010
|
MAIR0
|
Memory Attribute Indirection Register 0
|
1111 | 000 | 0111 | 1110 | 001 | DCCIMVAC | Data Cache line Clean and Invalidate by VA to PoC |
000
|
000
|
1010
|
1111
|
0010
|
PRRR
|
Primary Region Remap Register
|
1111 | 000 | 0111 | 1110 | 010 | DCCISW | Data Cache line Clean and Invalidate by Set/Way |
1001111
|
000
|
10101000
|
11110011
|
0010000
|
HMAIR0
TLBIALLIS |
HypTLB MemoryInvalidate AttributeAll, IndirectionInner Register 0Shareable
|
000
|
001
|
1010
|
1111
|
0010
|
MAIR1
|
Memory Attribute Indirection Register 1
|
1111 | 000 | 1000 | 0011 | 001 | TLBIMVAIS | TLB Invalidate by VA, Inner Shareable |
000
|
001
|
1010
|
1111
|
0010
|
NMRR
|
Normal Memory Remap Register
|
1111 | 000 | 1000 | 0011 | 010 | TLBIASIDIS | TLB Invalidate by ASID match, Inner Shareable |
100
|
001
|
1010
|
1111
|
0010
|
HMAIR1
|
Hyp Memory Attribute Indirection Register 1
|
1111 | 000 | 1000 | 0011 | 011 | TLBIMVAAIS | TLB Invalidate by VA, All ASID, Inner Shareable |
000
|
000
|
1110
|
1111
|
0010
|
CNTP_TVAL
|
Counter-timer Physical Timer TimerValue register
|
1111 | 000 | 1000 | 0011 | 101 | TLBIMVALIS | TLB Invalidate by VA, Last level, Inner Shareable |
1001111
|
000
|
11101000
|
11110011
|
0010111
|
CNTHP_TVAL
TLBIMVAALIS |
Counter-timerTLB HypInvalidate Physicalby TimerVA, TimerValueAll registerASID, Last level, Inner Shareable
|
000
|
001
|
1110
|
1111
|
0010
|
CNTP_CTL
|
Counter-timer Physical Timer Control register
|
1111 | 000 | 1000 | 0101 | 000 | ITLBIALL | Instruction TLB Invalidate All |
100
|
001
|
1110
|
1111
|
0010
|
CNTHP_CTL
|
Counter-timer Hyp Physical Timer Control register
|
1111 | 000 | 1000 | 0101 | 001 | ITLBIMVA | Instruction TLB Invalidate by VA |
000
|
010
|
0000
|
1110
|
0011
|
DBGDTRTXext
|
Debug OS Lock Data Transfer Register, Transmit
|
1111 | 000 | 1000 | 0101 | 010 | ITLBIASID | Instruction TLB Invalidate by ASID match |
000
|
100
|
0001
|
1110
|
0011
|
DBGOSDLR
|
Debug OS Double Lock Register
|
1111 | 000 | 1000 | 0110 | 000 | DTLBIALL | Data TLB Invalidate All |
000
|
001
|
0001
|
1111
|
0011
|
SDCR
|
Secure Debug Control Register
|
1111 | 000 | 1000 | 0110 | 001 | DTLBIMVA | Data TLB Invalidate by VA |
000
|
000
|
1000
|
1111
|
0011
|
TLBIALLIS
|
TLB Invalidate All, Inner Shareable
|
1111 | 000 | 1000 | 0110 | 010 | DTLBIASID | Data TLB Invalidate by ASID match |
1001111
|
000
|
1000
|
11110111
|
0011000
|
TLBIALLHIS
TLBIALL |
TLB Invalidate All, Hyp mode, Inner Shareable
|
000
|
001
|
1000
|
1111
|
0011
|
TLBIMVAIS
|
TLB Invalidate by VA, Inner Shareable
|
1111 | 000 | 1000 | 0111 | 001 | TLBIMVA | TLB Invalidate by VA |
1001111
|
001000
|
1000
|
11110111
|
0011010
|
TLBIMVAHIS
TLBIASID |
TLB Invalidate by VA,ASID Hyp mode, Inner Shareablematch
|
000
|
010
|
1000
|
1111
|
0011
|
TLBIASIDIS
|
TLB Invalidate by ASID match, Inner Shareable
|
1111 | 000 | 1000 | 0111 | 011 | TLBIMVAA | TLB Invalidate by VA, All ASID |
000
|
011
|
1000
|
1111
|
0011
|
TLBIMVAAIS
|
TLB Invalidate by VA, All ASID, Inner Shareable
|
1111 | 000 | 1000 | 0111 | 101 | TLBIMVAL | TLB Invalidate by VA, Last level |
1001111
|
100000
|
1000
|
11110111
|
0011111
|
TLBIALLNSNHIS
TLBIMVAAL |
TLB Invalidate Allby VA, Non-SecureAll Non-HypASID, InnerLast Shareablelevel
|
000
|
101
|
1000
|
1111
|
0011
|
TLBIMVALIS
|
TLB Invalidate by VA, Last level, Inner Shareable
|
1111 | 000 | 1001 | 1100 | 000 | PMCR | Performance Monitors Control Register |
100
|
101
|
1000
|
1111
|
0011
|
TLBIMVALHIS
|
TLB Invalidate by VA, Last level, Hyp mode, Inner Shareable
|
1111 | 000 | 1001 | 1100 | 001 | PMCNTENSET | Performance Monitors Count Enable Set register |
000
|
111
|
1000
|
1111
|
0011
|
TLBIMVAALIS
|
TLB Invalidate by VA, All ASID, Last level, Inner Shareable
|
1111 | 000 | 1001 | 1100 | 010 | PMCNTENCLR | Performance Monitors Count Enable Clear register |
000
|
000
|
1010
|
1111
|
0011
|
AMAIR0
|
Auxiliary Memory Attribute Indirection Register 0
|
1111 | 000 | 1001 | 1100 | 011 | PMOVSR | Performance Monitors Overflow Flag Status Register |
100
|
000
|
1010
|
1111
|
0011
|
HAMAIR0
|
Hyp Auxiliary Memory Attribute Indirection Register 0
|
1111 | 000 | 1001 | 1100 | 100 | PMSWINC | Performance Monitors Software Increment register |
000
|
001
|
1010
|
1111
|
0011
|
AMAIR1
|
Auxiliary Memory Attribute Indirection Register 1
|
1111 | 000 | 1001 | 1100 | 101 | PMSELR | Performance Monitors Event Counter Selection Register |
100
|
001
|
1010
|
1111
|
0011
|
HAMAIR1
|
Hyp Auxiliary Memory Attribute Indirection Register 1
|
1111 | 000 | 1001 | 1100 | 110 | PMCEID0 | Performance Monitors Common Event Identification register 0 |
000
|
000
|
1110
|
1111
|
0011
|
CNTHV_TVAL
|
Counter-timer Virtual Timer TimerValue register (EL2)
|
1111 | 000 | 1001 | 1100 | 111 | PMCEID1 | Performance Monitors Common Event Identification register 1 |
000
|
000
|
1110
|
1111
|
0011
|
CNTV_TVAL
|
Counter-timer Virtual Timer TimerValue register
|
1111 | 000 | 1001 | 1101 | 000 | PMCCNTR | Performance Monitors Cycle Count Register |
000
|
001
|
1110
|
1111
|
0011
|
CNTHV_CTL
|
Counter-timer Virtual Timer Control register (EL2)
|
1111 | 000 | 1001 | 1101 | 001 | PMXEVTYPER | Performance Monitors Selected Event Type Register |
000
|
001
|
1110
|
1111
|
0011
|
CNTV_CTL
|
Counter-timer Virtual Timer Control register
|
1111 | 000 | 1001 | 1101 | 010 | PMXEVCNTR | Performance Monitors Selected Event Count Register |
000
|
100
|
0001
|
1110
|
0100
|
DBGPRCR
|
Debug Power Control Register
|
1111 | 000 | 1001 | 1110 | 000 | PMUSERENR | Performance Monitors User Enable Register |
000
|
000
|
0111
|
1111
|
0100
|
PAR
|
Physical Address Register
|
1111 | 000 | 1001 | 1110 | 001 | PMINTENSET | Performance Monitors Interrupt Enable Set register |
100
|
001
|
1000
|
1111
|
0100
|
TLBIIPAS2
|
TLB Invalidate by Intermediate Physical Address, Stage 2
|
1111 | 000 | 1001 | 1110 | 010 | PMINTENCLR | Performance Monitors Interrupt Enable Clear register |
100
|
101
|
1000
|
1111
|
0100
|
TLBIIPAS2L
|
TLB Invalidate by Intermediate Physical Address, Stage 2, Last level
|
1111 | 000 | 1001 | 1110 | 011 | PMOVSSET | Performance Monitors Overflow Flag Status Set register |
000
|
000
|
0000
|
1110
|
0101
|
DBGDTRRXint
|
Debug Data Transfer Register, Receive
|
1111 | 000 | 1001 | 1110 | 100 | PMCEID2 | Performance Monitors Common Event Identification register 2 |
000
|
000
|
0000
|
1110
|
0101
|
DBGDTRTXint
|
Debug Data Transfer Register, Transmit
|
1111 | 000 | 1001 | 1110 | 101 | PMCEID3 | Performance Monitors Common Event Identification register 3 |
0111111
|
000
|
01001010
|
11110010
|
0101000
|
DSPSR
PRRR |
DebugPrimary SavedRegion Program StatusRemap Register
|
011
|
001
|
0100
|
1111
|
0101
|
DLR
|
Debug Link Register
|
1111 | 000 | 1010 | 0010 | 000 | MAIR0 | Memory Attribute Indirection Register 0 |
000
|
000
|
0111
|
1111
|
0101
|
ICIALLU
|
Instruction Cache Invalidate All to PoU
|
1111 | 000 | 1010 | 0010 | 001 | NMRR | Normal Memory Remap Register |
000
|
001
|
0111
|
1111
|
0101
|
ICIMVAU
|
Instruction Cache line Invalidate by VA to PoU
|
1111 | 000 | 1010 | 0010 | 001 | MAIR1 | Memory Attribute Indirection Register 1 |
000
|
100
|
0111
|
1111
|
0101
|
CP15ISB
|
Instruction Synchronization Barrier System instruction
|
1111 | 000 | 1010 | 0011 | 000 | AMAIR0 | Auxiliary Memory Attribute Indirection Register 0 |
000
|
110
|
0111
|
1111
|
0101
|
BPIALL
|
Branch Predictor Invalidate All
|
1111 | 000 | 1010 | 0011 | 001 | AMAIR1 | Auxiliary Memory Attribute Indirection Register 1 |
000
|
111
|
0111
|
1111
|
0101
|
BPIMVA
|
Branch Predictor Invalidate by VA
|
1111 | 000 | 1100 | 0000 | 000 | VBAR | Vector Base Address Register |
000
|
000
|
1000
|
1111
|
0101
|
ITLBIALL
|
Instruction TLB Invalidate All
|
1111 | 000 | 1100 | 0000 | 001 | MVBAR | Monitor Vector Base Address Register |
000
|
001
|
1000
|
1111
|
0101
|
ITLBIMVA
|
Instruction TLB Invalidate by VA
|
1111 | 000 | 1100 | 0000 | 001 | RVBAR | Reset Vector Base Address Register |
000
|
010
|
1000
|
1111
|
0101
|
ITLBIASID
|
Instruction TLB Invalidate by ASID match
|
1111 | 000 | 1100 | 0000 | 010 | RMR | Reset Management Register |
000
|
000
|
0000
|
1110
|
0110
|
DBGWFAR
|
Debug Watchpoint Fault Address Register
|
1111 | 000 | 1100 | 0001 | 000 | ISR | Interrupt Status Register |
000
|
010
|
0000
|
1110
|
0110
|
DBGOSECCR
|
Debug OS Lock Exception Catch Control Register
|
1111 | 000 | 1100 | 1000 | 000 | ICC_IAR0 | Interrupt Controller Interrupt Acknowledge Register 0 |
000
|
000
|
0100
|
1111
|
0110
|
ICC_PMR
|
Interrupt Controller Interrupt Priority Mask Register
|
1111 | 000 | 1100 | 1000 | 000 | ICV_IAR0 | Interrupt Controller Virtual Interrupt Acknowledge Register 0 |
000
|
000
|
0100
|
1111
|
0110
|
ICV_PMR
|
Interrupt Controller Virtual Interrupt Priority Mask Register
|
1111 | 000 | 1100 | 1000 | 001 | ICC_EOIR0 | Interrupt Controller End Of Interrupt Register 0 |
000
|
001
|
0111
|
1111
|
0110
|
DCIMVAC
|
Data Cache line Invalidate by VA to PoC
|
1111 | 000 | 1100 | 1000 | 001 | ICV_EOIR0 | Interrupt Controller Virtual End Of Interrupt Register 0 |
000
|
010
|
0111
|
1111
|
0110
|
DCISW
|
Data Cache line Invalidate by Set/Way
|
1111 | 000 | 1100 | 1000 | 010 | ICC_HPPIR0 | Interrupt Controller Highest Priority Pending Interrupt Register 0 |
000
|
000
|
1000
|
1111
|
0110
|
DTLBIALL
|
Data TLB Invalidate All
|
1111 | 000 | 1100 | 1000 | 010 | ICV_HPPIR0 | Interrupt Controller Virtual Highest Priority Pending Interrupt Register 0 |
000
|
001
|
1000
|
1111
|
0110
|
DTLBIMVA
|
Data TLB Invalidate by VA
|
1111 | 000 | 1100 | 1000 | 011 | ICC_BPR0 | Interrupt Controller Binary Point Register 0 |
000
|
010
|
1000
|
1111
|
0110
|
DTLBIASID
|
Data TLB Invalidate by ASID match
|
1111 | 000 | 1100 | 1000 | 011 | ICV_BPR0 | Interrupt Controller Virtual Binary Point Register 0 |
000
|
000
|
0000
|
1110
|
0111
|
DBGVCR
|
Debug Vector Catch Register
|
1111 | 000 | 1100 | 1000 | 1xx | ICC_AP0R<n> | Interrupt Controller Active Priorities Group 0 Registers |
000
|
000
|
1000
|
1111
|
0111
|
TLBIALL
|
TLB Invalidate All
|
1111 | 000 | 1100 | 1000 | 1xx | ICV_AP0R<n> | Interrupt Controller Virtual Active Priorities Group 0 Registers |
1001111
|
000
|
10001100
|
11111001
|
01110xx
|
TLBIALLH
ICC_AP1R<n> |
TLBInterrupt InvalidateController All,Active HypPriorities modeGroup 1 Registers
|
000
|
001
|
1000
|
1111
|
0111
|
TLBIMVA
|
TLB Invalidate by VA
|
1111 | 000 | 1100 | 1001 | 0xx | ICV_AP1R<n> | Interrupt Controller Virtual Active Priorities Group 1 Registers |
100
|
001
|
1000
|
1111
|
0111
|
TLBIMVAH
|
TLB Invalidate by VA, Hyp mode
|
1111 | 000 | 1100 | 1011 | 001 | ICC_DIR | Interrupt Controller Deactivate Interrupt Register |
000
|
010
|
1000
|
1111
|
0111
|
TLBIASID
|
TLB Invalidate by ASID match
|
1111 | 000 | 1100 | 1011 | 001 | ICV_DIR | Interrupt Controller Deactivate Virtual Interrupt Register |
000
|
011
|
1000
|
1111
|
0111
|
TLBIMVAA
|
TLB Invalidate by VA, All ASID
|
1111 | 000 | 1100 | 1011 | 011 | ICC_RPR | Interrupt Controller Running Priority Register |
100
|
100
|
1000
|
1111
|
0111
|
TLBIALLNSNH
|
TLB Invalidate All, Non-Secure Non-Hyp
|
1111 | 000 | 1100 | 1011 | 011 | ICV_RPR | Interrupt Controller Virtual Running Priority Register |
000
|
101
|
1000
|
1111
|
0111
|
TLBIMVAL
|
TLB Invalidate by VA, Last level
|
1111 | 000 | 1100 | 1100 | 000 | ICC_IAR1 | Interrupt Controller Interrupt Acknowledge Register 1 |
100
|
101
|
1000
|
1111
|
0111
|
TLBIMVALH
|
TLB Invalidate by VA, Last level, Hyp mode
|
1111 | 000 | 1100 | 1100 | 000 | ICV_IAR1 | Interrupt Controller Virtual Interrupt Acknowledge Register 1 |
000
|
111
|
1000
|
1111
|
0111
|
TLBIMVAAL
|
TLB Invalidate by VA, All ASID, Last level
|
1111 | 000 | 1100 | 1100 | 001 | ICC_EOIR1 | Interrupt Controller End Of Interrupt Register 1 |
000
|
110
|
0111
|
1110
|
1000
|
DBGCLAIMSET
|
Debug Claim Tag Set register
|
1111 | 000 | 1100 | 1100 | 001 | ICV_EOIR1 | Interrupt Controller Virtual End Of Interrupt Register 1 |
000
|
000
|
0111
|
1111
|
1000
|
ATS1CPR
|
Address Translate Stage 1 Current state PL1 Read
|
1111 | 000 | 1100 | 1100 | 010 | ICC_HPPIR1 | Interrupt Controller Highest Priority Pending Interrupt Register 1 |
1001111
|
000
|
01111100
|
11111100
|
1000010
|
ATS1HR
ICV_HPPIR1 |
AddressInterrupt TranslateController StageVirtual 1Highest HypPriority modePending ReadInterrupt Register 1
|
000
|
001
|
0111
|
1111
|
1000
|
ATS1CPW
|
Address Translate Stage 1 Current state PL1 Write
|
1111 | 000 | 1100 | 1100 | 011 | ICC_BPR1 | Interrupt Controller Binary Point Register 1 |
100
|
001
|
0111
|
1111
|
1000
|
ATS1HW
|
Address Translate Stage 1 Hyp mode Write
|
1111 | 000 | 1100 | 1100 | 011 | ICV_BPR1 | Interrupt Controller Virtual Binary Point Register 1 |
000
|
010
|
0111
|
1111
|
1000
|
ATS1CUR
|
Address Translate Stage 1 Current state Unprivileged Read
|
1111 | 000 | 1100 | 1100 | 100 | ICC_CTLR | Interrupt Controller Control Register |
000
|
011
|
0111
|
1111
|
1000
|
ATS1CUW
|
Address Translate Stage 1 Current state Unprivileged Write
|
1111 | 000 | 1100 | 1100 | 100 | ICV_CTLR | Interrupt Controller Virtual Control Register |
000
|
100
|
0111
|
1111
|
1000
|
ATS12NSOPR
|
Address Translate Stages 1 and 2 Non-secure Only PL1 Read
|
1111 | 000 | 1100 | 1100 | 101 | ICC_SRE | Interrupt Controller System Register Enable register |
000
|
101
|
0111
|
1111
|
1000
|
ATS12NSOPW
|
Address Translate Stages 1 and 2 Non-secure Only PL1 Write
|
1111 | 000 | 1100 | 1100 | 110 | ICC_IGRPEN0 | Interrupt Controller Interrupt Group 0 Enable register |
000
|
110
|
0111
|
1111
|
1000
|
ATS12NSOUR
|
Address Translate Stages 1 and 2 Non-secure Only Unprivileged Read
|
1111 | 000 | 1100 | 1100 | 110 | ICV_IGRPEN0 | Interrupt Controller Virtual Interrupt Group 0 Enable register |
000
|
111
|
0111
|
1111
|
1000
|
ATS12NSOUW
|
Address Translate Stages 1 and 2 Non-secure Only Unprivileged Write
|
1111 | 000 | 1100 | 1100 | 111 | ICC_IGRPEN1 | Interrupt Controller Interrupt Group 1 Enable register |
000
|
000
|
1100
|
1111
|
1000
|
ICC_IAR0
|
Interrupt Controller Interrupt Acknowledge Register 0
|
1111 | 000 | 1100 | 1100 | 111 | ICV_IGRPEN1 | Interrupt Controller Virtual Interrupt Group 1 Enable register |
000
|
000
|
1100
|
1111
|
1000
|
ICV_IAR0
|
Interrupt Controller Virtual Interrupt Acknowledge Register 0
|
1111 | 000 | 1101 | 0000 | 000 | FCSEIDR | FCSE Process ID register |
000
|
001
|
1100
|
1111
|
1000
|
ICC_EOIR0
|
Interrupt Controller End Of Interrupt Register 0
|
1111 | 000 | 1101 | 0000 | 001 | CONTEXTIDR | Context ID Register |
000
|
001
|
1100
|
1111
|
1000
|
ICV_EOIR0
|
Interrupt Controller Virtual End Of Interrupt Register 0
|
1111 | 000 | 1101 | 0000 | 010 | TPIDRURW | PL0 Read/Write Software Thread ID Register |
000
|
010
|
1100
|
1111
|
1000
|
ICC_HPPIR0
|
Interrupt Controller Highest Priority Pending Interrupt Register 0
|
1111 | 000 | 1101 | 0000 | 011 | TPIDRURO | PL0 Read-Only Software Thread ID Register |
000
|
010
|
1100
|
1111
|
1000
|
ICV_HPPIR0
|
Interrupt Controller Virtual Highest Priority Pending Interrupt Register 0
|
1111 | 000 | 1101 | 0000 | 100 | TPIDRPRW | PL1 Software Thread ID Register |
000
|
011
|
1100
|
1111
|
1000
|
ICC_BPR0
|
Interrupt Controller Binary Point Register 0
|
1111 | 000 | 1110 | 0000 | 000 | CNTFRQ | Counter-timer Frequency register |
000
|
011
|
1100
|
1111
|
1000
|
ICV_BPR0
|
Interrupt Controller Virtual Binary Point Register 0
|
1111 | 000 | 1110 | 0001 | 000 | CNTKCTL | Counter-timer Kernel Control register |
100
|
0xx
|
1100
|
1111
|
1000
|
ICH_AP0R<n>
|
Interrupt Controller Hyp Active Priorities Group 0 Registers
|
1111 | 000 | 1110 | 0010 | 000 | CNTP_TVAL | Counter-timer Physical Timer TimerValue register |
000
|
1xx
|
1100
|
1111
|
1000
|
ICC_AP0R<n>
|
Interrupt Controller Active Priorities Group 0 Registers
|
1111 | 000 | 1110 | 0010 | 001 | CNTP_CTL | Counter-timer Physical Timer Control register |
000
|
1xx
|
1100
|
1111
|
1000
|
ICV_AP0R<n>
|
Interrupt Controller Virtual Active Priorities Group 0 Registers
|
1111 | 000 | 1110 | 0011 | 000 | CNTV_TVAL | Counter-timer Virtual Timer TimerValue register |
000
|
110
|
0111
|
1110
|
1001
|
DBGCLAIMCLR
|
Debug Claim Tag Clear register
|
1111 | 000 | 1110 | 0011 | 001 | CNTV_CTL | Counter-timer Virtual Timer Control register |
000
|
000
|
0111
|
1111
|
1001
|
ATS1CPRP
|
Address Translate Stage 1 Current state PL1 Read PAN
|
1111 | 000 | 1110 | 10xx | xxx | PMEVCNTR<n> | Performance Monitors Event Count Registers |
000
|
001
|
0111
|
1111
|
1001
|
ATS1CPWP
|
Address Translate Stage 1 Current state PL1 Write PAN
|
1111 | 000 | 1110 | 1111 | 111 | PMCCFILTR | Performance Monitors Cycle Count Filter Register |
100
|
101
|
1100
|
1111
|
1001
|
ICC_HSRE
|
Interrupt Controller Hyp System Register Enable register
|
1111 | 000 | 1110 | 11xx | xxx | PMEVTYPER<n> | Performance Monitors Event Type Registers |
000
|
0xx
|
1100
|
1111
|
1001
|
ICC_AP1R<n>
|
Interrupt Controller Active Priorities Group 1 Registers
|
1111 | 001 | 0000 | 0000 | 000 | CCSIDR | Current Cache Size ID Register |
000
|
0xx
|
1100
|
1111
|
1001
|
ICV_AP1R<n>
|
Interrupt Controller Virtual Active Priorities Group 1 Registers
|
1111 | 001 | 0000 | 0000 | 001 | CLIDR | Cache Level ID Register |
100
|
0xx
|
1100
|
1111
|
1001
|
ICH_AP1R<n>
|
Interrupt Controller Hyp Active Priorities Group 1 Registers
|
1111 | 001 | 0000 | 0000 | 010 | CCSIDR2 | Current Cache Size ID Register 2 |
0001111
|
001
|
01110000
|
11110000
|
1010111
|
DCCMVAC
AIDR |
DataAuxiliary CacheID line Clean by VA to PoCRegister
|
000
|
010
|
0111
|
1111
|
1010
|
DCCSW
|
Data Cache line Clean by Set/Way
|
1111 | 010 | 0000 | 0000 | 000 | CSSELR | Cache Size Selection Register |
000
|
100
|
0111
|
1111
|
1010
|
CP15DSB
|
Data Synchronization Barrier System instruction
|
1111 | 011 | 0100 | 0101 | 000 | DSPSR | Debug Saved Program Status Register |
000
|
101
|
0111
|
1111
|
1010
|
CP15DMB
|
Data Memory Barrier System instruction
|
1111 | 011 | 0100 | 0101 | 001 | DLR | Debug Link Register |
000
|
001
|
0111
|
1111
|
1011
|
DCCMVAU
|
Data Cache line Clean by VA to PoU
|
1111 | 100 | 0000 | 0000 | 000 | VPIDR | Virtualization Processor ID Register |
100
|
000
|
1100
|
1111
|
1011
|
ICH_HCR
|
Interrupt Controller Hyp Control Register
|
1111 | 100 | 0000 | 0000 | 101 | VMPIDR | Virtualization Multiprocessor ID Register |
000
|
001
|
1100
|
1111
|
1011
|
ICC_DIR
|
Interrupt Controller Deactivate Interrupt Register
|
1111 | 100 | 0001 | 0000 | 000 | HSCTLR | Hyp System Control Register |
000
|
001
|
1100
|
1111
|
1011
|
ICV_DIR
|
Interrupt Controller Deactivate Virtual Interrupt Register
|
1111 | 100 | 0001 | 0000 | 001 | HACTLR | Hyp Auxiliary Control Register |
100
|
001
|
1100
|
1111
|
1011
|
ICH_VTR
|
Interrupt Controller VGIC Type Register
|
1111 | 100 | 0001 | 0000 | 011 | HACTLR2 | Hyp Auxiliary Control Register 2 |
100
|
010
|
1100
|
1111
|
1011
|
ICH_MISR
|
Interrupt Controller Maintenance Interrupt State Register
|
1111 | 100 | 0001 | 0001 | 000 | HCR | Hyp Configuration Register |
000
|
011
|
1100
|
1111
|
1011
|
ICC_RPR
|
Interrupt Controller Running Priority Register
|
1111 | 100 | 0001 | 0001 | 001 | HDCR | Hyp Debug Control Register |
000
|
011
|
1100
|
1111
|
1011
|
ICV_RPR
|
Interrupt Controller Virtual Running Priority Register
|
1111 | 100 | 0001 | 0001 | 010 | HCPTR | Hyp Architectural Feature Trap Register |
100
|
011
|
1100
|
1111
|
1011
|
ICH_EISR
|
Interrupt Controller End of Interrupt Status Register
|
1111 | 100 | 0001 | 0001 | 011 | HSTR | Hyp System Trap Register |
100
|
101
|
1100
|
1111
|
1011
|
ICH_ELRSR
|
Interrupt Controller Empty List Register Status Register
|
1111 | 100 | 0001 | 0001 | 100 | HCR2 | Hyp Configuration Register 2 |
100
|
111
|
1100
|
1111
|
1011
|
ICH_VMCR
|
Interrupt Controller Virtual Machine Control Register
|
1111 | 100 | 0001 | 0001 | 111 | HACR | Hyp Auxiliary Configuration Register |
000
|
000
|
1001
|
1111
|
1100
|
PMCR
|
Performance Monitors Control Register
|
1111 | 100 | 0010 | 0000 | 010 | HTCR | Hyp Translation Control Register |
000
|
001
|
1001
|
1111
|
1100
|
PMCNTENSET
|
Performance Monitors Count Enable Set register
|
1111 | 100 | 0010 | 0001 | 010 | VTCR | Virtualization Translation Control Register |
000
|
010
|
1001
|
1111
|
1100
|
PMCNTENCLR
|
Performance Monitors Count Enable Clear register
|
1111 | 100 | 0101 | 0001 | 000 | HADFSR | Hyp Auxiliary Data Fault Status Register |
000
|
011
|
1001
|
1111
|
1100
|
PMOVSR
|
Performance Monitors Overflow Flag Status Register
|
1111 | 100 | 0101 | 0001 | 001 | HAIFSR | Hyp Auxiliary Instruction Fault Status Register |
000
|
100
|
1001
|
1111
|
1100
|
PMSWINC
|
Performance Monitors Software Increment register
|
1111 | 100 | 0101 | 0010 | 000 | HSR | Hyp Syndrome Register |
000
|
101
|
1001
|
1111
|
1100
|
PMSELR
|
Performance Monitors Event Counter Selection Register
|
1111 | 100 | 0110 | 0000 | 000 | HDFAR | Hyp Data Fault Address Register |
000
|
110
|
1001
|
1111
|
1100
|
PMCEID0
|
Performance Monitors Common Event Identification register 0
|
1111 | 100 | 0110 | 0000 | 010 | HIFAR | Hyp Instruction Fault Address Register |
000
|
111
|
1001
|
1111
|
1100
|
PMCEID1
|
Performance Monitors Common Event Identification register 1
|
1111 | 100 | 0110 | 0000 | 100 | HPFAR | Hyp IPA Fault Address Register |
000
|
000
|
1100
|
1111
|
1100
|
ICC_IAR1
|
Interrupt Controller Interrupt Acknowledge Register 1
|
1111 | 100 | 0111 | 1000 | 000 | ATS1HR | Address Translate Stage 1 Hyp mode Read |
000
|
000
|
1100
|
1111
|
1100
|
ICV_IAR1
|
Interrupt Controller Virtual Interrupt Acknowledge Register 1
|
1111 | 100 | 0111 | 1000 | 001 | ATS1HW | Address Translate Stage 1 Hyp mode Write |
000
|
001
|
1100
|
1111
|
1100
|
ICC_EOIR1
|
Interrupt Controller End Of Interrupt Register 1
|
1111 | 100 | 1000 | 0000 | 001 | TLBIIPAS2IS | TLB Invalidate by Intermediate Physical Address, Stage 2, Inner Shareable |
000
|
001
|
1100
|
1111
|
1100
|
ICV_EOIR1
|
Interrupt Controller Virtual End Of Interrupt Register 1
|
1111 | 100 | 1000 | 0000 | 101 | TLBIIPAS2LIS | TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, Inner Shareable |
000
|
010
|
1100
|
1111
|
1100
|
ICC_HPPIR1
|
Interrupt Controller Highest Priority Pending Interrupt Register 1
|
1111 | 100 | 1000 | 0011 | 000 | TLBIALLHIS | TLB Invalidate All, Hyp mode, Inner Shareable |
000
|
010
|
1100
|
1111
|
1100
|
ICV_HPPIR1
|
Interrupt Controller Virtual Highest Priority Pending Interrupt Register 1
|
1111 | 100 | 1000 | 0011 | 001 | TLBIMVAHIS | TLB Invalidate by VA, Hyp mode, Inner Shareable |
000
|
011
|
1100
|
1111
|
1100
|
ICC_BPR1
|
Interrupt Controller Binary Point Register 1
|
1111 | 100 | 1000 | 0011 | 100 | TLBIALLNSNHIS | TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable |
000
|
011
|
1100
|
1111
|
1100
|
ICV_BPR1
|
Interrupt Controller Virtual Binary Point Register 1
|
1111 | 100 | 1000 | 0011 | 101 | TLBIMVALHIS | TLB Invalidate by VA, Last level, Hyp mode, Inner Shareable |
0001111
|
100
|
11001000
|
11110100
|
1100001
|
ICC_CTLR
TLBIIPAS2 |
InterruptTLB ControllerInvalidate Controlby RegisterIntermediate Physical Address, Stage 2
|
0001111
|
100
|
11001000
|
11110100
|
1100101
|
ICV_CTLR
TLBIIPAS2L |
InterruptTLB ControllerInvalidate Virtualby ControlIntermediate RegisterPhysical Address, Stage 2, Last level
|
1101111
|
100
|
11001000
|
11110111
|
1100000
|
ICC_MCTLR
TLBIALLH |
InterruptTLB ControllerInvalidate MonitorAll, ControlHyp Registermode
|
000
|
101
|
1100
|
1111
|
1100
|
ICC_SRE
|
Interrupt Controller System Register Enable register
|
1111 | 100 | 1000 | 0111 | 001 | TLBIMVAH | TLB Invalidate by VA, Hyp mode |
110
|
101
|
1100
|
1111
|
1100
|
ICC_MSRE
|
Interrupt Controller Monitor System Register Enable register
|
1111 | 100 | 1000 | 0111 | 100 | TLBIALLNSNH | TLB Invalidate All, Non-Secure Non-Hyp |
000
|
110
|
1100
|
1111
|
1100
|
ICC_IGRPEN0
|
Interrupt Controller Interrupt Group 0 Enable register
|
1111 | 100 | 1000 | 0111 | 101 | TLBIMVALH | TLB Invalidate by VA, Last level, Hyp mode |
000
|
110
|
1100
|
1111
|
1100
|
ICV_IGRPEN0
|
Interrupt Controller Virtual Interrupt Group 0 Enable register
|
1111 | 100 | 1010 | 0010 | 000 | HMAIR0 | Hyp Memory Attribute Indirection Register 0 |
000
|
111
|
1100
|
1111
|
1100
|
ICC_IGRPEN1
|
Interrupt Controller Interrupt Group 1 Enable register
|
1111 | 100 | 1010 | 0010 | 001 | HMAIR1 | Hyp Memory Attribute Indirection Register 1 |
000
|
111
|
1100
|
1111
|
1100
|
ICV_IGRPEN1
|
Interrupt Controller Virtual Interrupt Group 1 Enable register
|
1111 | 100 | 1010 | 0011 | 000 | HAMAIR0 | Hyp Auxiliary Memory Attribute Indirection Register 0 |
110
|
111
|
1100
|
1111
|
1100
|
ICC_MGRPEN1
|
Interrupt Controller Monitor Interrupt Group 1 Enable register
|
1111 | 100 | 1010 | 0011 | 001 | HAMAIR1 | Hyp Auxiliary Memory Attribute Indirection Register 1 |
000
|
000
|
1001
|
1111
|
1101
|
PMCCNTR
|
Performance Monitors Cycle Count Register
|
1111 | 100 | 1100 | 0000 | 000 | HVBAR | Hyp Vector Base Address Register |
000
|
001
|
1001
|
1111
|
1101
|
PMXEVTYPER
|
Performance Monitors Selected Event Type Register
|
1111 | 100 | 1100 | 0000 | 010 | HRMR | Hyp Reset Management Register |
000
|
010
|
1001
|
1111
|
1101
|
PMXEVCNTR
|
Performance Monitors Selected Event Count Register
|
1111 | 100 | 1100 | 1000 | 0xx | ICH_AP0R<n> | Interrupt Controller Hyp Active Priorities Group 0 Registers |
0001111
|
110100
|
01111100
|
11101001
|
11100xx
|
DBGAUTHSTATUS
ICH_AP1R<n> |
DebugInterrupt AuthenticationController StatusHyp registerActive Priorities Group 1 Registers
|
000
|
001
|
0111
|
1111
|
1110
|
DCCIMVAC
|
Data Cache line Clean and Invalidate by VA to PoC
|
1111 | 100 | 1100 | 1001 | 101 | ICC_HSRE | Interrupt Controller Hyp System Register Enable register |
000
|
010
|
0111
|
1111
|
1110
|
DCCISW
|
Data Cache line Clean and Invalidate by Set/Way
|
1111 | 100 | 1100 | 1011 | 000 | ICH_HCR | Interrupt Controller Hyp Control Register |
000
|
000
|
1001
|
1111
|
1110
|
PMUSERENR
|
Performance Monitors User Enable Register
|
1111 | 100 | 1100 | 1011 | 001 | ICH_VTR | Interrupt Controller VGIC Type Register |
000
|
001
|
1001
|
1111
|
1110
|
PMINTENSET
|
Performance Monitors Interrupt Enable Set register
|
1111 | 100 | 1100 | 1011 | 010 | ICH_MISR | Interrupt Controller Maintenance Interrupt State Register |
000
|
010
|
1001
|
1111
|
1110
|
PMINTENCLR
|
Performance Monitors Interrupt Enable Clear register
|
1111 | 100 | 1100 | 1011 | 011 | ICH_EISR | Interrupt Controller End of Interrupt Status Register |
000
|
011
|
1001
|
1111
|
1110
|
PMOVSSET
|
Performance Monitors Overflow Flag Status Set register
|
1111 | 100 | 1100 | 1011 | 101 | ICH_ELRSR | Interrupt Controller Empty List Register Status Register |
0001111
|
100
|
10011100
|
11111011
|
1110111
|
PMCEID2
ICH_VMCR |
PerformanceInterrupt MonitorsController CommonVirtual EventMachine IdentificationControl register 2Register
|
000
|
101
|
1001
|
1111
|
1110
|
PMCEID3
|
Performance Monitors Common Event Identification register 3
|
1111 | 100 | 1100 | 110x | xxx | ICH_LR<n> | Interrupt Controller List Registers |
000
|
111
|
1110
|
1111
|
1111
|
PMCCFILTR
|
Performance Monitors Cycle Count Filter Register
|
1111 | 100 | 1100 | 111x | xxx | ICH_LRC<n> | Interrupt Controller List Registers |
000
|
xxx
|
1110
|
1111
|
10xx
|
PMEVCNTR<n>
|
Performance Monitors Event Count Registers
|
1111 | 100 | 1101 | 0000 | 010 | HTPIDR | Hyp Software Thread ID Register |
100
|
xxx
|
1100
|
1111
|
110x
|
ICH_LR<n>
|
Interrupt Controller List Registers
|
1111 | 100 | 1110 | 0001 | 000 | CNTHCTL | Counter-timer Hyp Control register |
100
|
xxx
|
1100
|
1111
|
111x
|
ICH_LRC<n>
|
Interrupt Controller List Registers
|
1111 | 100 | 1110 | 0010 | 000 | CNTHP_TVAL | Counter-timer Hyp Physical Timer TimerValue register |
0001111
|
xxx100
|
1110
|
11110010
|
11xx001
|
PMEVTYPER<n>
CNTHP_CTL |
PerformanceCounter-timer MonitorsHyp EventPhysical TypeTimer RegistersControl register
|
000
|
100
|
0000
|
1110
|
xxxx
|
DBGBVR<n>
|
Debug Breakpoint Value Registers
|
1111 | 110 | 1100 | 1100 | 100 | ICC_MCTLR | Interrupt Controller Monitor Control Register |
000
|
101
|
0000
|
1110
|
xxxx
|
DBGBCR<n>
|
Debug Breakpoint Control Registers
|
1111 | 110 | 1100 | 1100 | 101 | ICC_MSRE | Interrupt Controller Monitor System Register Enable register |
0001111
|
110
|
00001100
|
11101100
|
xxxx111
|
DBGWVR<n>
ICC_MGRPEN1 |
DebugInterrupt WatchpointController ValueMonitor RegistersInterrupt Group 1 Enable register
|
000
|
111
|
0000
|
1110
|
xxxx
|
DBGWCR<n>
|
Debug Watchpoint Control Registers
|
000
|
001
|
0001
|
1110
|
xxxx
|
DBGBXVR<n>
|
Debug Breakpoint Extended Value Registers
|