System Register index by instruction and encoding

Below are indexes for registers and operations accessed in the following ways:

For AArch32

For AArch64

Registers and operations in AArch32

Accessed using MCR/MRC:

Register selectors Name Description
opc1 opc2 CRn coproc CRm
000 000 0000 1110 0000 DBGDIDR Debug ID Register
111 000 0000 1110 0000 JIDR Jazelle ID Register
000 010 0000 1110 0000 DBGDTRRXext Debug OS Lock Data Transfer Register, Receive, External View
000 000 0001 1110 0000 DBGDRAR Debug ROM Address Register
111 000 0001 1110 0000 JOSCR Jazelle OS Control Register
000 100 0001 1110 0000 DBGOSLAR Debug OS Lock Access Register
000 000 0010 1110 0000 DBGDSAR Debug Self Address Register
111 000 0010 1110 0000 JMCR Jazelle Main Configuration Register
000 111 0111 1110 0000 DBGDEVID2 Debug Device ID register 2
000 000 0000 1111 0000 MIDR Main ID Register
001 000 0000 1111 0000 CCSIDR Current Cache Size ID Register
010 000 0000 1111 0000 CSSELR Cache Size Selection Register
100 000 0000 1111 0000 VPIDR Virtualization Processor ID Register
000 001 0000 1111 0000 CTR Cache Type Register
001 001 0000 1111 0000 CLIDR Cache Level ID Register
000 010 0000 1111 0000 TCMTR TCM Type Register
001 010 0000 1111 0000 CCSIDR2 Current Cache Size ID Register 2
000 011 0000 1111 0000 TLBTR TLB Type Register
000 101 0000 1111 0000 MPIDR Multiprocessor Affinity Register
100 101 0000 1111 0000 VMPIDR Virtualization Multiprocessor ID Register
000 110 0000 1111 0000 REVIDR Revision ID Register
001 111 0000 1111 0000 AIDR Auxiliary ID Register
000 000 0001 1111 0000 SCTLR System Control Register
100 000 0001 1111 0000 HSCTLR Hyp System Control Register
000 001 0001 1111 0000 ACTLR Auxiliary Control Register
100 001 0001 1111 0000 HACTLR Hyp Auxiliary Control Register
000 010 0001 1111 0000 CPACR Architectural Feature Access Control Register
000 011 0001 1111 0000 ACTLR2 Auxiliary Control Register 2
100 011 0001 1111 0000 HACTLR2 Hyp Auxiliary Control Register 2
000 000 0010 1111 0000 TTBR0 Translation Table Base Register 0
000 001 0010 1111 0000 TTBR1 Translation Table Base Register 1
000 010 0010 1111 0000 TTBCR Translation Table Base Control Register
100 010 0010 1111 0000 HTCR Hyp Translation Control Register
000 011 0010 1111 0000 TTBCR2 Translation Table Base Control Register 2
000 000 0011 1111 0000 DACR Domain Access Control Register
000 000 0101 1111 0000 DFSR Data Fault Status Register
000 001 0101 1111 0000 IFSR Instruction Fault Status Register
000 000 0110 1111 0000 DFAR Data Fault Address Register
100 000 0110 1111 0000 HDFAR Hyp Data Fault Address Register
000 010 0110 1111 0000 IFAR Instruction Fault Address Register
100 010 0110 1111 0000 HIFAR Hyp Instruction Fault Address Register
100 100 0110 1111 0000 HPFAR Hyp IPA Fault Address Register
100 001 1000 1111 0000 TLBIIPAS2IS TLB Invalidate by Intermediate Physical Address, Stage 2, Inner Shareable
100 101 1000 1111 0000 TLBIIPAS2LIS TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, Inner Shareable
000 000 1100 1111 0000 VBAR Vector Base Address Register
100 000 1100 1111 0000 HVBAR Hyp Vector Base Address Register
000 001 1100 1111 0000 MVBAR Monitor Vector Base Address Register
000 001 1100 1111 0000 RVBAR Reset Vector Base Address Register
000 010 1100 1111 0000 RMR Reset Management Register
100 010 1100 1111 0000 HRMR Hyp Reset Management Register
000 000 1101 1111 0000 FCSEIDR FCSE Process ID register
000 001 1101 1111 0000 CONTEXTIDR Context ID Register
000 010 1101 1111 0000 TPIDRURW PL0 Read/Write Software Thread ID Register
100 010 1101 1111 0000 HTPIDR Hyp Software Thread ID Register
000 011 1101 1111 0000 TPIDRURO PL0 Read-Only Software Thread ID Register
000 100 1101 1111 0000 TPIDRPRW PL1 Software Thread ID Register
000 000 1110 1111 0000 CNTFRQ Counter-timer Frequency register
000 000 0000 1110 0001 DBGDSCRint Debug Status and Control Register, Internal View
000 100 0001 1110 0001 DBGOSLSR Debug OS Lock Status Register
000 111 0111 1110 0001 DBGDEVID1 Debug Device ID register 1
000 000 0000 1111 0001 ID_PFR0 Processor Feature Register 0
000 001 0000 1111 0001 ID_PFR1 Processor Feature Register 1
000 010 0000 1111 0001 ID_DFR0 Debug Feature Register 0
000 011 0000 1111 0001 ID_AFR0 Auxiliary Feature Register 0
000 100 0000 1111 0001 ID_MMFR0 Memory Model Feature Register 0
000 101 0000 1111 0001 ID_MMFR1 Memory Model Feature Register 1
000 110 0000 1111 0001 ID_MMFR2 Memory Model Feature Register 2
000 111 0000 1111 0001 ID_MMFR3 Memory Model Feature Register 3
000 000 0001 1111 0001 SCR Secure Configuration Register
100 000 0001 1111 0001 HCR Hyp Configuration Register
000 001 0001 1111 0001 SDER Secure Debug Enable Register
100 001 0001 1111 0001 HDCR Hyp Debug Control Register
000 010 0001 1111 0001 NSACR Non-Secure Access Control Register
100 010 0001 1111 0001 HCPTR Hyp Architectural Feature Trap Register
100 011 0001 1111 0001 HSTR Hyp System Trap Register
100 100 0001 1111 0001 HCR2 Hyp Configuration Register 2
100 111 0001 1111 0001 HACR Hyp Auxiliary Configuration Register
100 010 0010 1111 0001 VTCR Virtualization Translation Control Register
000 000 0101 1111 0001 ADFSR Auxiliary Data Fault Status Register
100 000 0101 1111 0001 HADFSR Hyp Auxiliary Data Fault Status Register
000 001 0101 1111 0001 AIFSR Auxiliary Instruction Fault Status Register
100 001 0101 1111 0001 HAIFSR Hyp Auxiliary Instruction Fault Status Register
000 000 0111 1111 0001 ICIALLUIS Instruction Cache Invalidate All to PoU, Inner Shareable
000 110 0111 1111 0001 BPIALLIS Branch Predictor Invalidate All, Inner Shareable
000 000 1100 1111 0001 ISR Interrupt Status Register
000 000 1110 1111 0001 CNTKCTL Counter-timer Kernel Control register
100 000 1110 1111 0001 CNTHCTL Counter-timer Hyp Control register
000 000 0000 1110 0010 DBGDCCINT DCC Interrupt Enable Register
000 010 0000 1110 0010 DBGDSCRext Debug Status and Control Register, External View
000 111 0111 1110 0010 DBGDEVID Debug Device ID register 0
000 000 0000 1111 0010 ID_ISAR0 Instruction Set Attribute Register 0
000 001 0000 1111 0010 ID_ISAR1 Instruction Set Attribute Register 1
000 010 0000 1111 0010 ID_ISAR2 Instruction Set Attribute Register 2
000 011 0000 1111 0010 ID_ISAR3 Instruction Set Attribute Register 3
000 100 0000 1111 0010 ID_ISAR4 Instruction Set Attribute Register 4
000 101 0000 1111 0010 ID_ISAR5 Instruction Set Attribute Register 5
000 110 0000 1111 0010 ID_MMFR4 Memory Model Feature Register 4
000 111 0000 1111 0010 ID_ISAR6 Instruction Set Attribute Register 6
100 000 0101 1111 0010 HSR Hyp Syndrome Register
000 000 1010 1111 0010 MAIR0 Memory Attribute Indirection Register 0
000 000 1010 1111 0010 PRRR Primary Region Remap Register
100 000 1010 1111 0010 HMAIR0 Hyp Memory Attribute Indirection Register 0
000 001 1010 1111 0010 MAIR1 Memory Attribute Indirection Register 1
000 001 1010 1111 0010 NMRR Normal Memory Remap Register
100 001 1010 1111 0010 HMAIR1 Hyp Memory Attribute Indirection Register 1
000 000 1110 1111 0010 CNTP_TVAL Counter-timer Physical Timer TimerValue register
100 000 1110 1111 0010 CNTHP_TVAL Counter-timer Hyp Physical Timer TimerValue register
000 001 1110 1111 0010 CNTP_CTL Counter-timer Physical Timer Control register
100 001 1110 1111 0010 CNTHP_CTL Counter-timer Hyp Physical Timer Control register
000 010 0000 1110 0011 DBGDTRTXext Debug OS Lock Data Transfer Register, Transmit
000 100 0001 1110 0011 DBGOSDLR Debug OS Double Lock Register
000 001 0001 1111 0011 SDCR Secure Debug Control Register
000 000 1000 1111 0011 TLBIALLIS TLB Invalidate All, Inner Shareable
100 000 1000 1111 0011 TLBIALLHIS TLB Invalidate All, Hyp mode, Inner Shareable
000 001 1000 1111 0011 TLBIMVAIS TLB Invalidate by VA, Inner Shareable
100 001 1000 1111 0011 TLBIMVAHIS TLB Invalidate by VA, Hyp mode, Inner Shareable
000 010 1000 1111 0011 TLBIASIDIS TLB Invalidate by ASID match, Inner Shareable
000 011 1000 1111 0011 TLBIMVAAIS TLB Invalidate by VA, All ASID, Inner Shareable
100 100 1000 1111 0011 TLBIALLNSNHIS TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
000 101 1000 1111 0011 TLBIMVALIS TLB Invalidate by VA, Last level, Inner Shareable
100 101 1000 1111 0011 TLBIMVALHIS TLB Invalidate by VA, Last level, Hyp mode, Inner Shareable
000 111 1000 1111 0011 TLBIMVAALIS TLB Invalidate by VA, All ASID, Last level, Inner Shareable
000 000 1010 1111 0011 AMAIR0 Auxiliary Memory Attribute Indirection Register 0
100 000 1010 1111 0011 HAMAIR0 Hyp Auxiliary Memory Attribute Indirection Register 0
000 001 1010 1111 0011 AMAIR1 Auxiliary Memory Attribute Indirection Register 1
100 001 1010 1111 0011 HAMAIR1 Hyp Auxiliary Memory Attribute Indirection Register 1
000 000 1110 1111 0011 CNTHV_TVAL Counter-timer Virtual Timer TimerValue register (EL2)
000 000 1110 1111 0011 CNTV_TVAL Counter-timer Virtual Timer TimerValue register
000 001 1110 1111 0011 CNTHV_CTL Counter-timer Virtual Timer Control register (EL2)
000 001 1110 1111 0011 CNTV_CTL Counter-timer Virtual Timer Control register
000 100 0001 1110 0100 DBGPRCR Debug Power Control Register
000 000 0111 1111 0100 PAR Physical Address Register
100 001 1000 1111 0100 TLBIIPAS2 TLB Invalidate by Intermediate Physical Address, Stage 2
100 101 1000 1111 0100 TLBIIPAS2L TLB Invalidate by Intermediate Physical Address, Stage 2, Last level
000 000 0000 1110 0101 DBGDTRRXint Debug Data Transfer Register, Receive
000 000 0000 1110 0101 DBGDTRTXint Debug Data Transfer Register, Transmit
011 000 0100 1111 0101 DSPSR Debug Saved Program Status Register
011 001 0100 1111 0101 DLR Debug Link Register
000 000 0111 1111 0101 ICIALLU Instruction Cache Invalidate All to PoU
000 001 0111 1111 0101 ICIMVAU Instruction Cache line Invalidate by VA to PoU
000 100 0111 1111 0101 CP15ISB Instruction Synchronization Barrier System instruction
000 110 0111 1111 0101 BPIALL Branch Predictor Invalidate All
000 111 0111 1111 0101 BPIMVA Branch Predictor Invalidate by VA
000 000 1000 1111 0101 ITLBIALL Instruction TLB Invalidate All
000 001 1000 1111 0101 ITLBIMVA Instruction TLB Invalidate by VA
000 010 1000 1111 0101 ITLBIASID Instruction TLB Invalidate by ASID match
000 000 0000 1110 0110 DBGWFAR Debug Watchpoint Fault Address Register
000 010 0000 1110 0110 DBGOSECCR Debug OS Lock Exception Catch Control Register
000 000 0100 1111 0110 ICC_PMR Interrupt Controller Interrupt Priority Mask Register
000 000 0100 1111 0110 ICV_PMR Interrupt Controller Virtual Interrupt Priority Mask Register
000 001 0111 1111 0110 DCIMVAC Data Cache line Invalidate by VA to PoC
000 010 0111 1111 0110 DCISW Data Cache line Invalidate by Set/Way
000 000 1000 1111 0110 DTLBIALL Data TLB Invalidate All
000 001 1000 1111 0110 DTLBIMVA Data TLB Invalidate by VA
000 010 1000 1111 0110 DTLBIASID Data TLB Invalidate by ASID match
000 000 0000 1110 0111 DBGVCR Debug Vector Catch Register
000 000 1000 1111 0111 TLBIALL TLB Invalidate All
100 000 1000 1111 0111 TLBIALLH TLB Invalidate All, Hyp mode
000 001 1000 1111 0111 TLBIMVA TLB Invalidate by VA
100 001 1000 1111 0111 TLBIMVAH TLB Invalidate by VA, Hyp mode
000 010 1000 1111 0111 TLBIASID TLB Invalidate by ASID match
000 011 1000 1111 0111 TLBIMVAA TLB Invalidate by VA, All ASID
100 100 1000 1111 0111 TLBIALLNSNH TLB Invalidate All, Non-Secure Non-Hyp
000 101 1000 1111 0111 TLBIMVAL TLB Invalidate by VA, Last level
100 101 1000 1111 0111 TLBIMVALH TLB Invalidate by VA, Last level, Hyp mode
000 111 1000 1111 0111 TLBIMVAAL TLB Invalidate by VA, All ASID, Last level
000 110 0111 1110 1000 DBGCLAIMSET Debug Claim Tag Set register
000 000 0111 1111 1000 ATS1CPR Address Translate Stage 1 Current state PL1 Read
100 000 0111 1111 1000 ATS1HR Address Translate Stage 1 Hyp mode Read
000 001 0111 1111 1000 ATS1CPW Address Translate Stage 1 Current state PL1 Write
100 001 0111 1111 1000 ATS1HW Address Translate Stage 1 Hyp mode Write
000 010 0111 1111 1000 ATS1CUR Address Translate Stage 1 Current state Unprivileged Read
000 011 0111 1111 1000 ATS1CUW Address Translate Stage 1 Current state Unprivileged Write
000 100 0111 1111 1000 ATS12NSOPR Address Translate Stages 1 and 2 Non-secure Only PL1 Read
000 101 0111 1111 1000 ATS12NSOPW Address Translate Stages 1 and 2 Non-secure Only PL1 Write
000 110 0111 1111 1000 ATS12NSOUR Address Translate Stages 1 and 2 Non-secure Only Unprivileged Read
000 111 0111 1111 1000 ATS12NSOUW Address Translate Stages 1 and 2 Non-secure Only Unprivileged Write
000 000 1100 1111 1000 ICC_IAR0 Interrupt Controller Interrupt Acknowledge Register 0
000 000 1100 1111 1000 ICV_IAR0 Interrupt Controller Virtual Interrupt Acknowledge Register 0
000 001 1100 1111 1000 ICC_EOIR0 Interrupt Controller End Of Interrupt Register 0
000 001 1100 1111 1000 ICV_EOIR0 Interrupt Controller Virtual End Of Interrupt Register 0
000 010 1100 1111 1000 ICC_HPPIR0 Interrupt Controller Highest Priority Pending Interrupt Register 0
000 010 1100 1111 1000 ICV_HPPIR0 Interrupt Controller Virtual Highest Priority Pending Interrupt Register 0
000 011 1100 1111 1000 ICC_BPR0 Interrupt Controller Binary Point Register 0
000 011 1100 1111 1000 ICV_BPR0 Interrupt Controller Virtual Binary Point Register 0
100 0xx 1100 1111 1000 ICH_AP0R<n> Interrupt Controller Hyp Active Priorities Group 0 Registers
000 1xx 1100 1111 1000 ICC_AP0R<n> Interrupt Controller Active Priorities Group 0 Registers
000 1xx 1100 1111 1000 ICV_AP0R<n> Interrupt Controller Virtual Active Priorities Group 0 Registers
000 110 0111 1110 1001 DBGCLAIMCLR Debug Claim Tag Clear register
000 000 0111 1111 1001 ATS1CPRP Address Translate Stage 1 Current state PL1 Read PAN
000 001 0111 1111 1001 ATS1CPWP Address Translate Stage 1 Current state PL1 Write PAN
100 101 1100 1111 1001 ICC_HSRE Interrupt Controller Hyp System Register Enable register
000 0xx 1100 1111 1001 ICC_AP1R<n> Interrupt Controller Active Priorities Group 1 Registers
000 0xx 1100 1111 1001 ICV_AP1R<n> Interrupt Controller Virtual Active Priorities Group 1 Registers
100 0xx 1100 1111 1001 ICH_AP1R<n> Interrupt Controller Hyp Active Priorities Group 1 Registers
000 001 0111 1111 1010 DCCMVAC Data Cache line Clean by VA to PoC
000 010 0111 1111 1010 DCCSW Data Cache line Clean by Set/Way
000 100 0111 1111 1010 CP15DSB Data Synchronization Barrier System instruction
000 101 0111 1111 1010 CP15DMB Data Memory Barrier System instruction
000 001 0111 1111 1011 DCCMVAU Data Cache line Clean by VA to PoU
100 000 1100 1111 1011 ICH_HCR Interrupt Controller Hyp Control Register
000 001 1100 1111 1011 ICC_DIR Interrupt Controller Deactivate Interrupt Register
000 001 1100 1111 1011 ICV_DIR Interrupt Controller Deactivate Virtual Interrupt Register
100 001 1100 1111 1011 ICH_VTR Interrupt Controller VGIC Type Register
100 010 1100 1111 1011 ICH_MISR Interrupt Controller Maintenance Interrupt State Register
000 011 1100 1111 1011 ICC_RPR Interrupt Controller Running Priority Register
000 011 1100 1111 1011 ICV_RPR Interrupt Controller Virtual Running Priority Register
100 011 1100 1111 1011 ICH_EISR Interrupt Controller End of Interrupt Status Register
100 101 1100 1111 1011 ICH_ELRSR Interrupt Controller Empty List Register Status Register
100 111 1100 1111 1011 ICH_VMCR Interrupt Controller Virtual Machine Control Register
000 000 1001 1111 1100 PMCR Performance Monitors Control Register
000 001 1001 1111 1100 PMCNTENSET Performance Monitors Count Enable Set register
000 010 1001 1111 1100 PMCNTENCLR Performance Monitors Count Enable Clear register
000 011 1001 1111 1100 PMOVSR Performance Monitors Overflow Flag Status Register
000 100 1001 1111 1100 PMSWINC Performance Monitors Software Increment register
000 101 1001 1111 1100 PMSELR Performance Monitors Event Counter Selection Register
000 110 1001 1111 1100 PMCEID0 Performance Monitors Common Event Identification register 0
000 111 1001 1111 1100 PMCEID1 Performance Monitors Common Event Identification register 1
000 000 1100 1111 1100 ICC_IAR1 Interrupt Controller Interrupt Acknowledge Register 1
000 000 1100 1111 1100 ICV_IAR1 Interrupt Controller Virtual Interrupt Acknowledge Register 1
000 001 1100 1111 1100 ICC_EOIR1 Interrupt Controller End Of Interrupt Register 1
000 001 1100 1111 1100 ICV_EOIR1 Interrupt Controller Virtual End Of Interrupt Register 1
000 010 1100 1111 1100 ICC_HPPIR1 Interrupt Controller Highest Priority Pending Interrupt Register 1
000 010 1100 1111 1100 ICV_HPPIR1 Interrupt Controller Virtual Highest Priority Pending Interrupt Register 1
000 011 1100 1111 1100 ICC_BPR1 Interrupt Controller Binary Point Register 1
000 011 1100 1111 1100 ICV_BPR1 Interrupt Controller Virtual Binary Point Register 1
000 100 1100 1111 1100 ICC_CTLR Interrupt Controller Control Register
000 100 1100 1111 1100 ICV_CTLR Interrupt Controller Virtual Control Register
110 100 1100 1111 1100 ICC_MCTLR Interrupt Controller Monitor Control Register
000 101 1100 1111 1100 ICC_SRE Interrupt Controller System Register Enable register
110 101 1100 1111 1100 ICC_MSRE Interrupt Controller Monitor System Register Enable register
000 110 1100 1111 1100 ICC_IGRPEN0 Interrupt Controller Interrupt Group 0 Enable register
000 110 1100 1111 1100 ICV_IGRPEN0 Interrupt Controller Virtual Interrupt Group 0 Enable register
000 111 1100 1111 1100 ICC_IGRPEN1 Interrupt Controller Interrupt Group 1 Enable register
000 111 1100 1111 1100 ICV_IGRPEN1 Interrupt Controller Virtual Interrupt Group 1 Enable register
110 111 1100 1111 1100 ICC_MGRPEN1 Interrupt Controller Monitor Interrupt Group 1 Enable register
000 000 1001 1111 1101 PMCCNTR Performance Monitors Cycle Count Register
000 001 1001 1111 1101 PMXEVTYPER Performance Monitors Selected Event Type Register
000 010 1001 1111 1101 PMXEVCNTR Performance Monitors Selected Event Count Register
000 110 0111 1110 1110 DBGAUTHSTATUS Debug Authentication Status register
000 001 0111 1111 1110 DCCIMVAC Data Cache line Clean and Invalidate by VA to PoC
000 010 0111 1111 1110 DCCISW Data Cache line Clean and Invalidate by Set/Way
000 000 1001 1111 1110 PMUSERENR Performance Monitors User Enable Register
000 001 1001 1111 1110 PMINTENSET Performance Monitors Interrupt Enable Set register
000 010 1001 1111 1110 PMINTENCLR Performance Monitors Interrupt Enable Clear register
000 011 1001 1111 1110 PMOVSSET Performance Monitors Overflow Flag Status Set register
000 100 1001 1111 1110 PMCEID2 Performance Monitors Common Event Identification register 2
000 101 1001 1111 1110 PMCEID3 Performance Monitors Common Event Identification register 3
000 111 1110 1111 1111 PMCCFILTR Performance Monitors Cycle Count Filter Register
000 xxx 1110 1111 10xx PMEVCNTR<n> Performance Monitors Event Count Registers
100 xxx 1100 1111 110x ICH_LR<n> Interrupt Controller List Registers
100 xxx 1100 1111 111x ICH_LRC<n> Interrupt Controller List Registers
000 xxx 1110 1111 11xx PMEVTYPER<n> Performance Monitors Event Type Registers
000 100 0000 1110 xxxx DBGBVR<n> Debug Breakpoint Value Registers
000 101 0000 1110 xxxx DBGBCR<n> Debug Breakpoint Control Registers
000 110 0000 1110 xxxx DBGWVR<n> Debug Watchpoint Value Registers
000 111 0000 1110 xxxx DBGWCR<n> Debug Watchpoint Control Registers
000 001 0001 1110 xxxx DBGBXVR<n> Debug Breakpoint Extended Value Registers

Accessed using MCRR/MRRC:

Register selectors Name Description
opc1 coproc CRm
0000 1110 0001 DBGDRAR Debug ROM Address Register
0000 1110 0010 DBGDSAR Debug Self Address Register
0000 1111 0010 TTBR0 Translation Table Base Register 0
0001 1111 0010 TTBR1 Translation Table Base Register 1
0100 1111 0010 HTTBR Hyp Translation Table Base Register
0110 1111 0010 VTTBR Virtualization Translation Table Base Register
0000 1111 0111 PAR Physical Address Register
0000 1111 1001 PMCCNTR Performance Monitors Cycle Count Register
0000 1111 1100 ICC_SGI1R Interrupt Controller Software Generated Interrupt Group 1 Register
0001 1111 1100 ICC_ASGI1R Interrupt Controller Alias Software Generated Interrupt Group 1 Register
0010 1111 1100 ICC_SGI0R Interrupt Controller Software Generated Interrupt Group 0 Register
0000 1111 1110 CNTPCT Counter-timer Physical Count register
0001 1111 1110 CNTVCT Counter-timer Virtual Count register
0010 1111 1110 CNTP_CVAL Counter-timer Physical Timer CompareValue register
0011 1111 1110 CNTHV_CVAL Counter-timer Virtual Timer CompareValue register (EL2)
0011 1111 1110 CNTV_CVAL Counter-timer Virtual Timer CompareValue register
0100 1111 1110 CNTVOFF Counter-timer Virtual Offset register
0110 1111 1110 CNTHP_CVAL Counter-timer Hyp Physical CompareValue register

Accessed using MRS/MSR:

Register selectors Name Description
R M M1
1 1 0000 SPSR_irq Saved Program Status Register (IRQ mode)
1 1 0010 SPSR_svc Saved Program Status Register (Supervisor mode)
1 1 0100 SPSR_abt Saved Program Status Register (Abort mode)
1 1 0110 SPSR_und Saved Program Status Register (Undefined mode)
1 1 1100 SPSR_mon Saved Program Status Register (Monitor mode)
1 0 1110 SPSR_fiq Saved Program Status Register (FIQ mode)
0 1 1110 ELR_hyp Exception Link Register (Hyp mode)
1 1 1110 SPSR_hyp Saved Program Status Register (Hyp mode)

Accessed using VMRS/VMSR:

Register selectors Name Description
reg
0000 FPSID Floating-Point System ID register
0001 FPSCR Floating-Point Status and Control Register
0101 MVFR2 Media and VFP Feature Register 2
0110 MVFR1 Media and VFP Feature Register 1
0111 MVFR0 Media and VFP Feature Register 0
1000 FPEXC Floating-Point Exception Control register

Registers and operations in AArch64

Accessed using AT:

Register selectors Name Description
op0 op1 CRn CRm op2
01 000 0111 1000 000 AT S1E1R Address Translate Stage 1 EL1 Read
01 100 0111 1000 000 AT S1E2R Address Translate Stage 1 EL2 Read
01 110 0111 1000 000 AT S1E3R Address Translate Stage 1 EL3 Read
01 000 0111 1001 000 AT S1E1RP Address Translate Stage 1 EL1 Read PAN
01 000 0111 1000 001 AT S1E1W Address Translate Stage 1 EL1 Write
01 100 0111 1000 001 AT S1E2W Address Translate Stage 1 EL2 Write
01 110 0111 1000 001 AT S1E3W Address Translate Stage 1 EL3 Write
01 000 0111 1001 001 AT S1E1WP Address Translate Stage 1 EL1 Write PAN
01 000 0111 1000 010 AT S1E0R Address Translate Stage 1 EL0 Read
01 000 0111 1000 011 AT S1E0W Address Translate Stage 1 EL0 Write
01 100 0111 1000 100 AT S12E1R Address Translate Stages 1 and 2 EL1 Read
01 100 0111 1000 101 AT S12E1W Address Translate Stages 1 and 2 EL1 Write
01 100 0111 1000 110 AT S12E0R Address Translate Stages 1 and 2 EL0 Read
01 100 0111 1000 111 AT S12E0W Address Translate Stages 1 and 2 EL0 Write

Accessed using DC:

Register selectors Name Description
op0 op1 CRn CRm op2
01 011 0111 0100 001 DC ZVA Data Cache Zero by VA
01 000 0111 0110 001 DC IVAC Data or unified Cache line Invalidate by VA to PoC
01 011 0111 1010 001 DC CVAC Data or unified Cache line Clean by VA to PoC
01 011 0111 1011 001 DC CVAU Data or unified Cache line Clean by VA to PoU
01 011 0111 1100 001 DC CVAP Data or unified Cache line Clean by VA to PoP
01 011 0111 1110 001 DC CIVAC Data or unified Cache line Clean and Invalidate by VA to PoC
01 000 0111 0110 010 DC ISW Data or unified Cache line Invalidate by Set/Way
01 000 0111 1010 010 DC CSW Data or unified Cache line Clean by Set/Way
01 000 0111 1110 010 DC CISW Data or unified Cache line Clean and Invalidate by Set/Way

Accessed using IC:

Register selectors Name Description
op0 op1 CRn CRm op2 Rt
01 011 0111 0101 001 - IC IVAU Instruction Cache line Invalidate by VA to PoU
01 000 0111 0001 000 11111 IC IALLUIS Instruction Cache Invalidate All to PoU, Inner Shareable
01 000 0111 0101 000 11111 IC IALLU Instruction Cache Invalidate All to PoU

Accessed using MRS/MSR:

Register selectors Name Description
op0 op1 CRn CRm op2
11 000 0000 0000 000 MIDR_EL1 Main ID Register
11 001 0000 0000 000 CCSIDR_EL1 Current Cache Size ID Register
11 010 0000 0000 000 CSSELR_EL1 Cache Size Selection Register
11 100 0000 0000 000 VPIDR_EL2 Virtualization Processor ID Register
10 000 0001 0000 000 MDRAR_EL1 Monitor Debug ROM Address Register
11 000 0001 0000 000 SCTLR_EL1 System Control Register (EL1)
11 100 0001 0000 000 SCTLR_EL2 System Control Register (EL2)
11 110 0001 0000 000 SCTLR_EL3 System Control Register (EL3)
11 000 0010 0000 000 TTBR0_EL1 Translation Table Base Register 0 (EL1)
11 100 0010 0000 000 TTBR0_EL2 Translation Table Base Register 0 (EL2)
11 110 0010 0000 000 TTBR0_EL3 Translation Table Base Register 0 (EL3)
11 100 0011 0000 000 DACR32_EL2 Domain Access Control Register
11 000 0100 0000 000 SPSR_EL1 Saved Program Status Register (EL1)
11 100 0100 0000 000 SPSR_EL2 Saved Program Status Register (EL2)
11 110 0100 0000 000 SPSR_EL3 Saved Program Status Register (EL3)
11 000 0110 0000 000 FAR_EL1 Fault Address Register (EL1)
11 100 0110 0000 000 FAR_EL2 Fault Address Register (EL2)
11 110 0110 0000 000 FAR_EL3 Fault Address Register (EL3)
11 000 1100 0000 000 VBAR_EL1 Vector Base Address Register (EL1)
11 100 1100 0000 000 PMSCR_EL2 Statistical Profiling Control Register (EL2)
11 100 1100 0000 000 VBAR_EL2 Vector Base Address Register (EL2)
11 110 1100 0000 000 VBAR_EL3 Vector Base Address Register (EL3)
11 011 1110 0000 000 CNTFRQ_EL0 Counter-timer Frequency register
11 000 0000 0001 000 ID_PFR0_EL1 AArch32 Processor Feature Register 0
10 011 0000 0001 000 MDCCSR_EL0 Monitor DCC Status Register
11 100 0001 0001 000 HCR_EL2 Hypervisor Configuration Register
11 110 0001 0001 000 SCR_EL3 Secure Configuration Register
11 000 0010 0001 000 APIAKeyLo_EL1 Pointer Authentication Key A for Instruction (bits[63:0])
11 100 0010 0001 000 VTTBR_EL2 Virtualization Translation Table Base Register
11 000 0100 0001 000 SP_EL0 Stack Pointer (EL0)
11 100 0100 0001 000 SP_EL1 Stack Pointer (EL1)
11 110 0100 0001 000 SP_EL2 Stack Pointer (EL2)
11 000 0101 0001 000 AFSR0_EL1 Auxiliary Fault Status Register 0 (EL1)
11 100 0101 0001 000 AFSR0_EL2 Auxiliary Fault Status Register 0 (EL2)
11 110 0101 0001 000 AFSR0_EL3 Auxiliary Fault Status Register 0 (EL3)
11 000 1100 0001 000 ISR_EL1 Interrupt Status Register
11 000 1110 0001 000 CNTKCTL_EL1 Counter-timer Kernel Control register
11 100 1110 0001 000 CNTHCTL_EL2 Counter-timer Hypervisor Control register
10 000 0000 0010 000 MDCCINT_EL1 Monitor DCC Interrupt Enable Register
11 000 0000 0010 000 ID_ISAR0_EL1 AArch32 Instruction Set Attribute Register 0
11 000 0010 0010 000 APDAKeyLo_EL1 Pointer Authentication Key A for Data (bits[63:0])
11 000 0100 0010 000 SPSel Stack Pointer Select
11 011 0100 0010 000 NZCV Condition Flags
11 000 0101 0010 000 ESR_EL1 Exception Syndrome Register (EL1)
11 100 0101 0010 000 ESR_EL2 Exception Syndrome Register (EL2)
11 110 0101 0010 000 ESR_EL3 Exception Syndrome Register (EL3)
11 000 1010 0010 000 MAIR_EL1 Memory Attribute Indirection Register (EL1)
11 100 1010 0010 000 MAIR_EL2 Memory Attribute Indirection Register (EL2)
11 110 1010 0010 000 MAIR_EL3 Memory Attribute Indirection Register (EL3)
11 011 1110 0010 000 CNTP_TVAL_EL0 Counter-timer Physical Timer TimerValue register
11 100 1110 0010 000 CNTHP_TVAL_EL2 Counter-timer Hypervisor Physical Timer TimerValue register
11 111 1110 0010 000 CNTPS_TVAL_EL1 Counter-timer Physical Secure Timer TimerValue register
11 000 0000 0011 000 MVFR0_EL1 AArch32 Media and VFP Feature Register 0
11 000 0010 0011 000 APGAKeyLo_EL1 Pointer Authentication Key A for Code (bits[63:0])
11 100 0100 0011 000 SPSR_irq Saved Program Status Register (IRQ mode)
11 100 0101 0011 000 FPEXC32_EL2 Floating-Point Exception Control register
11 000 1010 0011 000 AMAIR_EL1 Auxiliary Memory Attribute Indirection Register (EL1)
11 100 1010 0011 000 AMAIR_EL2 Auxiliary Memory Attribute Indirection Register (EL2)
11 110 1010 0011 000 AMAIR_EL3 Auxiliary Memory Attribute Indirection Register (EL3)
11 011 1110 0011 000 CNTV_TVAL_EL0 Counter-timer Virtual Timer TimerValue register
11 100 1110 0011 000 CNTHV_TVAL_EL2 Counter-timer Virtual Timer TimerValue register (EL2)
11 000 0000 0100 000 ID_AA64PFR0_EL1 AArch64 Processor Feature Register 0
10 011 0000 0100 000 DBGDTR_EL0 Debug Data Transfer Register, half-duplex
11 011 0100 0100 000 FPCR Floating-point Control Register
11 000 0111 0100 000 PAR_EL1 Physical Address Register
11 000 1010 0100 000 LORSA_EL1 LORegion Start Address (EL1)
11 000 0000 0101 000 ID_AA64DFR0_EL1 AArch64 Debug Feature Register 0
10 011 0000 0101 000 DBGDTRRX_EL0 Debug Data Transfer Register, Receive
10 011 0000 0101 000 DBGDTRTX_EL0 Debug Data Transfer Register, Transmit
11 011 0100 0101 000 DSPSR_EL0 Debug Saved Program Status Register
11 000 0000 0110 000 ID_AA64ISAR0_EL1 AArch64 Instruction Set Attribute Register 0
11 000 0100 0110 000 ICC_PMR_EL1 Interrupt Controller Interrupt Priority Mask Register
11 000 0100 0110 000 ICV_PMR_EL1 Interrupt Controller Virtual Interrupt Priority Mask Register
11 000 0000 0111 000 ID_AA64MMFR0_EL1 AArch64 Memory Model Feature Register 0
10 100 0000 0111 000 DBGVCR32_EL2 Debug Vector Catch Register
11 000 1100 1000 000 ICC_IAR0_EL1 Interrupt Controller Interrupt Acknowledge Register 0
11 000 1100 1000 000 ICV_IAR0_EL1 Interrupt Controller Virtual Interrupt Acknowledge Register 0
11 000 1001 1001 000 PMSCR_EL1 Statistical Profiling Control Register (EL1)
11 000 1001 1010 000 PMBLIMITR_EL1 Profiling Buffer Limit Address Register
11 000 1001 1010 000 PMSIRR_EL1 Sampling Interval Reload Register
11 100 1100 1011 000 ICH_HCR_EL2 Interrupt Controller Hyp Control Register
11 011 1001 1100 000 PMCR_EL0 Performance Monitors Control Register
11 000 1100 1100 000 ICC_IAR1_EL1 Interrupt Controller Interrupt Acknowledge Register 1
11 000 1100 1100 000 ICV_IAR1_EL1 Interrupt Controller Virtual Interrupt Acknowledge Register 1
11 011 1001 1101 000 PMCCNTR_EL0 Performance Monitors Cycle Count Register
11 011 1001 1110 000 PMUSERENR_EL0 Performance Monitors User Enable Register
11 001 0000 0000 001 CLIDR_EL1 Cache Level ID Register
11 011 0000 0000 001 CTR_EL0 Cache Type Register
11 000 0001 0000 001 ACTLR_EL1 Auxiliary Control Register (EL1)
11 100 0001 0000 001 ACTLR_EL2 Auxiliary Control Register (EL2)
11 110 0001 0000 001 ACTLR_EL3 Auxiliary Control Register (EL3)
11 000 0010 0000 001 TTBR1_EL1 Translation Table Base Register 1 (EL1)
11 100 0010 0000 001 TTBR1_EL2 Translation Table Base Register 1 (EL2)
11 000 0100 0000 001 ELR_EL1 Exception Link Register (EL1)
11 100 0100 0000 001 ELR_EL2 Exception Link Register (EL2)
11 110 0100 0000 001 ELR_EL3 Exception Link Register (EL3)
11 100 0101 0000 001 IFSR32_EL2 Instruction Fault Status Register (EL2)
11 000 1100 0000 001 RVBAR_EL1 Reset Vector Base Address Register (if EL2 and EL3 not implemented)
11 100 1100 0000 001 RVBAR_EL2 Reset Vector Base Address Register (if EL3 not implemented)
11 110 1100 0000 001 RVBAR_EL3 Reset Vector Base Address Register (if EL3 implemented)
11 000 1101 0000 001 CONTEXTIDR_EL1 Context ID Register (EL1)
11 100 1101 0000 001 CONTEXTIDR_EL2 Context ID Register (EL2)
11 011 1110 0000 001 CNTPCT_EL0 Counter-timer Physical Count register
11 000 0000 0001 001 ID_PFR1_EL1 AArch32 Processor Feature Register 1
11 100 0001 0001 001 MDCR_EL2 Monitor Debug Configuration Register (EL2)
11 110 0001 0001 001 SDER32_EL3 AArch32 Secure Debug Enable Register
11 000 0010 0001 001 APIAKeyHi_EL1 Pointer Authentication Key A for Instruction (bits[127:64])
11 000 0101 0001 001 AFSR1_EL1 Auxiliary Fault Status Register 1 (EL1)
11 100 0101 0001 001 AFSR1_EL2 Auxiliary Fault Status Register 1 (EL2)
11 110 0101 0001 001 AFSR1_EL3 Auxiliary Fault Status Register 1 (EL3)
11 000 0000 0010 001 ID_ISAR1_EL1 AArch32 Instruction Set Attribute Register 1
11 000 0010 0010 001 APDAKeyHi_EL1 Pointer Authentication Key A for Data (bits[127:64])
11 011 0100 0010 001 DAIF Interrupt Mask Bits
11 011 1110 0010 001 CNTP_CTL_EL0 Counter-timer Physical Timer Control register
11 100 1110 0010 001 CNTHP_CTL_EL2 Counter-timer Hypervisor Physical Timer Control register
11 111 1110 0010 001 CNTPS_CTL_EL1 Counter-timer Physical Secure Timer Control register
11 000 0000 0011 001 MVFR1_EL1 AArch32 Media and VFP Feature Register 1
11 110 0001 0011 001 MDCR_EL3 Monitor Debug Configuration Register (EL3)
11 000 0010 0011 001 APGAKeyHi_EL1 Pointer Authentication Key A for Code (bits[127:64])
11 100 0100 0011 001 SPSR_abt Saved Program Status Register (Abort mode)
11 011 1110 0011 001 CNTV_CTL_EL0 Counter-timer Virtual Timer Control register
11 100 1110 0011 001 CNTHV_CTL_EL2 Counter-timer Virtual Timer Control register (EL2)
11 000 0000 0100 001 ID_AA64PFR1_EL1 AArch64 Processor Feature Register 1
11 011 0100 0100 001 FPSR Floating-point Status Register
11 000 1010 0100 001 LOREA_EL1 LORegion End Address (EL1)
11 000 0000 0101 001 ID_AA64DFR1_EL1 AArch64 Debug Feature Register 1
11 011 0100 0101 001 DLR_EL0 Debug Link Register
11 000 0000 0110 001 ID_AA64ISAR1_EL1 AArch64 Instruction Set Attribute Register 1
11 000 0000 0111 001 ID_AA64MMFR1_EL1 AArch64 Memory Model Feature Register 1
11 000 1100 1000 001 ICC_EOIR0_EL1 Interrupt Controller End Of Interrupt Register 0
11 000 1100 1000 001 ICV_EOIR0_EL1 Interrupt Controller Virtual End Of Interrupt Register 0
11 000 1001 1010 001 PMBPTR_EL1 Profiling Buffer Write Pointer Register
11 000 1100 1011 001 ICC_DIR_EL1 Interrupt Controller Deactivate Interrupt Register
11 000 1100 1011 001 ICV_DIR_EL1 Interrupt Controller Deactivate Virtual Interrupt Register
11 100 1100 1011 001 ICH_VTR_EL2 Interrupt Controller VGIC Type Register
11 011 1001 1100 001 PMCNTENSET_EL0 Performance Monitors Count Enable Set register
11 000 1100 1100 001 ICC_EOIR1_EL1 Interrupt Controller End Of Interrupt Register 1
11 000 1100 1100 001 ICV_EOIR1_EL1 Interrupt Controller Virtual End Of Interrupt Register 1
11 011 1001 1101 001 PMXEVTYPER_EL0 Performance Monitors Selected Event Type Register
11 000 1001 1110 001 PMINTENSET_EL1 Performance Monitors Interrupt Enable Set register
10 000 0000 0000 010 OSDTRRX_EL1 OS Lock Data Transfer Register, Receive
11 001 0000 0000 010 CCSIDR2_EL1 Current Cache Size ID Register 2
11 000 0001 0000 010 CPACR_EL1 Architectural Feature Access Control Register
11 000 0010 0000 010 TCR_EL1 Translation Control Register (EL1)
11 100 0010 0000 010 TCR_EL2 Translation Control Register (EL2)
11 110 0010 0000 010 TCR_EL3 Translation Control Register (EL3)
11 000 1100 0000 010 RMR_EL1 Reset Management Register (EL1)
11 100 1100 0000 010 RMR_EL2 Reset Management Register (EL2)
11 110 1100 0000 010 RMR_EL3 Reset Management Register (EL3)
11 011 1101 0000 010 TPIDR_EL0 EL0 Read/Write Software Thread ID Register
11 100 1101 0000 010 TPIDR_EL2 EL2 Software Thread ID Register
11 110 1101 0000 010 TPIDR_EL3 EL3 Software Thread ID Register
11 011 1110 0000 010 CNTVCT_EL0 Counter-timer Virtual Count register
11 000 0000 0001 010 ID_DFR0_EL1 AArch32 Debug Feature Register 0
11 100 0001 0001 010 CPTR_EL2 Architectural Feature Trap Register (EL2)
11 110 0001 0001 010 CPTR_EL3 Architectural Feature Trap Register (EL3)
11 000 0010 0001 010 APIBKeyLo_EL1 Pointer Authentication Key B for Instruction (bits[63:0])
11 100 0010 0001 010 VTCR_EL2 Virtualization Translation Control Register
10 000 0000 0010 010 MDSCR_EL1 Monitor Debug System Control Register
11 000 0000 0010 010 ID_ISAR2_EL1 AArch32 Instruction Set Attribute Register 2
11 000 0010 0010 010 APDBKeyLo_EL1 Pointer Authentication Key B for Data (bits[63:0])
11 000 0100 0010 010 CurrentEL Current Exception Level
11 011 1110 0010 010 CNTP_CVAL_EL0 Counter-timer Physical Timer CompareValue register
11 100 1110 0010 010 CNTHP_CVAL_EL2 Counter-timer Hypervisor Physical Timer CompareValue register
11 111 1110 0010 010 CNTPS_CVAL_EL1 Counter-timer Physical Secure Timer CompareValue register
10 000 0000 0011 010 OSDTRTX_EL1 OS Lock Data Transfer Register, Transmit
11 000 0000 0011 010 MVFR2_EL1 AArch32 Media and VFP Feature Register 2
11 100 0100 0011 010 SPSR_und Saved Program Status Register (Undefined mode)
11 011 1110 0011 010 CNTV_CVAL_EL0 Counter-timer Virtual Timer CompareValue register
11 100 1110 0011 010 CNTHV_CVAL_EL2 Counter-timer Virtual Timer CompareValue register (EL2)
11 000 1010 0100 010 LORN_EL1 LORegion Number (EL1)
10 000 0000 0110 010 OSECCR_EL1 OS Lock Exception Catch Control Register
11 000 0000 0111 010 ID_AA64MMFR2_EL1 AArch64 Memory Model Feature Register 2
11 000 1100 1000 010 ICC_HPPIR0_EL1 Interrupt Controller Highest Priority Pending Interrupt Register 0
11 000 1100 1000 010 ICV_HPPIR0_EL1 Interrupt Controller Virtual Highest Priority Pending Interrupt Register 0
11 000 1001 1001 010 PMSICR_EL1 Sampling Interval Counter Register
11 100 1100 1011 010 ICH_MISR_EL2 Interrupt Controller Maintenance Interrupt State Register
11 011 1001 1100 010 PMCNTENCLR_EL0 Performance Monitors Count Enable Clear register
11 000 1100 1100 010 ICC_HPPIR1_EL1 Interrupt Controller Highest Priority Pending Interrupt Register 1
11 000 1100 1100 010 ICV_HPPIR1_EL1 Interrupt Controller Virtual Highest Priority Pending Interrupt Register 1
11 011 1001 1101 010 PMXEVCNTR_EL0 Performance Monitors Selected Event Count Register
11 000 1001 1110 010 PMINTENCLR_EL1 Performance Monitors Interrupt Enable Clear register
11 011 1101 0000 011 TPIDRRO_EL0 EL0 Read-Only Software Thread ID Register
11 100 1110 0000 011 CNTVOFF_EL2 Counter-timer Virtual Offset register
11 000 0000 0001 011 ID_AFR0_EL1 AArch32 Auxiliary Feature Register 0
11 100 0001 0001 011 HSTR_EL2 Hypervisor System Trap Register
11 000 0010 0001 011 APIBKeyHi_EL1 Pointer Authentication Key B for Instruction (bits[127:64])
11 000 0000 0010 011 ID_ISAR3_EL1 AArch32 Instruction Set Attribute Register 3
11 000 0010 0010 011 APDBKeyHi_EL1 Pointer Authentication Key B for Data (bits[127:64])
11 000 0100 0010 011 PAN Privileged Access Never
11 100 0100 0011 011 SPSR_fiq Saved Program Status Register (FIQ mode)
11 000 1010 0100 011 LORC_EL1 LORegion Control (EL1)
11 000 1100 1000 011 ICC_BPR0_EL1 Interrupt Controller Binary Point Register 0
11 000 1100 1000 011 ICV_BPR0_EL1 Interrupt Controller Virtual Binary Point Register 0
11 000 1001 1010 011 PMBSR_EL1 Profiling Buffer Status/syndrome Register
11 000 1100 1011 011 ICC_RPR_EL1 Interrupt Controller Running Priority Register
11 000 1100 1011 011 ICV_RPR_EL1 Interrupt Controller Virtual Running Priority Register
11 100 1100 1011 011 ICH_EISR_EL2 Interrupt Controller End of Interrupt Status Register
11 011 1001 1100 011 PMOVSCLR_EL0 Performance Monitors Overflow Flag Status Clear Register
11 000 1100 1100 011 ICC_BPR1_EL1 Interrupt Controller Binary Point Register 1
11 000 1100 1100 011 ICV_BPR1_EL1 Interrupt Controller Virtual Binary Point Register 1
11 011 1001 1110 011 PMOVSSET_EL0 Performance Monitors Overflow Flag Status Set register
10 000 0001 0000 100 OSLAR_EL1 OS Lock Access Register
11 100 0110 0000 100 HPFAR_EL2 Hypervisor IPA Fault Address Register
11 000 1101 0000 100 TPIDR_EL1 EL1 Software Thread ID Register
11 000 0000 0001 100 ID_MMFR0_EL1 AArch32 Memory Model Feature Register 0
10 000 0001 0001 100 OSLSR_EL1 OS Lock Status Register
11 000 0000 0010 100 ID_ISAR4_EL1 AArch32 Instruction Set Attribute Register 4
11 000 0100 0010 100 UAO User Access Override
10 000 0001 0011 100 OSDLR_EL1 OS Double Lock Register
10 000 0001 0100 100 DBGPRCR_EL1 Debug Power Control Register
11 000 0000 0101 100 ID_AA64AFR0_EL1 AArch64 Auxiliary Feature Register 0
11 000 1001 1001 100 PMSFCR_EL1 Sampling Filter Control Register
11 011 1001 1100 100 PMSWINC_EL0 Performance Monitors Software Increment register
11 000 1100 1100 100 ICC_CTLR_EL1 Interrupt Controller Control Register (EL1)
11 000 1100 1100 100 ICV_CTLR_EL1 Interrupt Controller Virtual Control Register
11 110 1100 1100 100 ICC_CTLR_EL3 Interrupt Controller Control Register (EL3)
10 000 0000 xxxx 100 DBGBVR<n>_EL1 Debug Breakpoint Value Registers
11 000 0000 0000 101 MPIDR_EL1 Multiprocessor Affinity Register
11 100 0000 0000 101 VMPIDR_EL2 Virtualization Multiprocessor ID Register
11 000 0000 0001 101 ID_MMFR1_EL1 AArch32 Memory Model Feature Register 1
11 000 0000 0010 101 ID_ISAR5_EL1 AArch32 Instruction Set Attribute Register 5
11 000 0000 0101 101 ID_AA64AFR1_EL1 AArch64 Auxiliary Feature Register 1
11 000 1001 1001 101 PMSEVFR_EL1 Sampling Event Filter Register
11 100 1100 1001 101 ICC_SRE_EL2 Interrupt Controller System Register Enable register (EL2)
11 000 1100 1011 101 ICC_SGI1R_EL1 Interrupt Controller Software Generated Interrupt Group 1 Register
11 100 1100 1011 101 ICH_ELRSR_EL2 Interrupt Controller Empty List Register Status Register
11 011 1001 1100 101 PMSELR_EL0 Performance Monitors Event Counter Selection Register
11 000 1100 1100 101 ICC_SRE_EL1 Interrupt Controller System Register Enable register (EL1)
11 110 1100 1100 101 ICC_SRE_EL3 Interrupt Controller System Register Enable register (EL3)
10 000 0000 xxxx 101 DBGBCR<n>_EL1 Debug Breakpoint Control Registers
11 000 0000 0000 110 REVIDR_EL1 Revision ID Register
11 000 0000 0001 110 ID_MMFR2_EL1 AArch32 Memory Model Feature Register 2
11 000 0000 0010 110 ID_MMFR4_EL1 AArch32 Memory Model Feature Register 4
10 000 0111 1000 110 DBGCLAIMSET_EL1 Debug Claim Tag Set register
10 000 0111 1001 110 DBGCLAIMCLR_EL1 Debug Claim Tag Clear register
11 000 1001 1001 110 PMSLATFR_EL1 Sampling Latency Filter Register
11 000 1100 1011 110 ICC_ASGI1R_EL1 Interrupt Controller Alias Software Generated Interrupt Group 1 Register
11 011 1001 1100 110 PMCEID0_EL0 Performance Monitors Common Event Identification register 0
11 000 1100 1100 110 ICC_IGRPEN0_EL1 Interrupt Controller Interrupt Group 0 Enable register
11 000 1100 1100 110 ICV_IGRPEN0_EL1 Interrupt Controller Virtual Interrupt Group 0 Enable register
10 000 0111 1110 110 DBGAUTHSTATUS_EL1 Debug Authentication Status register
10 000 0000 xxxx 110 DBGWVR<n>_EL1 Debug Watchpoint Value Registers
11 001 0000 0000 111 AIDR_EL1 Auxiliary ID Register
11 011 0000 0000 111 DCZID_EL0 Data Cache Zero ID register
11 000 0000 0001 111 ID_MMFR3_EL1 AArch32 Memory Model Feature Register 3
11 100 0001 0001 111 HACR_EL2 Hypervisor Auxiliary Control Register
11 000 0000 0010 111 ID_ISAR6_EL1 AArch32 Instruction Set Attribute Register 6
11 000 1010 0100 111 LORID_EL1 LORegionID (EL1)
11 000 1001 1001 111 PMSIDR_EL1 Sampling Profiling ID Register
11 000 1001 1010 111 PMBIDR_EL1 Profiling Buffer ID Register
11 000 1100 1011 111 ICC_SGI0R_EL1 Interrupt Controller Software Generated Interrupt Group 0 Register
11 100 1100 1011 111 ICH_VMCR_EL2 Interrupt Controller Virtual Machine Control Register
11 011 1001 1100 111 PMCEID1_EL0 Performance Monitors Common Event Identification register 1
11 000 1100 1100 111 ICC_IGRPEN1_EL1 Interrupt Controller Interrupt Group 1 Enable register
11 000 1100 1100 111 ICV_IGRPEN1_EL1 Interrupt Controller Virtual Interrupt Group 1 Enable register
11 110 1100 1100 111 ICC_IGRPEN1_EL3 Interrupt Controller Interrupt Group 1 Enable register (EL3)
11 011 1110 1111 111 PMCCFILTR_EL0 Performance Monitors Cycle Count Filter Register
10 000 0000 xxxx 111 DBGWCR<n>_EL1 Debug Watchpoint Control Registers
11 100 1100 1000 0xx ICH_AP0R<n>_EL2 Interrupt Controller Hyp Active Priorities Group 0 Registers
11 000 1100 1001 0xx ICC_AP1R<n>_EL1 Interrupt Controller Active Priorities Group 1 Registers
11 000 1100 1001 0xx ICV_AP1R<n>_EL1 Interrupt Controller Virtual Active Priorities Group 1 Registers
11 100 1100 1001 0xx ICH_AP1R<n>_EL2 Interrupt Controller Hyp Active Priorities Group 1 Registers
11 000 1100 1000 1xx ICC_AP0R<n>_EL1 Interrupt Controller Active Priorities Group 0 Registers
11 000 1100 1000 1xx ICV_AP0R<n>_EL1 Interrupt Controller Virtual Active Priorities Group 0 Registers
11 011 1110 10xx xxx PMEVCNTR<n>_EL0 Performance Monitors Event Count Registers
11 100 1100 110x xxx ICH_LR<n>_EL2 Interrupt Controller List Registers
11 011 1110 11xx xxx PMEVTYPER<n>_EL0 Performance Monitors Event Type Registers
11 xxx xxxx xxxx xxx S3_<op1>_<Cn>_<Cm>_<op2> IMPLEMENTATION DEFINED registers

Accessed using SYS/SYSL:

Register selectors Name Description
CRn op1 op2 CRm
xxxx xxx xxx xxxx S1_<op1>_<Cn>_<Cm>_<op2> IMPLEMENTATION DEFINED maintenance instructions

Accessed using TLBI:

Register selectors Name Description
op0 op1 CRn CRm op2 Rt
01 100 1000 0000 001 - TLBI IPAS2E1IS TLB Invalidate by Intermediate Physical Address, Stage 2, EL1, Inner Shareable
01 000 1000 0011 001 - TLBI VAE1IS TLB Invalidate by VA, EL1, Inner Shareable
01 100 1000 0011 001 - TLBI VAE2IS TLB Invalidate by VA, EL2, Inner Shareable
01 110 1000 0011 001 - TLBI VAE3IS TLB Invalidate by VA, EL3, Inner Shareable
01 100 1000 0100 001 - TLBI IPAS2E1 TLB Invalidate by Intermediate Physical Address, Stage 2, EL1
01 000 1000 0111 001 - TLBI VAE1 TLB Invalidate by VA, EL1
01 100 1000 0111 001 - TLBI VAE2 TLB Invalidate by VA, EL2
01 110 1000 0111 001 - TLBI VAE3 TLB Invalidate by VA, EL3
01 000 1000 0011 010 - TLBI ASIDE1IS TLB Invalidate by ASID, EL1, Inner Shareable
01 000 1000 0111 010 - TLBI ASIDE1 TLB Invalidate by ASID, EL1
01 000 1000 0011 011 - TLBI VAAE1IS TLB Invalidate by VA, All ASID, EL1, Inner Shareable
01 000 1000 0111 011 - TLBI VAAE1 TLB Invalidate by VA, All ASID, EL1
01 100 1000 0000 101 - TLBI IPAS2LE1IS TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Inner Shareable
01 000 1000 0011 101 - TLBI VALE1IS TLB Invalidate by VA, Last level, EL1, Inner Shareable
01 100 1000 0011 101 - TLBI VALE2IS TLB Invalidate by VA, Last level, EL2, Inner Shareable
01 110 1000 0011 101 - TLBI VALE3IS TLB Invalidate by VA, Last level, EL3, Inner Shareable
01 100 1000 0100 101 - TLBI IPAS2LE1 TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1
01 000 1000 0111 101 - TLBI VALE1 TLB Invalidate by VA, Last level, EL1
01 100 1000 0111 101 - TLBI VALE2 TLB Invalidate by VA, Last level, EL2
01 110 1000 0111 101 - TLBI VALE3 TLB Invalidate by VA, Last level, EL3
01 000 1000 0011 111 - TLBI VAALE1IS TLB Invalidate by VA, All ASID, Last Level, EL1, Inner Shareable
01 000 1000 0111 111 - TLBI VAALE1 TLB Invalidate by VA, All ASID, Last level, EL1
01 000 1000 0011 000 11111 TLBI VMALLE1IS TLB Invalidate by VMID, All at stage 1, EL1, Inner Shareable
01 100 1000 0011 000 11111 TLBI ALLE2IS TLB Invalidate All, EL2, Inner Shareable
01 110 1000 0011 000 11111 TLBI ALLE3IS TLB Invalidate All, EL3, Inner Shareable
01 000 1000 0111 000 11111 TLBI VMALLE1 TLB Invalidate by VMID, All at stage 1, EL1
01 100 1000 0111 000 11111 TLBI ALLE2 TLB Invalidate All, EL2
01 110 1000 0111 000 11111 TLBI ALLE3 TLB Invalidate All, EL3
01 100 1000 0011 100 11111 TLBI ALLE1IS TLB Invalidate All, EL1, Inner Shareable
01 100 1000 0111 100 11111 TLBI ALLE1 TLB Invalidate All, EL1
01 100 1000 0011 110 11111 TLBI VMALLS12E1IS TLB Invalidate by VMID, All at Stage 1 and 2, EL1, Inner Shareable
01 100 1000 0111 110 11111 TLBI VMALLS12E1 TLB Invalidate by VMID, All at Stage 1 and 2, EL1

28/09/2017 08:41

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