The TLBI VMALLS12E1IS characteristics are:
Invalidate cached copies of translation table entries from TLBs that meet all the following requirements:
The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this instructions.
For the EL1&0 translation regime, the invalidation applies to both:
This System instruction is part of the TLB maintenance instructions functional group.
There are no configuration notes.
TLBI VMALLS12E1IS is a 64-bit System instruction.
TLBI VMALLS12E1IS ignores the value in the register specified by the instruction encoding. Software does not have to write a value to the register before issuing this instruction.
This instruction is executed using TLBI with the following syntax:
TLBI <tlbi_op>
This syntax uses the following encoding in the System instruction encoding space:
<tlbi_op> | op0 | op1 | CRn | CRm | op2 | Rt |
---|---|---|---|---|---|---|
VMALLS12E1IS | 01 | 100 | 1000 | 0011 | 110 | 11111 |
The instruction is executable as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | - | n/a | WO |
0 | 0 | 1 | - | - | WO | WO |
0 | 1 | 1 | - | n/a | WO | WO |
1 | 0 | 1 | - | - | WO | WO |
1 | 1 | 1 | - | n/a | WO | WO |
This table applies to all syntax that can be used to execute this instruction.
If SCR_EL3.NS==0, or EL2 is not implemented, this instruction executes as a TLBI VMALLE1IS.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when executing this System instruction.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.NV==1, Non-secure execution of this instruction at EL1 is trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.NV==1, Non-secure execution of this instruction at EL1 is trapped to EL2.
28/09/2017 08:24
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