The ICC_MGRPEN1 characteristics are:
Controls whether Group 1 interrupts are enabled or not.
This register is part of:
This register is only accessible in Secure state.
AArch32 System register ICC_MGRPEN1 can be mapped to AArch64 System register ICC_IGRPEN1_EL3, but this is not architecturally mandated.
ICC_MGRPEN1 is a 32-bit register.
The ICC_MGRPEN1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | EnableGrp1S | EnableGrp1NS |
Reserved, RES0.
Enables Group 1 interrupts for the Secure state.
EnableGrp1S | Meaning |
---|---|
0 |
Secure Group 1 interrupts are disabled. |
1 |
Secure Group 1 interrupts are enabled. |
The Secure ICC_IGRPEN1.Enable bit is a read/write alias of the ICC_MGRPEN1.EnableGrp1S bit.
If the highest priority pending interrupt for that PE is a Group 1 interrupt using 1 of N model, then the interrupt will target another PE as a result of the Enable bit changing from 1 to 0.
When this register has an architecturally-defined reset value, this field resets to 0.
Enables Group 1 interrupts for the Non-secure state.
EnableGrp1NS | Meaning |
---|---|
0 |
Non-secure Group 1 interrupts are disabled. |
1 |
Non-secure Group 1 interrupts are enabled. |
The Non-secure ICC_IGRPEN1.Enable bit is a read/write alias of the ICC_MGRPEN1.EnableGrp1NS bit.
If the highest priority pending interrupt for that PE is a Group 1 interrupt using 1 of N model, then the interrupt will target another PE as a result of the Enable bit changing from 1 to 0.
When this register has an architecturally-defined reset value, this field resets to 0.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 6, <Rt>, c12, c12, 7 | 110 | 111 | 1100 | 1111 | 1100 |
The register is accessible as follows:
Control | Accessibility | ||||||
---|---|---|---|---|---|---|---|
FMO | IMO | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | x | 0 | - | - | n/a | RW |
x | x | 0 | 1 | - | - | - | RW |
x | x | 1 | 1 | - | n/a | - | RW |
This table applies to all instructions that can access this register.
If an interrupt is pending within the CPU interface when an Enable bit becomes 0, the interrupt must be released to allow the Distributor to forward the interrupt to a different PE.
This register is only accessible when executing in Monitor mode.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_MSRE.SRE==0, accesses to this register from EL3 are UNDEFINED.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If HSTR_EL2.T12==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T12==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HSTR.T12==1, Non-secure accesses to this register from EL1 are trapped to Hyp mode.
28/09/2017 08:24
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