The ICC_HPPIR1_EL1 characteristics are:
Indicates the highest priority pending Group 1 interrupt on the CPU interface.
This register is part of:
AArch64 System register ICC_HPPIR1_EL1 performs the same function as AArch32 System register ICC_HPPIR1.
ICC_HPPIR1_EL1 is a 32-bit register.
The ICC_HPPIR1_EL1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | INTID |
Reserved, RES0.
The INTID of the highest priority pending interrupt, if that interrupt is observable at the current Security state and Exception level.
If the highest priority pending interrupt is not observable, this field contains a special INTID to indicate the reason. These special INTIDs can be one of: 1020, 1021, or 1023. See Special INTIDs, for more information.
This field has either 16 or 24 bits implemented. The number of implemented bits can be found in ICC_CTLR_EL1.IDbits and ICC_CTLR_EL3.IDbits. If only 16 bits are implemented, bits [23:16] of this register are RES0.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
ICC_HPPIR1_EL1 | 11 | 000 | 1100 | 1100 | 010 |
When HCR_EL2.IMO is set to 1, execution of this encoding at Non-secure EL1 results in an access to ICV_HPPIR1_EL1.
The register is accessible as follows:
Control | Accessibility | ||||||
---|---|---|---|---|---|---|---|
FMO | IMO | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | x | 0 | - | RO | n/a | RO |
x | x | 1 | 1 | - | n/a | RO | RO |
x | 0 | 0 | 1 | - | RO | RO | RO |
x | 1 | 0 | 1 | - | ICV_HPPIR1_EL1 | RO | RO |
This table applies to all instructions that can access this register.
ICC_HPPIR1_EL1 is only accessible at Non-secure EL1 when HCR_EL2.IMO is set to 0.
When HCR_EL2.IMO is set to 1, at Non-secure EL1, the instruction encoding used to access ICC_HPPIR1_EL1 results in an access to ICV_HPPIR1_EL1.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_SRE_EL1.SRE==0, read accesses to this register from EL1 are trapped to EL1.
If ICC_SRE_EL2.SRE==0, read accesses to this register from EL2 are trapped to EL2.
If ICC_SRE_EL3.SRE==0, read accesses to this register from EL3 are trapped to EL3.
When SCR_EL3.NS==1 :
If ICH_HCR_EL2.TALL1==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL3 is implemented and is using AArch64 and SCR_EL3.NS==0 :
If SCR_EL3.IRQ==1, Secure read accesses to this register from EL1 are trapped to EL3.
When EL3 is implemented and is using AArch64 :
If SCR_EL3.IRQ==1, read accesses to this register from EL2 are trapped to EL3.
When EL3 is implemented and is using AArch64 and SCR_EL3.NS==1 :
28/09/2017 08:24
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