GICC_AIAR, CPU Interface Aliased Interrupt Acknowledge Register

The GICC_AIAR characteristics are:

Purpose

Provides the INTID of the signaled Group 1 interrupt. A read of this register by the PE acts as an acknowledge for the interrupt.

This register is part of the GIC physical CPU interface registers functional group.

Usage constraints

This register is accessible as follows:

Security disabledSecureNon-secure
RORORO

When affinity routing is enabled for a Security state, it is a programming error to use memory-mapped registers to access the GIC.

Configuration

When GICD_CTLR.DS==0, this register is an alias of the Non-secure view of GICC_IAR. A Secure access to this register is identical to a Non-secure access to GICC_IAR.

Attributes

GICC_AIAR is a 32-bit register.

Field descriptions

The GICC_AIAR bit assignments are:

313029282726252423222120191817161514131211109876543210
00000000INTID

Bits [31:24]

Reserved, RES0.

INTID, bits [23:0]

The INTID of the signaled interrupt.

Note

INTIDs 1020-1023 are reserved and convey additional information such as spurious interrupts.

When affinity routing is not enabled:

Accessing the GICC_AIAR

GICC_AIAR can be accessed through its memory-mapped interface:

ComponentOffset
GIC CPU interface0x0020-0x003C



28/09/2017 08:24

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