The CTIGATE characteristics are:
Determines whether events on channels propagate through the CTM to other ECT components, or from the CTM into the CTI.
This register is part of the Cross-Trigger Interface registers functional group.
This register is accessible as follows:
SLK | Default |
---|---|
RO | RW |
CTIGATE is in the Debug power domain. RW fields in this register reset to architecturally UNKNOWN values. These apply only on an External debug reset. The register is not affected by a Warm reset and is not affected by a Cold reset.
CTIGATE is a 32-bit register.
The CTIGATE bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GATE<x>, bit [x] |
Channel <x> gate enable.
Bits [31:N] are RAZ/WI. N is the number of ECT channels implemented as defined by the CTIDEVID.NUMCHAN field.
Possible values of this bit are:
GATE<x> | Meaning |
---|---|
0 |
Disable output and, if CTIDEVID.INOUT == 0b01, input channel <x> propagation. |
1 |
Enable output and, if CTIDEVID.INOUT == 0b01, input channel <x> propagation. |
If GATE[x] is set to 0, no new events will be propagated to the ECT, and if the ECT supports multicycle channel events any existing output channel events will be terminated.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
CTIGATE can be accessed through the external debug interface:
Component | Offset |
---|---|
CTI | 0x140 |
28/09/2017 08:24
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