GICC_ABPR, CPU Interface Aliased Binary Point Register

The GICC_ABPR characteristics are:

Purpose

Defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field. The group priority field determines Group 1 interrupt preemption.

This register is part of the GIC physical CPU interface registers functional group.

Usage constraints

This register is accessible as follows:

Security disabledSecureNon-secure
RWRWRW

This register is used only when System register access is not enabled. When System register access is enabled, the System registers ICC_BPR0_EL1 and ICC_BPR1_EL1 provide equivalent functionality.

Configuration

Some or all RW fields of this register have defined reset values.

In systems that support two Security states:

Attributes

The reset value of this register is defined as (minimum GICC_BPR.Binary_Point + 1), resulting in a permitted range of 0x1-0x4.

Field descriptions

The GICC_ABPR bit assignments are:

313029282726252423222120191817161514131211109876543210
00000000000000000000000000000Binary_Point

Bits [31:3]

Reserved, RES0.

Binary_Point, bits [2:0]

Controls how the 8-bit interrupt priority field is split into a group priority field, that determines interrupt preemption, and a subpriority field. The following list describes how this field determines the interrupt priority bits assigned to the group priority field:

When this register has an architecturally-defined reset value, this field resets to an architecturally UNKNOWN value.

Accessing the GICC_ABPR

GICC_ABPR can be accessed through its memory-mapped interface:

ComponentOffset
GIC CPU interface 0x001C



28/09/2017 08:24

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