no old filehtmldiff from-SysReg_v83A_xml-00bet4(new) SysReg_v83A_xml-00bet5

PMSCR_EL1, Statistical Profiling Control Register (EL1)

The PMSCR_EL1 characteristics are:

Purpose

Provides EL1 controls for Statistical Profiling

This register is part of the Statistical Profiling Extension registers functional group.

Configuration

Present only if the Statistical Profiling Extension is implemented. Direct reads and writes of PMSCR_EL1 are UNDEFINED otherwise

Attributes

PMSCR_EL1 is a 64-bit register.

Field descriptions

The PMSCR_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
00000000000000000000000000000000
0000000000000000000000000PCTTSPACX0E1SPEE0SPE
313029282726252423222120191817161514131211109876543210

Bits [63:7]

Reserved, RES0.

Bit [2]

Reserved, RES0.

PCT, bit [6]

Physical Timestamp

If timestamp sampling is enabled, determines which counter is collected

PCTMeaning
0b0

Virtual counter, CNTVCT_EL0, is collected

0b1

Physical counter, CNTPCT_EL0, is collected

If MDCR_EL2.E2PB != 0b00 and the PE is in Non-secure state, this bit is combined with PMSCR_EL2.PCT to determine which counter is collected

This bit is ignored by the PE when in Non-secure state and MDCR_EL2.E2PB == 0b00.

If EL2 is not implemented this bit is RES1.

TS, bit [5]

Timestamp Enable

TSMeaning
0b0

Timestamp sampling disabled

0b1

Timestamp sampling enabled

This bit is ignored by the PE when in Non-secure state and MDCR_EL2.E2PB == 0b00.

PA, bit [4]

Physical Address Sample Enable

PAMeaning
0b0

Physical addresses are not collected

0b1

Physical addresses are collected

If MDCR_EL2.E2PB != 0b00 and the PE is in Non-secure state, this bit is combined with PMSCR_EL2.PA to determine which address is collected

This bit is ignored by the PE when in Non-secure state and MDCR_EL2.E2PB == 0b00.

CX, bit [3]

CONTEXTIDR_EL1 Sample Enable

CXMeaning
0b0

CONTEXTIDR_EL1 is not collected

0b1

CONTEXTIDR_EL1 is collected

This bit is ignored by the PE when any of the following are true:

E1SPE, bit [1]

EL1 Statistical Profiling Enable

E1SPEMeaning
0b0

Sampling disabled at EL1

0b1

Sampling enabled at EL1

This bit is ignored by the PE when in Non-secure state and HCR_EL2.TGE == 1.

E0SPE, bit [0]

EL0 Statistical Profiling Enable

E0SPEMeaning
0b0

Sampling disabled at EL0

0b1

Sampling enabled at EL0

This bit is ignored by the PE when in Non-secure state and HCR_EL2.TGE == 1.

Accessing the PMSCR_EL1

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> CRnop0op1op2CRm
PMSCR_EL11001110000001001
PMSCR_EL121001111010001001

Accessibility

The register is accessible as follows:

<systemreg> Control Accessibility
E2HTGENSEL0EL1EL2EL3
PMSCR_EL1xx0 - RW n/a RW
PMSCR_EL1001 - RWRWRW
PMSCR_EL1011 - n/a RWRW
PMSCR_EL1101 - RWPMSCR_EL2RW
PMSCR_EL1111 - n/a PMSCR_EL2RW
PMSCR_EL12xx0 - - n/a -
PMSCR_EL12001 - - - -
PMSCR_EL12011 - n/a - -
PMSCR_EL12101 - - RWRW
PMSCR_EL12111 - n/a RWRW

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.




12/09/2017 18:03

Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.

no old filehtmldiff from-SysReg_v83A_xml-00bet4(new) SysReg_v83A_xml-00bet5