The ICC_ASGI1R_EL1 characteristics are:
Generates Group 1 SGIs for the Security state that is not the current Security state.
This register is part of:
AArch64 System register ICC_ASGI1R_EL1 performs the same function as AArch32 System register ICC_ASGI1R.
Under certain conditions a write to ICC_ASGI1R_EL1 can generate Group 0 interrupts, see Forwarding an SGI to a target PE.
ICC_ASGI1R_EL1 is a 64-bit register.
The ICC_ASGI1R_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Aff3 | RS | 0 | 0 | 0 | IRM | Aff2 | |||||||||||||||||
0 | 0 | 0 | 0 | INTID | Aff1 | TargetList | |||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
The affinity 3 value of the affinity path of the cluster for which SGI interrupts will be generated.
If the IRM bit is 1, this field is RES0.
RangeSelector
Controls which group of 16 values is represented by the TargetList field.
TargetList[n] represents aff0 value ((RS * 16) + n).
When ICC_CTLR_EL3.RSS==0 or ICC_CTLR_EL1.RSS==0, RS is RES0.
When ICC_CTLR_EL1}.RSS==1 and GICD_TYPER.RSS==0, writing this register with RS != 0 is a CONSTRAINED UNPREDICTABLE choice of :
Reserved, RES0.
Interrupt Routing Mode. Determines how the generated interrupts are distributed to PEs. Possible values are:
IRM | Meaning |
---|---|
0 |
Interrupts routed to the PEs specified by Aff3.Aff2.Aff1.<target list>. |
1 |
Interrupts routed to all PEs in the system, excluding "self". |
The affinity 2 value of the affinity path of the cluster for which SGI interrupts will be generated.
If the IRM bit is 1, this field is RES0.
Reserved, RES0.
The INTID of the SGI.
The affinity 1 value of the affinity path of the cluster for which SGI interrupts will be generated.
If the IRM bit is 1, this field is RES0.
Target List. The set of PEs for which SGI interrupts will be generated. Each bit corresponds to the PE within a cluster with an Affinity 0 value equal to the bit number.
If a bit is 1 and the bit does not correspond to a valid target PE, the bit must be ignored by the Distributor. It is IMPLEMENTATION DEFINED whether, in such cases, a Distributor can signal a system error.
This restricts a system to sending targeted SGIs to PEs with an affinity 0 number that is less than 16.
If SRE is set only for Secure EL3, software executing at EL3 might use the System register interface to generate SGIs. Therefore, the Distributor must always be able to receive and acknowledge Generate SGI packets received from CPU interface regardless of the ARE settings for a Security state. However, the Distributor might discard such packets.
If the IRM bit is 1, this field is RES0.
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
ICC_ASGI1R_EL1 | 11 | 000 | 1100 | 1011 | 110 |
The register is accessible as follows:
Control | Accessibility | ||||
---|---|---|---|---|---|
TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | 0 | - | WO | n/a | WO |
0 | 1 | - | WO | WO | WO |
1 | 1 | - | n/a | WO | WO |
This table applies to all instructions that can access this register.
This register allows software executing in a Secure state to generate Non-secure Group 1 SGIs. It will also allow software executing in a Non-secure state to generate Secure Group 1 SGIs, if permitted by the settings of GICR_NSACR in the Redistributor corresponding to the target PE.
When GICD_CTLR.DS==0, Non-secure writes do not generate an interrupt for a target PE if not permitted by the GICR_NSACR register associated with the target PE. For more information see Use of control registers for SGI forwarding.
Accesses at EL3 are treated as Secure regardless of the value of SCR_EL3.NS.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_SRE_EL1.SRE==0, write accesses to this register from EL1 are trapped to EL1.
If ICC_SRE_EL2.SRE==0, write accesses to this register from EL2 are trapped to EL2.
If ICC_SRE_EL3.SRE==0, write accesses to this register from EL3 are trapped to EL3.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If HCR_EL2.FMO==1, Non-secure write accesses to this register from EL1 are trapped to EL2.
If HCR_EL2.IMO==1, Non-secure write accesses to this register from EL1 are trapped to EL2.
When SCR_EL3.NS==1 :
If ICH_HCR_EL2.TC==1, Non-secure write accesses to this register from EL1 are trapped to EL2.
When EL3 is implemented and is using AArch64 and SCR_EL3.NS==0 :
If SCR_EL3.FIQ==1, and SCR_EL3.IRQ==1, Secure write accesses to this register from EL1 are trapped to EL3.
When EL3 is implemented and is using AArch64 :
When EL3 is implemented and is using AArch64 and SCR_EL3.NS==1 :
28/09/2017 08:24
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