The MAIR1 characteristics are:
Along with MAIR0, provides the memory attribute encodings corresponding to the possible AttrIndx values in a Long-descriptor format translation table entry for stage 1 translations.
AttrIndx[2] indicates the MAIR register to be used:
This register is part of the Virtual memory control registers functional group.
AArch32 System register MAIR1 is architecturally mapped to AArch64 System register MAIR_EL1[63:32] when TTBCR.EAE==1.
MAIR1 and NMRR are the same register, with a different view depending on the value of TTBCR.EAE:
When EL3 is using AArch32, write access to MAIR1(S) is disabled when the CP15SDISABLE signal is asserted HIGH.
RW fields in this register reset to architecturally UNKNOWN values.
MAIR1 is a 32-bit register.
The MAIR1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Attr7 | Attr6 | Attr5 | Attr4 |
The memory attribute encoding for an AttrIndx[2:0] entry in a Long descriptor format translation table entry, where:
Bits [7:4] are encoded as follows:
Attr<n>[7:4] | Meaning |
---|---|
0000 | Device memory. See encoding of Attr<n>[3:0] for the type of Device memory. |
00RW, RW not 00 | Normal memory, Outer Write-Through Transient |
0100 | Normal memory, Outer Non-cacheable |
01RW, RW not 00 | Normal memory, Outer Write-Back Transient |
10RW | Normal memory, Outer Write-Through Non-transient |
11RW | Normal memory, Outer Write-Back Non-transient |
R = Outer Read-Allocate policy, W = Outer Write-Allocate policy.
The meaning of bits [3:0] depends on the value of bits [7:4]:
Attr<n>[3:0] | Meaning when Attr<n>[7:4] is 0000 | Meaning when Attr<n>[7:4] is not 0000 |
---|---|---|
0000 | Device-nGnRnE memory | UNPREDICTABLE |
00RW, RW not 00 | UNPREDICTABLE | Normal memory, Inner Write-Through Transient |
0100 | Device-nGnRE memory | Normal memory, Inner Non-cacheable |
01RW, RW not 00 | UNPREDICTABLE | Normal memory, Inner Write-Back Transient |
1000 | Device-nGRE memory | Normal memory, Inner Write-Through Non-transient (RW=00) |
10RW, RW not 00 | UNPREDICTABLE | Normal memory, Inner Write-Through Non-transient |
1100 | Device-GRE memory | Normal memory, Inner Write-Back Non-transient (RW=00) |
11RW, RW not 00 | UNPREDICTABLE | Normal memory, Inner Write-Back Non-transient |
R = Inner Read-Allocate policy, W = Inner Write-Allocate policy.
The R and W bits in some Attr<n> fields have the following meanings:
R or W | Meaning |
---|---|
0 | No Allocate |
1 | Allocate |
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c10, c2, 1 | 000 | 001 | 1010 | 1111 | 0010 |
The register is accessible as follows:
Configuration | Control | Accessibility | Instance | |||||
---|---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | ||
EL3 using AArch32 | x | x | 0 | - | n/a | n/a | RW | MAIR1_s |
EL3 using AArch32 | x | 0 | 1 | - | RW | RW | RW | MAIR1_ns |
EL3 using AArch32 | x | 1 | 1 | - | n/a | RW | RW | MAIR1_ns |
EL3 not implemented | x | x | 0 | - | RW | n/a | n/a | MAIR1 |
EL3 not implemented | x | 0 | 1 | - | RW | RW | n/a | MAIR1 |
EL3 not implemented | x | 1 | 1 | - | n/a | RW | n/a | MAIR1 |
EL3 using AArch64 | x | x | 0 | - | RW | n/a | n/a | MAIR1 |
EL3 using AArch64 | x | 0 | 1 | - | RW | RW | n/a | MAIR1 |
EL3 using AArch64 | x | 1 | 1 | - | n/a | RW | n/a | MAIR1 |
This table applies to all instructions that can access this register.
When EL3 is using AArch32, write access to MAIR1_s is UNDEFINED when the CP15SDISABLE signal is asserted HIGH.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TVM==1, Non-secure write accesses to this register from EL1 are trapped to EL2.
If HCR_EL2.TRVM==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HSTR_EL2.T10==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TVM==1, Non-secure write accesses to this register from EL1 are trapped to EL2.
If HCR_EL2.TRVM==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HSTR_EL2.T10==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
28/09/2017 08:24
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