SysReg_v83A_xml-00bet4 (old)htmldiff from-SysReg_v83A_xml-00bet4(new) SysReg_v83A_xml-00bet5

System Register index by instruction and encoding

Below are indexes for registers and operations accessed in the following ways:

For AArch32

For AArch64

Registers and operations in AArch32

Accessed using MRC/MCR/MRC:

Register selectors Name Description
opc1 opc2 CRn coproc CRm
coprocopc1CRnCRmopc2
000 000 0000 1110 0000 DBGDIDR Debug ID Register
111000000000000000DBGDIDRDebug ID Register
111 000 0000 1110 0000 JIDR Jazelle ID Register
111000000000000010DBGDTRRXextDebug OS Lock Data Transfer Register, Receive, External View
000 010 0000 1110 0000 DBGDTRRXext Debug OS Lock Data Transfer Register, Receive, External View
111000000000001000DBGDSCRintDebug Status and Control Register, Internal View
000 000 0001 1110 0000 DBGDRAR Debug ROM Address Register
111000000000010000DBGDCCINTDCC Interrupt Enable Register
111 000 0001 1110 0000 JOSCR Jazelle OS Control Register
111000000000010010DBGDSCRextDebug Status and Control Register, External View
000 100 0001 1110 0000 DBGOSLAR Debug OS Lock Access Register
111000000000011010DBGDTRTXextDebug OS Lock Data Transfer Register, Transmit
000 000 0010 1110 0000 DBGDSAR Debug Self Address Register
111000000000101000DBGDTRRXintDebug Data Transfer Register, Receive
111 000 0010 1110 0000 JMCR Jazelle Main Configuration Register
111000000000101000DBGDTRTXintDebug Data Transfer Register, Transmit
000 111 0111 1110 0000 DBGDEVID2 Debug Device ID register 2
111000000000110000DBGWFARDebug Watchpoint Fault Address Register
000 000 0000 1111 0000 MIDR Main ID Register
111000000000110010DBGOSECCRDebug OS Lock Exception Catch Control Register
0011110 000 0000 11110111 0000000 CCSIDR DBGVCR CurrentDebug CacheVector Size IDCatch Register
0101110 000 0000 1111xxxx 0000100 CSSELR DBGBVR<n> CacheDebug SizeBreakpoint SelectionValue RegisterRegisters
1001110 000 0000 1111xxxx 0000101 VPIDR DBGBCR<n> VirtualizationDebug ProcessorBreakpoint IDControl RegisterRegisters
000 001 0000 1111 0000 CTR Cache Type Register
11100000000xxxx110DBGWVR<n>Debug Watchpoint Value Registers
0011110 001000 0000 1111xxxx 0000111 CLIDR DBGWCR<n> CacheDebug LevelWatchpoint IDControl RegisterRegisters
000 010 0000 1111 0000 TCMTR TCM Type Register
111000000010000000DBGDRARDebug ROM Address Register
001 010 0000 1111 0000 CCSIDR2 Current Cache Size ID Register 2
111000000010000100DBGOSLARDebug OS Lock Access Register
000 011 0000 1111 0000 TLBTR TLB Type Register
111000000010001100DBGOSLSRDebug OS Lock Status Register
000 101 0000 1111 0000 MPIDR Multiprocessor Affinity Register
111000000010011100DBGOSDLRDebug OS Double Lock Register
100 101 0000 1111 0000 VMPIDR Virtualization Multiprocessor ID Register
111000000010100100DBGPRCRDebug Power Control Register
000 110 0000 1111 0000 REVIDR Revision ID Register
11100000001xxxx001DBGBXVR<n>Debug Breakpoint Extended Value Registers
001 111 0000 1111 0000 AIDR Auxiliary ID Register
111000000100000000DBGDSARDebug Self Address Register
000 000 0001 1111 0000 SCTLR System Control Register
111000001110000111DBGDEVID2Debug Device ID register 2
100 000 0001 1111 0000 HSCTLR Hyp System Control Register
111000001110001111DBGDEVID1Debug Device ID register 1
000 001 0001 1111 0000 ACTLR Auxiliary Control Register
111000001110010111DBGDEVIDDebug Device ID register 0
1001110 001000 00010111 11111000 0000110 HACTLR DBGCLAIMSET HypDebug AuxiliaryClaim ControlTag RegisterSet register
000 010 0001 1111 0000 CPACR Architectural Feature Access Control Register
111000001111001110DBGCLAIMCLRDebug Claim Tag Clear register
000 011 0001 1111 0000 ACTLR2 Auxiliary Control Register 2
111000001111110110DBGAUTHSTATUSDebug Authentication Status register
100 011 0001 1111 0000 HACTLR2 Hyp Auxiliary Control Register 2
111011100000000000JIDRJazelle ID Register
000 000 0010 1111 0000 TTBR0 Translation Table Base Register 0
111011100010000000JOSCRJazelle OS Control Register
000 001 0010 1111 0000 TTBR1 Translation Table Base Register 1
111011100100000000JMCRJazelle Main Configuration Register
000 010 0010 1111 0000 TTBCR Translation Table Base Control Register
111100000000000000MIDRMain ID Register
100 010 0010 1111 0000 HTCR Hyp Translation Control Register
111100000000000001CTRCache Type Register
000 011 0010 1111 0000 TTBCR2 Translation Table Base Control Register 2
111100000000000010TCMTRTCM Type Register
000 000 0011 1111 0000 DACR Domain Access Control Register
111100000000000011TLBTRTLB Type Register
000 000 0101 1111 0000 DFSR Data Fault Status Register
111100000000000101MPIDRMultiprocessor Affinity Register
000 001 0101 1111 0000 IFSR Instruction Fault Status Register
111100000000000110REVIDRRevision ID Register
000 000 0110 1111 0000 DFAR Data Fault Address Register
111100000000001000ID_PFR0Processor Feature Register 0
100 000 0110 1111 0000 HDFAR Hyp Data Fault Address Register
111100000000001001ID_PFR1Processor Feature Register 1
000 010 0110 1111 0000 IFAR Instruction Fault Address Register
111100000000001010ID_DFR0Debug Feature Register 0
100 010 0110 1111 0000 HIFAR Hyp Instruction Fault Address Register
111100000000001011ID_AFR0Auxiliary Feature Register 0
100 100 0110 1111 0000 HPFAR Hyp IPA Fault Address Register
111100000000001100ID_MMFR0Memory Model Feature Register 0
100 001 1000 1111 0000 TLBIIPAS2IS TLB Invalidate by Intermediate Physical Address, Stage 2, Inner Shareable
111100000000001101ID_MMFR1Memory Model Feature Register 1
100 101 1000 1111 0000 TLBIIPAS2LIS TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, Inner Shareable
111100000000001110ID_MMFR2Memory Model Feature Register 2
000 000 1100 1111 0000 VBAR Vector Base Address Register
111100000000001111ID_MMFR3Memory Model Feature Register 3
100 000 1100 1111 0000 HVBAR Hyp Vector Base Address Register
111100000000010000ID_ISAR0Instruction Set Attribute Register 0
000 001 1100 1111 0000 MVBAR Monitor Vector Base Address Register
111100000000010001ID_ISAR1Instruction Set Attribute Register 1
000 001 1100 1111 0000 RVBAR Reset Vector Base Address Register
111100000000010010ID_ISAR2Instruction Set Attribute Register 2
000 010 1100 1111 0000 RMR Reset Management Register
111100000000010011ID_ISAR3Instruction Set Attribute Register 3
100 010 1100 1111 0000 HRMR Hyp Reset Management Register
111100000000010100ID_ISAR4Instruction Set Attribute Register 4
000 000 1101 1111 0000 FCSEIDR FCSE Process ID register
111100000000010101ID_ISAR5Instruction Set Attribute Register 5
000 001 1101 1111 0000 CONTEXTIDR Context ID Register
111100000000010110ID_MMFR4Memory Model Feature Register 4
000 010 1101 1111 0000 TPIDRURW PL0 Read/Write Software Thread ID Register
111100000000010111ID_ISAR6Instruction Set Attribute Register 6
100 010 1101 1111 0000 HTPIDR Hyp Software Thread ID Register
111100000010000000SCTLRSystem Control Register
000 011 1101 1111 0000 TPIDRURO PL0 Read-Only Software Thread ID Register
111100000010000001ACTLRAuxiliary Control Register
000 100 1101 1111 0000 TPIDRPRW PL1 Software Thread ID Register
111100000010000010CPACRArchitectural Feature Access Control Register
000 000 1110 1111 0000 CNTFRQ Counter-timer Frequency register
111100000010000011ACTLR2Auxiliary Control Register 2
000 000 0000 1110 0001 DBGDSCRint Debug Status and Control Register, Internal View
111100000010001000SCRSecure Configuration Register
000 100 0001 1110 0001 DBGOSLSR Debug OS Lock Status Register
111100000010001001SDERSecure Debug Enable Register
000 111 0111 1110 0001 DBGDEVID1 Debug Device ID register 1
111100000010001010NSACRNon-Secure Access Control Register
000 000 0000 1111 0001 ID_PFR0 Processor Feature Register 0
111100000010011001SDCRSecure Debug Control Register
000 001 0000 1111 0001 ID_PFR1 Processor Feature Register 1
111100000100000000TTBR0Translation Table Base Register 0
000 010 0000 1111 0001 ID_DFR0 Debug Feature Register 0
111100000100000001TTBR1Translation Table Base Register 1
000 011 0000 1111 0001 ID_AFR0 Auxiliary Feature Register 0
111100000100000010TTBCRTranslation Table Base Control Register
000 100 0000 1111 0001 ID_MMFR0 Memory Model Feature Register 0
111100000100000011TTBCR2Translation Table Base Control Register 2
000 101 0000 1111 0001 ID_MMFR1 Memory Model Feature Register 1
111100000110000000DACRDomain Access Control Register
000 110 0000 1111 0001 ID_MMFR2 Memory Model Feature Register 2
111100001000110000ICC_PMRInterrupt Controller Interrupt Priority Mask Register
000 111 0000 1111 0001 ID_MMFR3 Memory Model Feature Register 3
111100001000110000ICV_PMRInterrupt Controller Virtual Interrupt Priority Mask Register
000 000 0001 1111 0001 SCR Secure Configuration Register
111100001010000000DFSRData Fault Status Register
1001111 000 00010101 11110000 0001001 HCR IFSR HypInstruction ConfigurationFault Status Register
000 001 0001 1111 0001 SDER Secure Debug Enable Register
111100001010001000ADFSRAuxiliary Data Fault Status Register
100 001 0001 1111 0001 HDCR Hyp Debug Control Register
111100001010001001AIFSRAuxiliary Instruction Fault Status Register
000 010 0001 1111 0001 NSACR Non-Secure Access Control Register
111100001100000000DFARData Fault Address Register
100 010 0001 1111 0001 HCPTR Hyp Architectural Feature Trap Register
111100001100000010IFARInstruction Fault Address Register
100 011 0001 1111 0001 HSTR Hyp System Trap Register
111100001110001000ICIALLUISInstruction Cache Invalidate All to PoU, Inner Shareable
100 100 0001 1111 0001 HCR2 Hyp Configuration Register 2
111100001110001110BPIALLISBranch Predictor Invalidate All, Inner Shareable
100 111 0001 1111 0001 HACR Hyp Auxiliary Configuration Register
111100001110100000PARPhysical Address Register
100 010 0010 1111 0001 VTCR Virtualization Translation Control Register
111100001110101000ICIALLUInstruction Cache Invalidate All to PoU
000 000 0101 1111 0001 ADFSR Auxiliary Data Fault Status Register
111100001110101001ICIMVAUInstruction Cache line Invalidate by VA to PoU
100 000 0101 1111 0001 HADFSR Hyp Auxiliary Data Fault Status Register
111100001110101100CP15ISBInstruction Synchronization Barrier System instruction
000 001 0101 1111 0001 AIFSR Auxiliary Instruction Fault Status Register
111100001110101110BPIALLBranch Predictor Invalidate All
100 001 0101 1111 0001 HAIFSR Hyp Auxiliary Instruction Fault Status Register
111100001110101111BPIMVABranch Predictor Invalidate by VA
000 000 0111 1111 0001 ICIALLUIS Instruction Cache Invalidate All to PoU, Inner Shareable
111100001110110001DCIMVACData Cache line Invalidate by VA to PoC
000 110 0111 1111 0001 BPIALLIS Branch Predictor Invalidate All, Inner Shareable
111100001110110010DCISWData Cache line Invalidate by Set/Way
000 000 1100 1111 0001 ISR Interrupt Status Register
111100001111000000ATS1CPRAddress Translate Stage 1 Current state PL1 Read
000 000 1110 1111 0001 CNTKCTL Counter-timer Kernel Control register
111100001111000001ATS1CPWAddress Translate Stage 1 Current state PL1 Write
1001111 000 11100111 11111000 0001010 CNTHCTL ATS1CUR Counter-timerAddress HypTranslate ControlStage register1 Current state Unprivileged Read
000 000 0000 1110 0010 DBGDCCINT DCC Interrupt Enable Register
111100001111000011ATS1CUWAddress Translate Stage 1 Current state Unprivileged Write
000 010 0000 1110 0010 DBGDSCRext Debug Status and Control Register, External View
111100001111000100ATS12NSOPRAddress Translate Stages 1 and 2 Non-secure Only PL1 Read
000 111 0111 1110 0010 DBGDEVID Debug Device ID register 0
111100001111000101ATS12NSOPWAddress Translate Stages 1 and 2 Non-secure Only PL1 Write
000 000 0000 1111 0010 ID_ISAR0 Instruction Set Attribute Register 0
111100001111000110ATS12NSOURAddress Translate Stages 1 and 2 Non-secure Only Unprivileged Read
000 001 0000 1111 0010 ID_ISAR1 Instruction Set Attribute Register 1
111100001111000111ATS12NSOUWAddress Translate Stages 1 and 2 Non-secure Only Unprivileged Write
000 010 0000 1111 0010 ID_ISAR2 Instruction Set Attribute Register 2
111100001111001000ATS1CPRPAddress Translate Stage 1 Current state PL1 Read PAN
000 011 0000 1111 0010 ID_ISAR3 Instruction Set Attribute Register 3
111100001111001001ATS1CPWPAddress Translate Stage 1 Current state PL1 Write PAN
000 100 0000 1111 0010 ID_ISAR4 Instruction Set Attribute Register 4
111100001111010001DCCMVACData Cache line Clean by VA to PoC
000 101 0000 1111 0010 ID_ISAR5 Instruction Set Attribute Register 5
111100001111010010DCCSWData Cache line Clean by Set/Way
000 110 0000 1111 0010 ID_MMFR4 Memory Model Feature Register 4
111100001111010100CP15DSBData Synchronization Barrier System instruction
000 111 0000 1111 0010 ID_ISAR6 Instruction Set Attribute Register 6
111100001111010101CP15DMBData Memory Barrier System instruction
1001111 000 01010111 11111011 0010001 HSR DCCMVAU HypData SyndromeCache Registerline Clean by VA to PoU
000 000 1010 1111 0010 MAIR0 Memory Attribute Indirection Register 0
111100001111110001DCCIMVACData Cache line Clean and Invalidate by VA to PoC
000 000 1010 1111 0010 PRRR Primary Region Remap Register
111100001111110010DCCISWData Cache line Clean and Invalidate by Set/Way
1001111 000 10101000 11110011 0010000 HMAIR0 TLBIALLIS HypTLB MemoryInvalidate AttributeAll, IndirectionInner Register 0Shareable
000 001 1010 1111 0010 MAIR1 Memory Attribute Indirection Register 1
111100010000011001TLBIMVAISTLB Invalidate by VA, Inner Shareable
000 001 1010 1111 0010 NMRR Normal Memory Remap Register
111100010000011010TLBIASIDISTLB Invalidate by ASID match, Inner Shareable
100 001 1010 1111 0010 HMAIR1 Hyp Memory Attribute Indirection Register 1
111100010000011011TLBIMVAAISTLB Invalidate by VA, All ASID, Inner Shareable
000 000 1110 1111 0010 CNTP_TVAL Counter-timer Physical Timer TimerValue register
111100010000011101TLBIMVALISTLB Invalidate by VA, Last level, Inner Shareable
1001111 000 11101000 11110011 0010111 CNTHP_TVAL TLBIMVAALIS Counter-timerTLB HypInvalidate Physicalby TimerVA, TimerValueAll registerASID, Last level, Inner Shareable
000 001 1110 1111 0010 CNTP_CTL Counter-timer Physical Timer Control register
111100010000101000ITLBIALLInstruction TLB Invalidate All
100 001 1110 1111 0010 CNTHP_CTL Counter-timer Hyp Physical Timer Control register
111100010000101001ITLBIMVAInstruction TLB Invalidate by VA
000 010 0000 1110 0011 DBGDTRTXext Debug OS Lock Data Transfer Register, Transmit
111100010000101010ITLBIASIDInstruction TLB Invalidate by ASID match
000 100 0001 1110 0011 DBGOSDLR Debug OS Double Lock Register
111100010000110000DTLBIALLData TLB Invalidate All
000 001 0001 1111 0011 SDCR Secure Debug Control Register
111100010000110001DTLBIMVAData TLB Invalidate by VA
000 000 1000 1111 0011 TLBIALLIS TLB Invalidate All, Inner Shareable
111100010000110010DTLBIASIDData TLB Invalidate by ASID match
1001111 000 1000 11110111 0011000 TLBIALLHIS TLBIALL TLB Invalidate All, Hyp mode, Inner Shareable
000 001 1000 1111 0011 TLBIMVAIS TLB Invalidate by VA, Inner Shareable
111100010000111001TLBIMVATLB Invalidate by VA
1001111 001000 1000 11110111 0011010 TLBIMVAHIS TLBIASID TLB Invalidate by VA,ASID Hyp mode, Inner Shareablematch
000 010 1000 1111 0011 TLBIASIDIS TLB Invalidate by ASID match, Inner Shareable
111100010000111011TLBIMVAATLB Invalidate by VA, All ASID
000 011 1000 1111 0011 TLBIMVAAIS TLB Invalidate by VA, All ASID, Inner Shareable
111100010000111101TLBIMVALTLB Invalidate by VA, Last level
1001111 100000 1000 11110111 0011111 TLBIALLNSNHIS TLBIMVAAL TLB Invalidate Allby VA, Non-SecureAll Non-HypASID, InnerLast Shareablelevel
000 101 1000 1111 0011 TLBIMVALIS TLB Invalidate by VA, Last level, Inner Shareable
111100010011100000PMCRPerformance Monitors Control Register
100 101 1000 1111 0011 TLBIMVALHIS TLB Invalidate by VA, Last level, Hyp mode, Inner Shareable
111100010011100001PMCNTENSETPerformance Monitors Count Enable Set register
000 111 1000 1111 0011 TLBIMVAALIS TLB Invalidate by VA, All ASID, Last level, Inner Shareable
111100010011100010PMCNTENCLRPerformance Monitors Count Enable Clear register
000 000 1010 1111 0011 AMAIR0 Auxiliary Memory Attribute Indirection Register 0
111100010011100011PMOVSRPerformance Monitors Overflow Flag Status Register
100 000 1010 1111 0011 HAMAIR0 Hyp Auxiliary Memory Attribute Indirection Register 0
111100010011100100PMSWINCPerformance Monitors Software Increment register
000 001 1010 1111 0011 AMAIR1 Auxiliary Memory Attribute Indirection Register 1
111100010011100101PMSELRPerformance Monitors Event Counter Selection Register
100 001 1010 1111 0011 HAMAIR1 Hyp Auxiliary Memory Attribute Indirection Register 1
111100010011100110PMCEID0Performance Monitors Common Event Identification register 0
000 000 1110 1111 0011 CNTHV_TVAL Counter-timer Virtual Timer TimerValue register (EL2)
111100010011100111PMCEID1Performance Monitors Common Event Identification register 1
000 000 1110 1111 0011 CNTV_TVAL Counter-timer Virtual Timer TimerValue register
111100010011101000PMCCNTRPerformance Monitors Cycle Count Register
000 001 1110 1111 0011 CNTHV_CTL Counter-timer Virtual Timer Control register (EL2)
111100010011101001PMXEVTYPERPerformance Monitors Selected Event Type Register
000 001 1110 1111 0011 CNTV_CTL Counter-timer Virtual Timer Control register
111100010011101010PMXEVCNTRPerformance Monitors Selected Event Count Register
000 100 0001 1110 0100 DBGPRCR Debug Power Control Register
111100010011110000PMUSERENRPerformance Monitors User Enable Register
000 000 0111 1111 0100 PAR Physical Address Register
111100010011110001PMINTENSETPerformance Monitors Interrupt Enable Set register
100 001 1000 1111 0100 TLBIIPAS2 TLB Invalidate by Intermediate Physical Address, Stage 2
111100010011110010PMINTENCLRPerformance Monitors Interrupt Enable Clear register
100 101 1000 1111 0100 TLBIIPAS2L TLB Invalidate by Intermediate Physical Address, Stage 2, Last level
111100010011110011PMOVSSETPerformance Monitors Overflow Flag Status Set register
000 000 0000 1110 0101 DBGDTRRXint Debug Data Transfer Register, Receive
111100010011110100PMCEID2Performance Monitors Common Event Identification register 2
000 000 0000 1110 0101 DBGDTRTXint Debug Data Transfer Register, Transmit
111100010011110101PMCEID3Performance Monitors Common Event Identification register 3
0111111 000 01001010 11110010 0101000 DSPSR PRRR DebugPrimary SavedRegion Program StatusRemap Register
011 001 0100 1111 0101 DLR Debug Link Register
111100010100010000MAIR0Memory Attribute Indirection Register 0
000 000 0111 1111 0101 ICIALLU Instruction Cache Invalidate All to PoU
111100010100010001NMRRNormal Memory Remap Register
000 001 0111 1111 0101 ICIMVAU Instruction Cache line Invalidate by VA to PoU
111100010100010001MAIR1Memory Attribute Indirection Register 1
000 100 0111 1111 0101 CP15ISB Instruction Synchronization Barrier System instruction
111100010100011000AMAIR0Auxiliary Memory Attribute Indirection Register 0
000 110 0111 1111 0101 BPIALL Branch Predictor Invalidate All
111100010100011001AMAIR1Auxiliary Memory Attribute Indirection Register 1
000 111 0111 1111 0101 BPIMVA Branch Predictor Invalidate by VA
111100011000000000VBARVector Base Address Register
000 000 1000 1111 0101 ITLBIALL Instruction TLB Invalidate All
111100011000000001MVBARMonitor Vector Base Address Register
000 001 1000 1111 0101 ITLBIMVA Instruction TLB Invalidate by VA
111100011000000001RVBARReset Vector Base Address Register
000 010 1000 1111 0101 ITLBIASID Instruction TLB Invalidate by ASID match
111100011000000010RMRReset Management Register
000 000 0000 1110 0110 DBGWFAR Debug Watchpoint Fault Address Register
111100011000001000ISRInterrupt Status Register
000 010 0000 1110 0110 DBGOSECCR Debug OS Lock Exception Catch Control Register
111100011001000000ICC_IAR0Interrupt Controller Interrupt Acknowledge Register 0
000 000 0100 1111 0110 ICC_PMR Interrupt Controller Interrupt Priority Mask Register
111100011001000000ICV_IAR0Interrupt Controller Virtual Interrupt Acknowledge Register 0
000 000 0100 1111 0110 ICV_PMR Interrupt Controller Virtual Interrupt Priority Mask Register
111100011001000001ICC_EOIR0Interrupt Controller End Of Interrupt Register 0
000 001 0111 1111 0110 DCIMVAC Data Cache line Invalidate by VA to PoC
111100011001000001ICV_EOIR0Interrupt Controller Virtual End Of Interrupt Register 0
000 010 0111 1111 0110 DCISW Data Cache line Invalidate by Set/Way
111100011001000010ICC_HPPIR0Interrupt Controller Highest Priority Pending Interrupt Register 0
000 000 1000 1111 0110 DTLBIALL Data TLB Invalidate All
111100011001000010ICV_HPPIR0Interrupt Controller Virtual Highest Priority Pending Interrupt Register 0
000 001 1000 1111 0110 DTLBIMVA Data TLB Invalidate by VA
111100011001000011ICC_BPR0Interrupt Controller Binary Point Register 0
000 010 1000 1111 0110 DTLBIASID Data TLB Invalidate by ASID match
111100011001000011ICV_BPR0Interrupt Controller Virtual Binary Point Register 0
000 000 0000 1110 0111 DBGVCR Debug Vector Catch Register
1111000110010001xxICC_AP0R<n>Interrupt Controller Active Priorities Group 0 Registers
000 000 1000 1111 0111 TLBIALL TLB Invalidate All
1111000110010001xxICV_AP0R<n>Interrupt Controller Virtual Active Priorities Group 0 Registers
1001111 000 10001100 11111001 01110xx TLBIALLH ICC_AP1R<n> TLBInterrupt InvalidateController All,Active HypPriorities modeGroup 1 Registers
000 001 1000 1111 0111 TLBIMVA TLB Invalidate by VA
1111000110010010xxICV_AP1R<n>Interrupt Controller Virtual Active Priorities Group 1 Registers
100 001 1000 1111 0111 TLBIMVAH TLB Invalidate by VA, Hyp mode
111100011001011001ICC_DIRInterrupt Controller Deactivate Interrupt Register
000 010 1000 1111 0111 TLBIASID TLB Invalidate by ASID match
111100011001011001ICV_DIRInterrupt Controller Deactivate Virtual Interrupt Register
000 011 1000 1111 0111 TLBIMVAA TLB Invalidate by VA, All ASID
111100011001011011ICC_RPRInterrupt Controller Running Priority Register
100 100 1000 1111 0111 TLBIALLNSNH TLB Invalidate All, Non-Secure Non-Hyp
111100011001011011ICV_RPRInterrupt Controller Virtual Running Priority Register
000 101 1000 1111 0111 TLBIMVAL TLB Invalidate by VA, Last level
111100011001100000ICC_IAR1Interrupt Controller Interrupt Acknowledge Register 1
100 101 1000 1111 0111 TLBIMVALH TLB Invalidate by VA, Last level, Hyp mode
111100011001100000ICV_IAR1Interrupt Controller Virtual Interrupt Acknowledge Register 1
000 111 1000 1111 0111 TLBIMVAAL TLB Invalidate by VA, All ASID, Last level
111100011001100001ICC_EOIR1Interrupt Controller End Of Interrupt Register 1
000 110 0111 1110 1000 DBGCLAIMSET Debug Claim Tag Set register
111100011001100001ICV_EOIR1Interrupt Controller Virtual End Of Interrupt Register 1
000 000 0111 1111 1000 ATS1CPR Address Translate Stage 1 Current state PL1 Read
111100011001100010ICC_HPPIR1Interrupt Controller Highest Priority Pending Interrupt Register 1
1001111 000 01111100 11111100 1000010 ATS1HR ICV_HPPIR1 AddressInterrupt TranslateController StageVirtual 1Highest HypPriority modePending ReadInterrupt Register 1
000 001 0111 1111 1000 ATS1CPW Address Translate Stage 1 Current state PL1 Write
111100011001100011ICC_BPR1Interrupt Controller Binary Point Register 1
100 001 0111 1111 1000 ATS1HW Address Translate Stage 1 Hyp mode Write
111100011001100011ICV_BPR1Interrupt Controller Virtual Binary Point Register 1
000 010 0111 1111 1000 ATS1CUR Address Translate Stage 1 Current state Unprivileged Read
111100011001100100ICC_CTLRInterrupt Controller Control Register
000 011 0111 1111 1000 ATS1CUW Address Translate Stage 1 Current state Unprivileged Write
111100011001100100ICV_CTLRInterrupt Controller Virtual Control Register
000 100 0111 1111 1000 ATS12NSOPR Address Translate Stages 1 and 2 Non-secure Only PL1 Read
111100011001100101ICC_SREInterrupt Controller System Register Enable register
000 101 0111 1111 1000 ATS12NSOPW Address Translate Stages 1 and 2 Non-secure Only PL1 Write
111100011001100110ICC_IGRPEN0Interrupt Controller Interrupt Group 0 Enable register
000 110 0111 1111 1000 ATS12NSOUR Address Translate Stages 1 and 2 Non-secure Only Unprivileged Read
111100011001100110ICV_IGRPEN0Interrupt Controller Virtual Interrupt Group 0 Enable register
000 111 0111 1111 1000 ATS12NSOUW Address Translate Stages 1 and 2 Non-secure Only Unprivileged Write
111100011001100111ICC_IGRPEN1Interrupt Controller Interrupt Group 1 Enable register
000 000 1100 1111 1000 ICC_IAR0 Interrupt Controller Interrupt Acknowledge Register 0
111100011001100111ICV_IGRPEN1Interrupt Controller Virtual Interrupt Group 1 Enable register
000 000 1100 1111 1000 ICV_IAR0 Interrupt Controller Virtual Interrupt Acknowledge Register 0
111100011010000000FCSEIDRFCSE Process ID register
000 001 1100 1111 1000 ICC_EOIR0 Interrupt Controller End Of Interrupt Register 0
111100011010000001CONTEXTIDRContext ID Register
000 001 1100 1111 1000 ICV_EOIR0 Interrupt Controller Virtual End Of Interrupt Register 0
111100011010000010TPIDRURWPL0 Read/Write Software Thread ID Register
000 010 1100 1111 1000 ICC_HPPIR0 Interrupt Controller Highest Priority Pending Interrupt Register 0
111100011010000011TPIDRUROPL0 Read-Only Software Thread ID Register
000 010 1100 1111 1000 ICV_HPPIR0 Interrupt Controller Virtual Highest Priority Pending Interrupt Register 0
111100011010000100TPIDRPRWPL1 Software Thread ID Register
000 011 1100 1111 1000 ICC_BPR0 Interrupt Controller Binary Point Register 0
111100011100000000CNTFRQCounter-timer Frequency register
000 011 1100 1111 1000 ICV_BPR0 Interrupt Controller Virtual Binary Point Register 0
111100011100001000CNTKCTLCounter-timer Kernel Control register
100 0xx 1100 1111 1000 ICH_AP0R<n> Interrupt Controller Hyp Active Priorities Group 0 Registers
111100011100010000CNTP_TVALCounter-timer Physical Timer TimerValue register
000 1xx 1100 1111 1000 ICC_AP0R<n> Interrupt Controller Active Priorities Group 0 Registers
111100011100010001CNTP_CTLCounter-timer Physical Timer Control register
000 1xx 1100 1111 1000 ICV_AP0R<n> Interrupt Controller Virtual Active Priorities Group 0 Registers
111100011100011000CNTV_TVALCounter-timer Virtual Timer TimerValue register
000 110 0111 1110 1001 DBGCLAIMCLR Debug Claim Tag Clear register
111100011100011001CNTV_CTLCounter-timer Virtual Timer Control register
000 000 0111 1111 1001 ATS1CPRP Address Translate Stage 1 Current state PL1 Read PAN
1111000111010xxxxxPMEVCNTR<n>Performance Monitors Event Count Registers
000 001 0111 1111 1001 ATS1CPWP Address Translate Stage 1 Current state PL1 Write PAN
111100011101111111PMCCFILTRPerformance Monitors Cycle Count Filter Register
100 101 1100 1111 1001 ICC_HSRE Interrupt Controller Hyp System Register Enable register
1111000111011xxxxxPMEVTYPER<n>Performance Monitors Event Type Registers
000 0xx 1100 1111 1001 ICC_AP1R<n> Interrupt Controller Active Priorities Group 1 Registers
111100100000000000CCSIDRCurrent Cache Size ID Register
000 0xx 1100 1111 1001 ICV_AP1R<n> Interrupt Controller Virtual Active Priorities Group 1 Registers
111100100000000001CLIDRCache Level ID Register
100 0xx 1100 1111 1001 ICH_AP1R<n> Interrupt Controller Hyp Active Priorities Group 1 Registers
111100100000000010CCSIDR2Current Cache Size ID Register 2
0001111 001 01110000 11110000 1010111 DCCMVAC AIDR DataAuxiliary CacheID line Clean by VA to PoCRegister
000 010 0111 1111 1010 DCCSW Data Cache line Clean by Set/Way
111101000000000000CSSELRCache Size Selection Register
000 100 0111 1111 1010 CP15DSB Data Synchronization Barrier System instruction
111101101000101000DSPSRDebug Saved Program Status Register
000 101 0111 1111 1010 CP15DMB Data Memory Barrier System instruction
111101101000101001DLRDebug Link Register
000 001 0111 1111 1011 DCCMVAU Data Cache line Clean by VA to PoU
111110000000000000VPIDRVirtualization Processor ID Register
100 000 1100 1111 1011 ICH_HCR Interrupt Controller Hyp Control Register
111110000000000101VMPIDRVirtualization Multiprocessor ID Register
000 001 1100 1111 1011 ICC_DIR Interrupt Controller Deactivate Interrupt Register
111110000010000000HSCTLRHyp System Control Register
000 001 1100 1111 1011 ICV_DIR Interrupt Controller Deactivate Virtual Interrupt Register
111110000010000001HACTLRHyp Auxiliary Control Register
100 001 1100 1111 1011 ICH_VTR Interrupt Controller VGIC Type Register
111110000010000011HACTLR2Hyp Auxiliary Control Register 2
100 010 1100 1111 1011 ICH_MISR Interrupt Controller Maintenance Interrupt State Register
111110000010001000HCRHyp Configuration Register
000 011 1100 1111 1011 ICC_RPR Interrupt Controller Running Priority Register
111110000010001001HDCRHyp Debug Control Register
000 011 1100 1111 1011 ICV_RPR Interrupt Controller Virtual Running Priority Register
111110000010001010HCPTRHyp Architectural Feature Trap Register
100 011 1100 1111 1011 ICH_EISR Interrupt Controller End of Interrupt Status Register
111110000010001011HSTRHyp System Trap Register
100 101 1100 1111 1011 ICH_ELRSR Interrupt Controller Empty List Register Status Register
111110000010001100HCR2Hyp Configuration Register 2
100 111 1100 1111 1011 ICH_VMCR Interrupt Controller Virtual Machine Control Register
111110000010001111HACRHyp Auxiliary Configuration Register
000 000 1001 1111 1100 PMCR Performance Monitors Control Register
111110000100000010HTCRHyp Translation Control Register
000 001 1001 1111 1100 PMCNTENSET Performance Monitors Count Enable Set register
111110000100001010VTCRVirtualization Translation Control Register
000 010 1001 1111 1100 PMCNTENCLR Performance Monitors Count Enable Clear register
111110001010001000HADFSRHyp Auxiliary Data Fault Status Register
000 011 1001 1111 1100 PMOVSR Performance Monitors Overflow Flag Status Register
111110001010001001HAIFSRHyp Auxiliary Instruction Fault Status Register
000 100 1001 1111 1100 PMSWINC Performance Monitors Software Increment register
111110001010010000HSRHyp Syndrome Register
000 101 1001 1111 1100 PMSELR Performance Monitors Event Counter Selection Register
111110001100000000HDFARHyp Data Fault Address Register
000 110 1001 1111 1100 PMCEID0 Performance Monitors Common Event Identification register 0
111110001100000010HIFARHyp Instruction Fault Address Register
000 111 1001 1111 1100 PMCEID1 Performance Monitors Common Event Identification register 1
111110001100000100HPFARHyp IPA Fault Address Register
000 000 1100 1111 1100 ICC_IAR1 Interrupt Controller Interrupt Acknowledge Register 1
111110001111000000ATS1HRAddress Translate Stage 1 Hyp mode Read
000 000 1100 1111 1100 ICV_IAR1 Interrupt Controller Virtual Interrupt Acknowledge Register 1
111110001111000001ATS1HWAddress Translate Stage 1 Hyp mode Write
000 001 1100 1111 1100 ICC_EOIR1 Interrupt Controller End Of Interrupt Register 1
111110010000000001TLBIIPAS2ISTLB Invalidate by Intermediate Physical Address, Stage 2, Inner Shareable
000 001 1100 1111 1100 ICV_EOIR1 Interrupt Controller Virtual End Of Interrupt Register 1
111110010000000101TLBIIPAS2LISTLB Invalidate by Intermediate Physical Address, Stage 2, Last level, Inner Shareable
000 010 1100 1111 1100 ICC_HPPIR1 Interrupt Controller Highest Priority Pending Interrupt Register 1
111110010000011000TLBIALLHISTLB Invalidate All, Hyp mode, Inner Shareable
000 010 1100 1111 1100 ICV_HPPIR1 Interrupt Controller Virtual Highest Priority Pending Interrupt Register 1
111110010000011001TLBIMVAHISTLB Invalidate by VA, Hyp mode, Inner Shareable
000 011 1100 1111 1100 ICC_BPR1 Interrupt Controller Binary Point Register 1
111110010000011100TLBIALLNSNHISTLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
000 011 1100 1111 1100 ICV_BPR1 Interrupt Controller Virtual Binary Point Register 1
111110010000011101TLBIMVALHISTLB Invalidate by VA, Last level, Hyp mode, Inner Shareable
0001111 100 11001000 11110100 1100001 ICC_CTLR TLBIIPAS2 InterruptTLB ControllerInvalidate Controlby RegisterIntermediate Physical Address, Stage 2
0001111 100 11001000 11110100 1100101 ICV_CTLR TLBIIPAS2L InterruptTLB ControllerInvalidate Virtualby ControlIntermediate RegisterPhysical Address, Stage 2, Last level
1101111 100 11001000 11110111 1100000 ICC_MCTLR TLBIALLH InterruptTLB ControllerInvalidate MonitorAll, ControlHyp Registermode
000 101 1100 1111 1100 ICC_SRE Interrupt Controller System Register Enable register
111110010000111001TLBIMVAHTLB Invalidate by VA, Hyp mode
110 101 1100 1111 1100 ICC_MSRE Interrupt Controller Monitor System Register Enable register
111110010000111100TLBIALLNSNHTLB Invalidate All, Non-Secure Non-Hyp
000 110 1100 1111 1100 ICC_IGRPEN0 Interrupt Controller Interrupt Group 0 Enable register
111110010000111101TLBIMVALHTLB Invalidate by VA, Last level, Hyp mode
000 110 1100 1111 1100 ICV_IGRPEN0 Interrupt Controller Virtual Interrupt Group 0 Enable register
111110010100010000HMAIR0Hyp Memory Attribute Indirection Register 0
000 111 1100 1111 1100 ICC_IGRPEN1 Interrupt Controller Interrupt Group 1 Enable register
111110010100010001HMAIR1Hyp Memory Attribute Indirection Register 1
000 111 1100 1111 1100 ICV_IGRPEN1 Interrupt Controller Virtual Interrupt Group 1 Enable register
111110010100011000HAMAIR0Hyp Auxiliary Memory Attribute Indirection Register 0
110 111 1100 1111 1100 ICC_MGRPEN1 Interrupt Controller Monitor Interrupt Group 1 Enable register
111110010100011001HAMAIR1Hyp Auxiliary Memory Attribute Indirection Register 1
000 000 1001 1111 1101 PMCCNTR Performance Monitors Cycle Count Register
111110011000000000HVBARHyp Vector Base Address Register
000 001 1001 1111 1101 PMXEVTYPER Performance Monitors Selected Event Type Register
111110011000000010HRMRHyp Reset Management Register
000 010 1001 1111 1101 PMXEVCNTR Performance Monitors Selected Event Count Register
1111100110010000xxICH_AP0R<n>Interrupt Controller Hyp Active Priorities Group 0 Registers
0001111 110100 01111100 11101001 11100xx DBGAUTHSTATUS ICH_AP1R<n> DebugInterrupt AuthenticationController StatusHyp registerActive Priorities Group 1 Registers
000 001 0111 1111 1110 DCCIMVAC Data Cache line Clean and Invalidate by VA to PoC
111110011001001101ICC_HSREInterrupt Controller Hyp System Register Enable register
000 010 0111 1111 1110 DCCISW Data Cache line Clean and Invalidate by Set/Way
111110011001011000ICH_HCRInterrupt Controller Hyp Control Register
000 000 1001 1111 1110 PMUSERENR Performance Monitors User Enable Register
111110011001011001ICH_VTRInterrupt Controller VGIC Type Register
000 001 1001 1111 1110 PMINTENSET Performance Monitors Interrupt Enable Set register
111110011001011010ICH_MISRInterrupt Controller Maintenance Interrupt State Register
000 010 1001 1111 1110 PMINTENCLR Performance Monitors Interrupt Enable Clear register
111110011001011011ICH_EISRInterrupt Controller End of Interrupt Status Register
000 011 1001 1111 1110 PMOVSSET Performance Monitors Overflow Flag Status Set register
111110011001011101ICH_ELRSRInterrupt Controller Empty List Register Status Register
0001111 100 10011100 11111011 1110111 PMCEID2 ICH_VMCR PerformanceInterrupt MonitorsController CommonVirtual EventMachine IdentificationControl register 2Register
000 101 1001 1111 1110 PMCEID3 Performance Monitors Common Event Identification register 3
11111001100110xxxxICH_LR<n>Interrupt Controller List Registers
000 111 1110 1111 1111 PMCCFILTR Performance Monitors Cycle Count Filter Register
11111001100111xxxxICH_LRC<n>Interrupt Controller List Registers
000 xxx 1110 1111 10xx PMEVCNTR<n> Performance Monitors Event Count Registers
111110011010000010HTPIDRHyp Software Thread ID Register
100 xxx 1100 1111 110x ICH_LR<n> Interrupt Controller List Registers
111110011100001000CNTHCTLCounter-timer Hyp Control register
100 xxx 1100 1111 111x ICH_LRC<n> Interrupt Controller List Registers
111110011100010000CNTHP_TVALCounter-timer Hyp Physical Timer TimerValue register
0001111 xxx100 1110 11110010 11xx001 PMEVTYPER<n> CNTHP_CTL PerformanceCounter-timer MonitorsHyp EventPhysical TypeTimer RegistersControl register
000 100 0000 1110 xxxx DBGBVR<n> Debug Breakpoint Value Registers
111111011001100100ICC_MCTLRInterrupt Controller Monitor Control Register
000 101 0000 1110 xxxx DBGBCR<n> Debug Breakpoint Control Registers
111111011001100101ICC_MSREInterrupt Controller Monitor System Register Enable register
0001111 110 00001100 11101100 xxxx111 DBGWVR<n> ICC_MGRPEN1 DebugInterrupt WatchpointController ValueMonitor RegistersInterrupt Group 1 Enable register
000 111 0000 1110 xxxx DBGWCR<n> Debug Watchpoint Control Registers
000 001 0001 1110 xxxx DBGBXVR<n> Debug Breakpoint Extended Value Registers

Accessed using MCRR/MRRC:

Register selectors Name Description
opc1 coproc CRm
0000 1110 0001 DBGDRAR Debug ROM Address Register
0000 1110 0010 DBGDSAR Debug Self Address Register
0000 1111 0010 TTBR0 Translation Table Base Register 0
0001 1111 0010 TTBR1 Translation Table Base Register 1
0100 1111 0010 HTTBR Hyp Translation Table Base Register
0110 1111 0010 VTTBR Virtualization Translation Table Base Register
0000 1111 0111 PAR Physical Address Register
0000 1111 1001 PMCCNTR Performance Monitors Cycle Count Register
0000 1111 1100 ICC_SGI1R Interrupt Controller Software Generated Interrupt Group 1 Register
0001 1111 1100 ICC_ASGI1R Interrupt Controller Alias Software Generated Interrupt Group 1 Register
0010 1111 1100 ICC_SGI0R Interrupt Controller Software Generated Interrupt Group 0 Register
0000 1111 1110 CNTPCT Counter-timer Physical Count register
0001 1111 1110 CNTVCT Counter-timer Virtual Count register
0010 1111 1110 CNTP_CVAL Counter-timer Physical Timer CompareValue register
0011 1111 1110 CNTHV_CVAL Counter-timer Virtual Timer CompareValue register (EL2)
0011 1111 1110 CNTV_CVAL Counter-timer Virtual Timer CompareValue register
0100 1111 1110 CNTVOFF Counter-timer Virtual Offset register
0110 1111 1110 CNTHP_CVAL Counter-timer Hyp Physical CompareValue register

Accessed using MRS/MSR:

Register selectors Name Description
R M M1
mm1R
1 1 0000 SPSR_irq Saved Program Status Register (IRQ mode)
011101SPSR_fiqSaved Program Status Register (FIQ mode)
1 1 0010 SPSR_svc Saved Program Status Register (Supervisor mode)
100001SPSR_irqSaved Program Status Register (IRQ mode)
1 1 0100 SPSR_abt Saved Program Status Register (Abort mode)
100101SPSR_svcSaved Program Status Register (Supervisor mode)
1 1 0110 SPSR_und Saved Program Status Register (Undefined mode)
101001SPSR_abtSaved Program Status Register (Abort mode)
1 1 1100 SPSR_mon Saved Program Status Register (Monitor mode)
101101SPSR_undSaved Program Status Register (Undefined mode)
1 01100 11101 SPSR_fiq SPSR_mon Saved Program Status Register (FIQMonitor mode)
0 1 1110 ELR_hyp Exception Link Register (Hyp mode)
111100ELR_hypException Link Register (Hyp mode)
1 1 1110 SPSR_hyp Saved Program Status Register (Hyp mode)
111101SPSR_hypSaved Program Status Register (Hyp mode)

Accessed using VMRS/VMSR:

Register selectors Name Description
regspec_reg
0000 FPSID Floating-Point System ID register
0001 FPSCR Floating-Point Status and Control Register
0101 MVFR2 Media and VFP Feature Register 2
0110 MVFR1 Media and VFP Feature Register 1
0111 MVFR0 Media and VFP Feature Register 0
1000 FPEXC Floating-Point Exception Control register

Accessed using MRRC/MCRR:

Register selectorsNameDescription
coprocopc1CRm
111000000001DBGDRARDebug ROM Address Register
111000000010DBGDSARDebug Self Address Register
111100000010TTBR0Translation Table Base Register 0
111100010010TTBR1Translation Table Base Register 1
111101000010HTTBRHyp Translation Table Base Register
111101100010VTTBRVirtualization Translation Table Base Register
111100000111PARPhysical Address Register
111100001001PMCCNTRPerformance Monitors Cycle Count Register
111100001100ICC_SGI1RInterrupt Controller Software Generated Interrupt Group 1 Register
111100011100ICC_ASGI1RInterrupt Controller Alias Software Generated Interrupt Group 1 Register
111100101100ICC_SGI0RInterrupt Controller Software Generated Interrupt Group 0 Register
111100001110CNTPCTCounter-timer Physical Count register
111100011110CNTVCTCounter-timer Virtual Count register
111100101110CNTP_CVALCounter-timer Physical Timer CompareValue register
111100111110CNTV_CVALCounter-timer Virtual Timer CompareValue register
111101001110CNTVOFFCounter-timer Virtual Offset register
111101101110CNTHP_CVALCounter-timer Hyp Physical CompareValue register

Registers and operations in AArch64

Accessed using ATMRS/MSR:

Register selectors Name Description
op0 op1 CRn CRm op2
1000000010000000MDRAR_EL1Monitor Debug ROM Address Register
1000000010000100OSLAR_EL1OS Lock Access Register
1000000010001100OSLSR_EL1OS Lock Status Register
1000000010011100OSDLR_EL1OS Double Lock Register
1000000010100100DBGPRCR_EL1Debug Power Control Register
1000001111000110DBGCLAIMSET_EL1Debug Claim Tag Set register
1000001111001110DBGCLAIMCLR_EL1Debug Claim Tag Clear register
1000001111110110DBGAUTHSTATUS_EL1Debug Authentication Status register
1100000000000000MIDR_EL1Main ID Register
1100100000000000CCSIDR_EL1Current Cache Size ID Register
1101000000000000CSSELR_EL1Cache Size Selection Register
1110000000000000VPIDR_EL2Virtualization Processor ID Register
1100100000000001CLIDR_EL1Cache Level ID Register
1101100000000001CTR_EL0Cache Type Register
1100100000000010CCSIDR2_EL1Current Cache Size ID Register 2
1100000000000101MPIDR_EL1Multiprocessor Affinity Register
1110000000000101VMPIDR_EL2Virtualization Multiprocessor ID Register
1100000000000110REVIDR_EL1Revision ID Register
1100100000000111AIDR_EL1Auxiliary ID Register
1101100000000111DCZID_EL0Data Cache Zero ID register
1100000000001000ID_PFR0_EL1AArch32 Processor Feature Register 0
1100000000001001ID_PFR1_EL1AArch32 Processor Feature Register 1
1100000000001010ID_DFR0_EL1AArch32 Debug Feature Register 0
1100000000001011ID_AFR0_EL1AArch32 Auxiliary Feature Register 0
1100000000001100ID_MMFR0_EL1AArch32 Memory Model Feature Register 0
1100000000001101ID_MMFR1_EL1AArch32 Memory Model Feature Register 1
1100000000001110ID_MMFR2_EL1AArch32 Memory Model Feature Register 2
1100000000001111ID_MMFR3_EL1AArch32 Memory Model Feature Register 3
1100000000010000ID_ISAR0_EL1AArch32 Instruction Set Attribute Register 0
1100000000010001ID_ISAR1_EL1AArch32 Instruction Set Attribute Register 1
1100000000010010ID_ISAR2_EL1AArch32 Instruction Set Attribute Register 2
1100000000010011ID_ISAR3_EL1AArch32 Instruction Set Attribute Register 3
1100000000010100ID_ISAR4_EL1AArch32 Instruction Set Attribute Register 4
1100000000010101ID_ISAR5_EL1AArch32 Instruction Set Attribute Register 5
1100000000010110ID_MMFR4_EL1AArch32 Memory Model Feature Register 4
1100000000010111ID_ISAR6_EL1AArch32 Instruction Set Attribute Register 6
1100000000011000MVFR0_EL1AArch32 Media and VFP Feature Register 0
1100000000011001MVFR1_EL1AArch32 Media and VFP Feature Register 1
1100000000011010MVFR2_EL1AArch32 Media and VFP Feature Register 2
1100000000100000ID_AA64PFR0_EL1AArch64 Processor Feature Register 0
1100000000100001ID_AA64PFR1_EL1AArch64 Processor Feature Register 1
1100000000101000ID_AA64DFR0_EL1AArch64 Debug Feature Register 0
1100000000101001ID_AA64DFR1_EL1AArch64 Debug Feature Register 1
1100000000101100ID_AA64AFR0_EL1AArch64 Auxiliary Feature Register 0
1100000000101101ID_AA64AFR1_EL1AArch64 Auxiliary Feature Register 1
1100000000110000ID_AA64ISAR0_EL1AArch64 Instruction Set Attribute Register 0
1100000000110001ID_AA64ISAR1_EL1AArch64 Instruction Set Attribute Register 1
1100000000111000ID_AA64MMFR0_EL1AArch64 Memory Model Feature Register 0
1100000000111001ID_AA64MMFR1_EL1AArch64 Memory Model Feature Register 1
1100000000111010ID_AA64MMFR2_EL1AArch64 Memory Model Feature Register 2
1100000010000000SCTLR_EL1System Control Register (EL1)
1110000010000000SCTLR_EL2System Control Register (EL2)
1111000010000000SCTLR_EL3System Control Register (EL3)
1100000010000001ACTLR_EL1Auxiliary Control Register (EL1)
1110000010000001ACTLR_EL2Auxiliary Control Register (EL2)
1111000010000001ACTLR_EL3Auxiliary Control Register (EL3)
1100000010000010CPACR_EL1Architectural Feature Access Control Register
1110000010001000HCR_EL2Hypervisor Configuration Register
1111000010001000SCR_EL3Secure Configuration Register
1110000010001001MDCR_EL2Monitor Debug Configuration Register (EL2)
1111000010001001SDER32_EL3AArch32 Secure Debug Enable Register
1110000010001010CPTR_EL2Architectural Feature Trap Register (EL2)
1111000010001010CPTR_EL3Architectural Feature Trap Register (EL3)
1110000010001011HSTR_EL2Hypervisor System Trap Register
1110000010001111HACR_EL2Hypervisor Auxiliary Control Register
1111000010011001MDCR_EL3Monitor Debug Configuration Register (EL3)
1100000100000000TTBR0_EL1Translation Table Base Register 0 (EL1)
1110000100000000TTBR0_EL2Translation Table Base Register 0 (EL2)
1111000100000000TTBR0_EL3Translation Table Base Register 0 (EL3)
1100000100000001TTBR1_EL1Translation Table Base Register 1 (EL1)
1110000100000001TTBR1_EL2Translation Table Base Register 1 (EL2)
1100000100000010TCR_EL1Translation Control Register (EL1)
1110000100000010TCR_EL2Translation Control Register (EL2)
1111000100000010TCR_EL3Translation Control Register (EL3)
1100000100001000APIAKeyLo_EL1Pointer Authentication Key A for Instruction (bits[63:0])
1110000100001000VTTBR_EL2Virtualization Translation Table Base Register
1100000100001001APIAKeyHi_EL1Pointer Authentication Key A for Instruction (bits[127:64])
1100000100001010APIBKeyLo_EL1Pointer Authentication Key B for Instruction (bits[63:0])
1110000100001010VTCR_EL2Virtualization Translation Control Register
1100000100001011APIBKeyHi_EL1Pointer Authentication Key B for Instruction (bits[127:64])
1100000100010000APDAKeyLo_EL1Pointer Authentication Key A for Data (bits[63:0])
1100000100010001APDAKeyHi_EL1Pointer Authentication Key A for Data (bits[127:64])
1100000100010010APDBKeyLo_EL1Pointer Authentication Key B for Data (bits[63:0])
1100000100010011APDBKeyHi_EL1Pointer Authentication Key B for Data (bits[127:64])
1100000100011000APGAKeyLo_EL1Pointer Authentication Key A for Code (bits[63:0])
1100000100011001APGAKeyHi_EL1Pointer Authentication Key A for Code (bits[127:64])
1110000110000000DACR32_EL2Domain Access Control Register
1100001000000000SPSR_EL1Saved Program Status Register (EL1)
1110001000000000SPSR_EL2Saved Program Status Register (EL2)
1111001000000000SPSR_EL3Saved Program Status Register (EL3)
1100001000000001ELR_EL1Exception Link Register (EL1)
1110001000000001ELR_EL2Exception Link Register (EL2)
1111001000000001ELR_EL3Exception Link Register (EL3)
1100001000001000SP_EL0Stack Pointer (EL0)
1110001000001000SP_EL1Stack Pointer (EL1)
1111001000001000SP_EL2Stack Pointer (EL2)
1100001000010000SPSelStack Pointer Select
1101101000010000NZCVCondition Flags
1101101000010001DAIFInterrupt Mask Bits
1100001000010010CurrentELCurrent Exception Level
1100001000010011PANPrivileged Access Never
1100001000010100UAOUser Access Override
1110001000011000SPSR_irqSaved Program Status Register (IRQ mode)
1110001000011001SPSR_abtSaved Program Status Register (Abort mode)
1110001000011010SPSR_undSaved Program Status Register (Undefined mode)
1110001000011011SPSR_fiqSaved Program Status Register (FIQ mode)
1101101000100000FPCRFloating-point Control Register
1101101000100001FPSRFloating-point Status Register
1101101000101000DSPSR_EL0Debug Saved Program Status Register
1101101000101001DLR_EL0Debug Link Register
1100001000110000ICC_PMR_EL1Interrupt Controller Interrupt Priority Mask Register
1100001000110000ICV_PMR_EL1Interrupt Controller Virtual Interrupt Priority Mask Register
1110001010000001IFSR32_EL2Instruction Fault Status Register (EL2)
1100001010001000AFSR0_EL1Auxiliary Fault Status Register 0 (EL1)
1110001010001000AFSR0_EL2Auxiliary Fault Status Register 0 (EL2)
1111001010001000AFSR0_EL3Auxiliary Fault Status Register 0 (EL3)
1100001010001001AFSR1_EL1Auxiliary Fault Status Register 1 (EL1)
1110001010001001AFSR1_EL2Auxiliary Fault Status Register 1 (EL2)
1111001010001001AFSR1_EL3Auxiliary Fault Status Register 1 (EL3)
1100001010010000ESR_EL1Exception Syndrome Register (EL1)
1110001010010000ESR_EL2Exception Syndrome Register (EL2)
1111001010010000ESR_EL3Exception Syndrome Register (EL3)
1110001010011000FPEXC32_EL2Floating-Point Exception Control register
1100001100000000FAR_EL1Fault Address Register (EL1)
1110001100000000FAR_EL2Fault Address Register (EL2)
1111001100000000FAR_EL3Fault Address Register (EL3)
1110001100000100HPFAR_EL2Hypervisor IPA Fault Address Register
1100001110100000PAR_EL1Physical Address Register
1101110011100000PMCR_EL0Performance Monitors Control Register
1101110011100001PMCNTENSET_EL0Performance Monitors Count Enable Set register
1101110011100010PMCNTENCLR_EL0Performance Monitors Count Enable Clear register
1101110011100011PMOVSCLR_EL0Performance Monitors Overflow Flag Status Clear Register
1101110011100100PMSWINC_EL0Performance Monitors Software Increment register
1101110011100101PMSELR_EL0Performance Monitors Event Counter Selection Register
1101110011100110PMCEID0_EL0Performance Monitors Common Event Identification register 0
1101110011100111PMCEID1_EL0Performance Monitors Common Event Identification register 1
1101110011101000PMCCNTR_EL0Performance Monitors Cycle Count Register
1101110011101001PMXEVTYPER_EL0Performance Monitors Selected Event Type Register
1101110011101010PMXEVCNTR_EL0Performance Monitors Selected Event Count Register
1101110011110000PMUSERENR_EL0Performance Monitors User Enable Register
1100010011110001PMINTENSET_EL1Performance Monitors Interrupt Enable Set register
1100010011110010PMINTENCLR_EL1Performance Monitors Interrupt Enable Clear register
1101110011110011PMOVSSET_EL0Performance Monitors Overflow Flag Status Set register
1100010100010000MAIR_EL1Memory Attribute Indirection Register (EL1)
1110010100010000MAIR_EL2Memory Attribute Indirection Register (EL2)
1111010100010000MAIR_EL3Memory Attribute Indirection Register (EL3)
1100010100011000AMAIR_EL1Auxiliary Memory Attribute Indirection Register (EL1)
1110010100011000AMAIR_EL2Auxiliary Memory Attribute Indirection Register (EL2)
1111010100011000AMAIR_EL3Auxiliary Memory Attribute Indirection Register (EL3)
1100010100100000LORSA_EL1LORegion Start Address (EL1)
1100010100100001LOREA_EL1LORegion End Address (EL1)
1100010100100010LORN_EL1LORegion Number (EL1)
1100010100100011LORC_EL1LORegion Control (EL1)
1100010100100111LORID_EL1LORegionID (EL1)
1100011000000000VBAR_EL1Vector Base Address Register (EL1)
1110011000000000VBAR_EL2Vector Base Address Register (EL2)
1111011000000000VBAR_EL3Vector Base Address Register (EL3)
1100011000000001RVBAR_EL1Reset Vector Base Address Register (if EL2 and EL3 not implemented)
1110011000000001RVBAR_EL2Reset Vector Base Address Register (if EL3 not implemented)
1111011000000001RVBAR_EL3Reset Vector Base Address Register (if EL3 implemented)
1100011000000010RMR_EL1Reset Management Register (EL1)
1110011000000010RMR_EL2Reset Management Register (EL2)
1111011000000010RMR_EL3Reset Management Register (EL3)
1100011000001000ISR_EL1Interrupt Status Register
1100011001000000ICC_IAR0_EL1Interrupt Controller Interrupt Acknowledge Register 0
1100011001000000ICV_IAR0_EL1Interrupt Controller Virtual Interrupt Acknowledge Register 0
1100011001000001ICC_EOIR0_EL1Interrupt Controller End Of Interrupt Register 0
1100011001000001ICV_EOIR0_EL1Interrupt Controller Virtual End Of Interrupt Register 0
1100011001000010ICC_HPPIR0_EL1Interrupt Controller Highest Priority Pending Interrupt Register 0
1100011001000010ICV_HPPIR0_EL1Interrupt Controller Virtual Highest Priority Pending Interrupt Register 0
1100011001000011ICC_BPR0_EL1Interrupt Controller Binary Point Register 0
1100011001000011ICV_BPR0_EL1Interrupt Controller Virtual Binary Point Register 0
11100110010000xxICH_AP0R<n>_EL2Interrupt Controller Hyp Active Priorities Group 0 Registers
11000110010001xxICC_AP0R<n>_EL1Interrupt Controller Active Priorities Group 0 Registers
11000110010001xxICV_AP0R<n>_EL1Interrupt Controller Virtual Active Priorities Group 0 Registers
11000110010010xxICC_AP1R<n>_EL1Interrupt Controller Active Priorities Group 1 Registers
11000110010010xxICV_AP1R<n>_EL1Interrupt Controller Virtual Active Priorities Group 1 Registers
11100110010010xxICH_AP1R<n>_EL2Interrupt Controller Hyp Active Priorities Group 1 Registers
1110011001001101ICC_SRE_EL2Interrupt Controller System Register Enable register (EL2)
1110011001011000ICH_HCR_EL2Interrupt Controller Hyp Control Register
1100011001011001ICC_DIR_EL1Interrupt Controller Deactivate Interrupt Register
1100011001011001ICV_DIR_EL1Interrupt Controller Deactivate Virtual Interrupt Register
1110011001011001ICH_VTR_EL2Interrupt Controller VGIC Type Register
1110011001011010ICH_MISR_EL2Interrupt Controller Maintenance Interrupt State Register
1100011001011011ICC_RPR_EL1Interrupt Controller Running Priority Register
1100011001011011ICV_RPR_EL1Interrupt Controller Virtual Running Priority Register
1110011001011011ICH_EISR_EL2Interrupt Controller End of Interrupt Status Register
1100011001011101ICC_SGI1R_EL1Interrupt Controller Software Generated Interrupt Group 1 Register
1110011001011101ICH_ELRSR_EL2Interrupt Controller Empty List Register Status Register
1100011001011110ICC_ASGI1R_EL1Interrupt Controller Alias Software Generated Interrupt Group 1 Register
1100011001011111ICC_SGI0R_EL1Interrupt Controller Software Generated Interrupt Group 0 Register
1110011001011111ICH_VMCR_EL2Interrupt Controller Virtual Machine Control Register
1100011001100000ICC_IAR1_EL1Interrupt Controller Interrupt Acknowledge Register 1
1100011001100000ICV_IAR1_EL1Interrupt Controller Virtual Interrupt Acknowledge Register 1
1100011001100001ICC_EOIR1_EL1Interrupt Controller End Of Interrupt Register 1
1100011001100001ICV_EOIR1_EL1Interrupt Controller Virtual End Of Interrupt Register 1
1100011001100010ICC_HPPIR1_EL1Interrupt Controller Highest Priority Pending Interrupt Register 1
1100011001100010ICV_HPPIR1_EL1Interrupt Controller Virtual Highest Priority Pending Interrupt Register 1
1100011001100011ICC_BPR1_EL1Interrupt Controller Binary Point Register 1
1100011001100011ICV_BPR1_EL1Interrupt Controller Virtual Binary Point Register 1
1100011001100100ICC_CTLR_EL1Interrupt Controller Control Register (EL1)
1100011001100100ICV_CTLR_EL1Interrupt Controller Virtual Control Register
1111011001100100ICC_CTLR_EL3Interrupt Controller Control Register (EL3)
1100011001100101ICC_SRE_EL1Interrupt Controller System Register Enable register (EL1)
1111011001100101ICC_SRE_EL3Interrupt Controller System Register Enable register (EL3)
1100011001100110ICC_IGRPEN0_EL1Interrupt Controller Interrupt Group 0 Enable register
1100011001100110ICV_IGRPEN0_EL1Interrupt Controller Virtual Interrupt Group 0 Enable register
1100011001100111ICC_IGRPEN1_EL1Interrupt Controller Interrupt Group 1 Enable register
1100011001100111ICV_IGRPEN1_EL1Interrupt Controller Virtual Interrupt Group 1 Enable register
1111011001100111ICC_IGRPEN1_EL3Interrupt Controller Interrupt Group 1 Enable register (EL3)
111001100110xxxxICH_LR<n>_EL2Interrupt Controller List Registers
1100011010000001CONTEXTIDR_EL1Context ID Register (EL1)
1110011010000001CONTEXTIDR_EL2Context ID Register (EL2)
1101111010000010TPIDR_EL0EL0 Read/Write Software Thread ID Register
1110011010000010TPIDR_EL2EL2 Software Thread ID Register
1111011010000010TPIDR_EL3EL3 Software Thread ID Register
1101111010000011TPIDRRO_EL0EL0 Read-Only Software Thread ID Register
1100011010000100TPIDR_EL1EL1 Software Thread ID Register
1101111100000000CNTFRQ_EL0Counter-timer Frequency register
1101111100000001CNTPCT_EL0Counter-timer Physical Count register
1101111100000010CNTVCT_EL0Counter-timer Virtual Count register
1110011100000011CNTVOFF_EL2Counter-timer Virtual Offset register
1100011100001000CNTKCTL_EL1Counter-timer Kernel Control register
1110011100001000CNTHCTL_EL2Counter-timer Hypervisor Control register
1101111100010000CNTP_TVAL_EL0Counter-timer Physical Timer TimerValue register
1110011100010000CNTHP_TVAL_EL2Counter-timer Hypervisor Physical Timer TimerValue register
1111111100010000CNTPS_TVAL_EL1Counter-timer Physical Secure Timer TimerValue register
1101111100010001CNTP_CTL_EL0Counter-timer Physical Timer Control register
1110011100010001CNTHP_CTL_EL2Counter-timer Hypervisor Physical Timer Control register
1111111100010001CNTPS_CTL_EL1Counter-timer Physical Secure Timer Control register
1101111100010010CNTP_CVAL_EL0Counter-timer Physical Timer CompareValue register
1110011100010010CNTHP_CVAL_EL2Counter-timer Hypervisor Physical Timer CompareValue register
1111111100010010CNTPS_CVAL_EL1Counter-timer Physical Secure Timer CompareValue register
1101111100011000CNTV_TVAL_EL0Counter-timer Virtual Timer TimerValue register
1110011100011000CNTHV_TVAL_EL2Counter-timer Virtual Timer TimerValue register (EL2)
1101111100011001CNTV_CTL_EL0Counter-timer Virtual Timer Control register
1110011100011001CNTHV_CTL_EL2Counter-timer Virtual Timer Control register (EL2)
1101111100011010CNTV_CVAL_EL0Counter-timer Virtual Timer CompareValue register
1110011100011010CNTHV_CVAL_EL2Counter-timer Virtual Timer CompareValue register (EL2)
11011111010xxxxxPMEVCNTR<n>_EL0Performance Monitors Event Count Registers
1101111101111111PMCCFILTR_EL0Performance Monitors Cycle Count Filter Register
11011111011xxxxxPMEVTYPER<n>_EL0Performance Monitors Event Type Registers
11xxx1x11xxxxxxxS3_<op1>_<Cn>_<Cm>_<op2>IMPLEMENTATION DEFINED registers
0110 000 01110000 10000000 000010 AT S1E1R OSDTRRX_EL1 AddressOS TranslateLock StageData 1Transfer EL1Register, ReadReceive
0110 100011 01110000 10000001 000 AT S1E2R MDCCSR_EL0 AddressMonitor TranslateDCC StageStatus 1 EL2 ReadRegister
01 110 0111 1000 000 AT S1E3R Address Translate Stage 1 EL3 Read
1000000000010000MDCCINT_EL1Monitor DCC Interrupt Enable Register
0110 000 01110000 10010010 000010 AT S1E1RP MDSCR_EL1 AddressMonitor TranslateDebug StageSystem 1Control EL1 Read PANRegister
0110 000 01110000 10000011 001010 AT S1E1W OSDTRTX_EL1 AddressOS TranslateLock StageData 1Transfer EL1Register, WriteTransmit
0110 100011 01110000 10000100 001000 AT S1E2W DBGDTR_EL0 AddressDebug TranslateData StageTransfer 1Register, EL2 Writehalf-duplex
0110 110011 01110000 10000101 001000 AT S1E3W DBGDTRRX_EL0 AddressDebug TranslateData StageTransfer 1Register, EL3 WriteReceive
01 000 0111 1001 001 AT S1E1WP Address Translate Stage 1 EL1 Write PAN
1001100000101000DBGDTRTX_EL0Debug Data Transfer Register, Transmit
0110 000 01110000 10000110 010 AT S1E0R OSECCR_EL1 AddressOS TranslateLock StageException 1Catch EL0Control ReadRegister
01 000 0111 1000 011 AT S1E0W Address Translate Stage 1 EL0 Write
1010000000111000DBGVCR32_EL2Debug Vector Catch Register
01 100 0111 1000 100 AT S12E1R Address Translate Stages 1 and 2 EL1 Read
100000000xxxx100DBGBVR<n>_EL1Debug Breakpoint Value Registers
0110 100000 01110000 1000xxxx 101 AT S12E1W DBGBCR<n>_EL1 AddressDebug TranslateBreakpoint StagesControl 1 and 2 EL1 WriteRegisters
0110 100000 01110000 1000xxxx 110 AT S12E0R DBGWVR<n>_EL1 AddressDebug TranslateWatchpoint StagesValue 1 and 2 EL0 ReadRegisters
0110 100000 01110000 1000xxxx 111 AT S12E0W DBGWCR<n>_EL1 AddressDebug TranslateWatchpoint StagesControl 1 and 2 EL0 WriteRegisters

Accessed using DCTLBI:

Register selectors Name Description
op0 op1 CRn CRm op2
0100010000011011TLBI VAAE1ISTLB Invalidate by VA, All ASID, EL1, Inner Shareable
0110010000011100TLBI ALLE1ISTLB Invalidate All, EL1, Inner Shareable
0100010000011101TLBI VALE1ISTLB Invalidate by VA, Last level, EL1, Inner Shareable
0110010000011101TLBI VALE2ISTLB Invalidate by VA, Last level, EL2, Inner Shareable
0111010000011101TLBI VALE3ISTLB Invalidate by VA, Last level, EL3, Inner Shareable
0110010000011110TLBI VMALLS12E1ISTLB Invalidate by VMID, All at Stage 1 and 2, EL1, Inner Shareable
0100010000011111TLBI VAALE1ISTLB Invalidate by VA, All ASID, Last Level, EL1, Inner Shareable
0110010000100001TLBI IPAS2E1TLB Invalidate by Intermediate Physical Address, Stage 2, EL1
0110010000100101TLBI IPAS2LE1TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1
0100010000111000TLBI VMALLE1TLB Invalidate by VMID, All at stage 1, EL1
0110010000111000TLBI ALLE2TLB Invalidate All, EL2
0111010000111000TLBI ALLE3TLB Invalidate All, EL3
0100010000111001TLBI VAE1TLB Invalidate by VA, EL1
0110010000111001TLBI VAE2TLB Invalidate by VA, EL2
0111010000111001TLBI VAE3TLB Invalidate by VA, EL3
0100010000111010TLBI ASIDE1TLB Invalidate by ASID, EL1
0100010000111011TLBI VAAE1TLB Invalidate by VA, All ASID, EL1
0110010000111100TLBI ALLE1TLB Invalidate All, EL1
0100010000111101TLBI VALE1TLB Invalidate by VA, Last level, EL1
0110010000111101TLBI VALE2TLB Invalidate by VA, Last level, EL2
0111010000111101TLBI VALE3TLB Invalidate by VA, Last level, EL3
0110010000111110TLBI VMALLS12E1TLB Invalidate by VMID, All at Stage 1 and 2, EL1
0100010000111111TLBI VAALE1TLB Invalidate by VA, All ASID, Last level, EL1
01 011100 01111000 01000000 001 DC ZVA TLBI IPAS2E1IS DataTLB CacheInvalidate Zero by VAIntermediate Physical Address, Stage 2, EL1, Inner Shareable
01 000100 01111000 01100000 001101 DC IVAC TLBI IPAS2LE1IS DataTLB orInvalidate unifiedby CacheIntermediate linePhysical InvalidateAddress, byStage VA2, toLast PoClevel, EL1, Inner Shareable
01 011000 01111000 10100011 001000 DC CVAC TLBI VMALLE1IS DataTLB orInvalidate unifiedby CacheVMID, lineAll Cleanat bystage VA1, toEL1, PoCInner Shareable
01 011100 01111000 10110011 001000 DC CVAU TLBI ALLE2IS DataTLB orInvalidate unifiedAll, CacheEL2, lineInner Clean by VA to PoUShareable
01 011110 01111000 11000011 001000 DC CVAP TLBI ALLE3IS DataTLB orInvalidate unifiedAll, CacheEL3, lineInner Clean by VA to PoPShareable
01 011000 01111000 11100011 001 DC CIVAC TLBI VAE1IS DataTLB or unified Cache line Clean and Invalidate by VA, toEL1, PoCInner Shareable
01 000100 01111000 01100011 010001 DC ISW TLBI VAE2IS DataTLB orInvalidate unifiedby CacheVA, lineEL2, InvalidateInner by Set/WayShareable
01 000110 01111000 10100011 010001 DC CSW TLBI VAE3IS DataTLB orInvalidate unifiedby CacheVA, lineEL3, CleanInner by Set/WayShareable
01 000 01111000 11100011 010 DC CISW TLBI ASIDE1IS DataTLB orInvalidate unifiedby CacheASID, lineEL1, CleanInner and Invalidate by Set/WayShareable

Accessed using ICSYSL/SYS:

Register selectors Name Description
op0 op1 CRn CRm op2 Rt
01xxx 0111x11 0111xxxx 0101xxx 001 - IC IVAU S1_<op1>_<Cn>_<Cm>_<op2> InstructionIMPLEMENTATION CacheDEFINED linemaintenance Invalidate by VA to PoUinstructions
01 000 0111 0001 000 11111 IC IALLUIS Instruction Cache Invalidate All to PoU, Inner Shareable
01 000 0111 0101 000 11111 IC IALLU Instruction Cache Invalidate All to PoU

Accessed using MRSDC/MSRIC:

Register selectors Name Description
op0 op1 CRn CRm op2
1101 000 00000111 00000001 000 MIDR_EL1 IC IALLUIS MainInstruction IDCache RegisterInvalidate All to PoU, Inner Shareable
11 001 0000 0000 000 CCSIDR_EL1 Current Cache Size ID Register
0101101110100001DC ZVAData Cache Zero by VA
11 010 0000 0000 000 CSSELR_EL1 Cache Size Selection Register
0100001110101000IC IALLUInstruction Cache Invalidate All to PoU
1101 100011 00000111 00000101 000001 VPIDR_EL2 IC IVAU VirtualizationInstruction ProcessorCache IDline RegisterInvalidate by VA to PoU
1001 000 00010111 00000110 000001 MDRAR_EL1 DC IVAC MonitorData Debugor ROMunified AddressCache Registerline Invalidate by VA to PoC
1101 000 00010111 00000110 000010 SCTLR_EL1 DC ISW SystemData Controlor Registerunified (EL1)Cache line Invalidate by Set/Way
1101 100011 00010111 00001010 000001 SCTLR_EL2 DC CVAC SystemData Controlor Registerunified (EL2)Cache line Clean by VA to PoC
11 110 0001 0000 000 SCTLR_EL3 System Control Register (EL3)
0100001111010010DC CSWData or unified Cache line Clean by Set/Way
1101 000011 00100111 00001011 000001 TTBR0_EL1 DC CVAU TranslationData Tableor Baseunified RegisterCache 0line (EL1)Clean by VA to PoU
1101 100011 00100111 00001100 000001 TTBR0_EL2 DC CVAP TranslationData Tableor Baseunified RegisterCache 0line (EL2)Clean by VA to PoP
1101 110011 00100111 00001110 000001 TTBR0_EL3 DC CIVAC TranslationData Tableor Baseunified RegisterCache 0line (EL3)Clean and Invalidate by VA to PoC
11 100 0011 0000 000 DACR32_EL2 Domain Access Control Register
0100001111110010DC CISWData or unified Cache line Clean and Invalidate by Set/Way
11 000 0100 0000 000 SPSR_EL1 Saved Program Status Register (EL1)
11 100 0100 0000 000 SPSR_EL2 Saved Program Status Register (EL2)
11 110 0100 0000 000 SPSR_EL3 Saved Program Status Register (EL3)
11 000 0110 0000 000 FAR_EL1 Fault Address Register (EL1)
11 100 0110 0000 000 FAR_EL2 Fault Address Register (EL2)
11 110 0110 0000 000 FAR_EL3 Fault Address Register (EL3)
11 000 1100 0000 000 VBAR_EL1 Vector Base Address Register (EL1)
11 100 1100 0000 000 PMSCR_EL2 Statistical Profiling Control Register (EL2)
11 100 1100 0000 000 VBAR_EL2 Vector Base Address Register (EL2)
11 110 1100 0000 000 VBAR_EL3 Vector Base Address Register (EL3)
11 011 1110 0000 000 CNTFRQ_EL0 Counter-timer Frequency register
11 000 0000 0001 000 ID_PFR0_EL1 AArch32 Processor Feature Register 0
10 011 0000 0001 000 MDCCSR_EL0 Monitor DCC Status Register
11 100 0001 0001 000 HCR_EL2 Hypervisor Configuration Register
11 110 0001 0001 000 SCR_EL3 Secure Configuration Register
11 000 0010 0001 000 APIAKeyLo_EL1 Pointer Authentication Key A for Instruction (bits[63:0])
11 100 0010 0001 000 VTTBR_EL2 Virtualization Translation Table Base Register
11 000 0100 0001 000 SP_EL0 Stack Pointer (EL0)
11 100 0100 0001 000 SP_EL1 Stack Pointer (EL1)
11 110 0100 0001 000 SP_EL2 Stack Pointer (EL2)
11 000 0101 0001 000 AFSR0_EL1 Auxiliary Fault Status Register 0 (EL1)
11 100 0101 0001 000 AFSR0_EL2 Auxiliary Fault Status Register 0 (EL2)
11 110 0101 0001 000 AFSR0_EL3 Auxiliary Fault Status Register 0 (EL3)
11 000 1100 0001 000 ISR_EL1 Interrupt Status Register
11 000 1110 0001 000 CNTKCTL_EL1 Counter-timer Kernel Control register
11 100 1110 0001 000 CNTHCTL_EL2 Counter-timer Hypervisor Control register
10 000 0000 0010 000 MDCCINT_EL1 Monitor DCC Interrupt Enable Register
11 000 0000 0010 000 ID_ISAR0_EL1 AArch32 Instruction Set Attribute Register 0
11 000 0010 0010 000 APDAKeyLo_EL1 Pointer Authentication Key A for Data (bits[63:0])
11 000 0100 0010 000 SPSel Stack Pointer Select
11 011 0100 0010 000 NZCV Condition Flags
11 000 0101 0010 000 ESR_EL1 Exception Syndrome Register (EL1)
11 100 0101 0010 000 ESR_EL2 Exception Syndrome Register (EL2)
11 110 0101 0010 000 ESR_EL3 Exception Syndrome Register (EL3)
11 000 1010 0010 000 MAIR_EL1 Memory Attribute Indirection Register (EL1)
11 100 1010 0010 000 MAIR_EL2 Memory Attribute Indirection Register (EL2)
11 110 1010 0010 000 MAIR_EL3 Memory Attribute Indirection Register (EL3)
11 011 1110 0010 000 CNTP_TVAL_EL0 Counter-timer Physical Timer TimerValue register
11 100 1110 0010 000 CNTHP_TVAL_EL2 Counter-timer Hypervisor Physical Timer TimerValue register
11 111 1110 0010 000 CNTPS_TVAL_EL1 Counter-timer Physical Secure Timer TimerValue register
11 000 0000 0011 000 MVFR0_EL1 AArch32 Media and VFP Feature Register 0
11 000 0010 0011 000 APGAKeyLo_EL1 Pointer Authentication Key A for Code (bits[63:0])
11 100 0100 0011 000 SPSR_irq Saved Program Status Register (IRQ mode)
11 100 0101 0011 000 FPEXC32_EL2 Floating-Point Exception Control register
11 000 1010 0011 000 AMAIR_EL1 Auxiliary Memory Attribute Indirection Register (EL1)
11 100 1010 0011 000 AMAIR_EL2 Auxiliary Memory Attribute Indirection Register (EL2)
11 110 1010 0011 000 AMAIR_EL3 Auxiliary Memory Attribute Indirection Register (EL3)
11 011 1110 0011 000 CNTV_TVAL_EL0 Counter-timer Virtual Timer TimerValue register
11 100 1110 0011 000 CNTHV_TVAL_EL2 Counter-timer Virtual Timer TimerValue register (EL2)
11 000 0000 0100 000 ID_AA64PFR0_EL1 AArch64 Processor Feature Register 0
10 011 0000 0100 000 DBGDTR_EL0 Debug Data Transfer Register, half-duplex
11 011 0100 0100 000 FPCR Floating-point Control Register
11 000 0111 0100 000 PAR_EL1 Physical Address Register
11 000 1010 0100 000 LORSA_EL1 LORegion Start Address (EL1)
11 000 0000 0101 000 ID_AA64DFR0_EL1 AArch64 Debug Feature Register 0
10 011 0000 0101 000 DBGDTRRX_EL0 Debug Data Transfer Register, Receive
10 011 0000 0101 000 DBGDTRTX_EL0 Debug Data Transfer Register, Transmit
11 011 0100 0101 000 DSPSR_EL0 Debug Saved Program Status Register
11 000 0000 0110 000 ID_AA64ISAR0_EL1 AArch64 Instruction Set Attribute Register 0
11 000 0100 0110 000 ICC_PMR_EL1 Interrupt Controller Interrupt Priority Mask Register
11 000 0100 0110 000 ICV_PMR_EL1 Interrupt Controller Virtual Interrupt Priority Mask Register
11 000 0000 0111 000 ID_AA64MMFR0_EL1 AArch64 Memory Model Feature Register 0
10 100 0000 0111 000 DBGVCR32_EL2 Debug Vector Catch Register
11 000 1100 1000 000 ICC_IAR0_EL1 Interrupt Controller Interrupt Acknowledge Register 0
11 000 1100 1000 000 ICV_IAR0_EL1 Interrupt Controller Virtual Interrupt Acknowledge Register 0
11 000 1001 1001 000 PMSCR_EL1 Statistical Profiling Control Register (EL1)
11 000 1001 1010 000 PMBLIMITR_EL1 Profiling Buffer Limit Address Register
11 000 1001 1010 000 PMSIRR_EL1 Sampling Interval Reload Register
11 100 1100 1011 000 ICH_HCR_EL2 Interrupt Controller Hyp Control Register
11 011 1001 1100 000 PMCR_EL0 Performance Monitors Control Register
11 000 1100 1100 000 ICC_IAR1_EL1 Interrupt Controller Interrupt Acknowledge Register 1
11 000 1100 1100 000 ICV_IAR1_EL1 Interrupt Controller Virtual Interrupt Acknowledge Register 1
11 011 1001 1101 000 PMCCNTR_EL0 Performance Monitors Cycle Count Register
11 011 1001 1110 000 PMUSERENR_EL0 Performance Monitors User Enable Register
11 001 0000 0000 001 CLIDR_EL1 Cache Level ID Register
11 011 0000 0000 001 CTR_EL0 Cache Type Register
11 000 0001 0000 001 ACTLR_EL1 Auxiliary Control Register (EL1)
11 100 0001 0000 001 ACTLR_EL2 Auxiliary Control Register (EL2)
11 110 0001 0000 001 ACTLR_EL3 Auxiliary Control Register (EL3)
11 000 0010 0000 001 TTBR1_EL1 Translation Table Base Register 1 (EL1)
11 100 0010 0000 001 TTBR1_EL2 Translation Table Base Register 1 (EL2)
11 000 0100 0000 001 ELR_EL1 Exception Link Register (EL1)
11 100 0100 0000 001 ELR_EL2 Exception Link Register (EL2)
11 110 0100 0000 001 ELR_EL3 Exception Link Register (EL3)
11 100 0101 0000 001 IFSR32_EL2 Instruction Fault Status Register (EL2)
11 000 1100 0000 001 RVBAR_EL1 Reset Vector Base Address Register (if EL2 and EL3 not implemented)
11 100 1100 0000 001 RVBAR_EL2 Reset Vector Base Address Register (if EL3 not implemented)
11 110 1100 0000 001 RVBAR_EL3 Reset Vector Base Address Register (if EL3 implemented)
11 000 1101 0000 001 CONTEXTIDR_EL1 Context ID Register (EL1)
11 100 1101 0000 001 CONTEXTIDR_EL2 Context ID Register (EL2)
11 011 1110 0000 001 CNTPCT_EL0 Counter-timer Physical Count register
11 000 0000 0001 001 ID_PFR1_EL1 AArch32 Processor Feature Register 1
11 100 0001 0001 001 MDCR_EL2 Monitor Debug Configuration Register (EL2)
11 110 0001 0001 001 SDER32_EL3 AArch32 Secure Debug Enable Register
11 000 0010 0001 001 APIAKeyHi_EL1 Pointer Authentication Key A for Instruction (bits[127:64])
11 000 0101 0001 001 AFSR1_EL1 Auxiliary Fault Status Register 1 (EL1)
11 100 0101 0001 001 AFSR1_EL2 Auxiliary Fault Status Register 1 (EL2)
11 110 0101 0001 001 AFSR1_EL3 Auxiliary Fault Status Register 1 (EL3)
11 000 0000 0010 001 ID_ISAR1_EL1 AArch32 Instruction Set Attribute Register 1
11 000 0010 0010 001 APDAKeyHi_EL1 Pointer Authentication Key A for Data (bits[127:64])
11 011 0100 0010 001 DAIF Interrupt Mask Bits
11 011 1110 0010 001 CNTP_CTL_EL0 Counter-timer Physical Timer Control register
11 100 1110 0010 001 CNTHP_CTL_EL2 Counter-timer Hypervisor Physical Timer Control register
11 111 1110 0010 001 CNTPS_CTL_EL1 Counter-timer Physical Secure Timer Control register
11 000 0000 0011 001 MVFR1_EL1 AArch32 Media and VFP Feature Register 1
11 110 0001 0011 001 MDCR_EL3 Monitor Debug Configuration Register (EL3)
11 000 0010 0011 001 APGAKeyHi_EL1 Pointer Authentication Key A for Code (bits[127:64])
11 100 0100 0011 001 SPSR_abt Saved Program Status Register (Abort mode)
11 011 1110 0011 001 CNTV_CTL_EL0 Counter-timer Virtual Timer Control register
11 100 1110 0011 001 CNTHV_CTL_EL2 Counter-timer Virtual Timer Control register (EL2)
11 000 0000 0100 001 ID_AA64PFR1_EL1 AArch64 Processor Feature Register 1
11 011 0100 0100 001 FPSR Floating-point Status Register
11 000 1010 0100 001 LOREA_EL1 LORegion End Address (EL1)
11 000 0000 0101 001 ID_AA64DFR1_EL1 AArch64 Debug Feature Register 1
11 011 0100 0101 001 DLR_EL0 Debug Link Register
11 000 0000 0110 001 ID_AA64ISAR1_EL1 AArch64 Instruction Set Attribute Register 1
11 000 0000 0111 001 ID_AA64MMFR1_EL1 AArch64 Memory Model Feature Register 1
11 000 1100 1000 001 ICC_EOIR0_EL1 Interrupt Controller End Of Interrupt Register 0
11 000 1100 1000 001 ICV_EOIR0_EL1 Interrupt Controller Virtual End Of Interrupt Register 0
11 000 1001 1010 001 PMBPTR_EL1 Profiling Buffer Write Pointer Register
11 000 1100 1011 001 ICC_DIR_EL1 Interrupt Controller Deactivate Interrupt Register
11 000 1100 1011 001 ICV_DIR_EL1 Interrupt Controller Deactivate Virtual Interrupt Register
11 100 1100 1011 001 ICH_VTR_EL2 Interrupt Controller VGIC Type Register
11 011 1001 1100 001 PMCNTENSET_EL0 Performance Monitors Count Enable Set register
11 000 1100 1100 001 ICC_EOIR1_EL1 Interrupt Controller End Of Interrupt Register 1
11 000 1100 1100 001 ICV_EOIR1_EL1 Interrupt Controller Virtual End Of Interrupt Register 1
11 011 1001 1101 001 PMXEVTYPER_EL0 Performance Monitors Selected Event Type Register
11 000 1001 1110 001 PMINTENSET_EL1 Performance Monitors Interrupt Enable Set register
10 000 0000 0000 010 OSDTRRX_EL1 OS Lock Data Transfer Register, Receive
11 001 0000 0000 010 CCSIDR2_EL1 Current Cache Size ID Register 2
11 000 0001 0000 010 CPACR_EL1 Architectural Feature Access Control Register
11 000 0010 0000 010 TCR_EL1 Translation Control Register (EL1)
11 100 0010 0000 010 TCR_EL2 Translation Control Register (EL2)
11 110 0010 0000 010 TCR_EL3 Translation Control Register (EL3)
11 000 1100 0000 010 RMR_EL1 Reset Management Register (EL1)
11 100 1100 0000 010 RMR_EL2 Reset Management Register (EL2)
11 110 1100 0000 010 RMR_EL3 Reset Management Register (EL3)
11 011 1101 0000 010 TPIDR_EL0 EL0 Read/Write Software Thread ID Register
11 100 1101 0000 010 TPIDR_EL2 EL2 Software Thread ID Register
11 110 1101 0000 010 TPIDR_EL3 EL3 Software Thread ID Register
11 011 1110 0000 010 CNTVCT_EL0 Counter-timer Virtual Count register
11 000 0000 0001 010 ID_DFR0_EL1 AArch32 Debug Feature Register 0
11 100 0001 0001 010 CPTR_EL2 Architectural Feature Trap Register (EL2)
11 110 0001 0001 010 CPTR_EL3 Architectural Feature Trap Register (EL3)
11 000 0010 0001 010 APIBKeyLo_EL1 Pointer Authentication Key B for Instruction (bits[63:0])
11 100 0010 0001 010 VTCR_EL2 Virtualization Translation Control Register
10 000 0000 0010 010 MDSCR_EL1 Monitor Debug System Control Register
11 000 0000 0010 010 ID_ISAR2_EL1 AArch32 Instruction Set Attribute Register 2
11 000 0010 0010 010 APDBKeyLo_EL1 Pointer Authentication Key B for Data (bits[63:0])
11 000 0100 0010 010 CurrentEL Current Exception Level
11 011 1110 0010 010 CNTP_CVAL_EL0 Counter-timer Physical Timer CompareValue register
11 100 1110 0010 010 CNTHP_CVAL_EL2 Counter-timer Hypervisor Physical Timer CompareValue register
11 111 1110 0010 010 CNTPS_CVAL_EL1 Counter-timer Physical Secure Timer CompareValue register
10 000 0000 0011 010 OSDTRTX_EL1 OS Lock Data Transfer Register, Transmit
11 000 0000 0011 010 MVFR2_EL1 AArch32 Media and VFP Feature Register 2
11 100 0100 0011 010 SPSR_und Saved Program Status Register (Undefined mode)
11 011 1110 0011 010 CNTV_CVAL_EL0 Counter-timer Virtual Timer CompareValue register
11 100 1110 0011 010 CNTHV_CVAL_EL2 Counter-timer Virtual Timer CompareValue register (EL2)
11 000 1010 0100 010 LORN_EL1 LORegion Number (EL1)
10 000 0000 0110 010 OSECCR_EL1 OS Lock Exception Catch Control Register
11 000 0000 0111 010 ID_AA64MMFR2_EL1 AArch64 Memory Model Feature Register 2
11 000 1100 1000 010 ICC_HPPIR0_EL1 Interrupt Controller Highest Priority Pending Interrupt Register 0
11 000 1100 1000 010 ICV_HPPIR0_EL1 Interrupt Controller Virtual Highest Priority Pending Interrupt Register 0
11 000 1001 1001 010 PMSICR_EL1 Sampling Interval Counter Register
11 100 1100 1011 010 ICH_MISR_EL2 Interrupt Controller Maintenance Interrupt State Register
11 011 1001 1100 010 PMCNTENCLR_EL0 Performance Monitors Count Enable Clear register
11 000 1100 1100 010 ICC_HPPIR1_EL1 Interrupt Controller Highest Priority Pending Interrupt Register 1
11 000 1100 1100 010 ICV_HPPIR1_EL1 Interrupt Controller Virtual Highest Priority Pending Interrupt Register 1
11 011 1001 1101 010 PMXEVCNTR_EL0 Performance Monitors Selected Event Count Register
11 000 1001 1110 010 PMINTENCLR_EL1 Performance Monitors Interrupt Enable Clear register
11 011 1101 0000 011 TPIDRRO_EL0 EL0 Read-Only Software Thread ID Register
11 100 1110 0000 011 CNTVOFF_EL2 Counter-timer Virtual Offset register
11 000 0000 0001 011 ID_AFR0_EL1 AArch32 Auxiliary Feature Register 0
11 100 0001 0001 011 HSTR_EL2 Hypervisor System Trap Register
11 000 0010 0001 011 APIBKeyHi_EL1 Pointer Authentication Key B for Instruction (bits[127:64])
11 000 0000 0010 011 ID_ISAR3_EL1 AArch32 Instruction Set Attribute Register 3
11 000 0010 0010 011 APDBKeyHi_EL1 Pointer Authentication Key B for Data (bits[127:64])
11 000 0100 0010 011 PAN Privileged Access Never
11 100 0100 0011 011 SPSR_fiq Saved Program Status Register (FIQ mode)
11 000 1010 0100 011 LORC_EL1 LORegion Control (EL1)
11 000 1100 1000 011 ICC_BPR0_EL1 Interrupt Controller Binary Point Register 0
11 000 1100 1000 011 ICV_BPR0_EL1 Interrupt Controller Virtual Binary Point Register 0
11 000 1001 1010 011 PMBSR_EL1 Profiling Buffer Status/syndrome Register
11 000 1100 1011 011 ICC_RPR_EL1 Interrupt Controller Running Priority Register
11 000 1100 1011 011 ICV_RPR_EL1 Interrupt Controller Virtual Running Priority Register
11 100 1100 1011 011 ICH_EISR_EL2 Interrupt Controller End of Interrupt Status Register
11 011 1001 1100 011 PMOVSCLR_EL0 Performance Monitors Overflow Flag Status Clear Register
11 000 1100 1100 011 ICC_BPR1_EL1 Interrupt Controller Binary Point Register 1
11 000 1100 1100 011 ICV_BPR1_EL1 Interrupt Controller Virtual Binary Point Register 1
11 011 1001 1110 011 PMOVSSET_EL0 Performance Monitors Overflow Flag Status Set register
10 000 0001 0000 100 OSLAR_EL1 OS Lock Access Register
11 100 0110 0000 100 HPFAR_EL2 Hypervisor IPA Fault Address Register
11 000 1101 0000 100 TPIDR_EL1 EL1 Software Thread ID Register
11 000 0000 0001 100 ID_MMFR0_EL1 AArch32 Memory Model Feature Register 0
10 000 0001 0001 100 OSLSR_EL1 OS Lock Status Register
11 000 0000 0010 100 ID_ISAR4_EL1 AArch32 Instruction Set Attribute Register 4
11 000 0100 0010 100 UAO User Access Override
10 000 0001 0011 100 OSDLR_EL1 OS Double Lock Register
10 000 0001 0100 100 DBGPRCR_EL1 Debug Power Control Register
11 000 0000 0101 100 ID_AA64AFR0_EL1 AArch64 Auxiliary Feature Register 0
11 000 1001 1001 100 PMSFCR_EL1 Sampling Filter Control Register
11 011 1001 1100 100 PMSWINC_EL0 Performance Monitors Software Increment register
11 000 1100 1100 100 ICC_CTLR_EL1 Interrupt Controller Control Register (EL1)
11 000 1100 1100 100 ICV_CTLR_EL1 Interrupt Controller Virtual Control Register
11 110 1100 1100 100 ICC_CTLR_EL3 Interrupt Controller Control Register (EL3)
10 000 0000 xxxx 100 DBGBVR<n>_EL1 Debug Breakpoint Value Registers
11 000 0000 0000 101 MPIDR_EL1 Multiprocessor Affinity Register
11 100 0000 0000 101 VMPIDR_EL2 Virtualization Multiprocessor ID Register
11 000 0000 0001 101 ID_MMFR1_EL1 AArch32 Memory Model Feature Register 1
11 000 0000 0010 101 ID_ISAR5_EL1 AArch32 Instruction Set Attribute Register 5
11 000 0000 0101 101 ID_AA64AFR1_EL1 AArch64 Auxiliary Feature Register 1
11 000 1001 1001 101 PMSEVFR_EL1 Sampling Event Filter Register
11 100 1100 1001 101 ICC_SRE_EL2 Interrupt Controller System Register Enable register (EL2)
11 000 1100 1011 101 ICC_SGI1R_EL1 Interrupt Controller Software Generated Interrupt Group 1 Register
11 100 1100 1011 101 ICH_ELRSR_EL2 Interrupt Controller Empty List Register Status Register
11 011 1001 1100 101 PMSELR_EL0 Performance Monitors Event Counter Selection Register
11 000 1100 1100 101 ICC_SRE_EL1 Interrupt Controller System Register Enable register (EL1)
11 110 1100 1100 101 ICC_SRE_EL3 Interrupt Controller System Register Enable register (EL3)
10 000 0000 xxxx 101 DBGBCR<n>_EL1 Debug Breakpoint Control Registers
11 000 0000 0000 110 REVIDR_EL1 Revision ID Register
11 000 0000 0001 110 ID_MMFR2_EL1 AArch32 Memory Model Feature Register 2
11 000 0000 0010 110 ID_MMFR4_EL1 AArch32 Memory Model Feature Register 4
10 000 0111 1000 110 DBGCLAIMSET_EL1 Debug Claim Tag Set register
10 000 0111 1001 110 DBGCLAIMCLR_EL1 Debug Claim Tag Clear register
11 000 1001 1001 110 PMSLATFR_EL1 Sampling Latency Filter Register
11 000 1100 1011 110 ICC_ASGI1R_EL1 Interrupt Controller Alias Software Generated Interrupt Group 1 Register
11 011 1001 1100 110 PMCEID0_EL0 Performance Monitors Common Event Identification register 0
11 000 1100 1100 110 ICC_IGRPEN0_EL1 Interrupt Controller Interrupt Group 0 Enable register
11 000 1100 1100 110 ICV_IGRPEN0_EL1 Interrupt Controller Virtual Interrupt Group 0 Enable register
10 000 0111 1110 110 DBGAUTHSTATUS_EL1 Debug Authentication Status register
10 000 0000 xxxx 110 DBGWVR<n>_EL1 Debug Watchpoint Value Registers
11 001 0000 0000 111 AIDR_EL1 Auxiliary ID Register
11 011 0000 0000 111 DCZID_EL0 Data Cache Zero ID register
11 000 0000 0001 111 ID_MMFR3_EL1 AArch32 Memory Model Feature Register 3
11 100 0001 0001 111 HACR_EL2 Hypervisor Auxiliary Control Register
11 000 0000 0010 111 ID_ISAR6_EL1 AArch32 Instruction Set Attribute Register 6
11 000 1010 0100 111 LORID_EL1 LORegionID (EL1)
11 000 1001 1001 111 PMSIDR_EL1 Sampling Profiling ID Register
11 000 1001 1010 111 PMBIDR_EL1 Profiling Buffer ID Register
11 000 1100 1011 111 ICC_SGI0R_EL1 Interrupt Controller Software Generated Interrupt Group 0 Register
11 100 1100 1011 111 ICH_VMCR_EL2 Interrupt Controller Virtual Machine Control Register
11 011 1001 1100 111 PMCEID1_EL0 Performance Monitors Common Event Identification register 1
11 000 1100 1100 111 ICC_IGRPEN1_EL1 Interrupt Controller Interrupt Group 1 Enable register
11 000 1100 1100 111 ICV_IGRPEN1_EL1 Interrupt Controller Virtual Interrupt Group 1 Enable register
11 110 1100 1100 111 ICC_IGRPEN1_EL3 Interrupt Controller Interrupt Group 1 Enable register (EL3)
11 011 1110 1111 111 PMCCFILTR_EL0 Performance Monitors Cycle Count Filter Register
10 000 0000 xxxx 111 DBGWCR<n>_EL1 Debug Watchpoint Control Registers
11 100 1100 1000 0xx ICH_AP0R<n>_EL2 Interrupt Controller Hyp Active Priorities Group 0 Registers
11 000 1100 1001 0xx ICC_AP1R<n>_EL1 Interrupt Controller Active Priorities Group 1 Registers
11 000 1100 1001 0xx ICV_AP1R<n>_EL1 Interrupt Controller Virtual Active Priorities Group 1 Registers
11 100 1100 1001 0xx ICH_AP1R<n>_EL2 Interrupt Controller Hyp Active Priorities Group 1 Registers
11 000 1100 1000 1xx ICC_AP0R<n>_EL1 Interrupt Controller Active Priorities Group 0 Registers
11 000 1100 1000 1xx ICV_AP0R<n>_EL1 Interrupt Controller Virtual Active Priorities Group 0 Registers
11 011 1110 10xx xxx PMEVCNTR<n>_EL0 Performance Monitors Event Count Registers
11 100 1100 110x xxx ICH_LR<n>_EL2 Interrupt Controller List Registers
11 011 1110 11xx xxx PMEVTYPER<n>_EL0 Performance Monitors Event Type Registers
11 xxx xxxx xxxx xxx S3_<op1>_<Cn>_<Cm>_<op2> IMPLEMENTATION DEFINED registers

Accessed using SYS/SYSLAT:

Register selectors Name Description
CRn op1 op2 CRm
xxxx xxx xxx xxxx S1_<op1>_<Cn>_<Cm>_<op2> IMPLEMENTATION DEFINED maintenance instructions
Register selectorsNameDescription
op0op1CRnCRmop2
0100001111000000AT S1E1RAddress Translate Stage 1 EL1 Read
0110001111000000AT S1E2RAddress Translate Stage 1 EL2 Read
0111001111000000AT S1E3RAddress Translate Stage 1 EL3 Read
0100001111000001AT S1E1WAddress Translate Stage 1 EL1 Write
0110001111000001AT S1E2WAddress Translate Stage 1 EL2 Write
0111001111000001AT S1E3WAddress Translate Stage 1 EL3 Write
0100001111000010AT S1E0RAddress Translate Stage 1 EL0 Read
0100001111000011AT S1E0WAddress Translate Stage 1 EL0 Write
0110001111000100AT S12E1RAddress Translate Stages 1 and 2 EL1 Read
0110001111000101AT S12E1WAddress Translate Stages 1 and 2 EL1 Write
0110001111000110AT S12E0RAddress Translate Stages 1 and 2 EL0 Read
0110001111000111AT S12E0WAddress Translate Stages 1 and 2 EL0 Write
0100001111001000AT S1E1RPAddress Translate Stage 1 EL1 Read PAN
0100001111001001AT S1E1WPAddress Translate Stage 1 EL1 Write PAN

Accessed using TLBI:

Register selectors Name Description
op0 op1 CRn CRm op2 Rt
01 100 1000 0000 001 - TLBI IPAS2E1IS TLB Invalidate by Intermediate Physical Address, Stage 2, EL1, Inner Shareable
01 000 1000 0011 001 - TLBI VAE1IS TLB Invalidate by VA, EL1, Inner Shareable
01 100 1000 0011 001 - TLBI VAE2IS TLB Invalidate by VA, EL2, Inner Shareable
01 110 1000 0011 001 - TLBI VAE3IS TLB Invalidate by VA, EL3, Inner Shareable
01 100 1000 0100 001 - TLBI IPAS2E1 TLB Invalidate by Intermediate Physical Address, Stage 2, EL1
01 000 1000 0111 001 - TLBI VAE1 TLB Invalidate by VA, EL1
01 100 1000 0111 001 - TLBI VAE2 TLB Invalidate by VA, EL2
01 110 1000 0111 001 - TLBI VAE3 TLB Invalidate by VA, EL3
01 000 1000 0011 010 - TLBI ASIDE1IS TLB Invalidate by ASID, EL1, Inner Shareable
01 000 1000 0111 010 - TLBI ASIDE1 TLB Invalidate by ASID, EL1
01 000 1000 0011 011 - TLBI VAAE1IS TLB Invalidate by VA, All ASID, EL1, Inner Shareable
01 000 1000 0111 011 - TLBI VAAE1 TLB Invalidate by VA, All ASID, EL1
01 100 1000 0000 101 - TLBI IPAS2LE1IS TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Inner Shareable
01 000 1000 0011 101 - TLBI VALE1IS TLB Invalidate by VA, Last level, EL1, Inner Shareable
01 100 1000 0011 101 - TLBI VALE2IS TLB Invalidate by VA, Last level, EL2, Inner Shareable
01 110 1000 0011 101 - TLBI VALE3IS TLB Invalidate by VA, Last level, EL3, Inner Shareable
01 100 1000 0100 101 - TLBI IPAS2LE1 TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1
01 000 1000 0111 101 - TLBI VALE1 TLB Invalidate by VA, Last level, EL1
01 100 1000 0111 101 - TLBI VALE2 TLB Invalidate by VA, Last level, EL2
01 110 1000 0111 101 - TLBI VALE3 TLB Invalidate by VA, Last level, EL3
01 000 1000 0011 111 - TLBI VAALE1IS TLB Invalidate by VA, All ASID, Last Level, EL1, Inner Shareable
01 000 1000 0111 111 - TLBI VAALE1 TLB Invalidate by VA, All ASID, Last level, EL1
01 000 1000 0011 000 11111 TLBI VMALLE1IS TLB Invalidate by VMID, All at stage 1, EL1, Inner Shareable
01 100 1000 0011 000 11111 TLBI ALLE2IS TLB Invalidate All, EL2, Inner Shareable
01 110 1000 0011 000 11111 TLBI ALLE3IS TLB Invalidate All, EL3, Inner Shareable
01 000 1000 0111 000 11111 TLBI VMALLE1 TLB Invalidate by VMID, All at stage 1, EL1
01 100 1000 0111 000 11111 TLBI ALLE2 TLB Invalidate All, EL2
01 110 1000 0111 000 11111 TLBI ALLE3 TLB Invalidate All, EL3
01 100 1000 0011 100 11111 TLBI ALLE1IS TLB Invalidate All, EL1, Inner Shareable
01 100 1000 0111 100 11111 TLBI ALLE1 TLB Invalidate All, EL1
01 100 1000 0011 110 11111 TLBI VMALLS12E1IS TLB Invalidate by VMID, All at Stage 1 and 2, EL1, Inner Shareable
01 100 1000 0111 110 11111 TLBI VMALLS12E1 TLB Invalidate by VMID, All at Stage 1 and 2, EL1

28/0907/2017 0816:4140

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