TTBR0_EL2, Translation Table Base Register 0 (EL2)

The TTBR0_EL2 characteristics are:

Purpose

When HCR_EL2.E2H is 0, holds the base address of the translation table for the initial lookup for stage 1 of an address translation in the EL2 translation regime, and other information for this translation regime.

When HCR_EL2.E2H is 1, holds the base address of the translation table for the initial lookup for stage 1 of the translation of an address from the lower VA range in the EL2&0 translation regime, and other information for this translation regime.

This register is part of:

Configuration

AArch64 System register TTBR0_EL2 is architecturally mapped to AArch32 System register HTTBR.

If EL2 is not implemented, this register is RES0 from EL3.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

TTBR0_EL2 is a 64-bit register.

Field descriptions

The TTBR0_EL2 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
ASIDBADDR
BADDRCnP
313029282726252423222120191817161514131211109876543210

Any of the fields in this register are permitted to be cached in a TLB.

ASID, bits [63:48]
In ARMv8.3, ARMv8.2 and ARMv8.1:

When HCR_EL2.E2H is 0, this field is RES0.

When HCR_EL2.E2H is 1, it holds an ASID for the translation table base address. The TCR_EL2.A1 field selects either TTBR0_EL2.ASID or TTBR1_EL2.ASID.

If the implementation has only 8 bits of ASID, then the upper 8 bits of this field are RES0.


In ARMv8.0:

Reserved, RES0.

BADDR, bits [47:1]

Translation table base address, A[47:x] or A[51:x], bits[47:1].

Note

In an implementation that includes ARMv8.2-LPA, if the value of TCR_EL2.{I}PS is 110, then:

Note

In an implementation that includes ARMv8.2-LPA:

When the value of ID_AA64MMFR0_EL1.PARange indicates that the implementation does not support a 52 bit PA size, if a translation table lookup uses this register with the 64KB translation granule when the value of TCR_EL2.{I}PS is 110 and the value of register bits[5:2] is nonzero, an Address size fault is generated.

If the Effective value of TCR_EL2.{I}PS is not 110 then:

Note

This definition applies:

If any TTBR0_EL2[47:0] bit that is defined as RES0 has the value 1 when a translation table walk is performed using TTBR0_EL2, then the translation table base address might be misaligned, with effects that are CONSTRAINED UNPREDICTABLE, and must be one of the following:

The AArch64 Virtual Memory System Architecture chapter describes how x is calculated based on the value of TCR_EL2.T0SZ, the stage of translation, and the translation granule size.

CnP, bit [0]
In ARMv8.3 and ARMv8.2:

Common not Private. In an implementation that includes ARMv8.2-TTCNP, indicates whether each entry that is pointed to by TTBR0_EL2 is a member of a common set that can be used by every PE in the Inner Shareable domain for which the value of TTBR0_EL2.CnP is 1.

CnPMeaning
0

The translation table entries pointed to by TTBR0_EL2 for the current translation regime, and ASID if applicable, are permitted to differ from corresponding entries for TTBR0_EL2 for other PEs in the Inner Shareable domain. This is not affected by:

  • The value of TTBR0_EL2.CnP on those other PEs.
  • When the current translation regime is the EL2&0 regime, the value of the current ASID.
1

The translation table entries pointed to by TTBR0_EL2 are the same as the translation table entries for every other PE in the Inner Shareable domain for which the value of TTBR0_EL2.CnP is 1 and all of the following apply:

  • The translation table entries are pointed to by TTBR0_EL2.
  • The translation tables relate to the same translation regime.
  • If that translation regime is the EL2&0 regime, the ASID is the same as the current ASID.
Note

If the value of the TTBR0_EL2.CnP bit is 1 on multiple PEs in the same Inner Shareable domain and those TTBR0_EL2s do not point to the same translation table entries when the other conditions specified for the case when the value of CnP is 1 apply, then the results of translations are CONSTRAINED UNPREDICTABLE, see 'CONSTRAINED UNPREDICTABLE behaviors due to caching of control or data values' in the ARMv8-A ARM appendix K1.

In an implementation that does not include ARMv8.2-TTCNP this field is RES0.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

Accessing the TTBR0_EL2

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
TTBR0_EL21110000100000000
TTBR0_EL11100000100000000

Accessibility

The register is accessible as follows:

<systemreg> Control Accessibility
E2HTGENSEL0EL1EL2EL3
TTBR0_EL2xx0 - - n/a RW
TTBR0_EL2001 - - RWRW
TTBR0_EL2011 - n/a RWRW
TTBR0_EL2101 - - RWRW
TTBR0_EL2111 - n/a RWRW
TTBR0_EL1xx0 - TTBR0_EL1 n/a TTBR0_EL1
TTBR0_EL1001 - TTBR0_EL1 TTBR0_EL1 TTBR0_EL1
TTBR0_EL1011 - n/a TTBR0_EL1 TTBR0_EL1
TTBR0_EL1101 - TTBR0_EL1 RW TTBR0_EL1
TTBR0_EL1111 - n/a RW TTBR0_EL1

When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic TTBR0_EL2 or TTBR0_EL1 are not guaranteed to be ordered with respect to accesses using the other mnemonic.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :




28/09/2017 08:24

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