GICR_STATUSR, Error Reporting Status Register

The GICR_STATUSR characteristics are:

Purpose

Provides software with a mechanism to detect:

This register is part of the GIC Redistributor registers functional group.

Usage constraints

In an implementation that supports two Security states, there are separate Secure and Non-secure instances of this register:

Security disabledSecureNon-secure
GICR_STATUSR(S)RWRW-
GICR_STATUSR(NS)RW-RW

This is an optional register. If the register is not implemented, the location is RAZ/WI.

Configuration

A copy of this register is provided for each Redistributor.

If the GIC implementation supports two Security states this register is Banked to provide Secure and Non-secure copies.

Attributes

GICR_STATUSR is a 32-bit register.

Field descriptions

The GICR_STATUSR bit assignments are:

313029282726252423222120191817161514131211109876543210
0000000000000000000000000000WRODRWODWRDRRD

Bits [31:4]

Reserved, RES0.

WROD, bit [3]

Write to an RO location.

WRODMeaning
0

Normal operation.

1

A write to an RO location has been detected.

When a violation is detected, software must write 1 to this register to reset it.

RWOD, bit [2]

Read of a WO location.

RWODMeaning
0

Normal operation.

1

A read of a WO location has been detected.

When a violation is detected, software must write 1 to this register to reset it.

WRD, bit [1]

Write to a reserved location.

WRDMeaning
0

Normal operation.

1

A write to a reserved location has been detected.

When a violation is detected, software must write 1 to this register to reset it.

RRD, bit [0]

Read of a reserved location.

RRDMeaning
0

Normal operation.

1

A read of a reserved location has been detected.

When a violation is detected, software must write 1 to this register to reset it.

Accessing the GICR_STATUSR

GICR_STATUSR can be accessed through its memory-mapped interface:

ComponentFrameOffset
GIC RedistributorRD_base 0x0010



28/09/2017 08:24

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