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PMBSR_EL1, Profiling Buffer Status/syndrome Register

The PMBSR_EL1 characteristics are:

Purpose

Provides syndrome information to software when the buffer is disabled because the management interrupt has been raised.

This register is part of the Statistical Profiling Extension registers functional group.

Configuration

Present only if the Statistical Profiling Extension is implemented. Direct reads and writes of PMBSR_EL1 are UNDEFINED otherwise.

Attributes

PMBSR_EL1 is a 64-bit register.

Field descriptions

The PMBSR_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
00000000000000000000000000000000
EC000000DLEASCOLLMSS
313029282726252423222120191817161514131211109876543210

Bits [63:32]

Reserved, RES0.

Bits [25:20]

Reserved, RES0.

EC, bits [31:26]

Exception class

Top-level description of the cause of the buffer management event

ECMeaningMSS
0b100100

Stage 1 Data Abort on write to Profiling Buffer

stage-x-data-abort
0b100101

Stage 2 Data Abort on write to Profiling Buffer

stage-x-data-abort
0b000000

Other buffer management event. All buffer management events other than those described by other defined Exception class codes.

other-buffer-management-event

All other values are reserved. Reserved values might be defined in a future version of the architecture.

DL, bit [19]

Partial record lost

Following a buffer management event other than an asynchronous external abort, indicates whether the last record written to the Profiling Buffer is complete

DLMeaning
0b0

PMBPTR_EL1 points to the first byte after the last complete record written to the Profiling Buffer

0b1

Part of a record was lost because of a buffer management event or synchronous external abort. PMBPTR_EL1 might not point to the first byte after the last complete record written to the buffer, and so restarting collection might result in a data record stream that software cannot parse. All records prior to the last record have been written to the buffer

When the buffer management event was because of an asynchronous external abort, this bit is set to 1 and software must not assume that any valid data has been written to the Profiling Buffer

EA, bit [18]

External abort

EAMeaning
0b0

An external abort has not been asserted

0b1

An external abort has been asserted and detected by the Statistical Profiling Extension

This bit is RES0 if the PE never sets this bit as the result of an external abort.

S, bit [17]

Service

SMeaning
0b0

PMBIRQ is not asserted

0b1

PMBIRQ is asserted. All profiling data has either been written to the buffer or discarded

COLL, bit [16]

Collision detected

COLLMeaning
0b0

No collision events detected

0b1

At least one collision event was recorded

MSS, bits [15:0]

Management Event Specific Syndrome

Contains syndrome specific to the management event

The syndrome contents for each management event are described in the following sections

MSS encoding for 0b000000

This is the layout of the MSS field for exceptions with the following EC values:

1514131211109876543210
0000000000FSC

Bits [15:6]

Reserved, RES0.

FSC, bits [5:0]

Fault status code

FSCMeaning
0b0000xx

Address Size fault. Bits [1:0] encode the level

0b0001xx

Translation fault. Bits [1:0] encode the level

0b0010xx

Access Flag fault. Bits [1:0] encode the level

0b0011xx

Permission fault. Bits [1:0] encode the level

0b010000

Synchronous external abort on write

0b0101xx

Synchronous external abort on translation table walk or hardware update of translation table. Bits [1:0] encode the level

0b010001

Asynchronous external abort on write

0b100001

Alignment fault

0b110000

TLB Conflict fault

0b110101

Unsupported Access fault

All other values are reserved. Reserved values might be defined in a future version of the architecture.

MSS encoding for 0b10010x

This is the layout of the MSS field for exceptions with the following EC values:

1514131211109876543210
0000000000BSC

Bits [15:6]

Reserved, RES0.

BSC, bits [5:0]

Buffer status code

BSCMeaning
0b000000

Buffer not filled

0b000001

Buffer filled

All other values are reserved. Reserved values might be defined in a future version of the architecture.

Accessing the PMBSR_EL1

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> CRnop0op1op2CRm
PMBSR_EL11001110000111010

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RW n/a RW
x01 - RWRWRW
x11 - n/a RWRW

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.




12/09/2017 18:03

Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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