The ID_AA64DFR0_EL1 characteristics are:
Provides top level information about the debug system in AArch64 state.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.
This register is part of the Identification registers functional group.
The external register EDDFR gives information from this register.
ID_AA64DFR0_EL1 is a 64-bit register.
The ID_AA64DFR0_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | PMSVer | |||
CTX_CMPs | 0 | 0 | 0 | 0 | WRPs | 0 | 0 | 0 | 0 | BRPs | PMUVer | TraceVer | DebugVer | ||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Statistical Profiling Extension version. When the Statistical Profiling Extension is implemented, the defined values of this field are:
PMSVer | Meaning |
---|---|
0000 |
No Statistical Profiling extension. |
0001 |
Version 1 of the Statistical Profiling extension present. |
All other values are reserved.
When the Statistical Profiling Extension is not implemented this field is reserved, RES0.
Reserved, RES0.
Number of breakpoints that are context-aware, minus 1. These are the highest numbered breakpoints.
Reserved, RES0.
Number of watchpoints, minus 1. The value of 0b0000 is reserved.
Reserved, RES0.
Number of breakpoints, minus 1. The value of 0b0000 is reserved.
Performance Monitors Extension version. Indicates whether System register interface to Performance Monitors extension is implemented. Defined values are:
PMUVer | Meaning |
---|---|
0000 |
Performance Monitors Extension System registers not implemented. |
0001 |
Performance Monitors Extension System registers implemented, PMUv3. |
0100 |
Performance Monitors Extension System registers implemented, PMUv3, with a 16-bit evtCount field, and if EL2 is implemented, the addition of the MDCR_EL2.HPMD bit. |
1111 |
IMPLEMENTATION DEFINED form of performance monitors supported, PMUv3 not supported. |
ARMv8.1-PMU implements the functionality added by the value 0100.
All other values are reserved.
From ARMv8.1 the value 0001 is not permitted.
Trace support. Indicates whether System register interface to a trace macrocell is implemented. Defined values are:
TraceVer | Meaning |
---|---|
0000 |
Trace macrocell System registers not implemented. |
0001 |
Trace macrocell System registers implemented. |
All other values are reserved.
A value of 0b0000 only indicates that no System register interface to a trace macrocell is implemented. A trace macrocell might nevertheless be implemented without a System register interface.
Debug architecture version. Indicates presence of ARMv8 debug architecture.
DebugVer | Meaning |
---|---|
0110 |
ARMv8 debug architecture. |
0111 |
ARMv8 debug architecture with Virtualization Host Extensions. |
1000 |
ARMv8.2 debug architecture |
All other values are reserved.
ARMv8.2-Debug adds the functionality indicated by the value 1000.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
ID_AA64DFR0_EL1 | 11 | 000 | 0000 | 0101 | 000 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
28/09/2017 08:24
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