The OSLSR_EL1 characteristics are:
Provides the status of the OS lock.
This register is part of the Debug registers functional group.
AArch64 System register OSLSR_EL1 is architecturally mapped to AArch32 System register DBGOSLSR.
This register is in the Cold reset domain. Some or all RW fields of this register have defined reset values. On a Cold reset these apply only if the PE resets into an Exception level that is using AArch64. Otherwise, on a Cold reset RW fields in this register reset to architecturally UNKNOWN values. The register is not affected by a Warm reset.
OSLSR_EL1 is a 32-bit register.
The OSLSR_EL1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | OSLM[1] | nTT | OSLK | OSLM[0] |
Reserved, RES0.
See below for description of the OSLM field.
Not 32-bit access. This bit is always RAZ. It indicates that a 32-bit access is needed to write the key to the OS Lock Access Register.
OS Lock Status. The possible values are:
OSLK | Meaning |
---|---|
0 |
OS lock unlocked. |
1 |
OS lock locked. |
The OS lock is locked and unlocked by writing to the OS Lock Access Register.
When this register has an architecturally-defined reset value, this field resets to 1.
OS lock model implemented. Identifies the form of OS save and restore mechanism implemented. In ARMv8 these bits are as follows:
OSLM | Meaning |
---|---|
10 |
OS lock implemented. DBGOSSRR not implemented. |
All other values are reserved.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
OSLSR_EL1 | 10 | 000 | 0001 | 0001 | 100 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TDOSA==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TDOSA==1, read accesses to this register from EL1 and EL2 are trapped to EL3.
28/09/2017 08:24
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