The CNTKCTL characteristics are:
Controls the generation of an event stream from the virtual counter, and access from EL0 modes to the physical counter, virtual counter, EL1 physical timers, and the virtual timer.
This register is part of the Generic Timer registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register CNTKCTL is architecturally mapped to AArch64 System register CNTKCTL_EL1.
RW fields in this register reset to architecturally UNKNOWN values.
CNTKCTL is a 32-bit register.
The CNTKCTL bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | PL0PTEN | PL0VTEN | EVNTI | EVNTDIR | EVNTEN | PL0VCTEN | PL0PCTEN |
Reserved, RES0.
Traps PL0 accesses to the physical timer registers to Undefined mode.
PL0PTEN | Meaning |
---|---|
0 |
PL0 accesses to the CNTP_CTL, CNTP_CVAL, and CNTP_TVAL registers are trapped to Undefined mode. |
1 |
This control does not cause any instructions to be trapped. |
Traps PL0 accesses to the virtual timer registers to Undefined mode.
PL0VTEN | Meaning |
---|---|
0 |
PL0 accesses to the CNTV_CTL, CNTV_CVAL, and CNTV_TVAL registers are trapped to Undefined mode. |
1 |
This control does not cause any instructions to be trapped. |
Selects which bit (0 to 15) of the counter register CNTVCT is the trigger for the event stream generated from that counter, when that stream is enabled.
Controls which transition of the counter register CNTVCT trigger bit, defined by EVNTI, generates an event when the event stream is enabled:
EVNTDIR | Meaning |
---|---|
0 |
A 0 to 1 transition of the trigger bit triggers an event. |
1 |
A 1 to 0 transition of the trigger bit triggers an event. |
Enables the generation of an event stream from the counter register CNTVCT:
EVNTEN | Meaning |
---|---|
0 |
Disables the event stream. |
1 |
Enables the event stream. |
Traps PL0 accesses to the frequency register and virtual counter register to Undefined mode.
PL0VCTEN | Meaning |
---|---|
0 |
PL0 accesses to the CNTVCT are trapped to Undefined mode. PL0 accesses to the CNTFRQ register are trapped to Undefined mode, if CNTKCTL.PL0PCTEN is also 0. |
1 |
This control does not cause any instructions to be trapped. |
Traps PL0 accesses to the frequency register and physical counter register to Undefined mode.
PL0PCTEN | Meaning |
---|---|
0 |
PL0 accesses to the CNTPCT are trapped to Undefined mode. PL0 accesses to the CNTFRQ register are trapped to Undefined mode, if CNTKCTL.PL0VCTEN is also 0. |
1 |
This control does not cause any instructions to be trapped. |
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c14, c1, 0 | 000 | 000 | 1110 | 1111 | 0001 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RW | n/a | RW |
x | 0 | 1 | - | RW | RW | RW |
x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
28/09/2017 08:24
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