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The PMSCR_EL1 characteristics are:
Provides EL1 controls for Statistical Profiling
This register is part of the Statistical Profiling Extension registers functional group.
Present only if the Statistical Profiling Extension is implemented. Direct reads and writes of PMSCR_EL1 are UNDEFINED otherwise
PMSCR_EL1 is a 64-bit register.
The PMSCR_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | PCT | TS | PA | CX | 0 | E1SPE | E0SPE |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Reserved, RES0.
Physical Timestamp
If timestamp sampling is enabled, determines which counter is collected
PCT | Meaning |
---|---|
0b0 | Virtual counter, CNTVCT_EL0, is collected |
0b1 | Physical counter, CNTPCT_EL0, is collected |
If MDCR_EL2.E2PB != 0b00 and the PE is in Non-secure state, this bit is combined with PMSCR_EL2.PCT to determine which counter is collected
This bit is ignored by the PE when in Non-secure state and MDCR_EL2.E2PB == 0b00.
If EL2 is not implemented this bit is RES1.
Timestamp Enable
TS | Meaning |
---|---|
0b0 | Timestamp sampling disabled |
0b1 | Timestamp sampling enabled |
This bit is ignored by the PE when in Non-secure state and MDCR_EL2.E2PB == 0b00.
Physical Address Sample Enable
PA | Meaning |
---|---|
0b0 | Physical addresses are not collected |
0b1 | Physical addresses are collected |
If MDCR_EL2.E2PB != 0b00 and the PE is in Non-secure state, this bit is combined with PMSCR_EL2.PA to determine which address is collected
This bit is ignored by the PE when in Non-secure state and MDCR_EL2.E2PB == 0b00.
CONTEXTIDR_EL1 Sample Enable
CX | Meaning |
---|---|
0b0 | CONTEXTIDR_EL1 is not collected |
0b1 | CONTEXTIDR_EL1 is collected |
This bit is ignored by the PE when any of the following are true:
EL1 Statistical Profiling Enable
E1SPE | Meaning |
---|---|
0b0 | Sampling disabled at EL1 |
0b1 | Sampling enabled at EL1 |
This bit is ignored by the PE when in Non-secure state and HCR_EL2.TGE == 1.
EL0 Statistical Profiling Enable
E0SPE | Meaning |
---|---|
0b0 | Sampling disabled at EL0 |
0b1 | Sampling enabled at EL0 |
This bit is ignored by the PE when in Non-secure state and HCR_EL2.TGE == 1.
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | CRn | op0 | op1 | op2 | CRm |
---|---|---|---|---|---|
PMSCR_EL1 | 1001 | 11 | 000 | 000 | 1001 |
PMSCR_EL12 | 1001 | 11 | 101 | 000 | 1001 |
The register is accessible as follows:
<systemreg> | Control | Accessibility | |||||
---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | |
PMSCR_EL1 | x | x | 0 | - | RW | n/a | RW |
PMSCR_EL1 | 0 | 0 | 1 | - | RW | RW | RW |
PMSCR_EL1 | 0 | 1 | 1 | - | n/a | RW | RW |
PMSCR_EL1 | 1 | 0 | 1 | - | RW | PMSCR_EL2 | RW |
PMSCR_EL1 | 1 | 1 | 1 | - | n/a | PMSCR_EL2 | RW |
PMSCR_EL12 | x | x | 0 | - | - | n/a | - |
PMSCR_EL12 | 0 | 0 | 1 | - | - | - | - |
PMSCR_EL12 | 0 | 1 | 1 | - | n/a | - | - |
PMSCR_EL12 | 1 | 0 | 1 | - | - | RW | RW |
PMSCR_EL12 | 1 | 1 | 1 | - | n/a | RW | RW |
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
If AArch64-MDCR_EL2.TPMS == 0b1 && AArch64-SCR_EL3.NS == 0b1, then access from EL1 traps to EL2
If AArch64-MDCR_EL3.NSPB != 0b01 && AArch64-SCR_EL3.NS == 0b0, then access from EL1 traps to EL3
If AArch64-MDCR_EL3.NSPB != 0b11 && AArch64-SCR_EL3.NS == 0b1, then access from EL2 or EL1 traps to EL3
12/09/2017 18:03
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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