The CNTHP_CVAL characteristics are:
Holds the compare value for the Hyp mode physical timer.
This register is part of:
AArch32 System register CNTHP_CVAL is architecturally mapped to AArch64 System register CNTHP_CVAL_EL2.
If EL2 is not implemented, this register is RES0 from EL3.
RW fields in this register reset to architecturally UNKNOWN values.
CNTHP_CVAL is a 64-bit register.
The CNTHP_CVAL bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
CompareValue | |||||||||||||||||||||||||||||||
CompareValue | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Holds the EL2 physical timer CompareValue.
When CNTHP_CTL.ENABLE is 1, the timer condition is met when (CNTPCT - CompareValue) is greater than or equal to zero. This means that CompareValue acts like a 64-bit upcounter timer. When the timer condition is met:
When CNTHP_CTL.ENABLE is 0, the timer condition is not met, but CNTPCT continues to count.
This register can be read using MRRC with the following syntax:
MRRC <syntax>
This register can be written using MCRR with the following syntax:
MCRR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | coproc | CRm |
---|---|---|---|
p15, 6, <Rt>, <Rt2>, c14 | 0110 | 1111 | 1110 |
p15, 2, <Rt>, <Rt2>, c14 | 0010 | 1111 | 1110 |
The register is accessible as follows:
<syntax> | Control | Accessibility | |||||
---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | |
p15, 6, <Rt>, <Rt2>, c14 | x | x | 0 | - | - | n/a | - |
p15, 6, <Rt>, <Rt2>, c14 | x | 0 | 1 | - | - | RW | RW |
p15, 6, <Rt>, <Rt2>, c14 | x | 1 | 1 | - | n/a | RW | RW |
p15, 2, <Rt>, <Rt2>, c14 | x | x | 0 | CNTP_CVAL | CNTP_CVAL | n/a | CNTP_CVAL |
p15, 2, <Rt>, <Rt2>, c14 | 0 | 0 | 1 | CNTP_CVAL | CNTP_CVAL | CNTP_CVAL | CNTP_CVAL |
p15, 2, <Rt>, <Rt2>, c14 | 0 | 1 | 1 | CNTP_CVAL | n/a | CNTP_CVAL | CNTP_CVAL |
p15, 2, <Rt>, <Rt2>, c14 | 1 | 0 | 1 | CNTP_CVAL | CNTP_CVAL | n/a | n/a |
p15, 2, <Rt>, <Rt2>, c14 | 1 | 1 | 1 | RW | n/a | n/a | n/a |
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==1 :
If CNTHCTL_EL2.EL0PTEN==0, Non-secure accesses to this register from EL0 are trapped to EL2.
28/09/2017 08:24
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