The EDDEVARCH characteristics are:
Identifies the programmers' model architecture of the external debug component.
This register is part of the Debug registers functional group.
This register is accessible as follows:
Default |
---|
RO |
EDDEVARCH is in the Debug power domain.
Implementation of this register is OPTIONAL.
EDDEVARCH is a 32-bit register.
The EDDEVARCH bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ARCHITECT | PRESENT | REVISION | ARCHID |
Defines the architecture of the component. For debug, this is ARM Limited.
Bits [31:28] are the JEP106 continuation code, 0x4.
Bits [27:21] are the JEP106 ID code, 0x3B.
When set to 1, indicates that the DEVARCH is present.
This field is 1 in ARMv8.
Defines the architecture revision. For architectures defined by ARM this is the minor revision.
For debug, the revision defined by ARMv8 is 0x0.
All other values are reserved.
Defines this part to be an ARMv8 debug component. For architectures defined by ARM this is further subdivided.
For debug:
EDDEVARCH can be accessed through the external debug interface:
Component | Offset |
---|---|
Debug | 0xFBC |
28/09/2017 08:24
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