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The CNTHV_TVAL_EL2 characteristics are:
Holds the timer value for the EL2 virtual timer.
This register is part of the Generic Timer registers functional group.
AArch64 System register CNTHV_TVAL_EL2 is architecturally mapped to AArch32 System register CNTHV_TVAL.
If EL2 is not implemented, this register is RES0 from EL3.
RW fields in this register reset to architecturally UNKNOWN values.
This register is introduced in ARMv8.1.
CNTHV_TVAL_EL2 is a 32-bit register.
The CNTHV_TVAL_EL2 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TimerValue |
The TimerValue view of the EL2 virtual timer.
On a read of this register:
On a write of this register, CNTHV_CVAL_EL2 is set to (CNTVCT_EL0 + TimerValue), where TimerValue is treated as a signed 32-bit integer.
When CNTHV_CTL_EL2.ENABLE is 1, the timer condition is met when ((CNTVCT_EL0 - CNTHV_CVAL_EL2) is greater than or equal to zero. This means that TimerValue acts like a 32-bit downcounter timer. When the timer condition is met:
When CNTHV_CTL_EL2.ENABLE is 0, the timer condition is not met, but CNTVCT_EL0 continues to count, so the TimerValue view appears to continue to count down.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
CNTHV_TVAL_EL2 | 11 | 100 | 1110 | 0011 | 000 |
CNTV_TVAL_EL0 | 11 | 011 | 1110 | 0011 | 000 |
The register is accessible as follows:
<systemreg> | Control | Accessibility | |||||
---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | |
CNTHV_TVAL_EL2 | x | x | 0 | - | - | n/a | RW |
CNTHV_TVAL_EL2 | 0 | 0 | 1 | - | - | RW | RW |
CNTHV_TVAL_EL2 | 0 | 1 | 1 | - | n/a | RW | RW |
CNTHV_TVAL_EL2 | 1 | 0 | 1 | - | - | RW | RW |
CNTHV_TVAL_EL2 | 1 | 1 | 1 | - | n/a | RW | RW |
CNTV_TVAL_EL0 | x | x | 0 | CNTV_TVAL_EL0 | CNTV_TVAL_EL0 | n/a | CNTV_TVAL_EL0 |
CNTV_TVAL_EL0 | 0 | 0 | 1 | CNTV_TVAL_EL0 | CNTV_TVAL_EL0 | CNTV_TVAL_EL0 | CNTV_TVAL_EL0 |
CNTV_TVAL_EL0 | 0 | 1 | 1 | CNTV_TVAL_EL0 | n/a | CNTV_TVAL_EL0 | CNTV_TVAL_EL0 |
CNTV_TVAL_EL0 | 1 | 0 | 1 | CNTV_TVAL_EL0 | CNTV_TVAL_EL0 | RW | CNTV_TVAL_EL0 |
CNTV_TVAL_EL0 | 1 | 1 | 1 | RW | n/a | RW | CNTV_TVAL_EL0 |
When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic CNTHV_TVAL_EL2 or CNTV_TVAL_EL0 are not guaranteed to be ordered with respect to accesses using the other mnemonic.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.NV==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.NV==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==1 :
If CNTHCTL_EL2.EL0VTEN==0, Non-secure accesses to this register from EL0 are trapped to EL2.
28/0907/2017 0816:2440
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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