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PMSEVFR_EL1, Sampling Event Filter Register

The PMSEVFR_EL1 characteristics are:

Purpose

Controls sample filtering by events. The overall filter is the logical AND of these filters. For example, if E[3] and E[5] are both set to 1, only samples that have both event 3 (Level 1 unified or data cache refill) and event 5 set (TLB walk) are recorded

This register is part of the Statistical Profiling Extension registers functional group.

Configuration

Present only if the Statistical Profiling Extension is implemented. Direct reads and writes of PMSEVFR_EL1 are UNDEFINED otherwise.

Attributes

PMSEVFR_EL1 is a 64-bit register.

Field descriptions

The PMSEVFR_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
E0000000000000000
E00000000E0000E[7]0E[5]0E[3]0E[1]0
313029282726252423222120191817161514131211109876543210

E, bits [63:48]

E[n] is the event filter for event n. If event n is not implemented, or filtering on event n is not supported, the corresponding bit is RES0.

EMeaning
0b0

Event n is ignored.

0b1

Record samples that have event n == 1

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, if the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0b0

E, bits [31:24]

E[n] is the event filter for event n. If event n is not implemented, or filtering on event n is not supported, the corresponding bit is RES0.

EMeaning
0b0

Event n is ignored.

0b1

Record samples that have event n == 1

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, if the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0b0

E, bits [15:12]

E[n] is the event filter for event n. If event n is not implemented, or filtering on event n is not supported, the corresponding bit is RES0.

EMeaning
0b0

Event n is ignored.

0b1

Record samples that have event n == 1

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, if the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0b0

Bits [47:32]

Reserved, RES0.

Bits [23:16]

Reserved, RES0.

Bits [11:8]

Reserved, RES0.

Bit [6]

Reserved, RES0.

Bit [4]

Reserved, RES0.

Bit [2]

Reserved, RES0.

Bit [0]

Reserved, RES0.

E[7], bit [7]

Mispredicted

E[7]Meaning
0b0

Mispredicted event is ignored.

0b1

Record samples that have event 7 (Mispredicted) == 1

This bit is ignored by the PE when PMSFCR_EL1.FE == 0.

E[5], bit [5]

TLB walk

E[5]Meaning
0b0

TLB walk event is ignored.

0b1

Record samples that have event 5 (TLB walk) == 1

This bit is ignored by the PE when PMSFCR_EL1.FE == 0.

E[3], bit [3]

Level 1 data or unified cache refill

E[3]Meaning
0b0

Level 1 data or unified cache refill event is ignored.

0b1

Record samples that have event 3 (Level 1 data or unified cache refill) == 1

This bit is ignored by the PE when PMSFCR_EL1.FE == 0.

E[1], bit [1]

Architecturally retired

E[1]Meaning
0b0

Architecturally retired event is ignored.

0b1

Record samples that have event 1 (Architecturally retired) == 1

This bit is ignored by the PE when PMSFCR_EL1.FE == 0.

If the PE does not support sampling of speculative instructions this bit is RES1.

Accessing the PMSEVFR_EL1

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> CRnop0op1op2CRm
PMSEVFR_EL11001110001011001

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RW n/a RW
x01 - RWRWRW
x11 - n/a RWRW

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.




12/09/2017 18:03

Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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