The GICV_RPR characteristics are:
This register indicates the running priority of the virtual CPU interface.
This register corresponds to the physical CPU interface register GICC_RPR.
This register is part of the GIC virtual CPU interface registers functional group.
This register is accessible as follows:
Security disabled | Secure | Non-secure |
---|---|---|
RO | RO | RO |
This register is used only when System register access is not enabled. When System register access is enabled:
Depending on the implementation, if no bits are set to 1 in GICH_APR<n>, indicating no active virtual interrupts in the virtual CPU interface, the priority reads as 0xFF or 0xF8 to reflect the number of supported interrupt priority bits defined by GICH_VTR.PRIbits.
This register is available when the GIC implementation supports interrupt virtualization.
GICV_RPR is a 32-bit register.
The GICV_RPR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Priority |
Reserved, RES0.
The current running priority on the virtual CPU interface. This is the group priority of the current active interrupt.
If there are no active interrupts on the CPU interface, or all active interrupts have undergone a priority drop, the value returned is the Idle priority.
The priority returned is the group priority as if the BPR was set to the minimum value.
GICV_RPR can be accessed through its memory-mapped interface:
Component | Offset |
---|---|
GIC Virtual CPU interface | 0x0014 |
28/09/2017 08:24
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