ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2

The ID_MMFR2_EL1 characteristics are:

Purpose

Provides information about the implemented memory model and memory management support in AArch32 state.

Must be interpreted with ID_MMFR0_EL1, ID_MMFR1_EL1, ID_MMFR3_EL1, and ID_MMFR4_EL1.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.

This register is part of the Identification registers functional group.

Configuration

AArch64 System register ID_MMFR2_EL1 is architecturally mapped to AArch32 System register ID_MMFR2.

In an implementation that supports only AArch64 state, this register is UNKNOWN.

Attributes

ID_MMFR2_EL1 is a 32-bit register.

Field descriptions

The ID_MMFR2_EL1 bit assignments are:

313029282726252423222120191817161514131211109876543210
HWAccFlgWFIStallMemBarrUniTLBHvdTLBL1HvdRngL1HvdBGL1HvdFG

HWAccFlg, bits [31:28]

Hardware Access Flag. In earlier versions of the ARM Architecture, this field indicates support for a Hardware Access flag, as part of the VMSAv7 implementation. Defined values are:

HWAccFlgMeaning
0000

Not supported.

0001

Support for VMSAv7 Access flag, updated in hardware.

All other values are reserved.

In ARMv8 the only permitted value is 0000.

WFIStall, bits [27:24]

Wait For Interrupt Stall. Indicates the support for Wait For Interrupt (WFI) stalling. Defined values are:

WFIStallMeaning
0000

Not supported.

0001

Support for WFI stalling.

All other values are reserved.

In ARMv8 the permitted values are 0000 and 0001.

MemBarr, bits [23:20]

Memory Barrier. Indicates the supported memory barrier System instructions in the (coproc==1111) encoding space:

MemBarrMeaning
0000

None supported.

0001

Supported memory barrier System instructions are:

  • Data Synchronization Barrier (DSB).
0010

As for 0001, and adds:

  • Instruction Synchronization Barrier (ISB).
  • Data Memory Barrier (DMB).

All other values are reserved.

In ARMv8 the only permitted value is 0010.

ARM deprecates the use of these operations. ID_ISAR4.Barrier_instrs indicates the level of support for the preferred barrier instructions.

UniTLB, bits [19:16]

Unified TLB. Indicates the supported TLB maintenance operations, for a unified TLB implementation. Defined values are:

UniTLBMeaning
0000

Not supported.

0001

Supported unified TLB maintenance operations are:

  • Invalidate all entries in the TLB.
  • Invalidate TLB entry by VA.
0010

As for 0001, and adds:

  • Invalidate TLB entries by ASID match.
0011

As for 0010, and adds:

  • Invalidate instruction TLB and data TLB entries by VA All ASID. This is a shared unified TLB operation.
0100

As for 0011, and adds:

  • Invalidate Hyp mode unified TLB entry by VA.
  • Invalidate entire Non-secure PL1&0 unified TLB.
  • Invalidate entire Hyp mode unified TLB.
0101

As for 0100, and adds the following operations: TLBIMVALIS, TLBIMVAALIS, TLBIMVALHIS, TLBIMVAL, TLBIMVAAL, TLBIMVALH.

0110

As for 0101, and adds the following operations: TLBIIPAS2IS, TLBIIPAS2LIS, TLBIIPAS2, TLBIIPAS2L.

All other values are reserved.

In ARMv8-A the only permitted value is 0110.

HvdTLB, bits [15:12]

If the Unified TLB field (UniTLB, bits [19:16]) is not 0000, then the meaning of this field is IMPLEMENTATION DEFINED. ARM deprecates the use of this field by software.

L1HvdRng, bits [11:8]

Level 1 Harvard cache Range. Indicates the supported Level 1 cache maintenance range operations, for a Harvard cache implementation. Defined values are:

L1HvdRngMeaning
0000

Not supported.

0001

Supported Level 1 Harvard cache maintenance range operations are:

  • Invalidate data cache range by VA.
  • Invalidate instruction cache range by VA.
  • Clean data cache range by VA.
  • Clean and invalidate data cache range by VA.

All other values are reserved.

In ARMv8 the only permitted value is 0000.

L1HvdBG, bits [7:4]

Level 1 Harvard cache Background fetch. Indicates the supported Level 1 cache background fetch operations, for a Harvard cache implementation. When supported, background fetch operations are non-blocking operations. Defined values are:

L1HvdBGMeaning
0000

Not supported.

0001

Supported Level 1 Harvard cache background fetch operations are:

  • Fetch instruction cache range by VA.
  • Fetch data cache range by VA.

All other values are reserved.

In ARMv8 the only permitted value is 0000.

L1HvdFG, bits [3:0]

Level 1 Harvard cache Foreground fetch. Indicates the supported Level 1 cache foreground fetch operations, for a Harvard cache implementation. When supported, foreground fetch operations are blocking operations. Defined values are:

L1HvdFGMeaning
0000

Not supported.

0001

Supported Level 1 Harvard cache foreground fetch operations are:

  • Fetch instruction cache range by VA.
  • Fetch data cache range by VA.

All other values are reserved.

In ARMv8 the only permitted value is 0000.

Accessing the ID_MMFR2_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
ID_MMFR2_EL11100000000001110

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RO n/a RO
x01 - RORORO
x11 - n/a RORO

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :




28/09/2017 08:24

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