ICC_SRE, Interrupt Controller System Register Enable register

The ICC_SRE characteristics are:

Purpose

Controls whether the System register interface or the memory-mapped interface to the GIC CPU interface is used for EL0 and EL1.

This register is part of:

Configuration

AArch32 System register ICC_SRE (S) is architecturally mapped to AArch64 System register ICC_SRE_EL1 (S) .

AArch32 System register ICC_SRE (NS) is architecturally mapped to AArch64 System register ICC_SRE_EL1 (NS) .

Attributes

ICC_SRE is a 32-bit register.

Field descriptions

The ICC_SRE bit assignments are:

313029282726252423222120191817161514131211109876543210
00000000000000000000000000000DIBDFBSRE

Bits [31:3]

Reserved, RES0.

DIB, bit [2]

Disable IRQ bypass.

DIBMeaning
0

IRQ bypass enabled.

1

IRQ bypass disabled.

If EL3 is implemented and GICD_CTLR.DS == 0, this field is a read-only alias of ICC_MSRE.DIB.

If EL3 is implemented and GICD_CTLR.DS == 1, and EL2 is not implemented, this field is a read-write alias of ICC_MSRE.DIB.

If EL3 is not implemented or GICD_CTLR.DS == 1, and EL2 is implemented, this field is a read-only alias of ICC_HSRE.DIB.

In systems that do not support IRQ bypass, this field is RAO/WI.

When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.

DFB, bit [1]

Disable FIQ bypass.

DFBMeaning
0

FIQ bypass enabled.

1

FIQ bypass disabled.

If EL3 is implemented and GICD_CTLR.DS == 0, this field is a read-only alias of ICC_MSRE.DFB.

If EL3 is implemented and GICD_CTLR.DS == 1, and EL2 is not implemented, this field is a read-write alias of ICC_MSRE.DFB.

If EL3 is not implemented or GICD_CTLR.DS == 1, and EL2 is implemented, this field is a read-only alias of ICC_HSRE.DFB.

In systems that do not support FIQ bypass, this field is RAO/WI.

When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.

SRE, bit [0]

System Register Enable.

SREMeaning
0

The memory-mapped interface must be used. Accesses at EL1 to any ICC_* System register other than ICC_SRE are UNDEFINED.

1

The System register interface for the current Security state is enabled.

If software changes this bit from 1 to 0 in the Secure instance of this register, the results are UNPREDICTABLE.

If an implementation supports only a System register interface to the GIC CPU interface, this bit is RAO/WI.

If EL3 is implemented and using AArch64:

If EL3 is implemented and using AArch32:

If EL2 is implemented and using AArch64:

If EL2 is implemented and using AArch32:

When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to 0.

Accessing the ICC_SRE

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 0, <Rt>, c12, c12, 5000101110011111100

Accessibility

The register is accessible as follows:

Configuration Control Accessibility Instance
TGENSEL0EL1EL2EL3
EL3 not implemented x0 - RW n/a - ICC_SRE
EL3 not implemented 01 - RWRW - ICC_SRE
EL3 not implemented 11 - n/a RW - ICC_SRE
EL3 using AArch6401 - RWRW - ICC_SRE_ns
EL3 using AArch6411 - n/a RW - ICC_SRE_ns
EL3 using AArch3201 - RWRWRWICC_SRE_ns
EL3 using AArch3211 - n/a RWRWICC_SRE_ns
EL3 using AArch64x0 - RW n/a - ICC_SRE_s
EL3 using AArch32x0 - - - RWICC_SRE_s

This table applies to all instructions that can access this register.

The GIC architecture permits, but does not require, that registers can be shared between memory-mapped registers and the equivalent System registers. This means that if the memory-mapped registers have been accessed while ICC_SRE.SRE==0, then the System registers might be modified. Therefore, software must only rely on the reset values of the System registers if there has been no use of the GIC functionality while the memory-mapped registers are in use. Otherwise, the System register values must be treated as UNKNOWN.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :

When SCR_EL3.NS==1 :




28/09/2017 08:24

Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.