The RMR_EL1 characteristics are:
If EL1 is the highest implemented Exception level and this register is implemented:
This register is part of the Reset management registers functional group.
AArch64 System register RMR_EL1 is architecturally mapped to AArch32 System register RMR when EL1 is highest implemented Exception level.
Only implemented if EL1 is the highest implemented Exception level. In this case:
See the field descriptions for the reset values. These apply whenever the register is implemented.
RMR_EL1 is a 32-bit register.
The RMR_EL1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | RR | AA64 |
Reserved, RES0.
Reset Request. Setting this bit to 1 requests a Warm reset.
This field resets to 0 on a Warm or Cold reset.
When EL1 can use AArch32, determines which Execution state the PE boots into after a Warm reset:
AA64 | Meaning |
---|---|
0 |
AArch32. |
1 |
AArch64. |
On coming out of the Warm reset, execution starts at the IMPLEMENTATION DEFINED reset vector address of the specified Execution state.
If EL1 cannot use AArch32 this bit is RAO/WI.
When implemented as a RW field, this field resets to 1 on a Cold reset.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
RMR_EL1 | 11 | 000 | 1100 | 0000 | 010 |
The register is accessible as follows:
Configuration | Control | Accessibility | |||||
---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | |
EL1 is the highest implemented Exception level | x | x | x | - | RW | n/a | n/a |
This table applies to all instructions that can access this register.
When RMR_EL1 is not implemented, the encoding for this register is UNDEFINED.
28/09/2017 08:24
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