ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6

The ID_ISAR6_EL1 characteristics are:

Purpose

Provides information about the instruction sets implemented by the PE in AArch32 state.

Must be interpreted with ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR3_EL1, ID_ISAR4_EL1 and ID_ISAR5_EL1.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.

This register is part of the Identification registers functional group.

Configuration

AArch64 System register ID_ISAR6_EL1 is architecturally mapped to AArch32 System register ID_ISAR6.

In an implementation that supports only AArch64 state, this register is UNKNOWN.

This register is introduced in ARMv8.2.

Attributes

ID_ISAR6_EL1 is a 32-bit register.

Field descriptions

The ID_ISAR6_EL1 bit assignments are:

313029282726252423222120191817161514131211109876543210
000000000000000000000000DPJSCVT

Bits [31:8]

Reserved, RES0.

DP, bits [7:4]

Indicates the support for dot product instructions in AArch32 state.

DPMeaning
0000

No dot product instructions implemented.

0001

VUDOT and VSDOT instructions implemented.

All other values are reserved.

ARMv8.2-DotProd implements the functionality identified by the value 0001.

JSCVT, bits [3:0]
In ARMv8.3:

Indicates whether the Javascript conversion instruction is implemented in AArch32 state. Defined values are:

JSCVTMeaning
0000

The VJCVT instruction is not implemented.

0001

The VJCVT instruction is implemented.

All other values are reserved.

In ARMv8.0, ARMv8.1 and ARMv8.2 the only permitted value is 0000.

From ARMv8.3 the only permitted value is 0001. This feature is identified as ARMv8.3-JSConv.


In ARMv8.2:

Reserved, RES0.

Accessing the ID_ISAR6_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
ID_ISAR6_EL11100000000010111

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RO n/a RO
x01 - RORORO
x11 - n/a RORO

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :




28/09/2017 08:24

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