EDCIDR1, External Debug Component Identification Register 1

The EDCIDR1 characteristics are:

Purpose

Provides information to identify an external debug component.

For more information see 'About the Component identification scheme' in the ARMv8 ARM, section H8 (About the External Debug Registers).

This register is part of the Debug registers functional group.

Usage constraints

This register is accessible as follows:

Default
RO

Configuration

EDCIDR1 is in the Debug power domain.

Implementation of this register is OPTIONAL.

This register is required for CoreSight compliance.

Attributes

EDCIDR1 is a 32-bit register.

Field descriptions

The EDCIDR1 bit assignments are:

313029282726252423222120191817161514131211109876543210
000000000000000000000000CLASSPRMBL_1

Bits [31:8]

Reserved, RES0.

CLASS, bits [7:4]

Component class. Reads as 0x9, debug component.

PRMBL_1, bits [3:0]

Preamble. RAZ.

Accessing the EDCIDR1

EDCIDR1 can be accessed through the external debug interface:

ComponentOffset
Debug 0xFF4



28/09/2017 08:24

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