The HTCR characteristics are:
The control register for stage 1 of the EL2 translation regime.
This stage of translation always uses the Long-descriptor translation table format.
This register is part of:
AArch32 System register HTCR is architecturally mapped to AArch64 System register TCR_EL2.
If EL2 is not implemented, this register is RES0 from EL3.
RW fields in this register reset to architecturally UNKNOWN values.
HTCR is a 32-bit register.
The HTCR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | IMP DEF | 0 | HWU62 | HWU61 | HWU60 | HWU59 | HPD | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SH0 | ORGN0 | IRGN0 | 0 | 0 | 0 | 0 | 0 | T0SZ |
Reserved, RES1.
IMPLEMENTATION DEFINED.
Reserved, RES0.
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[62] of the stage 1 translation table Block or Page entry.
Defined values are:
HWU62 | Meaning |
---|---|
0 |
Bit[62] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. |
1 |
Bit[62] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of HTCR.HPD is 1. |
This bit is RES0 if ARMv8.2-TTPBHA is not implemented.
The Effective value of this field is 0 if the value of HTCR.HPD is 0.
Reserved, RES0.
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[61] of the stage 1 translation table Block or Page entry.
Defined values are:
HWU61 | Meaning |
---|---|
0 |
Bit[61] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. |
1 |
Bit[61] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of HTCR.HPD is 1. |
This bit is RES0 if ARMv8.2-TTPBHA is not implemented.
The Effective value of this field is 0 if the value of HTCR.HPD is 0.
Reserved, RES0.
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[60] of the stage 1 translation table Block or Page entry.
Defined values are:
HWU60 | Meaning |
---|---|
0 |
Bit[60] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. |
1 |
Bit[60] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of HTCR.HPD is 1. |
This bit is RES0 if ARMv8.2-TTPBHA is not implemented.
The Effective value of this field is 0 if the value of HTCR.HPD is 0.
Reserved, RES0.
Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[59] of the stage 1 translation table Block or Page entry.
Defined values are:
HWU59 | Meaning |
---|---|
0 |
Bit[59] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. |
1 |
Bit[59] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of HTCR.HPD is 1. |
This bit is RES0 if ARMv8.2-TTPBHA is not implemented.
The Effective value of this field is 0 if the value of HTCR.HPD is 0.
Reserved, RES0.
Hierarchical Permission Disables. This affects the hierarchical control bits, APTable, XNTable, and PXNTable, in the PL2 translation regime.
Defined values are:
HPD | Meaning |
---|---|
0 |
Hierarchical permissions are enabled. |
1 |
Hierarchical permissions are disabled. |
When disabled, the permissions are treated as if the bits are zero.
This bit is RES0 if ARMv8.2-AA32HPD is not implemented.
Reserved, RES0.
Reserved, RES1.
Reserved, RES0.
Shareability attribute for memory associated with translation table walks using HTTBR.
SH0 | Meaning |
---|---|
00 |
Non-shareable |
10 |
Outer Shareable |
11 |
Inner Shareable |
Other values are reserved. The effect of programming this field to a Reserved value is that behavior is CONSTRAINED UNPREDICTABLE, as described in 'Unallocated values in fields of AArch32 System registers and translation table entries' in the ARM ARM, section K1.1.11.
Outer cacheability attribute for memory associated with translation table walks using HTTBR.
ORGN0 | Meaning |
---|---|
00 |
Normal memory, Outer Non-cacheable |
01 |
Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable |
10 |
Normal memory, Outer Write-Through Read-Allocate No Write-Allocate Cacheable |
11 |
Normal memory, Outer Write-Back Read-Allocate No Write-Allocate Cacheable |
Inner cacheability attribute for memory associated with translation table walks using HTTBR.
IRGN0 | Meaning |
---|---|
00 |
Normal memory, Inner Non-cacheable |
01 |
Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable |
10 |
Normal memory, Inner Write-Through Read-Allocate No Write-Allocate Cacheable |
11 |
Normal memory, Inner Write-Back Read-Allocate No Write-Allocate Cacheable |
Reserved, RES0.
The size offset of the memory region addressed by HTTBR. The region size is 2(32-T0SZ) bytes.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 4, <Rt>, c2, c0, 2 | 100 | 010 | 0010 | 1111 | 0000 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | - | n/a | - |
x | 0 | 1 | - | - | RW | RW |
x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HSTR_EL2.T2==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T2==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HSTR.T2==1, Non-secure accesses to this register from EL1 are trapped to Hyp mode.
28/09/2017 08:24
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