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The PMBLIMITR_EL1 characteristics are:
Defines the upper limit for the profiling buffer, and enables the profiling buffer
This register is part of the Statistical Profiling Extension registers functional group.
Present only if the Statistical Profiling Extension is implemented. Direct reads and writes of PMBLIMITR_EL1 are UNDEFINED at EL0.
PMBLIMITR_EL1 is a 64-bit register.
The PMBLIMITR_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
LIMIT | |||||||||||||||||||||||||||||||
LIMIT | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | FM | E | ||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Limit address, plus one. Read/write. Defines the limit of the buffer. If the smallest implemented translation granule is not 4KB, then bits [N-1:12] are RES0, where N is the IMPLEMENTATION DEFINED value, Log2(smallest implemented translation granule).
Reserved, RES0.
Fill mode
FM | Meaning |
---|---|
0b00 | Stop collection and raise maintenance interrupt on buffer fill |
All other values are reserved. If this field is programmed with a reserved value, the PE behaves as if this field has a defined value, other than for a direct read of the register. Software must not rely on the behavior of reserved values, as they might change in a future version of the architecture.
Profiling Buffer enable
E | Meaning |
---|---|
0b0 | All output is discarded |
0b1 | Enabled |
When this register has an architecturally-defined reset value, this field resets to 0 on Warm or Cold reset.
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | CRn | op0 | op1 | op2 | CRm |
---|---|---|---|---|---|
PMBLIMITR_EL1 | 1001 | 11 | 000 | 000 | 1010 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RW | n/a | RW |
x | 0 | 1 | - | RW | RW | RW |
x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
If (AArch64-MDCR_EL2.E2PB != 0b00 || AArch64-MDCR_EL2.E2PB != 0b10) && AArch64-SCR_EL3.NS == 0b1, then access from EL1 traps to EL2
If AArch64-MDCR_EL3.NSPB != 0b01 && AArch64-SCR_EL3.NS == 0b0, then access from EL1 traps to EL3
If AArch64-MDCR_EL3.NSPB != 0b11 && AArch64-SCR_EL3.NS == 0b1, then access from EL2 or EL1 traps to EL3
12/09/2017 18:03
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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