The EDACR characteristics are:
Allows implementations to support IMPLEMENTATION DEFINED controls.
This register is part of the Debug registers functional group.
This register is accessible as follows:
Off | DLK | OSLK | SLK | Default |
---|---|---|---|---|
IMP DEF | IMP DEF | IMP DEF | RO | RW |
It is IMPLEMENTATION DEFINED whether EDACR is implemented in the Core power domain or in the Debug power domain. RW fields in this register reset to architecturally UNKNOWN values, and:
Changing this register from its reset value causes IMPLEMENTATION DEFINED behavior, including possible deviation from the architecturally-defined behavior.
If the EDACR contains any control bits that must be preserved over power down, then these bits must be accessible by the external debug interface when OSLSR_EL1.OSLK == 1 (OS lock is locked) and when the Core is powered off.
EDACR is a 32-bit register.
The EDACR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED |
IMPLEMENTATION DEFINED.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
EDACR can be accessed through the external debug interface:
Component | Offset |
---|---|
Debug | 0x094 |
28/09/2017 08:24
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