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The PMINTENSET characteristics are:
Enables the generation of interrupt requests on overflows from the Cycle Count Register, PMCCNTR, and the event counters PMEVCNTR<n>. Reading the register shows which overflow interrupt requests are enabled.
PMINTENSET is used in conjunction with the PMINTENCLR register.
This register is part of the Performance Monitors registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register PMINTENSET is architecturally mapped to AArch64 System register PMINTENSET_EL1.
AArch32 System register PMINTENSET is architecturally mapped to External register PMINTENSET_EL1.
This register is in the Warm reset domain. On a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.
PMINTENSET is a 32-bit register.
The PMINTENSET bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
C | P<n>, bit [n] |
PMCCNTR overflow interrupt request enable bit. Possible values are:
C | Meaning |
---|---|
0 | When read, means the cycle counter overflow interrupt request is disabled. When written, has no effect. |
1 | When read, means the cycle counter overflow interrupt request is enabled. When written, enables the cycle count overflow interrupt request. |
Event counter overflow interrupt request enable bit for PMEVCNTR<n>.
When EL2 is implemented, in Non-secure EL1 and EL0, N is the value in HDCR.HPMN. Otherwise, N is the value in PMCR.N.
Bits [30:N] are RAZ/WI.
Possible values are:
P<n> | Meaning |
---|---|
0 | When read, means that the PMEVCNTR<n> event counter interrupt request is disabled. When written, has no effect. |
1 | When read, means that the PMEVCNTR<n> event counter interrupt request is enabled. When written, enables the PMEVCNTR<n> interrupt request. |
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c9, c14, 1 | 000 | 001 | 1001 | 1111 | 1110 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RW | n/a | RW |
x | 0 | 1 | - | RW | RW | RW |
x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
If EL2 is implemented, in Non-secure EL1 and EL0 modes, the value of HDCR.HPMN can change the behavior of accesses to PMINTENSET. See the description of the P<n> bit.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HSTR_EL2.T9==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TPM==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T9==1, Non-secure write accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HDCR.TPM==1, Non-secure accesses to this register from EL1 are trapped to Hyp mode.
If HSTR.T9==1, Non-secure accesses to this register from EL1 are trapped to Hyp mode.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TPM==1, accesses to this register from EL1 and EL2 are trapped to EL3.
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