PMCCNTR_EL0, Performance Monitors Cycle Count Register

The PMCCNTR_EL0 characteristics are:

Purpose

Holds the value of the processor Cycle Counter, CCNT, that counts processor clock cycles. See 'Time as measured by the Performance Monitors cycle counter' in the ARMv8 ARM, section D5 for more information.

PMCCFILTR_EL0 determines the modes and states in which the PMCCNTR_EL0 can increment.

This register is part of the Performance Monitors registers functional group.

Configuration

AArch64 System register PMCCNTR_EL0 is architecturally mapped to AArch32 System register PMCCNTR when accessing as a 64-bit register.

AArch64 System register PMCCNTR_EL0 is architecturally mapped to External register PMCCNTR_EL0.

All counters are subject to any changes in clock frequency, including clock stopping caused by the WFI and WFE instructions. This means that it is CONSTRAINED UNPREDICTABLE whether or not PMCCNTR_EL0 continues to increment when clocks are stopped by WFI and WFE instructions.

This register is in the Warm reset domain. On a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.

Attributes

PMCCNTR_EL0 is a 64-bit register.

Field descriptions

The PMCCNTR_EL0 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
CCNT
CCNT
313029282726252423222120191817161514131211109876543210

CCNT, bits [63:0]

Cycle count. Depending on the values of PMCR_EL0.{LC,D}, this field increments in one of the following ways:

Writing 1 to PMCR_EL0.C sets this field to 0.

Accessing the PMCCNTR_EL0

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
PMCCNTR_EL01101110011101000

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0RWRW n/a RW
x01RWRWRWRW
x11RW n/a RWRW

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :

When EL3 is implemented and is using AArch64 :




28/09/2017 08:24

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