The ID_MMFR0 characteristics are:
Provides information about the implemented memory model and memory management support in AArch32 state.
Must be interpreted with ID_MMFR1, ID_MMFR2, ID_MMFR3, and ID_MMFR4.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section G4.14.6.
This register is part of the Identification registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register ID_MMFR0 is architecturally mapped to AArch64 System register ID_MMFR0_EL1.
ID_MMFR0 is a 32-bit register.
The ID_MMFR0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
InnerShr | FCSE | AuxReg | TCM | ShareLvl | OuterShr | PMSA | VMSA |
Innermost Shareability. Indicates the innermost shareability domain implemented. Defined values are:
InnerShr | Meaning |
---|---|
0000 |
Implemented as Non-cacheable. |
0001 |
Implemented with hardware coherency support. |
1111 |
Shareability ignored. |
All other values are reserved.
In ARMv8 the permitted values are 0000, 0001, and 1111.
This field is valid only if the implementation supports two levels of shareability, as indicated by ID_MMFR0.ShareLvl having the value 0001.
When ID_MMFR0.ShareLvl is zero, this field is UNK.
Indicates whether the implementation includes the FCSE. Defined values are:
FCSE | Meaning |
---|---|
0000 |
Not supported. |
0001 |
Support for FCSE. |
All other values are reserved.
In ARMv8 the only permitted value is 0000.
Auxiliary Registers. Indicates support for Auxiliary registers. Defined values are:
AuxReg | Meaning |
---|---|
0000 |
None supported. |
0001 |
Support for Auxiliary Control Register only. |
0010 |
Support for Auxiliary Fault Status Registers (AIFSR and ADFSR) and Auxiliary Control Register. |
All other values are reserved.
In ARMv8 the only permitted value is 0010.
Accesses to unimplemented Auxiliary registers are UNDEFINED.
Indicates support for TCMs and associated DMAs. Defined values are:
TCM | Meaning |
---|---|
0000 |
Not supported. |
0001 |
Support is IMPLEMENTATION DEFINED. ARMv7 requires this setting. |
0010 |
Support for TCM only, ARMv6 implementation. |
0011 |
Support for TCM and DMA, ARMv6 implementation. |
All other values are reserved.
In ARMv8-A the only permitted value is 0000.
Shareability Levels. Indicates the number of shareability levels implemented. Defined values are:
ShareLvl | Meaning |
---|---|
0000 |
One level of shareability implemented. |
0001 |
Two levels of shareability implemented. |
All other values are reserved.
In ARMv8 the only permitted value is 0001.
Outermost Shareability. Indicates the outermost shareability domain implemented. Defined values are:
OuterShr | Meaning |
---|---|
0000 |
Implemented as Non-cacheable. |
0001 |
Implemented with hardware coherency support. |
1111 |
Shareability ignored. |
All other values are reserved.
In ARMv8 the permitted values are 0000, 0001, and 1111.
Indicates support for a PMSA. Defined values are:
PMSA | Meaning |
---|---|
0000 |
Not supported. |
0001 |
Support for IMPLEMENTATION DEFINED PMSA. |
0010 |
Support for PMSAv6, with a Cache Type Register implemented. |
0011 |
Support for PMSAv7, with support for memory subsections. ARMv7-R profile. |
All other values are reserved.
In ARMv8-A the only permitted value is 0000.
Indicates support for a VMSA. Defined values are:
VMSA | Meaning |
---|---|
0000 |
Not supported. |
0001 |
Support for IMPLEMENTATION DEFINED VMSA. |
0010 |
Support for VMSAv6, with Cache and TLB Type Registers implemented. |
0011 |
Support for VMSAv7, with support for remapping and the Access flag. ARMv7-A profile. |
0100 |
As for 0011, and adds support for the PXN bit in the Short-descriptor translation table format descriptors. |
0101 |
As for 0100, and adds support for the Long-descriptor translation table format. |
All other values are reserved.
In ARMv8-A the only permitted value is 0101.
This register can be read using MRC with the following syntax:
MRC <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c0, c1, 4 | 000 | 100 | 0000 | 1111 | 0001 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HSTR_EL2.T0==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HSTR_EL2.T0==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
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