ICC_DIR_EL1, Interrupt Controller Deactivate Interrupt Register

The ICC_DIR_EL1 characteristics are:

Purpose

When interrupt priority drop is separated from interrupt deactivation, a write to this register deactivates the specified interrupt.

This register is part of:

Configuration

AArch64 System register ICC_DIR_EL1 performs the same function as AArch32 System register ICC_DIR.

Attributes

ICC_DIR_EL1 is a 32-bit register.

Field descriptions

The ICC_DIR_EL1 bit assignments are:

313029282726252423222120191817161514131211109876543210
00000000INTID

Bits [31:24]

Reserved, RES0.

INTID, bits [23:0]

The INTID of the interrupt to be deactivated.

This field has either 16 or 24 bits implemented. The number of implemented bits can be found in ICC_CTLR_EL1.IDbits and ICC_CTLR_EL3.IDbits. If only 16 bits are implemented, bits [23:16] of this register are RES0.

Accessing the ICC_DIR_EL1

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
ICC_DIR_EL11100011001011001

This encoding results in an access to ICV_DIR_EL1 at Non-secure EL1 in the following cases:

Accessibility

The register is accessible as follows:

Control Accessibility
FMOIMOTGENSEL0EL1EL2EL3
xxx0 - WO n/a WO
xx11 - n/a WOWO
x101 - ICV_DIR_EL1 WOWO
1x01 - ICV_DIR_EL1 WOWO
0001 - WOWOWO

This table applies to all instructions that can access this register.

The ICC_DIR_EL1 register is only accessible at Non-secure EL1 when HCR_EL2.{FMO, IMO} == {0, 0}.

Note

At Non-secure EL1, the instruction encoding used to access ICC_DIR_EL1 results in an access to ICV_DIR_EL1 in the following cases:

There are two cases when writing to ICC_DIR_EL1 that were UNPREDICTABLE for a corresponding GICv2 write to GICC_DIR:

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When SCR_EL3.NS==1 :

When EL3 is implemented and is using AArch64 and SCR_EL3.NS==0 :

When EL3 is implemented and is using AArch64 :

When EL3 is implemented and is using AArch64 and SCR_EL3.NS==1 :




28/09/2017 08:24

Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.