The ICC_IGRPEN1 characteristics are:
Controls whether Group 1 interrupts are enabled for the current Security state.
This register is part of:
AArch32 System register ICC_IGRPEN1 (S) is architecturally mapped to AArch64 System register ICC_IGRPEN1_EL1 (S) .
AArch32 System register ICC_IGRPEN1 (NS) is architecturally mapped to AArch64 System register ICC_IGRPEN1_EL1 (NS) .
ICC_IGRPEN1 is a 32-bit register.
The ICC_IGRPEN1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Enable |
Reserved, RES0.
Enables Group 1 interrupts for the current Security state.
Enable | Meaning |
---|---|
0 |
Group 1 interrupts are disabled for the current Security state. |
1 |
Group 1 interrupts are enabled for the current Security state. |
Virtual accesses to this register update ICH_VMCR.VENG1.
If EL3 is present:
When this register has an architecturally-defined reset value, this field resets to 0.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c12, c12, 7 | 000 | 111 | 1100 | 1111 | 1100 |
When HCR.IMO is set to 1, execution of this encoding at Non-secure EL1 results in an access to ICV_IGRPEN1.
The register is accessible as follows:
Configuration | Control | Accessibility | Instance | ||||||
---|---|---|---|---|---|---|---|---|---|
FMO | IMO | TGE | NS | EL0 | EL1 | EL2 | EL3 | ||
EL3 not implemented | x | x | x | 0 | - | RW | n/a | n/a | ICC_IGRPEN1 |
EL3 not implemented | x | x | 1 | 1 | - | n/a | RW | n/a | ICC_IGRPEN1 |
EL3 not implemented | x | 0 | 0 | 1 | - | RW | RW | n/a | ICC_IGRPEN1 |
EL3 not implemented | x | 1 | 0 | 1 | - | ICV_IGRPEN1 | RW | n/a | ICC_IGRPEN1 |
EL3 using AArch64 | x | x | 1 | 1 | - | n/a | RW | n/a | ICC_IGRPEN1_ns |
EL3 using AArch64 | x | 0 | 0 | 1 | - | RW | RW | n/a | ICC_IGRPEN1_ns |
EL3 using AArch64 | x | 1 | 0 | 1 | - | ICV_IGRPEN1 | RW | n/a | ICC_IGRPEN1_ns |
EL3 using AArch32 | x | x | 1 | 1 | - | n/a | RW | RW | ICC_IGRPEN1_ns |
EL3 using AArch32 | x | 0 | 0 | 1 | - | RW | RW | RW | ICC_IGRPEN1_ns |
EL3 using AArch32 | x | 1 | 0 | 1 | - | ICV_IGRPEN1 | RW | RW | ICC_IGRPEN1_ns |
EL3 using AArch64 | x | x | x | 0 | - | RW | n/a | n/a | ICC_IGRPEN1_s |
EL3 using AArch32 | x | x | x | 0 | - | - | - | RW | ICC_IGRPEN1_s |
This table applies to all instructions that can access this register.
ICC_IGRPEN1 is only accessible at Non-secure EL1 when HCR.IMO is set to 0.
When HCR.IMO is set to 1, at Non-secure EL1, the instruction encoding used to access ICC_IGRPEN1 results in an access to ICV_IGRPEN1.
The lowest Exception level at which this register can be accessed is governed by the Exception level to which IRQ is routed. This routing depends on SCR.IRQ, SCR.NS and HCR.IMO.
If an interrupt is pending within the CPU interface when Enable becomes 0, the interrupt must be released to allow the Distributor to forward the interrupt to a different PE.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_SRE.SRE==0, accesses to this register from EL1 are UNDEFINED.
If ICC_HSRE.SRE==0, accesses to this register from EL2 are UNDEFINED.
If ICC_MSRE.SRE==0, accesses to this register from EL3 are UNDEFINED.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If HSTR_EL2.T12==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T12==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HSTR.T12==1, Non-secure accesses to this register from EL1 are trapped to Hyp mode.
When SCR_EL3.NS==1 :
If ICH_HCR.TALL1==1, Non-secure accesses to this register from EL1 are trapped to EL2.
If ICH_HCR_EL2.TALL1==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL3 is implemented and is using AArch32 :
If SCR.IRQ==1, accesses to this register from EL2 and EL3 modes other than Monitor mode are UNDEFINED.
When EL3 is implemented and is using AArch32 and SCR_EL3.NS==1 :
When EL3 is implemented and is using AArch64 and SCR_EL3.NS==0 :
If SCR_EL3.IRQ==1, Secure accesses to this register from EL1 are trapped to EL3.
When EL3 is implemented and is using AArch64 :
If SCR_EL3.IRQ==1, accesses to this register from EL2 are trapped to EL3.
When EL3 is implemented and is using AArch64 and SCR_EL3.NS==1 :
28/09/2017 08:24
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