CONTEXTIDR, Context ID Register

The CONTEXTIDR characteristics are:

Purpose

Identifies the current Process Identifier and, when using the Short-descriptor translation table format, the Address Space Identifier.

The value of the whole of this register is called the Context ID and is used by:

The significance of this register is for debug and trace use only.

This register is part of the Virtual memory control registers functional group.

Configuration

AArch32 System register CONTEXTIDR is architecturally mapped to AArch64 System register CONTEXTIDR_EL1.

The register format depends on whether address translation is using the Long-descriptor or the Short-descriptor translation table format.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

CONTEXTIDR is a 32-bit register.

Field descriptions

The CONTEXTIDR bit assignments are:

When TTBCR.EAE==0:

313029282726252423222120191817161514131211109876543210
PROCIDASID

PROCID, bits [31:8]

Process Identifier. This field must be programmed with a unique value that identifies the current process.

ASID, bits [7:0]

Address Space Identifier. This field is programmed with the value of the current ASID.

When TTBCR.EAE==1:

313029282726252423222120191817161514131211109876543210
PROCID

PROCID, bits [31:0]

Process Identifier. This field must be programmed with a unique value that identifies the current process.

Accessing the CONTEXTIDR

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 0, <Rt>, c13, c0, 1000001110111110000

Accessibility

The register is accessible as follows:

Configuration Control Accessibility Instance
E2HTGENSEL0EL1EL2EL3
EL3 using AArch32x01 - RWRWRWCONTEXTIDR_ns
EL3 using AArch32x11 - n/a RWRWCONTEXTIDR_ns
EL3 using AArch32xx0 - n/a n/a RWCONTEXTIDR_s
EL3 not implemented xx0 - RW n/a n/a CONTEXTIDR
EL3 not implemented x01 - RWRW n/a CONTEXTIDR
EL3 not implemented x11 - n/a RW n/a CONTEXTIDR
EL3 using AArch64xx0 - RW n/a n/a CONTEXTIDR
EL3 using AArch64x01 - RWRW n/a CONTEXTIDR
EL3 using AArch64x11 - n/a RW n/a CONTEXTIDR

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :




28/09/2017 08:24

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