The PMEVTYPER<n>_EL0 characteristics are:
Configures event counter n, where n is 0 to 30.
This register is part of the Performance Monitors registers functional group.
This register is accessible as follows:
Off | DLK | OSLK | EPMAD | SLK | Default |
---|---|---|---|---|---|
Error | Error | Error | Error | RO | RW |
External register PMEVTYPER<n>_EL0 is architecturally mapped to AArch64 System register PMEVTYPER<n>_EL0.
External register PMEVTYPER<n>_EL0 is architecturally mapped to AArch32 System register PMEVTYPER<n>.
PMEVTYPER<n>_EL0 is in the Core power domain. RW fields in this register reset to architecturally UNKNOWN values. These apply on a Warm or Cold reset. The register is not affected by an External debug reset.
PMEVTYPER<n>_EL0 is a 32-bit register.
The PMEVTYPER<n>_EL0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
P | U | NSK | NSU | NSH | M | MT | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | evtCount[15:10] | evtCount[9:0] |
Privileged filtering bit. Controls counting in EL1. If EL3 is implemented, then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are:
P | Meaning |
---|---|
0 |
Count events in EL1. |
1 |
Do not count events in EL1. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
User filtering bit. Controls counting in EL0. If EL3 is implemented, then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are:
U | Meaning |
---|---|
0 |
Count events in EL0. |
1 |
Do not count events in EL0. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Non-secure EL1 (kernel) modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented, this bit is RES0.
If the value of this bit is equal to the value of P, events in Non-secure EL1 are counted.
Otherwise, events in Non-secure EL1 are not counted.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Non-secure EL0 (Unprivileged) filtering. Controls counting in Non-secure EL0. If EL3 is not implemented, this bit is RES0.
If the value of this bit is equal to the value of U, events in Non-secure EL0 are counted.
Otherwise, events in Non-secure EL0 are not counted.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Non-secure EL2 (Hypervisor) filtering. Controls counting in Non-secure EL2. If EL2 is not implemented, this bit is RES0.
NSH | Meaning |
---|---|
0 |
Do not count events in EL2. |
1 |
Count events in EL2. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Secure EL3 filtering bit. If EL3 is not implemented, this bit is RES0.
If the value of this bit is equal to the value of P, cycles in Secure EL3 are counted.
Otherwise, cycles in Secure EL3 are not counted.
Most applications can ignore this field and set its value to 0.
This field is not visible in the AArch32 PMEVTYPER System register.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Multithreading. When the implementation is multi-threaded, the valid values for this bit are:
MT | Meaning |
---|---|
0 |
Count events only on controlling PE. |
1 |
Count events from any PE with the same affinity at level 1 and above as this PE. |
When the implementation is not multi-threaded, this bit is RES0.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Reserved, RES0.
Extension to evtCount[9:0]. See evtCount[9:0] for more details.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Reserved, RES0.
Event to count. The event number of the event that is counted by event counter PMEVCNTR<n>_EL0.
Software must program this field with an event that is supported by the PE being programmed.
There are three ranges of event numbers:
If evtCount is programmed to an event that is reserved or not supported by the PE, the behavior depends on the event type:
UNPREDICTABLE means the event must not expose privileged information.
ARM recommends that the behavior across a family of implementations is defined such that if a given implementation does not include an event from a set of common IMPLEMENTATION DEFINED events, then no event is counted and the value read back on evtCount is the value written.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
PMEVTYPER<n>_EL0 can be accessed through the external debug interface:
Component | Offset |
---|---|
PMU | 0x400 + 4n |
28/09/2017 08:24
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