SysReg_v83A_xml-00bet4 (old) | htmldiff from-SysReg_v83A_xml-00bet4 | (new) SysReg_v83A_xml-00bet5 |
Below are indexes for external registers in the following blocks:
Offset | Name | Description |
---|---|---|
0x000 |
CTICONTROL
|
CTI |
0x010 |
CTIINTACK
|
CTI |
0x014 |
CTIAPPSET
|
CTI |
0x018 |
CTIAPPCLEAR
|
CTI |
0x01C |
CTIAPPPULSE
|
CTI |
0x020 + 4n |
CTIINEN<n>
|
CTI |
0x0A0 + 4n |
CTIOUTEN<n>
|
CTI |
0x130 |
CTITRIGINSTATUS
|
CTI |
0x134 |
CTITRIGOUTSTATUS
|
CTI |
0x138 |
CTICHINSTATUS
|
CTI |
0x13C |
CTICHOUTSTATUS
|
CTI |
0x140 |
CTIGATE
|
CTI |
0x144 |
ASICCTL
|
CTI |
0xF00 |
CTIITCTRL
|
CTI |
0xFA0 |
CTICLAIMSET
|
CTI |
0xFA4 |
CTICLAIMCLR
|
CTI |
0xFA8 |
CTIDEVAFF0
|
CTI |
0xFAC |
CTIDEVAFF1
|
CTI |
0xFB0 |
CTILAR
|
CTI |
0xFB4 |
CTILSR
|
CTI |
0xFB8 |
CTIAUTHSTATUS
|
CTI |
0xFBC |
CTIDEVARCH
|
CTI |
0xFC0 |
CTIDEVID2
|
CTI |
0xFC4 |
CTIDEVID1
|
CTI |
0xFC8 |
CTIDEVID
|
CTI |
0xFCC |
CTIDEVTYPE
|
CTI |
0xFD0 |
CTIPIDR4
|
CTI |
0xFE0 |
CTIPIDR0
|
CTI |
0xFE4 |
CTIPIDR1
|
CTI |
0xFE8 |
CTIPIDR2
|
CTI |
0xFEC |
CTIPIDR3
|
CTI |
0xFF0 |
CTICIDR0
|
CTI |
0xFF4 |
CTICIDR1
|
CTI |
0xFF8 |
CTICIDR2
|
CTI |
0xFFC |
CTICIDR3
|
CTI |
Offset | Name | Description |
---|---|---|
0x020 | EDESR | External Debug Event Status Register |
0x024 | EDECR | External Debug Execution Control Register |
0x030 | EDWAR[31:0] | External Debug Watchpoint Address Register |
0x034 | EDWAR[63:32] | External Debug Watchpoint Address Register |
0x080 | DBGDTRRX_EL0 | Debug Data Transfer Register, Receive |
0x084 | EDITR | External Debug Instruction Transfer Register |
0x088 | EDSCR | External Debug Status and Control Register |
0x08C | DBGDTRTX_EL0 | Debug Data Transfer Register, Transmit |
0x090 | EDRCR | External Debug Reserve Control Register |
0x094 | EDACR | External Debug Auxiliary Control Register |
0x098 | EDECCR | External Debug Exception Catch Control Register |
0x0A0 | EDPCSR[31:0] | External Debug Program Counter Sample Register |
0x0A4 | EDCIDSR | External Debug Context ID Sample Register |
0x0A8 | EDVIDSR | External Debug Virtual Context Sample Register |
0x0AC | EDPCSR[63:32] | External Debug Program Counter Sample Register |
0x300 | OSLAR_EL1 | OS Lock Access Register |
0x310 | EDPRCR | External Debug Power/Reset Control Register |
0x314 | EDPRSR | External Debug Processor Status Register |
0x400 + 16n | DBGBVR<n>_EL1[31:0] | Debug Breakpoint Value Registers |
0x404 + 16n | DBGBVR<n>_EL1[63:32] | Debug Breakpoint Value Registers |
0x408 + 16n | DBGBCR<n>_EL1 | Debug Breakpoint Control Registers |
0x800 + 16n | DBGWVR<n>_EL1[31:0] | Debug Watchpoint Value Registers |
0x804 + 16n | DBGWVR<n>_EL1[63:32] | Debug Watchpoint Value Registers |
0x808 + 16n | DBGWCR<n>_EL1 | Debug Watchpoint Control Registers |
0xD00 | MIDR_EL1 | Main ID Register |
0xD20 | EDPFR[31:0] | External Debug Processor Feature Register |
0xD24 | EDPFR[63:32] | External Debug Processor Feature Register |
0xD28 | EDDFR[31:0] | External Debug Feature Register |
0xD2C | EDDFR[63:32] | External Debug Feature Register |
0xD60 | EDAA32PFR | External Debug AArch32 Processor Feature Register |
0xF00 | EDITCTRL | External Debug Integration mode Control register |
0xFA0 | DBGCLAIMSET_EL1 | Debug Claim Tag Set register |
0xFA4 | DBGCLAIMCLR_EL1 | Debug Claim Tag Clear register |
0xFA8 | EDDEVAFF0 | External Debug Device Affinity register 0 |
0xFAC | EDDEVAFF1 | External Debug Device Affinity register 1 |
0xFB0 | EDLAR | External Debug Lock Access Register |
0xFB4 | EDLSR | External Debug Lock Status Register |
0xFB8 | DBGAUTHSTATUS_EL1 | Debug Authentication Status register |
0xFBC | EDDEVARCH | External Debug Device Architecture register |
0xFC0 | EDDEVID2 | External Debug Device ID register 2 |
0xFC4 | EDDEVID1 | External Debug Device ID register 1 |
0xFC8 | EDDEVID | External Debug Device ID register 0 |
0xFCC | EDDEVTYPE | External Debug Device Type register |
0xFD0 | EDPIDR4 | External Debug Peripheral Identification Register 4 |
0xFE0 | EDPIDR0 | External Debug Peripheral Identification Register 0 |
0xFE4 | EDPIDR1 | External Debug Peripheral Identification Register 1 |
0xFE8 | EDPIDR2 | External Debug Peripheral Identification Register 2 |
0xFEC | EDPIDR3 | External Debug Peripheral Identification Register 3 |
0xFF0 | EDCIDR0 | External Debug Component Identification Register 0 |
0xFF4 | EDCIDR1 | External Debug Component Identification Register 1 |
0xFF8 | EDCIDR2 | External Debug Component Identification Register 2 |
0xFFC | EDCIDR3 | External Debug Component Identification Register 3 |
Offset | Name | Description |
---|---|---|
0x0000 | GICC_CTLR | CPU Interface Control Register |
0x0004 | GICC_PMR | CPU Interface Priority Mask Register |
0x0008 | GICC_BPR | CPU Interface Binary Point Register |
0x000C | GICC_IAR | CPU Interface Interrupt Acknowledge Register |
0x0010 | GICC_EOIR | CPU Interface End Of Interrupt Register |
0x0014 | GICC_RPR | CPU Interface Running Priority Register |
0x0018 | GICC_HPPIR | CPU Interface Highest Priority Pending Interrupt Register |
0x001C | GICC_ABPR | CPU Interface Aliased Binary Point Register |
0x0020-0x003C | GICC_AIAR | CPU Interface Aliased Interrupt Acknowledge Register |
0x0024 | GICC_AEOIR | CPU Interface Aliased End Of Interrupt Register |
0x0028 | GICC_AHPPIR | CPU Interface Aliased Highest Priority Pending Interrupt Register |
0x002C | GICC_STATUSR | CPU Interface Status Register |
0x00D0 + 4n | GICC_APR<n> | CPU Interface Active Priorities Registers |
0x00E0 + 4n | GICC_NSAPR<n> | CPU Interface Non-secure Active Priorities Registers |
0x00FC | GICC_IIDR | CPU Interface Identification Register |
0x1000 | GICC_DIR | CPU Interface Deactivate Interrupt Register |
Offset | Name | Description |
---|---|---|
0x0000 |
GICD_CTLR
|
Distributor |
0x0004 |
GICD_TYPER
|
Interrupt Controller |
0x0008 |
GICD_IIDR
|
Distributor |
0x0010 |
GICD_STATUSR
|
Error |
0x0040 |
GICD_SETSPI_NSR
|
Set |
0x0048 |
GICD_CLRSPI_NSR
|
Clear |
0x0050 |
GICD_SETSPI_SR
|
Set |
0x0058 |
GICD_CLRSPI_SR
|
Clear |
0x0080 + 4n | GICD_IGROUPR<n> | Interrupt Group Registers |
0x0100 + 4n | GICD_ISENABLER<n> | Interrupt Set-Enable Registers |
0x0180 + 4n | GICD_ICENABLER<n> | Interrupt Clear-Enable Registers |
0x0200 + 4n | GICD_ISPENDR<n> | Interrupt Set-Pending Registers |
0x0280 + 4n | GICD_ICPENDR<n> | Interrupt Clear-Pending Registers |
0x0300 + 4n | GICD_ISACTIVER<n> | Interrupt Set-Active Registers |
0x0380 + 4n | GICD_ICACTIVER<n> | Interrupt Clear-Active Registers |
0x0400 + 4n | GICD_IPRIORITYR<n> | Interrupt Priority Registers |
0x0800 + 4n | GICD_ITARGETSR<n> | Interrupt Processor Targets Registers |
0x0C00 + 4n | GICD_ICFGR<n> | Interrupt Configuration Registers |
0x0D00 + 4n | GICD_IGRPMODR<n> | Interrupt Group Modifier Registers |
0x0E00 + 4n | GICD_NSACR<n> | Non-secure Access Control Registers |
0x0F00 | GICD_SGIR | Software Generated Interrupt Register |
0x0F10 + 4n | GICD_CPENDSGIR<n> | SGI Clear-Pending Registers |
0x0F20 + 4n | GICD_SPENDSGIR<n> | SGI Set-Pending Registers |
0x6000 + 8n | GICD_IROUTER<n> | Interrupt Routing Registers |
Offset | Name | Description |
---|---|---|
0x0000 | GITS_CTLR | ITS Control Register |
0x0004 | GITS_IIDR | ITS Identification Register |
0x0008-0x000C | GITS_TYPER | ITS Type Register |
0x0080-0x0084 | GITS_CBASER | ITS Command Queue Descriptor |
0x0088-0x008C | GITS_CWRITER | ITS Write Register |
0x0090-0x0094 | GITS_CREADR | ITS Read Register |
0x0100 + 8n | GITS_BASER<n> | ITS Translation Table Descriptors |
Offset | Name | Description |
---|---|---|
0x0040 |
GITS_TRANSLATER
|
ITS |
Frame | Offset | Name | Description |
---|---|---|---|
RD_base | 0x0000 | GICR_CTLR | Redistributor Control Register |
RD_base | 0x0004 | GICR_IIDR | Redistributor Implementer Identification Register |
RD_base | 0x0008-0x000C | GICR_TYPER | Redistributor Type Register |
RD_base | 0x0010 | GICR_STATUSR | Error Reporting Status Register |
RD_base | 0x0014 | GICR_WAKER | Redistributor Wake Register |
RD_base | 0x0040-0x0044 | GICR_SETLPIR | Set LPI Pending Register |
RD_base | 0x0048-0x004C | GICR_CLRLPIR | Clear LPI Pending Register |
RD_base | 0x0070-0x0074 | GICR_PROPBASER | Redistributor Properties Base Address Register |
RD_base | 0x0078-0x007C | GICR_PENDBASER | Redistributor LPI Pending Table Base Address Register |
RD_base | 0x00A0-0x00A4 | GICR_INVLPIR | Redistributor Invalidate LPI Register |
RD_base | 0x00B0-0x00B4 | GICR_INVALLR | Redistributor Invalidate All Register |
RD_base | 0x00C0-0x00C4 | GICR_SYNCR | Redistributor Synchronize Register |
SGI_base |
0x0080 |
GICR_IGROUPR0
|
Interrupt |
SGI_base |
0x0100 |
GICR_ISENABLER0
|
Interrupt |
SGI_base |
0x0180 |
GICR_ICENABLER0
|
Interrupt Clear-Enable |
SGI_base |
0x0200 |
GICR_ISPENDR0
|
Interrupt Set-Pending |
SGI_base |
0x0280 |
GICR_ICPENDR0
|
Interrupt Clear-Pending |
SGI_base |
0x0300 |
GICR_ISACTIVER0
|
Interrupt Set-Active |
SGI_base |
0x0380 |
GICR_ICACTIVER0
|
Interrupt Clear-Active |
SGI_base |
0x0400 + 4n |
GICR_IPRIORITYR<n>
|
Interrupt Priority |
SGI_base |
0x0C00 |
GICR_ICFGR0
|
Interrupt Configuration |
SGI_base |
0x0C04 |
GICR_ICFGR1
|
Interrupt Configuration |
SGI_base |
0x0D00 |
GICR_IGRPMODR0
|
Interrupt Group Modifier |
SGI_base |
0x0E00 |
GICR_NSACR
|
Non-secure |
VLPI_base |
0x0070-0x0074 |
GICR_VPROPBASER
|
Virtual |
VLPI_base |
0x0078-0x007C |
GICR_VPENDBASER
|
Virtual |
Offset | Name | Description |
---|---|---|
0x0000 | GICV_CTLR | Virtual Machine Control Register |
0x0004 | GICV_PMR | Virtual Machine Priority Mask Register |
0x0008 | GICV_BPR | Virtual Machine Binary Point Register |
0x000C | GICV_IAR | Virtual Machine Interrupt Acknowledge Register |
0x0010 | GICV_EOIR | Virtual Machine End Of Interrupt Register |
0x0014 | GICV_RPR | Virtual Machine Running Priority Register |
0x0018 | GICV_HPPIR | Virtual Machine Highest Priority Pending Interrupt Register |
0x001C | GICV_ABPR | Virtual Machine Aliased Binary Point Register |
0x0020 | GICV_AIAR | Virtual Machine Aliased Interrupt Acknowledge Register |
0x0024 | GICV_AEOIR | Virtual Machine Aliased End Of Interrupt Register |
0x0028 | GICV_AHPPIR | Virtual Machine Aliased Highest Priority Pending Interrupt Register |
0x002C | GICV_STATUSR | Virtual Machine Error Reporting Status Register |
0x00D0 + 4n | GICV_APR<n> | Virtual Machine Active Priorities Registers |
0x00FC | GICV_IIDR | Virtual Machine CPU Interface Identification Register |
0x1000 | GICV_DIR | Virtual Machine Deactivate Interrupt Register |
Offset | Name | Description |
---|---|---|
0x0000 |
GICH_HCR
|
Hypervisor |
0x0004 |
GICH_VTR
|
Virtual |
0x0008 |
GICH_VMCR
|
Virtual |
0x0010 |
GICH_MISR
|
Maintenance |
0x0020 |
GICH_EISR
|
End |
0x0030 |
GICH_ELRSR
|
Empty |
0x00F0 |
GICH_APR<n>
|
Active |
0x0100 + 4n | GICH_LR<n> | List Registers |
Offset | Name | Description |
---|---|---|
0x000 + 8n |
PMEVCNTR<n>_EL0
|
Performance |
0x0F8 | PMCCNTR_EL0[31:0] | Performance Monitors Cycle Counter |
0x0FC | PMCCNTR_EL0[63:32] | Performance Monitors Cycle Counter |
0x200 | PMPCSR[31:0] | Program Counter Sample Register |
0x204 | PMPCSR[63:32] | Program Counter Sample Register |
0x208 | PMCID1SR | CONTEXTIDR_EL1 Sample Register |
0x20C | PMVIDSR | VMID Sample Register |
0x220 | PMPCSR[31:0] | Program Counter Sample Register |
0x224 | PMPCSR[63:32] | Program Counter Sample Register |
0x228 | PMCID1SR | CONTEXTIDR_EL1 Sample Register |
0x22C | PMCID2SR | CONTEXTIDR_EL2 Sample Register |
0x400 + 4n | PMEVTYPER<n>_EL0 | Performance Monitors Event Type Registers |
0x47C | PMCCFILTR_EL0 | Performance Monitors Cycle Counter Filter Register |
0xC00 | PMCNTENSET_EL0 | Performance Monitors Count Enable Set register |
0xC20 | PMCNTENCLR_EL0 | Performance Monitors Count Enable Clear register |
0xC40 | PMINTENSET_EL1 | Performance Monitors Interrupt Enable Set register |
0xC60 | PMINTENCLR_EL1 | Performance Monitors Interrupt Enable Clear register |
0xC80 | PMOVSCLR_EL0 | Performance Monitors Overflow Flag Status Clear register |
0xCA0 | PMSWINC_EL0 | Performance Monitors Software Increment register |
0xCC0 | PMOVSSET_EL0 | Performance Monitors Overflow Flag Status Set register |
0xE00 | PMCFGR | Performance Monitors Configuration Register |
0xE04 | PMCR_EL0 | Performance Monitors Control Register |
0xE20 | PMCEID0 | Performance Monitors Common Event Identification register 0 |
0xE24 | PMCEID1 | Performance Monitors Common Event Identification register 1 |
0xE28 | PMCEID2 | Performance Monitors Common Event Identification register 2 |
0xE2C | PMCEID3 | Performance Monitors Common Event Identification register 3 |
0xF00 | PMITCTRL | Performance Monitors Integration mode Control register |
0xFA8 | PMDEVAFF0 | Performance Monitors Device Affinity register 0 |
0xFAC | PMDEVAFF1 | Performance Monitors Device Affinity register 1 |
0xFB0 | PMLAR | Performance Monitors Lock Access Register |
0xFB4 | PMLSR | Performance Monitors Lock Status Register |
0xFB8 | PMAUTHSTATUS | Performance Monitors Authentication Status register |
0xFBC | PMDEVARCH | Performance Monitors Device Architecture register |
0xFC8 | PMDEVID | Performance Monitors Device ID register |
0xFCC | PMDEVTYPE | Performance Monitors Device Type register |
0xFD0 | PMPIDR4 | Performance Monitors Peripheral Identification Register 4 |
0xFE0 | PMPIDR0 | Performance Monitors Peripheral Identification Register 0 |
0xFE4 | PMPIDR1 | Performance Monitors Peripheral Identification Register 1 |
0xFE8 | PMPIDR2 | Performance Monitors Peripheral Identification Register 2 |
0xFEC | PMPIDR3 | Performance Monitors Peripheral Identification Register 3 |
0xFF0 | PMCIDR0 | Performance Monitors Component Identification Register 0 |
0xFF4 | PMCIDR1 | Performance Monitors Component Identification Register 1 |
0xFF8 | PMCIDR2 | Performance Monitors Component Identification Register 2 |
0xFFC | PMCIDR3 | Performance Monitors Component Identification Register 3 |
Frame | Offset | Name | Description |
---|---|---|---|
CNTBaseN | 0x000 |
CNTPCT[31:0]
|
Counter-timer |
CNTBaseN | 0x004 |
CNTPCT[63:32]
|
Counter-timer |
CNTBaseN | 0x008 |
CNTVCT[31:0]
|
Counter-timer |
CNTBaseN | 0x00C |
CNTVCT[63:32]
|
Counter-timer |
CNTBaseN | 0x010 |
CNTFRQ
|
Counter-timer |
CNTBaseN | 0x014 |
CNTEL0ACR
|
Counter-timer |
CNTBaseN | 0x018 |
CNTVOFF[31:0]
|
Counter-timer |
CNTBaseN | 0x01C |
CNTVOFF[63:32]
|
Counter-timer |
CNTBaseN | 0x020 |
CNTP_CVAL[31:0]
|
Counter-timer |
CNTBaseN | 0x024 |
CNTP_CVAL[63:32]
|
Counter-timer |
CNTBaseN | 0x028 |
CNTP_TVAL
|
Counter-timer |
CNTBaseN | 0x02C |
CNTP_CTL
|
Counter-timer |
CNTBaseN | 0x030 |
CNTV_CVAL[31:0]
|
Counter-timer |
CNTBaseN | 0x034 |
CNTV_CVAL[63:32]
|
Counter-timer |
CNTBaseN | 0x038 |
CNTV_TVAL
|
Counter-timer |
CNTBaseN | 0x03C |
CNTV_CTL
|
Counter-timer |
CNTBaseN | 0xFD0 + 4n |
CounterID<n>
|
Counter |
CNTCTLBase | 0x000 |
CNTFRQ
|
Counter-timer |
CNTCTLBase | 0x004 |
CNTNSAR
|
Counter-timer |
CNTCTLBase | 0x008 |
CNTTIDR
|
Counter-timer |
CNTCTLBase | 0x040 + 4n |
CNTACR<n>
|
Counter-timer |
CNTCTLBase | 0x080 + 8n |
CNTVOFF<n>[31:0]
|
Counter-timer |
CNTCTLBase | 0x084 + 8n |
CNTVOFF<n>[63:32]
|
Counter-timer |
CNTCTLBase | 0xFD0 + 4n |
CounterID<n>
|
Counter |
CNTControlBase | 0x000 |
CNTCR
|
Counter |
CNTControlBase | 0x004 |
CNTSR
|
Counter |
CNTControlBase | 0x008 |
CNTCV[31:0]
|
Counter |
CNTControlBase | 0x00C |
CNTCV[63:32]
|
Counter |
CNTControlBase | 0x020 + 4n |
CNTFID<n>
|
Counter |
CNTControlBase | 0x020 |
CNTFID0
|
Counter |
CNTControlBase | 0xFD0 + 4n |
CounterID<n>
|
Counter |
CNTEL0BaseN | 0x000 |
CNTPCT[31:0]
|
Counter-timer |
CNTEL0BaseN | 0x004 |
CNTPCT[63:32]
|
Counter-timer |
CNTEL0BaseN | 0x008 |
CNTVCT[31:0]
|
Counter-timer |
CNTEL0BaseN | 0x00C |
CNTVCT[63:32]
|
Counter-timer |
CNTEL0BaseN | 0x010 | CNTFRQ | Counter-timer Frequency |
CNTEL0BaseN | 0x020 | CNTP_CVAL[31:0] | Counter-timer Physical Timer CompareValue |
CNTEL0BaseN | 0x024 | CNTP_CVAL[63:32] | Counter-timer Physical Timer CompareValue |
CNTEL0BaseN | 0x028 | CNTP_TVAL | Counter-timer Physical Timer TimerValue |
CNTEL0BaseN | 0x02C | CNTP_CTL | Counter-timer Physical Timer Control |
CNTEL0BaseN | 0x030 | CNTV_CVAL[31:0] | Counter-timer Virtual Timer CompareValue |
CNTEL0BaseN | 0x034 | CNTV_CVAL[63:32] | Counter-timer Virtual Timer CompareValue |
CNTEL0BaseN | 0x038 | CNTV_TVAL | Counter-timer Virtual Timer TimerValue |
CNTEL0BaseN | 0x03C | CNTV_CTL | Counter-timer Virtual Timer Control |
CNTEL0BaseN | 0xFD0 + 4n | CounterID<n> | Counter ID registers |
CNTReadBase | 0x000 | CNTCV[31:0] | Counter Count Value register |
CNTReadBase | 0x004 | CNTCV[63:32] | Counter Count Value register |
CNTReadBase | 0xFD0 + 4n | CounterID<n> | Counter ID registers |
28/0907/2017 0816:4140
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.
SysReg_v83A_xml-00bet4 (old) | htmldiff from-SysReg_v83A_xml-00bet4 | (new) SysReg_v83A_xml-00bet5 |