The PMPCSR characteristics are:
Holds a sampled instruction address value.
This register is part of the Performance Monitors registers functional group.
This register is accessible as follows:
Off | DLK | OSLK | SLK | Default |
---|---|---|---|---|
Error | Error | Error | RO | RO |
IMPLEMENTATION DEFINED extensions to external debug might make the value of this register UNKNOWN, see the section describing 'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN' in chapter H7 'The PC Sample-based Profiling Extension' of the ARM Architecture Reference Manual, for ARMv8-A architecture profile.
PMPCSR is in the Core power domain.
Fields in this register reset to architecturally UNKNOWN values. These apply only on a Cold reset. The register is not affected by a Warm reset and is not affected by an External debug reset.
Implemented only when ARMv8.2-PCSample is implemented.
Before ARMv8.2, the PC Sample-based Profiling Extension can be implemented in the external debug register space, as indicated by the value of EDDEVID.PCSample.
Support for 64-bit atomic reads is IMPLEMENTATION DEFINED. If 64-bit atomic reads are implemented, a 64-bit read of PMPCSR has the same side-effect as a 32-bit read of PMCSR[31:0] followed by a 32-bit read of PMPCSR[63:32], returning the combined value. For example, if the PE is in Debug state then a 64-bit atomic read returns bits[31:0] == 0xFFFFFFFF and bits[63:32] UNKNOWN.
This register is introduced in ARMv8.2.
PMPCSR is a 64-bit register.
The PMPCSR bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
NS | EL | 0 | 0 | 0 | 0 | 0 | PC Sample[55:32] | ||||||||||||||||||||||||
PC Sample[31:1] | SBZ | ||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Non-secure state sample. Indicates the Security state that is associated with the most recent PMPCSR sample or, when it is read as a single atomic 64-bit read, the current PMPCSR sample.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Exception level status sample. Indicates the Exception level that is associated with the most recent PMPCSR sample or, when it is read as a single atomic 64-bit read, the current PMPCSR sample.
EL | Meaning |
---|---|
00 |
Sample is from EL0. |
01 |
Sample is from EL1. |
10 |
Sample is from EL2. |
11 |
Sample is from EL3. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Reserved, RES0.
Bits[55:32] of the sampled instruction address value. The translation regime that PMPCSR samples can be determined from PMPCSR.{NS,EL}.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Bits[31:1] of the sampled instruction address value. The translation regime that PMPCSR samples can be determined from PMPCSR.{NS,EL}.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Reserved, SBZ.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
For a read of PMPCSR[31:0] from the memory-mapped interface, if PMLSR.SLK == 1, meaning the OPTIONAL Software Lock is locked, then the access has no side-effects.
In any other cases, a read of PMPCSR[31:0] has the side-effect of indirectly writing to PMPCSR[63:32], PMCID1SR, PMCID2SR, and PMVIDSR:
PMPCSR[31:0] can be accessed through the external debug interface:
Component | Offset |
---|---|
PMU | 0x200 |
PMU | 0x220 |
PMPCSR[63:32] can be accessed through the external debug interface:
Component | Offset |
---|---|
PMU | 0x204 |
PMU | 0x224 |
28/09/2017 08:24
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.