ICV_AP0R<n>_EL1, Interrupt Controller Virtual Active Priorities Group 0 Registers, n = 0 - 3

The ICV_AP0R<n>_EL1 characteristics are:

Purpose

Provides information about virtual Group 0 active priorities.

This register is part of:

Configuration

AArch64 System register ICV_AP0R<n>_EL1 is architecturally mapped to AArch32 System register ICV_AP0R<n>.

Attributes

ICV_AP0R<n>_EL1 is a 32-bit register.

Field descriptions

The ICV_AP0R<n>_EL1 bit assignments are:

313029282726252423222120191817161514131211109876543210
IMPLEMENTATION DEFINED

IMPLEMENTATION DEFINED, bits [31:0]

IMPLEMENTATION DEFINED.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

The contents of these registers are IMPLEMENTATION DEFINED with the one architectural requirement that the value 0x00000000 is consistent with no interrupts being active.

Accessing the ICV_AP0R<n>_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
ICC_AP0R<n>_EL111000110010001:n<1:0>

When HCR_EL2.FMO is set to 0, execution of this encoding at Non-secure EL1 results in an access to ICC_AP0R<n>_EL1.

Accessibility

The register is accessible as follows:

Control Accessibility
FMOIMOTGENSEL0EL1EL2EL3
xxx0 - ICC_AP0R<n>_EL1 n/a ICC_AP0R<n>_EL1
xx11 - n/a ICC_AP0R<n>_EL1 ICC_AP0R<n>_EL1
0x01 - ICC_AP0R<n>_EL1 ICC_AP0R<n>_EL1 ICC_AP0R<n>_EL1
1x01 - RW ICC_AP0R<n>_EL1 ICC_AP0R<n>_EL1

This table applies to all instructions that can access this register.

The ICV_AP0R<n>_EL1 registers are only accessible at Non-secure EL1 when HCR_EL2.FMO is set to 1.

Note

When HCR_EL2.FMO is set to 0, at Non-secure EL1, the instruction encoding used to access ICV_AP0R<n>_EL1 results in an access to ICC_AP0R<n>_EL1.

Writing to these registers with any value other than the last read value of the register (or 0x00000000 when there are no Group 0 active priorities) might result in UNPREDICTABLE behavior of the virtual interrupt prioritization system, causing:

ICV_AP0R1_EL1 is only implemented in implementations that support 6 or more bits of priority. ICV_AP0R2_EL1 and ICV_AP0R3_EL1 are only implemented in implementations that support 7 bits of priority. Unimplemented registers are UNDEFINED.

Writing to the active priority registers in any order other than the following order might result in UNPREDICTABLE behavior of the interrupt prioritization system:

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When SCR_EL3.NS==1 :




28/09/2017 08:24

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