The DC CIVAC characteristics are:
Clean and Invalidate data cache by address to Point of Coherency.
This System instruction is part of the Cache maintenance instructions functional group.
AArch64 System instruction DC CIVAC performs the same function as AArch32 System instruction DCCIMVAC.
DC CIVAC is a 64-bit System instruction.
The DC CIVAC input value bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
Virtual address to use | |||||||||||||||||||||||||||||||
Virtual address to use | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Virtual address to use.
This instruction is executed using DC with the following syntax:
DC <dc_op>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<dc_op> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
CIVAC | 01 | 011 | 0111 | 1110 | 001 |
The instruction is executable as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | WO | WO | n/a | WO |
x | 0 | 1 | WO | WO | WO | WO |
x | 1 | 1 | WO | n/a | WO | WO |
This table applies to all syntax that can be used to execute this instruction.
If EL0 access is enabled, when executed at EL0, this instruction requires read access permission to the VA, otherwise it generates a Permission Fault, subject to the constraints described in the subsection describing 'Permission fault' in Chapter D4 of the ARMv8 Architecture Reference Manual for ARMv8-A architecture profile.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when executing this System instruction.
In both Security states, and not dependent on other configuration bits:
If SCTLR_EL1.UCI==0, execution of this instruction at EL0 is trapped to EL1.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TPC==1, Non-secure execution of this instruction at EL1 is trapped to EL2.
If HCR_EL2.TPC==1, and SCTLR_EL1.UCI==1, Non-secure execution of this instruction at EL0 is trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TPC==1, Non-secure execution of this instruction at EL0 is trapped to EL2.
28/09/2017 08:24
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