The GICD_ISACTIVER<n> characteristics are:
Activates the corresponding interrupt. These registers are used when saving and restoring GIC state.
This register is part of the GIC Distributor registers functional group.
This register is accessible as follows:
Security disabled | Secure | Non-secure |
---|---|---|
RW | RW | RW |
When affinity routing is enabled for the Security state of an interrupt, bits corresponding to SGIs and PPIs are RAZ/WI, and equivalent functionality for SGIs and PPIs is provided by GICR_ISACTIVER0.
Bits corresponding to unimplemented interrupts are RAZ/WI.
If GICD_CTLR.DS==0, unless the GICD_NSACR<n> registers permit Non-secure software to control Group 0 and Secure Group 1 interrupts, any bits that correspond to Group 0 or Secure Group 1 interrupts are accessible only by Secure accesses and are RAZ/WI to Non-secure accesses.
The bit reads as one if the status of the interrupt is active or active and pending. GICD_ISPENDR<n> and GICD_ICPENDR<n> provide the pending status of the interrupt.
Some or all RW fields of this register have defined reset values.
These registers are available in all GIC configurations. If GICD_CTLR.DS==0, these registers are Common.
The number of implemented GICD_ISACTIVER<n> registers is (GICD_TYPER.ITLinesNumber+1). Registers are numbered from 0.
GICD_ISACTIVER0 is Banked for each connected PE with GICR_TYPER.Processor_Number < 8.
Accessing GICD_ISACTIVER0 from a PE with GICR_TYPER.Processor_Number > 7 is CONSTRAINED UNPREDICTABLE:
GICD_ISACTIVER<n> is a 32-bit register.
The GICD_ISACTIVER<n> bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Set_active_bit<x>, bit [x], for x = 0 to 31 |
Adds the active state to interrupt number 32n + x. Reads and writes have the following behavior:
Set_active_bit<x> | Meaning |
---|---|
0 |
If read, indicates that the corresponding interrupt is not active, and is not active and pending. If written, has no effect. |
1 |
If read, indicates that the corresponding interrupt is active, or is active and pending. If written, activates the corresponding interrupt, if the interrupt is not already active. If the interrupt is already active, the write has no effect. After a write of 1 to this bit, a subsequent read of this bit returns 1. |
When this register has an architecturally-defined reset value, this field resets to 0.
For INTID m, when DIV and MOD are the integer division and modulo operations:
GICD_ISACTIVER<n> can be accessed through its memory-mapped interface:
Component | Offset |
---|---|
GIC Distributor | 0x0300 + 4n |
28/09/2017 08:24
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