APGAKeyLo_EL1, Pointer Authentication Key A for Code (bits[63:0])

The APGAKeyLo_EL1 characteristics are:

Purpose

Holds bits[63:0] of key used for generic pointer authentication code.

Note

The term APGAKey_EL1 is used to describe the concatenation of APGAKeyHi_EL1: APGAKeyLo_EL1.

This register is part of the Pointer authentication functional group.

Configuration

RW fields in this register reset to architecturally UNKNOWN values.

This register is introduced in ARMv8.3.

Attributes

APGAKeyLo_EL1 is a 64-bit register.

Field descriptions

The APGAKeyLo_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
64 bit value, bits[63:0] of the 128 bit pointer authentication key value
64 bit value, bits[63:0] of the 128 bit pointer authentication key value
313029282726252423222120191817161514131211109876543210

Bits [63:0]

64 bit value, bits[63:0] of the 128 bit pointer authentication key value.

Accessing the APGAKeyLo_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
APGAKeyLo_EL11100000100011000

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RW n/a RW
x01 - RWRWRW
x11 - n/a RWRW

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :

When EL3 is implemented and is using AArch64 :




28/09/2017 08:24

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