ICC_BPR0, Interrupt Controller Binary Point Register 0

The ICC_BPR0 characteristics are:

Purpose

Defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field. The group priority field determines Group 0 interrupt preemption.

This register is part of:

Configuration

There is one instance of this register that is used in both Secure and Non-secure states.

AArch32 System register ICC_BPR0 is architecturally mapped to AArch64 System register ICC_BPR0_EL1.

Attributes

ICC_BPR0 is a 32-bit register.

Field descriptions

The ICC_BPR0 bit assignments are:

313029282726252423222120191817161514131211109876543210
00000000000000000000000000000BinaryPoint

Bits [31:3]

Reserved, RES0.

BinaryPoint, bits [2:0]

The value of this field controls how the 8-bit interrupt priority field is split into a group priority field, that determines interrupt preemption, and a subpriority field. This is done as follows:

Binary point value Group priority field Subpriority field Field with binary point
0 [7:1] [0] ggggggg.s
1 [7:2] [1:0] gggggg.ss
2 [7:3] [2:0] ggggg.sss
3 [7:4] [3:0] gggg.ssss
4 [7:5] [4:0] ggg.sssss
5 [7:6] [5:0] gg.ssssss
6 [7] [6:0] g.sssssss
7 No preemption [7:0] .ssssssss

Accessing the ICC_BPR0

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 0, <Rt>, c12, c8, 3000011110011111000

When HCR.FMO is set to 1, execution of this encoding at Non-secure EL1 results in an access to ICV_BPR0.

Accessibility

The register is accessible as follows:

Control Accessibility
FMOIMOTGENSEL0EL1EL2EL3
xxx0 - RW n/a RW
xx11 - n/a RWRW
0x01 - RWRWRW
1x01 - ICV_BPR0 RWRW

This table applies to all instructions that can access this register.

ICC_BPR0 is only accessible at Non-secure EL1 when HCR.FMO is set to 0.

Note

When HCR.FMO is set to 1, at Non-secure EL1, the instruction encoding used to access ICC_BPR0 results in an access to ICV_BPR0.

The minimum binary point value is derived from the number of implemented priority bits. The number of priority bits is IMPLEMENTATION DEFINED, and reported by ICC_CTLR.PRIbits and ICC_MCTLR.PRIbits.

An attempt to program the binary point field to a value less than the minimum value sets the field to the minimum value. On a reset, the binary point field is set to the minimum supported value.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :

When SCR_EL3.NS==1 :

When EL3 is implemented and is using AArch32 :

When EL3 is implemented and is using AArch32 and SCR_EL3.NS==1 :

When EL3 is implemented and is using AArch64 and SCR_EL3.NS==0 :

When EL3 is implemented and is using AArch64 :

When EL3 is implemented and is using AArch64 and SCR_EL3.NS==1 :




28/09/2017 08:24

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