SysReg_v83A_xml-00bet4 (old) | htmldiff from-SysReg_v83A_xml-00bet4 | (new) SysReg_v83A_xml-00bet5 |
The DBGWVR<n> characteristics are:
Holds a data address value for use in watchpoint matching. Forms watchpoint n together with control register DBGWCR<n>.
This register is part of the Debug registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register DBGWVR<n> is architecturally mapped to AArch64 System register DBGWVR<n>_EL1[31:0] .
AArch32 System register DBGWVR<n> is architecturally mapped to External register DBGWVR<n>_EL1[31:0] .
If breakpoint n is not implemented then this register is unallocated.
This register is in the Cold reset domain. On a Cold reset RW fields in this register reset to architecturally UNKNOWN values. The register is not affected by a Warm reset.
DBGWVR<n> is a 32-bit register.
The DBGWVR<n> bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VA | 0 | 0 |
Bits[31:2] of the address value for comparison.
ARM deprecates setting DBGWVR<n>[2] == 1.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Reserved, RES0.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p14, 0, <Rt>, c0, <CRm>, 6 | 000 | 110 | 0000 | 1110 | n<3:0> |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RW | n/a | RW |
x | 0 | 1 | - | RW | RW | RW |
x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If EDSCR.TDA==1, and DBGOSLSR.OSLK==0, and halting is allowed, accesses to this register from PL1 and PL2 generateare atrapped Softwareto AccessDebug debug event.state.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TDA==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TDA==1, accesses to this register from EL1 and EL2 are trapped to EL3.
28/0907/2017 0816:2440
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.
SysReg_v83A_xml-00bet4 (old) | htmldiff from-SysReg_v83A_xml-00bet4 | (new) SysReg_v83A_xml-00bet5 |