The DBGDTRRXext characteristics are:
Used for save/restore of DBGDTRRXint. It is a component of the Debug Communications Channel.
This register is part of the Debug registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register DBGDTRRXext is architecturally mapped to AArch64 System register OSDTRRX_EL1.
DBGDTRRXext is a 32-bit register.
The DBGDTRRXext bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Update DTRRX without side-effect |
Update DTRRX without side-effect.
Writes to this register update the value in DTRRX and do not change RXfull.
Reads of this register return the last value written to DTRRX and do not change RXfull.
For the full behavior of the Debug Communications Channel, see 'The Debug Communication Channel and Instruction Transfer Register' in the ARM ARM, chapter H4.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN on Cold reset. This field is not affected on Warm reset.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p14, 0, <Rt>, c0, c0, 2 | 000 | 010 | 0000 | 1110 | 0000 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RW | n/a | RW |
x | 0 | 1 | - | RW | RW | RW |
x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
ARM deprecates reads and writes of DBGDTRRXext through the System register interface when the OS lock is unlocked.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TDA==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HDCR.TDA==1, Non-secure accesses to this register from EL1 are trapped to Hyp mode.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TDA==1, accesses to this register from EL1 and EL2 are trapped to EL3.
28/09/2017 08:24
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