The ICV_DIR characteristics are:
When interrupt priority drop is separated from interrupt deactivation, a write to this register deactivates the specified virtual interrupt.
This register is part of:
AArch32 System register ICV_DIR performs the same function as AArch64 System register ICV_DIR_EL1.
ICV_DIR is a 32-bit register.
The ICV_DIR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | INTID |
Reserved, RES0.
The INTID of the virtual interrupt to be deactivated.
This field has either 16 or 24 bits implemented. The number of implemented bits can be found in ICV_CTLR.IDbits. If only 16 bits are implemented, bits [23:16] of this register are RES0.
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c12, c11, 1 | 000 | 001 | 1100 | 1111 | 1011 |
This encoding results in an access to ICV_DIR at Non-secure EL1 in the following cases:
This encoding results in an access to ICC_DIR at Non-secure EL1 in the following cases:
The register is accessible as follows:
Control | Accessibility | ||||||
---|---|---|---|---|---|---|---|
FMO | IMO | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | x | 0 | - | ICC_DIR | n/a | ICC_DIR |
x | x | 1 | 1 | - | n/a | ICC_DIR | ICC_DIR |
x | 1 | 0 | 1 | - | WO | ICC_DIR | ICC_DIR |
1 | x | 0 | 1 | - | WO | ICC_DIR | ICC_DIR |
0 | 0 | 0 | 1 | - | ICC_DIR | ICC_DIR | ICC_DIR |
This table applies to all instructions that can access this register.
The ICV_DIR register is only accessible at Non-secure EL1 in the following cases:
At Non-secure EL1, the instruction encoding used to access ICV_DIR results in an access to ICC_DIR when HCR.{FMO, IMO} == {0, 0}.
When EOImode == 0, writes are ignored In systems supporting system error generation, an implementation might generate an SEI.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_SRE.SRE==0, Non-secure write accesses to this register from EL1 are UNDEFINED.
If ICC_SRE_EL1.SRE==0, Non-secure write accesses to this register from EL1 are trapped to EL1.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If HSTR_EL2.T12==1, Non-secure write accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T12==1, Non-secure write accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HSTR.T12==1, Non-secure write accesses to this register from EL1 are trapped to Hyp mode.
When SCR_EL3.NS==1 :
If ICH_HCR.TC==1, Non-secure write accesses to this register from EL1 are trapped to EL2.
If ICH_HCR_EL2.TC==1, Non-secure write accesses to this register from EL1 are trapped to EL2.
28/09/2017 08:24
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