The GICC_AHPPIR characteristics are:
If the highest priority pending interrupt is in Group 1, this register provides the INTID of the highest priority pending interrupt on the CPU interface.
This register is part of the GIC physical CPU interface registers functional group.
This register is accessible as follows:
Security disabled | Secure | Non-secure |
---|---|---|
RO | RO | RO |
This register is used only when System register access is not enabled. When System register access is enabled:
If the highest priority pending interrupt is in Group 0, a read of this register returns the special INTID 1023.
Interrupt identifiers corresponding to an interrupt group that is not enabled are ignored.
If the highest priority pending interrupt is a direct interrupt that is both individually enabled in the Distributor and part of an interrupt group that is enabled in the Distributor, and the interrupt group is disabled in the CPU interface for this PE, this register returns the special INTID 1023.
See Preemption for more information about pending interrupts that are not considered when determining the highest priority pending interrupt.
When affinity routing is enabled for a Security state, it is a programming error to use memory-mapped registers to access the GIC.
If GICD_CTLR.DS==0, this register is an alias of the Non-secure view of GICC_HPPIR. A Secure access to this register is identical to a Non-secure access to GICC_HPPIR.
GICC_AHPPIR is a 32-bit register.
The GICC_AHPPIR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | INTID |
Reserved, RES0.
The INTID of the signaled interrupt.
INTIDs 1020-1023 are reserved and convey additional information such as spurious interrupts.
When affinity routing is not enabled:
GICC_AHPPIR can be accessed through its memory-mapped interface:
Component | Offset |
---|---|
GIC CPU interface | 0x0028 |
28/09/2017 08:24
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