The PMEVCNTR<n>_EL0 characteristics are:
Holds event counter n, which counts events, where n is 0 to 30.
This register is part of the Performance Monitors registers functional group.
This register is accessible as follows:
Off | DLK | OSLK | EPMAD | SLK | Default |
---|---|---|---|---|---|
Error | Error | Error | Error | RO | RW |
External accesses to the performance monitors ignore PMUSERENR_EL0 and, if implemented, MDCR_EL2.{TPM, TPMCR, HPMN} and MDCR_EL3.TPM. This means that all counters are accessible regardless of the current EL or privilege of the access.
External register PMEVCNTR<n>_EL0 is architecturally mapped to AArch64 System register PMEVCNTR<n>_EL0.
External register PMEVCNTR<n>_EL0 is architecturally mapped to AArch32 System register PMEVCNTR<n>.
PMEVCNTR<n>_EL0 is in the Core power domain. RW fields in this register reset to architecturally UNKNOWN values. These apply on a Warm or Cold reset. The register is not affected by an External debug reset.
PMEVCNTR<n>_EL0 is a 32-bit register.
The PMEVCNTR<n>_EL0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Event counter n |
Event counter n. Value of event counter n, where n is the number of this register and is a number from 0 to 30.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
PMEVCNTR<n>_EL0 can be accessed through the external debug interface:
Component | Offset |
---|---|
PMU | 0x000 + 8n |
28/09/2017 08:24
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