The EDPRSR characteristics are:
Holds information about the reset and powerdown state of the PE.
This register is part of the Debug registers functional group.
This register is accessible as follows:
SLK | Default |
---|---|
RO | RO |
On permitted accesses to the register, other access controls affect the behavior of some fields. See the field descriptions for more information.
If the Core power domain is powered up (EDPRSR.PU == 1), then following a read of EDPRSR:
If the Core power domain is powered down (EDPRSR.PU == 0), then:
The clearing of bits is an indirect write to EDPRSR.
EDPRSR contains fields that are in the Core power domain and fields that are in the Debug power domain.
Some of the fields in the Core power domain are in the Cold reset domain and others are in the Warm reset domain. See the field descriptions for more information. However:
EDPRSR is a 32-bit register.
The EDPRSR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SDR | SPMAD | EPMAD | SDAD | EDAD | DLK | OSLK | HALTED | SR | R | SPD | PU |
Reserved, RES0.
Sticky debug restart. Set to 1 when the PE exits Debug state.
This bit is UNKNOWN on reads if any of the following are true:
Otherwise permitted values are:
SDR | Meaning |
---|---|
0 |
The PE has not restarted since EDPRSR was last read. |
1 |
The PE has restarted since EDPRSR was last read. |
If a reset occurs when the PE is in Debug state, the PE exits Debug state. SDR is UNKNOWN on Warm reset, meaning a debugger must also use the SR bit to determine whether the PE has left Debug state.
If EDPRSR.PU reads as 1, which means that the Core power domain is in a powerup state, then following a read of EDPRSR:
This field is in the Core power domain and the Warm reset domain. On a Warm or Cold reset it resets to an UNKNOWN value.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
This field resets to its defined reset value on Warm reset.
This table summarizes the effect of the register access controls on the behavior of this field:
Off | DLK | SLK | Default |
---|---|---|---|
UNK | UNK | RO | RC |
'Access permissions for the External debug interface registers' in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile, section H8.6.1 describes the conditions shown in this table. These conditions are prioritized, with the leftmost condition having the highest priority and priority decreasing from left to right.
Sticky EPMAD error. Set to 1 if an external debug interface access to a Performance Monitors register returns an error because AllowExternalPMUAccess() == FALSE.
This bit is UNKNOWN on reads if any of the following are true:
Otherwise permitted values are:
SPMAD | Meaning |
---|---|
0 |
No accesses to the external Performance Monitors registers have failed since EDPRSR was last read. |
1 |
At least one access to the external Performance Monitors registers has failed since EDPRSR was last read. |
If the Core power domain is powered up, then, following a read of EDPRSR:
The write to SPMAD is an indirect write to EDPRSR that is a side effect of the access. The indirect write might not occur for a memory-mapped access to the external debug interface.
This field is in the Core power domain and the Cold reset domain. On a Cold reset it resets to 0.
When this register has an architecturally-defined reset value, this field resets to 0.
This field resets to its defined reset value on Cold reset.
This table summarizes the effect of the register access controls on the behavior of this field:
Off | DLK | OSLK | SLK | Default |
---|---|---|---|---|
UNK | UNK | UNK | RO | RC |
'Access permissions for the External debug interface registers' in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile, section H8.6.1 describes the conditions shown in this table. These conditions are prioritized, with the leftmost condition having the highest priority and priority decreasing from left to right.
External Performance Monitors access disable status.
This bit is UNKNOWN on reads if any of the following is true:
Otherwise permitted values are:
EPMAD | Meaning |
---|---|
0 |
External Performance Monitors access enabled. AllowExternalPMUAccess() == TRUE. |
1 |
External Performance Monitors access disabled. AllowExternalPMUAccess() == FALSE. |
If external performance monitors access is not implemented, EPMAD is RAO.
This field is in the Core power domain.
This table summarizes the effect of the register access controls on the behavior of this field:
Off | DLK | OSLK | EPMAD | Default |
---|---|---|---|---|
UNK | UNK | UNK | RAO | RO |
'Access permissions for the External debug interface registers' in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile, section H8.6.1 describes the conditions shown in this table. These conditions are prioritized, with the leftmost condition having the highest priority and priority decreasing from left to right.
Sticky EDAD error. Set to 1 if an external debug interface access to a debug register returns an error because AllowExternalDebugAccess() == FALSE.
This bit is UNKNOWN on reads if any of the following are true:
Otherwise permitted values are:
SDAD | Meaning |
---|---|
0 |
No accesses to the external debug registers have failed since EDPRSR was last read. |
1 |
At least one access to the external debug registers has failed since EDPRSR was last read. |
If the Core power domain is powered up, then, following a read of EDPRSR:
The write to SDAD is an indirect write to EDPRSR that is a side effect of the access. The indirect write might not occur for a memory-mapped access to the external debug interface.
This field is in the Core power domain and the Cold reset domain. On a Cold reset it resets to 0.
When this register has an architecturally-defined reset value, this field resets to 0.
This field resets to its defined reset value on Cold reset.
This table summarizes the effect of the register access controls on the behavior of this field:
Off | DLK | OSLK | SLK | Default |
---|---|---|---|---|
UNK | UNK | See text | RO | RC |
'Access permissions for the External debug interface registers' in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile, section H8.6.1 describes the conditions shown in this table. These conditions are prioritized, with the leftmost condition having the highest priority and priority decreasing from left to right.
External debug access disable status.
This bit is UNKNOWN on reads if any of the following are true:
Otherwise permitted values are:
EDAD | Meaning |
---|---|
0 |
External debug access enabled. AllowExternalDebugAccess() == TRUE. |
1 |
External debug access disabled. AllowExternalDebugAccess() == FALSE. |
This field is in the Core power domain.
This table summarizes the effect of the register access controls on the behavior of this field:
Off | DLK | OSLK | EDAD | Default |
---|---|---|---|---|
UNK | UNK | See text | RAO | RAZ |
'Access permissions for the External debug interface registers' in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile, section H8.6.1 describes the conditions shown in this table. These conditions are prioritized, with the leftmost condition having the highest priority and priority decreasing from left to right.
OS Double Lock status bit. Returns the result of the pseudocode function DoubleLockStatus().
This bit is UNKNOWN on reads if EDPRSR.PU is 0.
Otherwise reads as zero if any of the following are true, that is when DoubleLockStatus() == FALSE:
In ARMv8.0 and ARMv8.1, if the Core power domain is powered up and DoubleLockStatus() == TRUE, it is IMPLEMENTATION DEFINED whether:
From ARMv8.2, if the Core power domain is powered up and DoubleLockStatus() == TRUE, then EDPRSR.PU reads as 0, EDPRSR.DLK is UNKNOWN, and EDPRSR.SPD reads as 0.
If the Core power domain is powered up and entered reset state with the OS double-lock locked this bit has a CONSTRAINED UNPREDICTABLE value, for more information see 'EDPRSR.{DLK, R} and reset state' in the ARMv8 ARM, section H6 (Debug Reset and Powerdown Support)
EDPRSR.{DLK, SPD, PU} describe whether registers in the Core power domain can be accessed, and whether their state has been lost since the last time the register was read. For more information, see 'EDPRSR.{DLK, SPD, PU} bits record accessibility and lost of state in Core power domain' in the ARMv8 ARM, section H6 (Debug Reset and Powerdown Support)
Use of this bit by debuggers is deprecated from ARMv8.2.
This field is in the Core power domain.
This table summarizes the effect of the register access controls on the behavior of this field:
Off | DLK | Default |
---|---|---|
UNK | See text | RAZ |
'Access permissions for the External debug interface registers' in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile, section H8.6.1 describes the conditions shown in this table. These conditions are prioritized, with the leftmost condition having the highest priority and priority decreasing from left to right.
OS lock status bit.
This bit is UNKNOWN on reads if either:
A read of this bit returns the value of OSLSR_EL1.OSLK.
This field is in the Core power domain.
This table summarizes the effect of the register access controls on the behavior of this field:
Off | DLK | OSLK | Default |
---|---|---|---|
UNK | UNK | RAO | RAZ |
'Access permissions for the External debug interface registers' in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile, section H8.6.1 describes the conditions shown in this table. These conditions are prioritized, with the leftmost condition having the highest priority and priority decreasing from left to right.
Halted status bit.
This bit is UNKNOWN on reads if EDPRSR.PU is 0.
Otherwise permitted values are:
HALTED | Meaning |
---|---|
0 |
PE is in Non-debug state. |
1 |
PE is in Debug state. |
Because the OS Double Lock is never set when the PE is in Debug state, this bit is always RAZ when DoubleLockStatus() == TRUE.
This field is in the Core power domain.
This table summarizes the effect of the register access controls on the behavior of this field:
Off | DLK | Default |
---|---|---|
UNK | See text | RO |
'Access permissions for the External debug interface registers' in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile, section H8.6.1 describes the conditions shown in this table. These conditions are prioritized, with the leftmost condition having the highest priority and priority decreasing from left to right.
Sticky core reset status bit.
This bit is UNKNOWN on reads if either:
Otherwise permitted values are:
SR | Meaning |
---|---|
0 |
The non-debug logic of the PE is not in reset state and has not been reset since the last time EDPRSR was read. |
1 |
The non-debug logic of the PE is in reset state or has been reset since the last time EDPRSR was read. |
If EDPRSR.PU reads as 1 and EDPRSR.R reads as 0, which means that the Core power domain is in a powerup state and that the non-debug logic of the PE is not in reset state, then following a read of EDPRSR:
This field is in the Core power domain and the Warm reset domain. On a Warm or Cold reset it resets to 1.
When this register has an architecturally-defined reset value, this field resets to 1.
This field resets to its defined reset value on Warm reset.
This table summarizes the effect of the register access controls on the behavior of this field:
Off | DLK | SLK | Default |
---|---|---|---|
UNK | UNK | RO | RC |
'Access permissions for the External debug interface registers' in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile, section H8.6.1 describes the conditions shown in this table. These conditions are prioritized, with the leftmost condition having the highest priority and priority decreasing from left to right.
PE reset status bit.
This bit is UNKNOWN on reads if either:
Otherwise permitted values are:
R | Meaning |
---|---|
0 |
The non-debug logic of the PE is not in reset state. |
1 |
The non-debug logic of the PE is in reset state. |
If the Core power domain is powered up and entered reset state with the OS double-lock locked this bit has a CONSTRAINED UNPREDICTABLE value, for more information see 'EDPRSR.{DLK, R} and reset state' in the ARMv8 ARM, section H6 (Debug Reset and Powerdown Support)
This field is in the Core power domain.
This table summarizes the effect of the register access controls on the behavior of this field:
Off | DLK | Default |
---|---|---|
UNK | UNK | RO |
'Access permissions for the External debug interface registers' in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile, section H8.6.1 describes the conditions shown in this table. These conditions are prioritized, with the leftmost condition having the highest priority and priority decreasing from left to right.
Sticky core powerdown status bit.
This bit is UNKNOWN on reads if EDPRSR.PU is 1 and DoubleLockStatus() == TRUE .
Otherwise, permitted values are:
SPD | Meaning |
---|---|
0 |
If EDPRSR.PU is 0, it is not known whether the state of the debug registers in the Core power domain is lost. If EDPRSR.PU is 1, the state of the debug registers in the Core power domain has not been lost. |
1 |
The state of the debug registers in the Core power domain has been lost. |
If the Core power domain is powered up, then, following a read of EDPRSR:
When the value of EDPRSR.PU is 0 indicating that the Core power domain is in either retention or powerdown state, EDPRSR.SPD reads as 0. For more information, see 'EDPRSR.SPD when the Core domain is in either retention or powerdown state' in the ARMv8 ARM, section H6 (Debug Reset and Powerdown Support).
EDPRSR.{DLK, SPD, PU} describe whether registers in the Core power domain can be accessed, and whether their state has been lost since the last time the register was read. For more information, see 'EDPRSR.{DLK, SPD, PU} bits record accessibility and lost of state in Core power domain' in the ARMv8 ARM, section H6 (Debug Reset and Powerdown Support).
This field is in the Core power domain and the Cold reset domain. On a Cold reset it resets to 1.
When this register has an architecturally-defined reset value, this field resets to 1.
This field resets to its defined reset value on Cold reset.
This table summarizes the effect of the register access controls on the behavior of this field:
Off | DLK | SLK | Default |
---|---|---|---|
RO | UNK | RO | RC |
'Access permissions for the External debug interface registers' in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile, section H8.6.1 describes the conditions shown in this table. These conditions are prioritized, with the leftmost condition having the highest priority and priority decreasing from left to right.
Core powerup status bit. Indicates whether the Core power domain debug registers can be accessed.
When the Core power domain is powered-up and OS double-lock is locked, then:
See the description of DLK for more information.
Otherwise, permitted values are:
PU | Meaning |
---|---|
0 |
Core is in a low-power or powerdown state where the debug registers cannot be accessed. |
1 |
Core is in a powerup state where the debug registers can be accessed. |
If the Core power domain is powered up and entered reset state with the OS double-lock locked this bit has a CONSTRAINED UNPREDICTABLE value, for more information see 'EDPRSR.{DLK, R} and reset state' in the ARMv8 ARM, section H6 (Debug Reset and Powerdown Support)
EDPRSR.{DLK, SPD, PU} describe whether registers in the Core power domain can be accessed, and whether their state has been lost since the last time the register was read. For more information, see 'EDPRSR.{DLK, SPD, PU} bits record accessibility and lost of state in Core power domain' in the ARMv8 ARM, section H6 (Debug Reset and Powerdown Support)
This table summarizes the effect of the register access controls on the behavior of this field:
Off | DLK | Default |
---|---|---|
RAZ | See text | RAO |
'Access permissions for the External debug interface registers' in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile, section H8.6.1 describes the conditions shown in this table. These conditions are prioritized, with the leftmost condition having the highest priority and priority decreasing from left to right.
EDPRSR can be accessed through the external debug interface:
Component | Offset |
---|---|
Debug | 0x314 |
28/09/2017 08:24
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