ISR, Interrupt Status Register

The ISR characteristics are:

Purpose

Shows the pending status of the IRQ, FIQ, or External abort. When executing at EL2, EL3 or secure EL1, this shows the pending status of the physical interrupts. When executing at Non-secure EL1:

This register is part of the Exception and fault handling registers functional group.

Configuration

There is one instance of this register that is used in both Secure and Non-secure states.

AArch32 System register ISR is architecturally mapped to AArch64 System register ISR_EL1.

Attributes

ISR is a 32-bit register.

Field descriptions

The ISR bit assignments are:

313029282726252423222120191817161514131211109876543210
00000000000000000000000AIF000000

Bits [31:9]

Reserved, RES0.

A, bit [8]

Asynchronous External abort pending bit:

AMeaning
0

No pending asynchronous External abort.

1

An asynchronous External abort is pending.

I, bit [7]

IRQ pending bit. Indicates whether an IRQ interrupt is pending:

IMeaning
0

No pending IRQ.

1

An IRQ interrupt is pending.

F, bit [6]

FIQ pending bit. Indicates whether an FIQ interrupt is pending.

FMeaning
0

No pending FIQ.

1

An FIQ interrupt is pending.

Bits [5:0]

Reserved, RES0.

Accessing the ISR

This register can be read using MRC with the following syntax:

MRC <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 0, <Rt>, c12, c1, 0000000110011110001

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RO n/a RO
x01 - RORORO
x11 - n/a RORO

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :




28/09/2017 08:24

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