The EDESR characteristics are:
Indicates the status of internally pending Halting debug events.
This register is part of the Debug registers functional group.
This register is accessible as follows:
Off | DLK | SLK | Default |
---|---|---|---|
Error | Error | RO | RW |
If a request to clear a pending Halting debug event is received at or about the time when halting becomes allowed, it is CONSTRAINED UNPREDICTABLE whether the event is taken.
If Core power is removed while a Halting debug event is pending, it is lost. However, it might become pending again when the Core is powered back on and Cold reset.
EDESR is in the Core power domain. Some or all RW fields of this register have defined reset values. These apply on a Warm or Cold reset. The register is not affected by an External debug reset.
EDESR is a 32-bit register.
The EDESR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SS | RC | OSUC |
Reserved, RES0.
Halting step debug event pending. Possible values of this field are:
SS | Meaning |
---|---|
0 |
Reading this means that a Halting step debug event is not pending. Writing this means no action. |
1 |
Reading this means that a Halting step debug event is pending. Writing this clears the pending Halting step debug event. |
When this register has an architecturally-defined reset value, this field resets to the value of EDECR.SS.
Reset Catch debug event pending. Possible values of this field are:
RC | Meaning |
---|---|
0 |
Reading this means that a Reset Catch debug event is not pending. Writing this means no action. |
1 |
Reading this means that a Reset Catch debug event is pending. Writing this clears the pending Reset Catch debug event. |
When this register has an architecturally-defined reset value, this field resets to the value of EDECR.RCE.
OS Unlock Catch debug event pending. Possible values of this field are:
OSUC | Meaning |
---|---|
0 |
Reading this means that an OS Unlock Catch debug event is not pending. Writing this means no action. |
1 |
Reading this means that an OS Unlock Catch debug event is pending. Writing this clears the pending OS Unlock Catch debug event. |
When this register has an architecturally-defined reset value, this field resets to 0.
EDESR can be accessed through the external debug interface:
Component | Offset |
---|---|
Debug | 0x020 |
28/09/2017 08:24
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.