ICC_IGRPEN0_EL1, Interrupt Controller Interrupt Group 0 Enable register

The ICC_IGRPEN0_EL1 characteristics are:

Purpose

Controls whether Group 0 interrupts are enabled or not.

This register is part of:

Configuration

AArch64 System register ICC_IGRPEN0_EL1 is architecturally mapped to AArch32 System register ICC_IGRPEN0.

Attributes

ICC_IGRPEN0_EL1 is a 32-bit register.

Field descriptions

The ICC_IGRPEN0_EL1 bit assignments are:

313029282726252423222120191817161514131211109876543210
0000000000000000000000000000000Enable

Bits [31:1]

Reserved, RES0.

Enable, bit [0]

Enables Group 0 interrupts.

EnableMeaning
0

Group 0 interrupts are disabled.

1

Group 0 interrupts are enabled.

Virtual accesses to this register update ICH_VMCR_EL2.VENG0.

If the highest priority pending interrupt for that PE is a Group 0 interrupt using 1 of N model, then the interrupt will be targeted to another PE as a result of the Enable bit changing from 1 to 0.

When this register has an architecturally-defined reset value, this field resets to 0.

Accessing the ICC_IGRPEN0_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
ICC_IGRPEN0_EL11100011001100110

When HCR_EL2.FMO is set to 1, execution of this encoding at Non-secure EL1 results in an access to ICV_IGRPEN0_EL1.

Accessibility

The register is accessible as follows:

Control Accessibility
FMOIMOTGENSEL0EL1EL2EL3
xxx0 - RW n/a RW
xx11 - n/a RWRW
0x01 - RWRWRW
1x01 - ICV_IGRPEN0_EL1 RWRW

This table applies to all instructions that can access this register.

ICC_IGRPEN0_EL1 is only accessible at Non-secure EL1 when HCR_EL2.FMO is set to 0.

Note

When HCR_EL2.FMO is set to 1, at Non-secure EL1, the instruction encoding used to access ICC_IGRPEN0_EL1 results in an access to ICV_IGRPEN0_EL1.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When SCR_EL3.NS==1 :

When EL3 is implemented and is using AArch64 and SCR_EL3.NS==0 :

When EL3 is implemented and is using AArch64 :

When EL3 is implemented and is using AArch64 and SCR_EL3.NS==1 :




28/09/2017 08:24

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