The MPIDR_EL1 characteristics are:
In a multiprocessor system, provides an additional PE identification mechanism for scheduling purposes.
This register is part of the Identification registers functional group.
AArch64 System register MPIDR_EL1 is architecturally mapped to AArch32 System register MPIDR.
The assigned value of the MPIDR.{Aff2, Aff1, Aff0} or MPIDR_EL1.{Aff3, Aff2, Aff1, Aff0} set of fields of each PE must be unique within the system as a whole.
In a uniprocessor system ARM recommends that each Aff<n> field of this register returns a value of 0.
MPIDR_EL1 is a 64-bit register.
The MPIDR_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Aff3 | |||||||
1 | U | 0 | 0 | 0 | 0 | 0 | MT | Aff2 | Aff1 | Aff0 | |||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Affinity level 3. Highest level affinity field.
Reserved, RES1.
Indicates a Uniprocessor system, as distinct from PE 0 in a multiprocessor system. The possible values of this bit are:
U | Meaning |
---|---|
0 |
Processor is part of a multiprocessor system. |
1 |
Processor is part of a uniprocessor system. |
Reserved, RES0.
Indicates whether the lowest level of affinity consists of logical PEs that are implemented using a multithreading type approach. The possible values of this bit are:
MT | Meaning |
---|---|
0 |
Performance of PEs at the lowest affinity level is largely independent. |
1 |
Performance of PEs at the lowest affinity level is very interdependent. |
Affinity level 2. Second highest level affinity field.
Affinity level 1. Third highest level affinity field.
Affinity level 0. Lowest level affinity field.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
MPIDR_EL1 | 11 | 000 | 0000 | 0000 | 101 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
28/09/2017 08:24
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