S1_<op1>_<Cn>_<Cm>_<op2>, IMPLEMENTATION DEFINED maintenance instructions

The S1_<op1>_<Cn>_<Cm>_<op2> characteristics are:

Purpose

This area of the System instruction encoding space is reserved for IMPLEMENTATION DEFINED System instructions.

This System instruction is part of the IMPLEMENTATION DEFINED functional group.

Configuration

There are no configuration notes.

Attributes

S1_<op1>_<Cn>_<Cm>_<op2> is a 64-bit System instruction.

Field descriptions

The S1_<op1>_<Cn>_<Cm>_<op2> input value bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
IMPLEMENTATION DEFINED
IMPLEMENTATION DEFINED
313029282726252423222120191817161514131211109876543210

IMPLEMENTATION DEFINED, bits [63:0]

IMPLEMENTATION DEFINED.

Executing the S1_<op1>_<Cn>_<Cm>_<op2> instruction

This instruction is executed using SYS with the following syntax:

SYS <op1>, C<Cn>, C<Cm>, <op2>

This instruction is executed using SYSL with the following syntax:

SYSL <op1>, C<Cn>, C<Cm>, <op2>

This syntax uses the following encoding in the System instruction encoding space:

CRnop1op2CRm
Cn<3:0> op1<2:0> op2<2:0> Cm<3:0>

The value of <Cn> must be either 11 or 15. Other values may refer to architecturally-defined system instructions.

Accessibility

The accessibility of system instructions with these encodings is IMPLEMENTATION DEFINED.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when executing this System instruction.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :




28/09/2017 08:24

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