The PMEVTYPER<n>_EL0 characteristics are:
Configures event counter n, where n is 0 to 30.
This register is part of the Performance Monitors registers functional group.
AArch64 System register PMEVTYPER<n>_EL0 is architecturally mapped to AArch32 System register PMEVTYPER<n>.
AArch64 System register PMEVTYPER<n>_EL0 is architecturally mapped to External register PMEVTYPER<n>_EL0.
This register is in the Warm reset domain. On a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.
PMEVTYPER<n>_EL0 is a 32-bit register.
The PMEVTYPER<n>_EL0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
P | U | NSK | NSU | NSH | M | MT | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | evtCount[15:10] | evtCount[9:0] |
Privileged filtering bit. Controls counting in EL1. If EL3 is implemented, then counting in Non-secure EL1 is further controlled by the NSK bit. The possible values of this bit are:
P | Meaning |
---|---|
0 |
Count events in EL1. |
1 |
Do not count events in EL1. |
User filtering bit. Controls counting in EL0. If EL3 is implemented, then counting in Non-secure EL0 is further controlled by the NSU bit. The possible values of this bit are:
U | Meaning |
---|---|
0 |
Count events in EL0. |
1 |
Do not count events in EL0. |
Non-secure EL1 (kernel) modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented, this bit is RES0.
If the value of this bit is equal to the value of P, events in Non-secure EL1 are counted.
Otherwise, events in Non-secure EL1 are not counted.
Non-secure EL0 (Unprivileged) filtering. Controls counting in Non-secure EL0. If EL3 is not implemented, this bit is RES0.
If the value of this bit is equal to the value of U, events in Non-secure EL0 are counted.
Otherwise, events in Non-secure EL0 are not counted.
Non-secure EL2 (Hypervisor) filtering. Controls counting in Non-secure EL2. If EL2 is not implemented, this bit is RES0.
NSH | Meaning |
---|---|
0 |
Do not count events in EL2. |
1 |
Count events in EL2. |
Secure EL3 filtering bit. If EL3 is not implemented, this bit is RES0.
If the value of this bit is equal to the value of P, cycles in Secure EL3 are counted.
Otherwise, cycles in Secure EL3 are not counted.
Most applications can ignore this field and set its value to 0.
This field is not visible in the AArch32 PMEVTYPER System register.
Multithreading. When the implementation is multi-threaded, the valid values for this bit are:
MT | Meaning |
---|---|
0 |
Count events only on controlling PE. |
1 |
Count events from any PE with the same affinity at level 1 and above as this PE. |
When the implementation is not multi-threaded, this bit is RES0.
Reserved, RES0.
Extension to evtCount[9:0]. See evtCount[9:0] for more details.
Reserved, RES0.
Event to count. The event number of the event that is counted by event counter PMEVCNTR<n>_EL0.
Software must program this field with an event that is supported by the PE being programmed.
There are three ranges of event numbers:
If evtCount is programmed to an event that is reserved or not supported by the PE, the behavior depends on the event type:
UNPREDICTABLE means the event must not expose privileged information.
ARM recommends that the behavior across a family of implementations is defined such that if a given implementation does not include an event from a set of common IMPLEMENTATION DEFINED events, then no event is counted and the value read back on evtCount is the value written.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
PMEVTYPER<n>_EL0 | 11 | 011 | 1110 | 11:n<4:3> | n<2:0> |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | RW | RW | n/a | RW |
x | 0 | 1 | RW | RW | RW | RW |
x | 1 | 1 | RW | n/a | RW | RW |
This table applies to all instructions that can access this register.
PMEVTYPER<n>_EL0 can also be accessed by using PMXEVTYPER_EL0 with PMSELR_EL0.SEL set to n.
If <n> is greater than or equal to the number of accessible counters, reads and writes of PMEVTYPER<n>_EL0 are CONSTRAINED UNPREDICTABLE, and the following behaviors are permitted:
In an implementation that includes EL2, in Non-secure state at EL0 and EL1, MDCR_EL2.HPMN identifies the number of accessible counters. Otherwise, the number of accessible counters is the number of implemented counters.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If PMUSERENR_EL0.EN==0, accesses to this register from EL0 are trapped to EL1.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TPM==1, Non-secure accesses to this register from EL0 and EL1 are trapped to EL2.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TPM==1, accesses to this register from EL0, EL1, and EL2 are trapped to EL3.
28/09/2017 08:24
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.