The PMBSR_EL1 characteristics are:
Provides syndrome information to software when the buffer is disabled because the management interrupt has been raised.
This register is part of the Statistical Profiling Extension registers functional group.
Present only if the Statistical Profiling Extension is implemented. Direct reads and writes of PMBSR_EL1 are UNDEFINED otherwise.
PMBSR_EL1 is a 64-bit register.
The PMBSR_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
EC | 0 | 0 | 0 | 0 | 0 | 0 | DL | EA | S | COLL | MSS | ||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Reserved, RES0.
Exception class
Top-level description of the cause of the buffer management event
EC | Meaning | MSS |
---|---|---|
0b100100 |
Stage 1 Data Abort on write to Profiling Buffer | stage-x-data-abort |
0b100101 |
Stage 2 Data Abort on write to Profiling Buffer | stage-x-data-abort |
0b000000 |
Other buffer management event. All buffer management events other than those described by other defined Exception class codes. | other-buffer-management-event |
All other values are reserved. Reserved values might be defined in a future version of the architecture.
Partial record lost
Following a buffer management event other than an asynchronous external abort, indicates whether the last record written to the Profiling Buffer is complete
DL | Meaning |
---|---|
0b0 |
PMBPTR_EL1 points to the first byte after the last complete record written to the Profiling Buffer |
0b1 |
Part of a record was lost because of a buffer management event or synchronous external abort. PMBPTR_EL1 might not point to the first byte after the last complete record written to the buffer, and so restarting collection might result in a data record stream that software cannot parse. All records prior to the last record have been written to the buffer |
When the buffer management event was because of an asynchronous external abort, this bit is set to 1 and software must not assume that any valid data has been written to the Profiling Buffer
External abort
EA | Meaning |
---|---|
0b0 |
An external abort has not been asserted |
0b1 |
An external abort has been asserted and detected by the Statistical Profiling Extension |
This bit is RES0 if the PE never sets this bit as the result of an external abort.
Service
S | Meaning |
---|---|
0b0 |
PMBIRQ is not asserted |
0b1 |
PMBIRQ is asserted. All profiling data has either been written to the buffer or discarded |
Collision detected
COLL | Meaning |
---|---|
0b0 |
No collision events detected |
0b1 |
At least one collision event was recorded |
Management Event Specific Syndrome
Contains syndrome specific to the management event
The syndrome contents for each management event are described in the following sections
This is the layout of the MSS field for exceptions with the following EC values:
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | FSC |
Reserved, RES0.
Fault status code
FSC | Meaning |
---|---|
0b0000xx |
Address Size fault. Bits [1:0] encode the level |
0b0001xx |
Translation fault. Bits [1:0] encode the level |
0b0010xx |
Access Flag fault. Bits [1:0] encode the level |
0b0011xx |
Permission fault. Bits [1:0] encode the level |
0b010000 |
Synchronous external abort on write |
0b0101xx |
Synchronous external abort on translation table walk or hardware update of translation table. Bits [1:0] encode the level |
0b010001 |
Asynchronous external abort on write |
0b100001 |
Alignment fault |
0b110000 |
TLB Conflict fault |
0b110101 |
Unsupported Access fault |
All other values are reserved. Reserved values might be defined in a future version of the architecture.
This is the layout of the MSS field for exceptions with the following EC values:
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | BSC |
Reserved, RES0.
Buffer status code
BSC | Meaning |
---|---|
0b000000 |
Buffer not filled |
0b000001 |
Buffer filled |
All other values are reserved. Reserved values might be defined in a future version of the architecture.
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | CRn | op0 | op1 | op2 | CRm |
---|---|---|---|---|---|
PMBSR_EL1 | 1001 | 11 | 000 | 011 | 1010 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RW | n/a | RW |
x | 0 | 1 | - | RW | RW | RW |
x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
If (AArch64-MDCR_EL2.E2PB == 0b00 || AArch64-MDCR_EL2.E2PB == 0b10) && AArch64-SCR_EL3.NS == 0b1, then access from EL1 traps to EL2
If AArch64-MDCR_EL3.NSPB != 0b01 && AArch64-SCR_EL3.NS == 0b0, then access from EL1 traps to EL3
If AArch64-MDCR_EL3.NSPB != 0b11 && AArch64-SCR_EL3.NS == 0b1, then access from EL2 or EL1 traps to EL3
12/09/2017 18:03
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