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PMPCSR, Program Counter Sample Register

The PMPCSR characteristics are:

Purpose

Holds a sampled instruction address value.

This register is part of the Performance Monitors registers functional group.

Usage constraints

This register is accessible as follows:

OffDLKOSLKSLKDefault
ErrorErrorErrorRORO

IMPLEMENTATION DEFINED extensions to external debug might make the value of this register UNKNOWN, see the section describing 'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN' in chapter H7 'The PC Sample-based Profiling Extension' of the ARM Architecture Reference Manual, for ARMv8-A architecture profile.

Configuration

PMPCSR is in the Core power domain.

Fields in this register reset to architecturally UNKNOWN values. These apply only on a Cold reset. The register is not affected by a Warm reset and is not affected by an External debug reset.

Implemented only when ARMv8.2-PCSample is implemented.

Note

Before ARMv8.2, the PC Sample-based Profiling Extension can be implemented in the external debug register space, as indicated by the value of EDDEVID.PCSample.

Support for 64-bit atomic reads is IMPLEMENTATION DEFINED. If 64-bit atomic reads are implemented, a 64-bit read of PMPCSR has the same side-effect as a 32-bit read of PMCSR[31:0] followed by a 32-bit read of PMPCSR[63:32], returning the combined value. For example, if the PE is in Debug state then a 64-bit atomic read returns bits[31:0] == 0xFFFFFFFF and bits[63:32] UNKNOWN.

This register is introduced in ARMv8.2.

Attributes

PMPCSR is a 64-bit register.

Field descriptions

The PMPCSR bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
NSEL00000PC Sample[55:32]
PC Sample[31:1]PC Sample[31:0]SBZ
313029282726252423222120191817161514131211109876543210

NS, bit [63]

Non-secure state sample. Indicates the Security state that is associated with the most recent PMPCSR sample or, when it is read as a single atomic 64-bit read, the current PMPCSR sample.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

EL, bits [62:61]

Exception level status sample. Indicates the Exception level that is associated with the most recent PMPCSR sample or, when it is read as a single atomic 64-bit read, the current PMPCSR sample.

ELMeaning
00

Sample is from EL0.

01

Sample is from EL1.

10

Sample is from EL2.

11

Sample is from EL3.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bits [60:56]

Reserved, RES0.

PC Sample[55:32], bits [55:32]

Bits[55:32] of the sampled instruction address value. The translation regime that PMPCSR samples can be determined from PMPCSR.{NS,EL}.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

PC Sample[31:10], bits [31:10]

Bits[31:10] of the sampled instruction address value. The translation regime that PMPCSR samples can be determined from PMPCSR.{NS,EL}.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

SBZ, bit [0]

Reserved, SBZ.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

For a read of PMPCSR[31:0] from the memory-mapped interface, if PMLSR.SLK == 1, meaning the OPTIONAL Software Lock is locked, then the access has no side-effects.

In any other cases, a read of PMPCSR[31:0] has the side-effect of indirectly writing to PMPCSR[63:32], PMCID1SR, PMCID2SR, and PMVIDSR:

Accessing the PMPCSR

PMPCSR[31:0] can be accessed through the external debug interface:

ComponentOffset
PMU0x200
PMU0x220

PMPCSR[63:32] can be accessed through the external debug interface:

ComponentOffset
PMU0x204
PMU0x224



28/0907/2017 0816:2440

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