ICC_HPPIR1, Interrupt Controller Highest Priority Pending Interrupt Register 1

The ICC_HPPIR1 characteristics are:

Purpose

Indicates the highest priority pending Group 1 interrupt on the CPU interface.

This register is part of:

Configuration

There is one instance of this register that is used in both Secure and Non-secure states.

AArch32 System register ICC_HPPIR1 performs the same function as AArch64 System register ICC_HPPIR1_EL1.

Attributes

ICC_HPPIR1 is a 32-bit register.

Field descriptions

The ICC_HPPIR1 bit assignments are:

313029282726252423222120191817161514131211109876543210
00000000INTID

Bits [31:24]

Reserved, RES0.

INTID, bits [23:0]

The INTID of the highest priority pending interrupt, if that interrupt is observable at the current Security state and Exception level.

If the highest priority pending interrupt is not observable, this field contains a special INTID to indicate the reason. This special INTID can take the value 1023 only. See Special INTIDs, for more information.

This field has either 16 or 24 bits implemented. The number of implemented bits can be found in ICC_CTLR.IDbits and ICC_MCTLR.IDbits. If only 16 bits are implemented, bits [23:16] of this register are RES0.

Accessing the ICC_HPPIR1

This register can be read using MRC with the following syntax:

MRC <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 0, <Rt>, c12, c12, 2000010110011111100

When HCR.IMO is set to 1, execution of this encoding at Non-secure EL1 results in an access to ICV_HPPIR1.

Accessibility

The register is accessible as follows:

Control Accessibility
FMOIMOTGENSEL0EL1EL2EL3
xxx0 - RO n/a RO
xx11 - n/a RORO
x001 - RORORO
x101 - ICV_HPPIR1 RORO

This table applies to all instructions that can access this register.

ICC_HPPIR1 is only accessible at Non-secure EL1 when HCR.IMO is set to 0.

Note

When HCR.IMO is set to 1, at Non-secure EL1, the instruction encoding used to access ICC_HPPIR1 results in an access to ICV_HPPIR1.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :

When SCR_EL3.NS==1 :

When EL3 is implemented and is using AArch32 :

When EL3 is implemented and is using AArch32 and SCR_EL3.NS==1 :

When EL3 is implemented and is using AArch64 and SCR_EL3.NS==0 :

When EL3 is implemented and is using AArch64 :

When EL3 is implemented and is using AArch64 and SCR_EL3.NS==1 :




28/09/2017 08:24

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