SysReg_v83A_xml-00bet4 (old)htmldiff from-SysReg_v83A_xml-00bet4(new) SysReg_v83A_xml-00bet5

External register index by offset

Below are indexes for external registers in the following blocks:

In the CTIPMU block:

Offset Name Description
0xFD0PMPIDR4Performance Monitors Peripheral Identification Register 4
0xFE0PMPIDR0Performance Monitors Peripheral Identification Register 0
0xFE4PMPIDR1Performance Monitors Peripheral Identification Register 1
0xFE8PMPIDR2Performance Monitors Peripheral Identification Register 2
0xFECPMPIDR3Performance Monitors Peripheral Identification Register 3
0xFF0PMCIDR0Performance Monitors Component Identification Register 0
0xFF4PMCIDR1Performance Monitors Component Identification Register 1
0xFF8PMCIDR2Performance Monitors Component Identification Register 2
0xFFCPMCIDR3Performance Monitors Component Identification Register 3
0x000 + 8n CTICONTROL PMEVCNTR<n>_EL0CTIPerformance ControlMonitors registerEvent Count Registers
0x0100x0F8 CTIINTACK PMCCNTR_EL0[31:0]CTIPerformance OutputMonitors TriggerCycle Acknowledge registerCounter
0x0140x0FC CTIAPPSET PMCCNTR_EL0[63:32]CTIPerformance ApplicationMonitors TriggerCycle Set registerCounter
0x0180x200 CTIAPPCLEAR PMPCSR[31:0]CTIProgram ApplicationCounter TriggerSample Clear registerRegister
0x01C0x204 CTIAPPPULSE PMPCSR[63:32]CTIProgram ApplicationCounter PulseSample registerRegister
0x020 + 4n0x208 CTIINEN<n> PMCID1SRCTICONTEXTIDR_EL1 InputSample Trigger to Output Channel Enable registersRegister
0x0A0 + 4n0x20C CTIOUTEN<n> PMVIDSRCTIVMID InputSample Channel to Output Trigger Enable registersRegister
0x1300x220 CTITRIGINSTATUS PMPCSR[31:0]CTIProgram TriggerCounter InSample Status registerRegister
0x1340x224 CTITRIGOUTSTATUS PMPCSR[63:32]CTIProgram TriggerCounter OutSample Status registerRegister
0x1380x228 CTICHINSTATUS PMCID1SRCTICONTEXTIDR_EL1 ChannelSample In Status registerRegister
0x13C0x22C CTICHOUTSTATUS PMCID2SRCTICONTEXTIDR_EL2 ChannelSample Out Status registerRegister
0x1400x400 + 4n CTIGATE PMEVTYPER<n>_EL0CTIPerformance ChannelMonitors GateEvent EnableType registerRegisters
0x1440x47C ASICCTL PMCCFILTR_EL0CTIPerformance ExternalMonitors MultiplexerCycle ControlCounter registerFilter Register
0xF000xC00 CTIITCTRL PMCNTENSET_EL0CTIPerformance IntegrationMonitors modeCount ControlEnable Set register
0xFA00xC20 CTICLAIMSET PMCNTENCLR_EL0CTIPerformance ClaimMonitors TagCount SetEnable Clear register
0xFA40xC40 CTICLAIMCLR PMINTENSET_EL1CTIPerformance ClaimMonitors TagInterrupt ClearEnable Set register
0xFA80xC60 CTIDEVAFF0 PMINTENCLR_EL1CTIPerformance DeviceMonitors AffinityInterrupt Enable Clear register 0
0xFAC0xC80 CTIDEVAFF1 PMOVSCLR_EL0CTIPerformance DeviceMonitors AffinityOverflow Flag Status Clear register 1
0xFB00xCA0 CTILAR PMSWINC_EL0CTIPerformance LockMonitors AccessSoftware RegisterIncrement register
0xFB40xCC0 CTILSR PMOVSSET_EL0CTIPerformance LockMonitors Overflow Flag Status RegisterSet register
0xFB80xE00 CTIAUTHSTATUS PMCFGRCTIPerformance AuthenticationMonitors StatusConfiguration registerRegister
0xFBC0xE04 CTIDEVARCH PMCR_EL0CTIPerformance DeviceMonitors ArchitectureControl registerRegister
0xFC00xE20 CTIDEVID2 PMCEID0CTIPerformance DeviceMonitors IDCommon Event Identification register 20
0xFC40xE24 CTIDEVID1 PMCEID1CTIPerformance DeviceMonitors IDCommon Event Identification register 1
0xFC80xE28 CTIDEVID PMCEID2CTIPerformance DeviceMonitors IDCommon Event Identification register 02
0xFCC0xE2C CTIDEVTYPE PMCEID3CTIPerformance DeviceMonitors TypeCommon Event Identification register 3
0xFD00xF00 CTIPIDR4 PMITCTRLCTIPerformance PeripheralMonitors IdentificationIntegration Registermode 4Control register
0xFE00xFA8 CTIPIDR0 PMDEVAFF0CTIPerformance PeripheralMonitors IdentificationDevice RegisterAffinity register 0
0xFE40xFAC CTIPIDR1 PMDEVAFF1CTIPerformance PeripheralMonitors IdentificationDevice RegisterAffinity register 1
0xFE80xFB0 CTIPIDR2 PMLARCTIPerformance PeripheralMonitors IdentificationLock Access Register 2
0xFEC0xFB4 CTIPIDR3 PMLSRCTIPerformance PeripheralMonitors IdentificationLock Status Register 3
0xFF00xFB8 CTICIDR0 PMAUTHSTATUSCTIPerformance ComponentMonitors IdentificationAuthentication RegisterStatus 0register
0xFF40xFBC CTICIDR1 PMDEVARCHCTIPerformance ComponentMonitors IdentificationDevice RegisterArchitecture 1register
0xFF80xFC8 CTICIDR2 PMDEVIDCTIPerformance ComponentMonitors IdentificationDevice RegisterID 2register
0xFFC0xFCC CTICIDR3 PMDEVTYPECTIPerformance ComponentMonitors IdentificationDevice RegisterType 3register

In the Debug block:

Offset Name Description
0x020 EDESR External Debug Event Status Register
0x024 EDECR External Debug Execution Control Register
0x030 EDWAR[31:0] External Debug Watchpoint Address Register
0x034 EDWAR[63:32] External Debug Watchpoint Address Register
0x080 DBGDTRRX_EL0 Debug Data Transfer Register, Receive
0x084 EDITR External Debug Instruction Transfer Register
0x088 EDSCR External Debug Status and Control Register
0x08C DBGDTRTX_EL0 Debug Data Transfer Register, Transmit
0x090 EDRCR External Debug Reserve Control Register
0x094 EDACR External Debug Auxiliary Control Register
0x098 EDECCR External Debug Exception Catch Control Register
0x0A0 EDPCSR[31:0] External Debug Program Counter Sample Register
0x0A4 EDCIDSR External Debug Context ID Sample Register
0x0A8 EDVIDSR External Debug Virtual Context Sample Register
0x0AC EDPCSR[63:32] External Debug Program Counter Sample Register
0x300 OSLAR_EL1 OS Lock Access Register
0x310 EDPRCR External Debug Power/Reset Control Register
0x314 EDPRSR External Debug Processor Status Register
0x400 + 16n DBGBVR<n>_EL1[31:0] Debug Breakpoint Value Registers
0x404 + 16n DBGBVR<n>_EL1[63:32] Debug Breakpoint Value Registers
0x408 + 16n DBGBCR<n>_EL1 Debug Breakpoint Control Registers
0x800 + 16n DBGWVR<n>_EL1[31:0] Debug Watchpoint Value Registers
0x804 + 16n DBGWVR<n>_EL1[63:32] Debug Watchpoint Value Registers
0x808 + 16n DBGWCR<n>_EL1 Debug Watchpoint Control Registers
0xD00 MIDR_EL1 Main ID Register
0xD20 EDPFR[31:0] External Debug Processor Feature Register
0xD24 EDPFR[63:32] External Debug Processor Feature Register
0xD28 EDDFR[31:0] External Debug Feature Register
0xD2C EDDFR[63:32] External Debug Feature Register
0xD60 EDAA32PFR External Debug AArch32 Processor Feature Register
0xF00 EDITCTRL External Debug Integration mode Control register
0xFA0 DBGCLAIMSET_EL1 Debug Claim Tag Set register
0xFA4 DBGCLAIMCLR_EL1 Debug Claim Tag Clear register
0xFA8 EDDEVAFF0 External Debug Device Affinity register 0
0xFAC EDDEVAFF1 External Debug Device Affinity register 1
0xFB0 EDLAR External Debug Lock Access Register
0xFB4 EDLSR External Debug Lock Status Register
0xFB8 DBGAUTHSTATUS_EL1 Debug Authentication Status register
0xFBC EDDEVARCH External Debug Device Architecture register
0xFC0 EDDEVID2 External Debug Device ID register 2
0xFC4 EDDEVID1 External Debug Device ID register 1
0xFC8 EDDEVID External Debug Device ID register 0
0xFCC EDDEVTYPE External Debug Device Type register
0xFD0 EDPIDR4 External Debug Peripheral Identification Register 4
0xFE0 EDPIDR0 External Debug Peripheral Identification Register 0
0xFE4 EDPIDR1 External Debug Peripheral Identification Register 1
0xFE8 EDPIDR2 External Debug Peripheral Identification Register 2
0xFEC EDPIDR3 External Debug Peripheral Identification Register 3
0xFF0 EDCIDR0 External Debug Component Identification Register 0
0xFF4 EDCIDR1 External Debug Component Identification Register 1
0xFF8 EDCIDR2 External Debug Component Identification Register 2
0xFFC EDCIDR3 External Debug Component Identification Register 3

In the GIC CPU interface block:

Offset Name Description
0x0000 GICC_CTLR CPU Interface Control Register
0x0004 GICC_PMR CPU Interface Priority Mask Register
0x0008 GICC_BPR CPU Interface Binary Point Register
0x000C GICC_IAR CPU Interface Interrupt Acknowledge Register
0x0010 GICC_EOIR CPU Interface End Of Interrupt Register
0x0014 GICC_RPR CPU Interface Running Priority Register
0x0018 GICC_HPPIR CPU Interface Highest Priority Pending Interrupt Register
0x001C GICC_ABPR CPU Interface Aliased Binary Point Register
0x0020-0x003C GICC_AIAR CPU Interface Aliased Interrupt Acknowledge Register
0x0024 GICC_AEOIR CPU Interface Aliased End Of Interrupt Register
0x0028 GICC_AHPPIR CPU Interface Aliased Highest Priority Pending Interrupt Register
0x002C GICC_STATUSR CPU Interface Status Register
0x00D0 + 4n GICC_APR<n> CPU Interface Active Priorities Registers
0x00E0 + 4n GICC_NSAPR<n> CPU Interface Non-secure Active Priorities Registers
0x00FC GICC_IIDR CPU Interface Identification Register
0x1000 GICC_DIR CPU Interface Deactivate Interrupt Register

In the GIC DistributorVirtual interface control block:

Offset Name Description
0x0000 GICD_CTLR GICH_HCRDistributorHypervisor Control Register
0x0004 GICD_TYPER GICH_VTRInterrupt ControllerVirtual Type Register
0x0008 GICD_IIDR GICH_VMCRDistributorVirtual ImplementerMachine IdentificationControl Register
0x0010 GICD_STATUSR GICH_MISRErrorMaintenance ReportingInterrupt Status Register
0x00400x0020 GICD_SETSPI_NSR GICH_EISRSetEnd Non-secureInterrupt SPI PendingStatus Register
0x00480x0030 GICD_CLRSPI_NSR GICH_ELRSRClearEmpty Non-secureList SPIRegister PendingStatus Register
0x00500x00F0 + 4n GICD_SETSPI_SR GICH_APR<n>SetActive SecurePriorities SPI Pending RegisterRegisters
0x00580x0100 + 4n GICD_CLRSPI_SR GICH_LR<n>ClearList Secure SPI Pending RegisterRegisters
0x0080 + 4n GICD_IGROUPR<n> Interrupt Group Registers
0x0100 + 4n GICD_ISENABLER<n> Interrupt Set-Enable Registers
0x0180 + 4n GICD_ICENABLER<n> Interrupt Clear-Enable Registers
0x0200 + 4n GICD_ISPENDR<n> Interrupt Set-Pending Registers
0x0280 + 4n GICD_ICPENDR<n> Interrupt Clear-Pending Registers
0x0300 + 4n GICD_ISACTIVER<n> Interrupt Set-Active Registers
0x0380 + 4n GICD_ICACTIVER<n> Interrupt Clear-Active Registers
0x0400 + 4n GICD_IPRIORITYR<n> Interrupt Priority Registers
0x0800 + 4n GICD_ITARGETSR<n> Interrupt Processor Targets Registers
0x0C00 + 4n GICD_ICFGR<n> Interrupt Configuration Registers
0x0D00 + 4n GICD_IGRPMODR<n> Interrupt Group Modifier Registers
0x0E00 + 4n GICD_NSACR<n> Non-secure Access Control Registers
0x0F00 GICD_SGIR Software Generated Interrupt Register
0x0F10 + 4n GICD_CPENDSGIR<n> SGI Clear-Pending Registers
0x0F20 + 4n GICD_SPENDSGIR<n> SGI Set-Pending Registers
0x6000 + 8n GICD_IROUTER<n> Interrupt Routing Registers

In the GIC ITS controlTimer block:

Offset Name Description
0x0000 GITS_CTLR ITS Control Register
0x0004 GITS_IIDR ITS Identification Register
0x0008-0x000C GITS_TYPER ITS Type Register
0x0080-0x0084 GITS_CBASER ITS Command Queue Descriptor
0x0088-0x008C GITS_CWRITER ITS Write Register
0x0090-0x0094 GITS_CREADR ITS Read Register
0x0100 + 8n GITS_BASER<n> ITS Translation Table Descriptors
FrameOffsetNameDescription
CNTControlBase0x000CNTCRCounter Control Register
CNTControlBase0x004CNTSRCounter Status Register
CNTControlBase0x008CNTCV[31:0]Counter Count Value register
CNTControlBase0x00CCNTCV[63:32]Counter Count Value register
CNTControlBase0x020CNTFID0Counter Frequency ID
CNTControlBase0x020 + 4nCNTFID<n>Counter Frequency IDs
CNTControlBase0xFD0 + 4nCounterID<n>Counter ID registers
CNTReadBase0x000CNTCV[31:0]Counter Count Value register
CNTReadBase0x004CNTCV[63:32]Counter Count Value register
CNTReadBase0xFD0 + 4nCounterID<n>Counter ID registers
CNTBaseN0x000CNTPCT[31:0]Counter-timer Physical Count
CNTBaseN0x004CNTPCT[63:32]Counter-timer Physical Count
CNTBaseN0x008CNTVCT[31:0]Counter-timer Virtual Count
CNTBaseN0x00CCNTVCT[63:32]Counter-timer Virtual Count
CNTBaseN0x010CNTFRQCounter-timer Frequency
CNTBaseN0x014CNTEL0ACRCounter-timer EL0 Access Control Register
CNTBaseN0x018CNTVOFF[31:0]Counter-timer Virtual Offset
CNTBaseN0x01CCNTVOFF[63:32]Counter-timer Virtual Offset
CNTBaseN0x020CNTP_CVAL[31:0]Counter-timer Physical Timer CompareValue
CNTBaseN0x024CNTP_CVAL[63:32]Counter-timer Physical Timer CompareValue
CNTBaseN0x028CNTP_TVALCounter-timer Physical Timer TimerValue
CNTBaseN0x02CCNTP_CTLCounter-timer Physical Timer Control
CNTBaseN0x030CNTV_CVAL[31:0]Counter-timer Virtual Timer CompareValue
CNTBaseN0x034CNTV_CVAL[63:32]Counter-timer Virtual Timer CompareValue
CNTBaseN0x038CNTV_TVALCounter-timer Virtual Timer TimerValue
CNTBaseN0x03CCNTV_CTLCounter-timer Virtual Timer Control
CNTBaseN0xFD0 + 4nCounterID<n>Counter ID registers
CNTEL0BaseN0x000CNTPCT[31:0]Counter-timer Physical Count
CNTEL0BaseN0x004CNTPCT[63:32]Counter-timer Physical Count
CNTEL0BaseN0x008CNTVCT[31:0]Counter-timer Virtual Count
CNTEL0BaseN0x00CCNTVCT[63:32]Counter-timer Virtual Count
CNTEL0BaseN0x010CNTFRQCounter-timer Frequency
CNTEL0BaseN0x020CNTP_CVAL[31:0]Counter-timer Physical Timer CompareValue
CNTEL0BaseN0x024CNTP_CVAL[63:32]Counter-timer Physical Timer CompareValue
CNTEL0BaseN0x028CNTP_TVALCounter-timer Physical Timer TimerValue
CNTEL0BaseN0x02CCNTP_CTLCounter-timer Physical Timer Control
CNTEL0BaseN0x030CNTV_CVAL[31:0]Counter-timer Virtual Timer CompareValue
CNTEL0BaseN0x034CNTV_CVAL[63:32]Counter-timer Virtual Timer CompareValue
CNTEL0BaseN0x038CNTV_TVALCounter-timer Virtual Timer TimerValue
CNTEL0BaseN0x03CCNTV_CTLCounter-timer Virtual Timer Control
CNTEL0BaseN0xFD0 + 4nCounterID<n>Counter ID registers
CNTCTLBase0x000CNTFRQCounter-timer Frequency
CNTCTLBase0x004CNTNSARCounter-timer Non-secure Access Register
CNTCTLBase0x008CNTTIDRCounter-timer Timer ID Register
CNTCTLBase0x040 + 4nCNTACR<n>Counter-timer Access Control Registers
CNTCTLBase0x080 + 8nCNTVOFF<n>[31:0]Counter-timer Virtual Offsets
CNTCTLBase0x084 + 8nCNTVOFF<n>[63:32]Counter-timer Virtual Offsets
CNTCTLBase0xFD0 + 4nCounterID<n>Counter ID registers

In the GIC ITS translationDebug block:

Offset Name Description
0x024EDECRExternal Debug Execution Control Register
0x030EDWAR[31:0]External Debug Watchpoint Address Register
0x034EDWAR[63:32]External Debug Watchpoint Address Register
0x080DBGDTRRX_EL0Debug Data Transfer Register, Receive
0x084EDITRExternal Debug Instruction Transfer Register
0x088EDSCRExternal Debug Status and Control Register
0x08CDBGDTRTX_EL0Debug Data Transfer Register, Transmit
0x090EDRCRExternal Debug Reserve Control Register
0x094EDACRExternal Debug Auxiliary Control Register
0x098EDECCRExternal Debug Exception Catch Control Register
0x0A0EDPCSR[31:0]External Debug Program Counter Sample Register
0x0A4EDCIDSRExternal Debug Context ID Sample Register
0x0A8EDVIDSRExternal Debug Virtual Context Sample Register
0x0ACEDPCSR[63:32]External Debug Program Counter Sample Register
0x300OSLAR_EL1OS Lock Access Register
0x310EDPRCRExternal Debug Power/Reset Control Register
0x314EDPRSRExternal Debug Processor Status Register
0x400 + 16nDBGBVR<n>_EL1[31:0]Debug Breakpoint Value Registers
0x404 + 16nDBGBVR<n>_EL1[63:32]Debug Breakpoint Value Registers
0x408 + 16nDBGBCR<n>_EL1Debug Breakpoint Control Registers
0x800 + 16nDBGWVR<n>_EL1[31:0]Debug Watchpoint Value Registers
0x804 + 16nDBGWVR<n>_EL1[63:32]Debug Watchpoint Value Registers
0x808 + 16nDBGWCR<n>_EL1Debug Watchpoint Control Registers
0xD00MIDR_EL1Main ID Register
0xD20EDPFR[31:0]External Debug Processor Feature Register
0xD24EDPFR[63:32]External Debug Processor Feature Register
0xD28EDDFR[31:0]External Debug Feature Register
0xD2CEDDFR[63:32]External Debug Feature Register
0xD60EDAA32PFRExternal Debug AArch32 Processor Feature Register
0xF00EDITCTRLExternal Debug Integration mode Control register
0xFA0DBGCLAIMSET_EL1Debug Claim Tag Set register
0xFA4DBGCLAIMCLR_EL1Debug Claim Tag Clear register
0xFA8EDDEVAFF0External Debug Device Affinity register 0
0xFACEDDEVAFF1External Debug Device Affinity register 1
0xFB0EDLARExternal Debug Lock Access Register
0xFB4EDLSRExternal Debug Lock Status Register
0xFB8DBGAUTHSTATUS_EL1Debug Authentication Status register
0xFBCEDDEVARCHExternal Debug Device Architecture register
0xFC0EDDEVID2External Debug Device ID register 2
0xFC4EDDEVID1External Debug Device ID register 1
0xFC8EDDEVIDExternal Debug Device ID register 0
0xFCCEDDEVTYPEExternal Debug Device Type register
0xFD0EDPIDR4External Debug Peripheral Identification Register 4
0xFE0EDPIDR0External Debug Peripheral Identification Register 0
0xFE4EDPIDR1External Debug Peripheral Identification Register 1
0xFE8EDPIDR2External Debug Peripheral Identification Register 2
0xFECEDPIDR3External Debug Peripheral Identification Register 3
0xFF0EDCIDR0External Debug Component Identification Register 0
0xFF4EDCIDR1External Debug Component Identification Register 1
0xFF8EDCIDR2External Debug Component Identification Register 2
0xFFCEDCIDR3External Debug Component Identification Register 3
0x00400x020 GITS_TRANSLATER EDESRITSExternal TranslationDebug Event Status Register

In the GIC Redistributor block:

Frame Offset Name Description
RD_base 0x0000 GICR_CTLR Redistributor Control Register
RD_base 0x0004 GICR_IIDR Redistributor Implementer Identification Register
RD_base 0x0008-0x000C GICR_TYPER Redistributor Type Register
RD_base 0x0010 GICR_STATUSR Error Reporting Status Register
RD_base 0x0014 GICR_WAKER Redistributor Wake Register
RD_base 0x0040-0x0044 GICR_SETLPIR Set LPI Pending Register
RD_base 0x0048-0x004C GICR_CLRLPIR Clear LPI Pending Register
RD_base 0x0070-0x0074 GICR_PROPBASER Redistributor Properties Base Address Register
RD_base 0x0078-0x007C GICR_PENDBASER Redistributor LPI Pending Table Base Address Register
RD_base 0x00A0-0x00A4 GICR_INVLPIR Redistributor Invalidate LPI Register
RD_base 0x00B0-0x00B4 GICR_INVALLR Redistributor Invalidate All Register
RD_base 0x00C0-0x00C4 GICR_SYNCR Redistributor Synchronize Register
SGI_baseVLPI_base0x00800x0070-0x0074 GICR_IGROUPR0 GICR_VPROPBASERInterruptVirtual GroupRedistributor Properties Base Address Register 0
SGI_baseVLPI_base0x01000x0078-0x007C GICR_ISENABLER0 GICR_VPENDBASERInterruptVirtual Set-EnableRedistributor LPI Pending Table Base Address Register 0
SGI_base 0x01800x0080 GICR_ICENABLER0 GICR_IGROUPR0 Interrupt Clear-EnableGroup Register 0
SGI_base 0x02000x0100 GICR_ISPENDR0 GICR_ISENABLER0 Interrupt Set-PendingSet-Enable Register 0
SGI_base 0x02800x0180 GICR_ICPENDR0 GICR_ICENABLER0 Interrupt Clear-PendingClear-Enable Register 0
SGI_base 0x03000x0200 GICR_ISACTIVER0 GICR_ISPENDR0 Interrupt Set-ActiveSet-Pending Register 0
SGI_base 0x03800x0280 GICR_ICACTIVER0 GICR_ICPENDR0 Interrupt Clear-ActiveClear-Pending Register 0
SGI_base 0x0400 + 4n0x0300 GICR_IPRIORITYR<n> GICR_ISACTIVER0 Interrupt PrioritySet-Active RegistersRegister 0
SGI_base 0x0C000x0380 GICR_ICFGR0 GICR_ICACTIVER0 Interrupt ConfigurationClear-Active Register 0
SGI_base 0x0C040x0400 + 4n GICR_ICFGR1 GICR_IPRIORITYR<n> Interrupt ConfigurationPriority Register 1Registers
SGI_base 0x0D000x0C00 GICR_IGRPMODR0 GICR_ICFGR0 Interrupt Group ModifierConfiguration Register 0
SGI_base 0x0E000x0C04 GICR_NSACR GICR_ICFGR1Non-secureInterrupt AccessConfiguration ControlRegister Register1
VLPI_baseSGI_base0x0070-0x00740x0D00 GICR_VPROPBASER GICR_IGRPMODR0VirtualInterrupt RedistributorGroup PropertiesModifier BaseRegister Address Register0
VLPI_baseSGI_base0x0078-0x007C0x0E00 GICR_VPENDBASER GICR_NSACRVirtualNon-secure RedistributorAccess LPI Pending Table Base AddressControl Register

In the GIC Virtual CPU interface block:

Offset Name Description
0x0000 GICV_CTLR Virtual Machine Control Register
0x0004 GICV_PMR Virtual Machine Priority Mask Register
0x0008 GICV_BPR Virtual Machine Binary Point Register
0x000C GICV_IAR Virtual Machine Interrupt Acknowledge Register
0x0010 GICV_EOIR Virtual Machine End Of Interrupt Register
0x0014 GICV_RPR Virtual Machine Running Priority Register
0x0018 GICV_HPPIR Virtual Machine Highest Priority Pending Interrupt Register
0x001C GICV_ABPR Virtual Machine Aliased Binary Point Register
0x0020 GICV_AIAR Virtual Machine Aliased Interrupt Acknowledge Register
0x0024 GICV_AEOIR Virtual Machine Aliased End Of Interrupt Register
0x0028 GICV_AHPPIR Virtual Machine Aliased Highest Priority Pending Interrupt Register
0x002C GICV_STATUSR Virtual Machine Error Reporting Status Register
0x00D0 + 4n GICV_APR<n> Virtual Machine Active Priorities Registers
0x00FC GICV_IIDR Virtual Machine CPU Interface Identification Register
0x1000 GICV_DIR Virtual Machine Deactivate Interrupt Register

In the GIC Virtual interfaceITS control block:

Offset Name Description
0x0000 GICH_HCR GITS_CTLRHypervisorITS Control Register
0x0004 GICH_VTR GITS_IIDRVirtualITS TypeIdentification Register
0x00080x0008-0x000C GICH_VMCR GITS_TYPERVirtualITS Machine ControlType Register
0x00100x0080-0x0084 GICH_MISR GITS_CBASERMaintenanceITS InterruptCommand StatusQueue RegisterDescriptor
0x00200x0088-0x008C GICH_EISR GITS_CWRITEREndITS Interrupt StatusWrite Register
0x00300x0090-0x0094 GICH_ELRSR GITS_CREADREmptyITS List Register StatusRead Register
0x00F00x0100 + 4n8n GICH_APR<n> GITS_BASER<n>ActiveITS PrioritiesTranslation RegistersTable Descriptors
0x0100 + 4n GICH_LR<n> List Registers

In the PMUGIC ITS translation block:

Offset Name Description
0x000 + 8n0x0040 PMEVCNTR<n>_EL0 GITS_TRANSLATERPerformanceITS MonitorsTranslation Event Count RegistersRegister
0x0F8 PMCCNTR_EL0[31:0] Performance Monitors Cycle Counter
0x0FC PMCCNTR_EL0[63:32] Performance Monitors Cycle Counter
0x200 PMPCSR[31:0] Program Counter Sample Register
0x204 PMPCSR[63:32] Program Counter Sample Register
0x208 PMCID1SR CONTEXTIDR_EL1 Sample Register
0x20C PMVIDSR VMID Sample Register
0x220 PMPCSR[31:0] Program Counter Sample Register
0x224 PMPCSR[63:32] Program Counter Sample Register
0x228 PMCID1SR CONTEXTIDR_EL1 Sample Register
0x22C PMCID2SR CONTEXTIDR_EL2 Sample Register
0x400 + 4n PMEVTYPER<n>_EL0 Performance Monitors Event Type Registers
0x47C PMCCFILTR_EL0 Performance Monitors Cycle Counter Filter Register
0xC00 PMCNTENSET_EL0 Performance Monitors Count Enable Set register
0xC20 PMCNTENCLR_EL0 Performance Monitors Count Enable Clear register
0xC40 PMINTENSET_EL1 Performance Monitors Interrupt Enable Set register
0xC60 PMINTENCLR_EL1 Performance Monitors Interrupt Enable Clear register
0xC80 PMOVSCLR_EL0 Performance Monitors Overflow Flag Status Clear register
0xCA0 PMSWINC_EL0 Performance Monitors Software Increment register
0xCC0 PMOVSSET_EL0 Performance Monitors Overflow Flag Status Set register
0xE00 PMCFGR Performance Monitors Configuration Register
0xE04 PMCR_EL0 Performance Monitors Control Register
0xE20 PMCEID0 Performance Monitors Common Event Identification register 0
0xE24 PMCEID1 Performance Monitors Common Event Identification register 1
0xE28 PMCEID2 Performance Monitors Common Event Identification register 2
0xE2C PMCEID3 Performance Monitors Common Event Identification register 3
0xF00 PMITCTRL Performance Monitors Integration mode Control register
0xFA8 PMDEVAFF0 Performance Monitors Device Affinity register 0
0xFAC PMDEVAFF1 Performance Monitors Device Affinity register 1
0xFB0 PMLAR Performance Monitors Lock Access Register
0xFB4 PMLSR Performance Monitors Lock Status Register
0xFB8 PMAUTHSTATUS Performance Monitors Authentication Status register
0xFBC PMDEVARCH Performance Monitors Device Architecture register
0xFC8 PMDEVID Performance Monitors Device ID register
0xFCC PMDEVTYPE Performance Monitors Device Type register
0xFD0 PMPIDR4 Performance Monitors Peripheral Identification Register 4
0xFE0 PMPIDR0 Performance Monitors Peripheral Identification Register 0
0xFE4 PMPIDR1 Performance Monitors Peripheral Identification Register 1
0xFE8 PMPIDR2 Performance Monitors Peripheral Identification Register 2
0xFEC PMPIDR3 Performance Monitors Peripheral Identification Register 3
0xFF0 PMCIDR0 Performance Monitors Component Identification Register 0
0xFF4 PMCIDR1 Performance Monitors Component Identification Register 1
0xFF8 PMCIDR2 Performance Monitors Component Identification Register 2
0xFFC PMCIDR3 Performance Monitors Component Identification Register 3

In the TimerCTI block:

Frame Offset Name Description
CNTBaseN 0x000 CNTPCT[31:0] CTICONTROLCounter-timerCTI PhysicalControl Countregister
CNTBaseN0x010 0x004 CNTPCT[63:32] CTIINTACKCounter-timerCTI PhysicalOutput CountTrigger Acknowledge register
CNTBaseN0x014 0x008 CNTVCT[31:0] CTIAPPSETCounter-timerCTI VirtualApplication CountTrigger Set register
CNTBaseN0x018 0x00C CNTVCT[63:32] CTIAPPCLEARCounter-timerCTI VirtualApplication CountTrigger Clear register
CNTBaseN0x01C 0x010 CNTFRQ CTIAPPPULSECounter-timerCTI FrequencyApplication Pulse register
CNTBaseN0x020 + 4n 0x014 CNTEL0ACR CTIINEN<n>Counter-timerCTI EL0Input AccessTrigger Controlto RegisterOutput Channel Enable registers
CNTBaseN0x0A0 + 4n 0x018 CNTVOFF[31:0] CTIOUTEN<n>Counter-timerCTI VirtualInput OffsetChannel to Output Trigger Enable registers
CNTBaseN0x130 0x01C CNTVOFF[63:32] CTITRIGINSTATUSCounter-timerCTI VirtualTrigger OffsetIn Status register
CNTBaseN0x134 0x020 CNTP_CVAL[31:0] CTITRIGOUTSTATUSCounter-timerCTI PhysicalTrigger TimerOut CompareValueStatus register
CNTBaseN0x138 0x024 CNTP_CVAL[63:32] CTICHINSTATUSCounter-timerCTI PhysicalChannel TimerIn CompareValueStatus register
CNTBaseN0x13C 0x028 CNTP_TVAL CTICHOUTSTATUSCounter-timerCTI PhysicalChannel TimerOut TimerValueStatus register
CNTBaseN0x140 0x02C CNTP_CTL CTIGATECounter-timerCTI PhysicalChannel TimerGate ControlEnable register
CNTBaseN0x144 0x030 CNTV_CVAL[31:0] ASICCTLCounter-timerCTI VirtualExternal TimerMultiplexer CompareValueControl register
CNTBaseN0xF00 0x034 CNTV_CVAL[63:32] CTIITCTRLCounter-timerCTI VirtualIntegration Timermode CompareValueControl register
CNTBaseN0xFA0 0x038 CNTV_TVAL CTICLAIMSETCounter-timerCTI VirtualClaim TimerTag TimerValueSet register
CNTBaseN0xFA4 0x03C CNTV_CTL CTICLAIMCLRCounter-timerCTI VirtualClaim TimerTag ControlClear register
CNTBaseN0xFA8 0xFD0 + 4n CounterID<n> CTIDEVAFF0CounterCTI IDDevice registersAffinity register 0
CNTCTLBase0xFAC 0x000 CNTFRQ CTIDEVAFF1Counter-timerCTI FrequencyDevice Affinity register 1
CNTCTLBase0xFB0 0x004 CNTNSAR CTILARCounter-timerCTI Non-secureLock Access Register
CNTCTLBase0xFB4 0x008 CNTTIDR CTILSRCounter-timerCTI TimerLock IDStatus Register
CNTCTLBase0xFB8 0x040 + 4n CNTACR<n> CTIAUTHSTATUSCounter-timerCTI AccessAuthentication ControlStatus Registersregister
CNTCTLBase0xFBC 0x080 + 8n CNTVOFF<n>[31:0] CTIDEVARCHCounter-timerCTI VirtualDevice OffsetsArchitecture register
CNTCTLBase0xFC0 0x084 + 8n CNTVOFF<n>[63:32] CTIDEVID2Counter-timerCTI VirtualDevice OffsetsID register 2
CNTCTLBase0xFC4 0xFD0 + 4n CounterID<n> CTIDEVID1CounterCTI Device ID registersregister 1
CNTControlBase0xFC8 0x000 CNTCR CTIDEVIDCounterCTI ControlDevice RegisterID register 0
CNTControlBase0xFCC 0x004 CNTSR CTIDEVTYPECounterCTI StatusDevice RegisterType register
CNTControlBase0xFD0 0x008 CNTCV[31:0] CTIPIDR4CounterCTI CountPeripheral ValueIdentification registerRegister 4
CNTControlBase0xFE0 0x00C CNTCV[63:32] CTIPIDR0CounterCTI CountPeripheral ValueIdentification registerRegister 0
CNTControlBase0xFE4 0x020 + 4n CNTFID<n> CTIPIDR1CounterCTI FrequencyPeripheral IDs,Identification nRegister > 01
CNTControlBase0xFE8 0x020 CNTFID0 CTIPIDR2CounterCTI FrequencyPeripheral IDIdentification Register 2
CNTControlBase0xFEC 0xFD0 + 4n CounterID<n> CTIPIDR3CounterCTI IDPeripheral registersIdentification Register 3
CNTEL0BaseN0xFF0 0x000 CNTPCT[31:0] CTICIDR0Counter-timerCTI PhysicalComponent CountIdentification Register 0
CNTEL0BaseN0xFF4 0x004 CNTPCT[63:32] CTICIDR1Counter-timerCTI PhysicalComponent CountIdentification Register 1
CNTEL0BaseN0xFF8 0x008 CNTVCT[31:0] CTICIDR2Counter-timerCTI VirtualComponent CountIdentification Register 2
CNTEL0BaseN0xFFC 0x00C CNTVCT[63:32] CTICIDR3Counter-timerCTI VirtualComponent CountIdentification Register 3
CNTEL0BaseN 0x010 CNTFRQ Counter-timer Frequency
CNTEL0BaseN 0x020 CNTP_CVAL[31:0] Counter-timer Physical Timer CompareValue
CNTEL0BaseN 0x024 CNTP_CVAL[63:32] Counter-timer Physical Timer CompareValue
CNTEL0BaseN 0x028 CNTP_TVAL Counter-timer Physical Timer TimerValue
CNTEL0BaseN 0x02C CNTP_CTL Counter-timer Physical Timer Control
CNTEL0BaseN 0x030 CNTV_CVAL[31:0] Counter-timer Virtual Timer CompareValue
CNTEL0BaseN 0x034 CNTV_CVAL[63:32] Counter-timer Virtual Timer CompareValue
CNTEL0BaseN 0x038 CNTV_TVAL Counter-timer Virtual Timer TimerValue
CNTEL0BaseN 0x03C CNTV_CTL Counter-timer Virtual Timer Control
CNTEL0BaseN 0xFD0 + 4n CounterID<n> Counter ID registers
CNTReadBase 0x000 CNTCV[31:0] Counter Count Value register
CNTReadBase 0x004 CNTCV[63:32] Counter Count Value register
CNTReadBase 0xFD0 + 4n CounterID<n> Counter ID registers

In the GIC Distributor block:

OffsetNameDescription
0x0000GICD_CTLRDistributor Control Register
0x0004GICD_TYPERInterrupt Controller Type Register
0x0008GICD_IIDRDistributor Implementer Identification Register
0x0010GICD_STATUSRError Reporting Status Register
0x0040GICD_SETSPI_NSRSet Non-secure SPI Pending Register
0x0048GICD_CLRSPI_NSRClear Non-secure SPI Pending Register
0x0050GICD_SETSPI_SRSet Secure SPI Pending Register
0x0058GICD_CLRSPI_SRClear Secure SPI Pending Register
0x0080 + 4nGICD_IGROUPR<n>Interrupt Group Registers
0x0100 + 4nGICD_ISENABLER<n>Interrupt Set-Enable Registers
0x0180 + 4nGICD_ICENABLER<n>Interrupt Clear-Enable Registers
0x0200 + 4nGICD_ISPENDR<n>Interrupt Set-Pending Registers
0x0280 + 4nGICD_ICPENDR<n>Interrupt Clear-Pending Registers
0x0300 + 4nGICD_ISACTIVER<n>Interrupt Set-Active Registers
0x0380 + 4nGICD_ICACTIVER<n>Interrupt Clear-Active Registers
0x0400 + 4nGICD_IPRIORITYR<n>Interrupt Priority Registers
0x0800 + 4nGICD_ITARGETSR<n>Interrupt Processor Targets Registers
0x0C00 + 4nGICD_ICFGR<n>Interrupt Configuration Registers
0x0D00 + 4nGICD_IGRPMODR<n>Interrupt Group Modifier Registers
0x0E00 + 4nGICD_NSACR<n>Non-secure Access Control Registers
0x0F00GICD_SGIRSoftware Generated Interrupt Register
0x0F10 + 4nGICD_CPENDSGIR<n>SGI Clear-Pending Registers
0x0F20 + 4nGICD_SPENDSGIR<n>SGI Set-Pending Registers
0x6000 + 8nGICD_IROUTER<n>Interrupt Routing Registers

28/0907/2017 0816:4140

Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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