The ISR_EL1 characteristics are:
Shows the pending status of the IRQ, FIQ, or SError interrupt. When executing at EL2, EL3 or secure EL1, this shows the pending status of the physical interrupts. When executing at Non-secure EL1:
This register is part of the Exception and fault handling registers functional group.
AArch64 System register ISR_EL1 is architecturally mapped to AArch32 System register ISR.
ISR_EL1 is a 32-bit register.
The ISR_EL1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | A | I | F | 0 | 0 | 0 | 0 | 0 | 0 |
Reserved, RES0.
SError interrupt pending bit:
A | Meaning |
---|---|
0 |
No pending SError. |
1 |
An SError interrupt is pending. |
IRQ pending bit. Indicates whether an IRQ interrupt is pending:
I | Meaning |
---|---|
0 |
No pending IRQ. |
1 |
An IRQ interrupt is pending. |
FIQ pending bit. Indicates whether an FIQ interrupt is pending.
F | Meaning |
---|---|
0 |
No pending FIQ. |
1 |
An FIQ interrupt is pending. |
Reserved, RES0.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
ISR_EL1 | 11 | 000 | 1100 | 0001 | 000 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
28/09/2017 08:24
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