The FPCR characteristics are:
Controls floating-point behavior.
This register is part of:
The named fields in this register map to the equivalent fields in the AArch32 FPSCR.
It is IMPLEMENTATION DEFINED whether the Len and Stride fields can be programmed to non-zero values, which will cause some AArch32 floating-point instruction encodings to be UNDEFINED, or whether these fields are RAZ.
RW fields in this register reset to architecturally UNKNOWN values.
FPCR is a 32-bit register.
The FPCR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | AHP | DN | FZ | RMode | Stride | FZ16 | Len | IDE | 0 | 0 | IXE | UFE | OFE | DZE | IOE | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Reserved, RES0.
Alternative half-precision control bit:
AHP | Meaning |
---|---|
0 |
IEEE half-precision format selected. |
1 |
Alternative half-precision format selected. |
This bit is only used for conversions between half-precision floating-point and other floating-point formats.
The data-processing instructions added as part of the ARMv8.2-FP16 extension always use the IEEE half-precision format, and ignore the value of this bit.
Default NaN mode control bit:
DN | Meaning |
---|---|
0 |
NaN operands propagate through to the output of a floating-point operation. |
1 |
Any operation involving one or more NaNs returns the Default NaN. |
The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.
Flush-to-zero mode control bit:
FZ | Meaning |
---|---|
0 |
Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard. |
1 |
Flush-to-zero mode enabled. |
The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.
This bit has no effect on half-precision calculations.
Rounding Mode control field. The encoding of this field is:
RMode | Meaning |
---|---|
00 |
Round to Nearest (RN) mode |
01 |
Round towards Plus Infinity (RP) mode |
10 |
Round towards Minus Infinity (RM) mode |
11 |
Round towards Zero (RZ) mode. |
The specified rounding mode is used by both scalar and Advanced SIMD floating-point instructions.
This field has no function in AArch64 state, and non-zero values are ignored during execution in AArch64 state. It is included only for context saving and restoration of the AArch32 FPSCR.Stride field.
When ARMv8.2-FP16 is implemented, flush-to-zero mode control bit on half-precision data-processing instructions:
FZ16 | Meaning |
---|---|
0 |
Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard. |
1 |
Flush-to-zero mode enabled. |
The value of this bit applies to both scalar and Advanced SIMD floating-point half-precision calculations. A half-precision floating-point number that is flushed to zero as a result of the value of the FZ16 bit does not generate an Input Denormal exception.
When ARMv8.2-FP16 is not implemented, this bit is RES0.
Reserved, RES0.
This field has no function in AArch64 state, and non-zero values are ignored during execution in AArch64 state. It is included only for context saving and restoration of the AArch32 FPSCR.Len field.
Input Denormal floating-point exception trap enable. Possible values are:
IDE | Meaning |
---|---|
0 |
Untrapped exception handling selected. If the floating-point exception occurs then the FPSR.IDC bit is set to 1. |
1 |
Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.IDC bit. The trap handling software can decide whether to set the FPSR.IDC bit to 1. |
The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.
If the implementation does not support this exception, this bit is RAZ/WI.
Reserved, RES0.
Inexact floating-point exception trap enable. Possible values are:
IXE | Meaning |
---|---|
0 |
Untrapped exception handling selected. If the floating-point exception occurs then the FPSR.IXC bit is set to 1. |
1 |
Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.IXC bit. The trap handling software can decide whether to set the FPSR.IXC bit to 1. |
The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.
If the implementation does not support this exception, this bit is RAZ/WI.
Underflow floating-point exception trap enable. Possible values are:
UFE | Meaning |
---|---|
0 |
Untrapped exception handling selected. If the floating-point exception occurs then the FPSR.UFC bit is set to 1. |
1 |
Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.UFC bit. The trap handling software can decide whether to set the FPSR.UFC bit to 1. |
The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.
If the implementation does not support this exception, this bit is RAZ/WI.
Overflow floating-point exception trap enable. Possible values are:
OFE | Meaning |
---|---|
0 |
Untrapped exception handling selected. If the floating-point exception occurs then the FPSR.OFC bit is set to 1. |
1 |
Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.OFC bit. The trap handling software can decide whether to set the FPSR.OFC bit to 1. |
The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.
If the implementation does not support this exception, this bit is RAZ/WI.
Divide by Zero floating-point exception trap enable. Possible values are:
DZE | Meaning |
---|---|
0 |
Untrapped exception handling selected. If the floating-point exception occurs then the FPSR.DZC bit is set to 1. |
1 |
Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.DZC bit. The trap handling software can decide whether to set the FPSR.DZC bit to 1. |
The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.
If the implementation does not support this exception, this bit is RAZ/WI.
Invalid Operation floating-point exception trap enable. Possible values are:
IOE | Meaning |
---|---|
0 |
Untrapped exception handling selected. If the floating-point exception occurs then the FPSR.IOC bit is set to 1. |
1 |
Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.IOC bit. The trap handling software can decide whether to set the FPSR.IOC bit to 1. |
The value of this bit controls both scalar and Advanced SIMD floating-point arithmetic.
If the implementation does not support this exception, this bit is RAZ/WI.
Reserved, RES0.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
FPCR | 11 | 011 | 0100 | 0100 | 000 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | RW | RW | n/a | RW |
x | 0 | 1 | RW | RW | RW | RW |
x | 1 | 1 | RW | n/a | RW | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When HCR_EL2.E2H==0 :
If CPACR_EL1.FPEN==00, accesses to this register from EL0 and EL1 are trapped to EL1.
If CPACR_EL1.FPEN==01, accesses to this register from EL0 are trapped to EL1.
If CPACR_EL1.FPEN==10, accesses to this register from EL0 and EL1 are trapped to EL1.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If CPTR_EL2.TFP==1, Non-secure accesses to this register from EL0, EL1, and EL2 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If CPACR_EL1.FPEN==00, Non-secure accesses to this register from EL0 and EL1 are trapped to EL1.
If CPACR_EL1.FPEN==01, Non-secure accesses to this register from EL0 are trapped to EL1.
If CPACR_EL1.FPEN==10, Non-secure accesses to this register from EL0 and EL1 are trapped to EL1.
If CPTR_EL2.FPEN==00, Non-secure accesses to this register from EL0, EL1, and EL2 are trapped to EL2.
If CPTR_EL2.FPEN==10, Non-secure accesses to this register from EL0, EL1, and EL2 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==1 :
If CPTR_EL2.FPEN==00, Non-secure accesses to this register from EL0 and EL2 are trapped to EL2.
If CPTR_EL2.FPEN==01, Non-secure accesses to this register from EL0 are trapped to EL2.
If CPTR_EL2.FPEN==10, Non-secure accesses to this register from EL0 and EL2 are trapped to EL2.
When EL3 is implemented and is using AArch64 :
If CPTR_EL3.TFP==1, accesses to this register from EL0, EL1, EL2, and EL3 are trapped to EL3.
28/09/2017 08:24
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