GICH_MISR, Maintenance Interrupt Status Register

The GICH_MISR characteristics are:

Purpose

Indicates which maintenance interrupts are asserted.

This register is part of the GIC virtualised guest interface control registers functional group.

Usage constraints

This register is accessible as follows:

Security disabledSecureNon-secure
RORORO

This register is used only when System register access is not enabled. When System register access is enabled:

A maintenance interrupt is asserted only if at least one bit is set to 1 in this register and if GICH_HCR.En == 1.

Configuration

Some or all RW fields of this register have defined reset values.

This register is available when the GIC implementation supports interrupt virtualization.

Attributes

GICH_MISR is a 32-bit register.

Field descriptions

The GICH_MISR bit assignments are:

313029282726252423222120191817161514131211109876543210
000000000000000000000000VGrp1DVGrp1EVGrp0DVGrp0ENPLRENPUEOI

Bits [31:8]

Reserved, RES0.

VGrp1D, bit [7]

vPE Group 1 Disabled.

VGrp1DMeaning
0

vPE Group 1 Disabled maintenance interrupt not asserted.

1

vPE Group 1 Disabled maintenance interrupt asserted.

This maintenance interrupt is asserted when GICH_HCR.VGrp1DIE == 1 and GICH_VMCR.VENG1 == 0.

When this register has an architecturally-defined reset value, this field resets to 0.

VGrp1E, bit [6]

vPE Group 1 Enabled.

VGrp1EMeaning
0

vPE Group 1 Enabled maintenance interrupt not asserted.

1

vPE Group 1 Enabled maintenance interrupt asserted.

This maintenance interrupt is asserted when GICH_HCR.VGrp1EIE == 1 and GICH_VMCR.VENG1 == 1.

When this register has an architecturally-defined reset value, this field resets to 0.

VGrp0D, bit [5]

vPE Group 0 Disabled.

VGrp0DMeaning
0

vPE Group 0 Disabled maintenance interrupt not asserted.

1

vPE Group 0 Disabled maintenance interrupt asserted.

This maintenance interrupt is asserted when GICH_HCR.VGrp0DIE == 1 and GICH_VMCR.VENG0 == 0.

When this register has an architecturally-defined reset value, this field resets to 0.

VGrp0E, bit [4]

vPE Group 0 Enabled.

VGrp0EMeaning
0

vPE Group 0 Enabled maintenance interrupt not asserted.

1

vPE Group 0 Enabled maintenance interrupt asserted.

This maintenance interrupt is asserted when GICH_HCR.VGrp0EIE == 1 and GICH_VMCR.VENG0 == 1.

When this register has an architecturally-defined reset value, this field resets to 0.

NP, bit [3]

No Pending.

NPMeaning
0

No Pending maintenance interrupt not asserted.

1

No Pending maintenance interrupt asserted.

This maintenance interrupt is asserted when GICH_HCR.NPIE == 1 and no List register is in the pending state.

When this register has an architecturally-defined reset value, this field resets to 0.

LRENP, bit [2]

List Register Entry Not Present.

LRENPMeaning
0

List Register Entry Not Present maintenance interrupt not asserted.

1

List Register Entry Not Present maintenance interrupt asserted.

This maintenance interrupt is asserted when GICH_HCR.LRENPIE == 1 and GICH_HCR.EOICount is nonzero.

When this register has an architecturally-defined reset value, this field resets to 0.

U, bit [1]

Underflow.

UMeaning
0

Underflow maintenance interrupt not asserted.

1

Underflow maintenance interrupt asserted.

This maintenance interrupt is asserted when GICH_HCR.UIE == 1 and zero or one of the List register entries are marked as a valid interrupt.

When this register has an architecturally-defined reset value, this field resets to 0.

EOI, bit [0]

End Of Interrupt.

EOIMeaning
0

End Of Interrupt maintenance interrupt not asserted.

1

End Of Interrupt maintenance interrupt asserted.

This maintenance interrupt is asserted when at least one bit in GICH_EISR == 1.

When this register has an architecturally-defined reset value, this field resets to 0.

Note

A List register is in the pending state only if the corresponding GICH_LR<n> value is 01, that is, pending. The active and pending state is not included.

Accessing the GICH_MISR

GICH_MISR can be accessed through its memory-mapped interface:

ComponentOffset
GIC Virtual interface control 0x0010



28/09/2017 08:24

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