VPIDR, Virtualization Processor ID Register

The VPIDR characteristics are:

Purpose

Holds the value of the Virtualization Processor ID. This is the value returned by Non-secure EL1 reads of MIDR.

This register is part of:

Configuration

AArch32 System register VPIDR is architecturally mapped to AArch64 System register VPIDR_EL2.

If EL2 is not implemented but EL3 is implemented, this register takes the value of the MIDR.

Some or all RW fields of this register have defined reset values. These apply only if the PE resets into EL2 with EL2 using AArch32, or into EL3 with EL3 using AArch32. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.

Attributes

VPIDR is a 32-bit register.

Field descriptions

The VPIDR bit assignments are:

313029282726252423222120191817161514131211109876543210
ImplementerVariantArchitecturePartNumRevision

Implementer, bits [31:24]

The Implementer code. This field must hold an implementer code that has been assigned by ARM. Assigned codes include the following:

Hex representation ASCII representation Implementer
0x41 A ARM Limited
0x42 B Broadcom Corporation
0x43 C Cavium Inc.
0x44 D Digital Equipment Corporation
0x49 I Infineon Technologies AG
0x4D M Motorola or Freescale Semiconductor Inc.
0x4E N NVIDIA Corporation
0x50 P Applied Micro Circuits Corporation
0x51 Q Qualcomm Inc.
0x56 V Marvell International Ltd.
0x69 i Intel Corporation

ARM can assign codes that are not published in this manual. All values not assigned by ARM are reserved and must not be used.

When this register has an architecturally-defined reset value, this field resets to the value of MIDR.Implementer.

Variant, bits [23:20]

An IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product.

When this register has an architecturally-defined reset value, this field resets to the value of MIDR.Variant.

Architecture, bits [19:16]

The permitted values of this field are:

ArchitectureMeaning
0001

ARMv4

0010

ARMv4T

0011

ARMv5 (obsolete)

0100

ARMv5T

0101

ARMv5TE

0110

ARMv5TEJ

0111

ARMv6

1111

Architectural features are individually identified in the ID_* registers, see 'ID registers' in the ARMv8 ARM, section K12.5.3.

All other values are reserved.

When this register has an architecturally-defined reset value, this field resets to the value of MIDR.Architecture.

PartNum, bits [15:4]

An IMPLEMENTATION DEFINED primary part number for the device.

On processors implemented by ARM, if the top four bits of the primary part number are 0x0 or 0x7, the variant and architecture are encoded differently.

When this register has an architecturally-defined reset value, this field resets to the value of MIDR.PartNum.

Revision, bits [3:0]

An IMPLEMENTATION DEFINED revision number for the device.

When this register has an architecturally-defined reset value, this field resets to the value of MIDR.Revision.

Accessing the VPIDR

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 4, <Rt>, c0, c0, 0100000000011110000

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - - n/a -
x01 - - RWRW
x11 - n/a RWRW

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :




28/09/2017 08:24

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