TCR_EL3, Translation Control Register (EL3)

The TCR_EL3 characteristics are:

Purpose

The control register for stage 1 of the EL3 translation regime.

This register is part of the Virtual memory control registers functional group.

Configuration

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

TCR_EL3 is a 32-bit register.

Field descriptions

The TCR_EL3 bit assignments are:

313029282726252423222120191817161514131211109876543210
10TBIDHWU62HWU61HWU60HWU59HPD1HDHATBI0PSTG0SH0ORGN0IRGN000T0SZ

Any of the bits in TCR_EL3 are permitted to be cached in a TLB.

Bit [31]

Reserved, RES1.

Bit [30]

Reserved, RES0.

TBID, bit [29]
In ARMv8.3:

Present only if ARMv8.3-TPAuth is implemented.

Controls the use of the top byte of instruction addresses for address matching. Defined values are:

TBIDMeaning
0

TCR_EL3.TBI applies to Instruction and Data accesses.

1

TCR_EL3.TBI applies to Data accesses only.

This affects addresses where the address would be translated by tables pointed to by TTBR0_EL3.

If ARMv8.3-TPAuth is not implemented, this field is RES0.


In ARMv8.2, ARMv8.1 and ARMv8.0:

Reserved, RES0.

HWU62, bit [28]
In ARMv8.3 and ARMv8.2:

Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[62] of the stage 1 translation table Block or Page entry.

Defined values are:

HWU62Meaning
0

Bit[62] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose.

1

Bit[62] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of TCR_EL3.HPD is 1.

This bit is RES0 if ARMv8.2-TTPBHA is not implemented.

The Effective value of this field is 0 if the value of TCR_EL3.HPD is 0.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

HWU61, bit [27]
In ARMv8.3 and ARMv8.2:

Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[61] of the stage 1 translation table Block or Page entry.

Defined values are:

HWU61Meaning
0

Bit[61] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose.

1

Bit[61] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of TCR_EL3.HPD is 1.

This bit is RES0 if ARMv8.2-TTPBHA is not implemented.

The Effective value of this field is 0 if the value of TCR_EL3.HPD is 0.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

HWU60, bit [26]
In ARMv8.3 and ARMv8.2:

Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[60] of the stage 1 translation table Block or Page entry.

Defined values are:

HWU60Meaning
0

Bit[60] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose.

1

Bit[60] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of TCR_EL3.HPD is 1.

This bit is RES0 if ARMv8.2-TTPBHA is not implemented.

The Effective value of this field is 0 if the value of TCR_EL3.HPD is 0.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

HWU59, bit [25]
In ARMv8.3 and ARMv8.2:

Hardware Use. Indicates IMPLEMENTATION DEFINED hardware use of bit[59] of the stage 1 translation table Block or Page entry.

Defined values are:

HWU59Meaning
0

Bit[59] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose.

1

Bit[59] of each stage 1 translation table Block or Page entry can be used by hardware for an IMPLEMENTATION DEFINED purpose if the value of TCR_EL3.HPD is 1.

This bit is RES0 if ARMv8.2-TTPBHA is not implemented.

The Effective value of this field is 0 if the value of TCR_EL3.HPD is 0.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

HPD, bit [24]
In ARMv8.3, ARMv8.2 and ARMv8.1:

Hierarchical Permission Disables. This affects the hierarchical control bits, APTable, PXNTable, and UXNTable, except NSTable, in the translation tables pointed to by TTBR0_EL3.

Defined values are:

HPDMeaning
0

Hierarchical permissions are enabled.

1

Hierarchical permissions are disabled.

Note

In this case bit[61] (APTable[0]) and bit[59] (PXNTable) of the next level descriptor attributes are required to be ignored by the PE, and are no longer reserved, allowing them to be used by software.

When disabled, the permissions are treated as if the bits are zero.

This bit is RES0 if ARMv8.1-HPD is not implemented.


In ARMv8.0:

Reserved, RES0.

Bit [23]

Reserved, RES1.

HD, bit [22]
In ARMv8.3, ARMv8.2 and ARMv8.1:

Hardware management of dirty state in stage 1 translations from EL3.

Defined values are:

HDMeaning
0

Stage 1 hardware management of dirty state disabled.

1

Stage 1 hardware management of dirty state enabled, only if the HA bit is also set to 1.

This bit is RES0 if ARMv8.1-TTHM is not implemented.


In ARMv8.0:

Reserved, RES0.

HA, bit [21]
In ARMv8.3, ARMv8.2 and ARMv8.1:

Hardware Access flag update in stage 1 translations from EL3.

Defined values are:

HAMeaning
0

Stage 1 Access flag update disabled.

1

Stage 1 Access flag update enabled.

This bit is RES0 if ARMv8.1-TTHM is not implemented.


In ARMv8.0:

Reserved, RES0.

TBI, bit [20]

Top Byte ignored - indicates whether the top byte of an address is used for address match for the TTBR0_EL3 region, or ignored and used for tagged addresses.

TBIMeaning
0

Top Byte used in the address calculation.

1

Top Byte ignored in the address calculation.

This affects addresses generated in EL3 using AArch64 where the address would be translated by tables pointed to by TTBR0_EL3. It has an effect whether the EL3 translation regime is enabled or not.

If ARMv8.3-TPAuth is implemented and TCR_EL3.TBID is 1, then this field only applies to Data accesses.

Otherwise, if the value of TBI is 1, then bits[63:56] of that target address are also set to 0 before the address is stored in the PC, in the following cases:

Bit [19]

Reserved, RES0.

PS, bits [18:16]

Physical Address Size.

PSMeaning
000

32 bits, 4GB.

001

36 bits, 64GB.

010

40 bits, 1TB.

011

42 bits, 4TB.

100

44 bits, 16TB.

101

48 bits, 256TB.

110

52 bits, 4PB

Other values are reserved.

The reserved values behave in the same way as the 101 encoding, but software must not rely on this property as the behavior of the reserved values might change in a future revision of the architecture.

The value 110 is permitted only if ARMv8.2-LPA is implemented and the translation granule size is 64KB.

In an implementation that supports 52-bit PAs, if the value of this field is not 110, then bits[51:48] of every translation table base address for the stage of translation controlled by TCR_EL3 are 0000.

TG0, bits [15:14]

Granule size for the TTBR0_EL3.

TG0Meaning
00

4KB

01

64KB

10

16KB

Other values are reserved.

If the value is programmed to either a reserved value, or a size that has not been implemented, then the hardware will treat the field as if it has been programmed to an IMPLEMENTATION DEFINED choice of the sizes that has been implemented for all purposes other than the value read back from this register.

It is IMPLEMENTATION DEFINED whether the value read back is the value programmed or the value that corresponds to the size chosen.

SH0, bits [13:12]

Shareability attribute for memory associated with translation table walks using TTBR0_EL3.

SH0Meaning
00

Non-shareable

10

Outer Shareable

11

Inner Shareable

Other values are reserved. The effect of programming this field to a Reserved value is that behavior is CONSTRAINED UNPREDICTABLE, as described in 'Reserved values in AArch64 System registers and translation table entries' in the ARM ARM, section K1.2.2.

ORGN0, bits [11:10]

Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL3.

ORGN0Meaning
00

Normal memory, Outer Non-cacheable

01

Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable

10

Normal memory, Outer Write-Through Read-Allocate No Write-Allocate Cacheable

11

Normal memory, Outer Write-Back Read-Allocate No Write-Allocate Cacheable

IRGN0, bits [9:8]

Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3.

IRGN0Meaning
00

Normal memory, Inner Non-cacheable

01

Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable

10

Normal memory, Inner Write-Through Read-Allocate No Write-Allocate Cacheable

11

Normal memory, Inner Write-Back Read-Allocate No Write-Allocate Cacheable

Bits [7:6]

Reserved, RES0.

T0SZ, bits [5:0]

The size offset of the memory region addressed by TTBR0_EL3. The region size is 2(64-T0SZ) bytes.

The maximum and minimum possible values for T0SZ depend on the level of translation table and the memory translation granule size, as described in the AArch64 Virtual Memory System Architecture chapter.

Accessing the TCR_EL3

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
TCR_EL31111000100000010

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - - n/a RW
001 - - - RW
011 - n/a - RW
101 - - - RW
111 - n/a - RW

This table applies to all instructions that can access this register.




28/09/2017 08:24

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