The PMCNTENCLR_EL0 characteristics are:
Disables the Cycle Count Register, PMCCNTR_EL0, and any implemented event counters PMEVCNTR<n>. Reading this register shows which counters are enabled.
This register is part of the Performance Monitors registers functional group.
AArch64 System register PMCNTENCLR_EL0 is architecturally mapped to AArch32 System register PMCNTENCLR.
AArch64 System register PMCNTENCLR_EL0 is architecturally mapped to External register PMCNTENCLR_EL0.
This register is in the Warm reset domain. On a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.
PMCNTENCLR_EL0 is a 32-bit register.
The PMCNTENCLR_EL0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
C | P<n>, bit [n] |
PMCCNTR_EL0 disable bit. Disables the cycle counter register. Possible values are:
C | Meaning |
---|---|
0 |
When read, means the cycle counter is disabled. When written, has no effect. |
1 |
When read, means the cycle counter is enabled. When written, disables the cycle counter. |
Event counter disable bit for PMEVCNTR<n>_EL0.
Bits [30:N] are RAZ/WI. When EL2 is implemented, in Non-secure EL1 and EL0, N is the value in MDCR_EL2.HPMN. Otherwise, N is the value in PMCR_EL0.N.
Possible values of each bit are:
P<n> | Meaning |
---|---|
0 |
When read, means that PMEVCNTR<n>_EL0 is disabled. When written, has no effect. |
1 |
When read, means that PMEVCNTR<n>_EL0 is enabled. When written, disables PMEVCNTR<n>_EL0. |
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
PMCNTENCLR_EL0 | 11 | 011 | 1001 | 1100 | 010 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | RW | RW | n/a | RW |
x | 0 | 1 | RW | RW | RW | RW |
x | 1 | 1 | RW | n/a | RW | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If PMUSERENR_EL0.EN==0, accesses to this register from EL0 are trapped to EL1.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TPM==1, Non-secure accesses to this register from EL0 and EL1 are trapped to EL2.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TPM==1, accesses to this register from EL0, EL1, and EL2 are trapped to EL3.
28/09/2017 08:24
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