The DBGVCR32_EL2 characteristics are:
Allows access to the AArch32 register DBGVCR from AArch64 state only. Its value has no effect on execution in AArch64 state.
This register is part of the Debug registers functional group.
AArch64 System register DBGVCR32_EL2 is architecturally mapped to AArch32 System register DBGVCR.
If EL1 does not support AArch32, this register is UNDEFINED.
If EL2 is not implemented but EL3 is implemented, and EL1 is capable of using AArch32, then this register is not RES0.
This register is in the Warm reset domain. On a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.
DBGVCR32_EL2 is a 32-bit register.
The DBGVCR32_EL2 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NSF | NSI | 0 | NSD | NSP | NSS | NSU | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SF | SI | 0 | SD | SP | SS | SU | 0 |
FIQ vector catch enable in Non-secure state.
The exception vector offset is 0x1C.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
IRQ vector catch enable in Non-secure state.
The exception vector offset is 0x18.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Reserved, RES0.
Data Abort vector catch enable in Non-secure state.
The exception vector offset is 0x10.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Prefetch Abort vector catch enable in Non-secure state.
The exception vector offset is 0x0C.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Supervisor Call (SVC) vector catch enable in Non-secure state.
The exception vector offset is 0x08.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Undefined Instruction vector catch enable in Non-secure state.
The exception vector offset is 0x04.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Reserved, RES0.
FIQ vector catch enable in Secure state.
The exception vector offset is 0x1C.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
IRQ vector catch enable in Secure state.
The exception vector offset is 0x18.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Reserved, RES0.
Data Abort vector catch enable in Secure state.
The exception vector offset is 0x10.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Prefetch Abort vector catch enable in Secure state.
The exception vector offset is 0x0C.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Supervisor Call (SVC) vector catch enable in Secure state.
The exception vector offset is 0x08.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Undefined Instruction vector catch enable in Secure state.
The exception vector offset is 0x04.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Reserved, RES0.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | F | I | 0 | D | P | S | U | 0 |
Reserved, RES0.
FIQ vector catch enable.
The exception vector offset is 0x1C.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
IRQ vector catch enable.
The exception vector offset is 0x18.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Reserved, RES0.
Data Abort vector catch enable.
The exception vector offset is 0x10.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Prefetch Abort vector catch enable.
The exception vector offset 0x0C.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Supervisor Call (SVC) vector catch enable.
The exception vector offset is 0x08.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Undefined Instruction vector catch enable.
The exception vector offset is 0x04.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Reserved, RES0.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
DBGVCR32_EL2 | 10 | 100 | 0000 | 0111 | 000 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | - | n/a | RW |
x | 0 | 1 | - | - | RW | RW |
x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.NV==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.NV==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TDA==1, accesses to this register from EL2 are trapped to EL3.
28/09/2017 08:24
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