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ID_MMFR3_EL1, AArch32 Memory Model Feature Register 3

The ID_MMFR3_EL1 characteristics are:

Purpose

Provides information about the implemented memory model and memory management support in AArch32 state.

Must be interpreted with ID_MMFR0_EL1, ID_MMFR1_EL1, ID_MMFR2_EL1, and ID_MMFR4_EL1.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.

This register is part of the Identification registers functional group.

Configuration

AArch64 System register ID_MMFR3_EL1 is architecturally mapped to AArch32 System register ID_MMFR3.

In an implementation that supports only AArch64 state, this register is UNKNOWN.

Attributes

ID_MMFR3_EL1 is a 32-bit register.

Field descriptions

The ID_MMFR3_EL1 bit assignments are:

313029282726252423222120191817161514131211109876543210
SupersecCMemSzCohWalkPANMaintBcstBPMaintCMaintSWCMaintVA

Supersec, bits [31:28]

Supersections. On a VMSA implementation, indicates whether Supersections are supported. Defined values are:

SupersecMeaning
0000

Supersections supported.

1111

Supersections not supported.

All other values are reserved.

In ARMv8-A the permitted values are 0000 and 1111.

CMemSz, bits [27:24]

Cached Memory Size. Indicates the physical memory size supported by the caches. Defined values are:

CMemSzMeaning
0000

4GB, corresponding to a 32-bit physical address range.

0001

64GB, corresponding to a 36-bit physical address range.

0010

1TB or more, corresponding to a 40-bit or larger physical address range.

All other values are reserved.

In ARMv8-A the permitted values are 0000, 0001, and 0010.

CohWalk, bits [23:20]

Coherent Walk. Indicates whether Translation table updates require a clean to the point of unification. Defined values are:

CohWalkMeaning
0000

Updates to the translation tables require a clean to the point of unification to ensure visibility by subsequent translation table walks.

0001

Updates to the translation tables do not require a clean to the point of unification to ensure visibility by subsequent translation table walks.

All other values are reserved.

In ARMv8-A the only permitted value is 0001.

PAN, bits [19:16]
In ARMv8.3, ARMv8.2 and ARMv8.1:

Privileged Access Never. Indicates support for the PAN bit in CPSR, SPSR, and DSPSR in AArch32 state. Defined values are:

PANMeaning
0000

PAN not supported.

0001

PAN supported.

0010

PAN supported and ATS1CPRP and ATS1CPWP instructions supported.

All other values are reserved.

ARMv8.1-PAN implements the functionality identified by the value 0001.

ARMv8.2-ATS1E1 implements the functionality added by the value 0010.

In ARMv8.1 the value is 0000 is not permitted.

From ARMv8.2, the only permitted value is 0010.


In ARMv8.0:

Reserved, RES0.

MaintBcst, bits [15:12]

Maintenance Broadcast. Indicates whether Cache, TLB, and branch predictor operations are broadcast. Defined values are:

MaintBcstMeaning
0000

Cache, TLB, and branch predictor operations only affect local structures.

0001

Cache and branch predictor operations affect structures according to shareability and defined behavior of instructions. TLB operations only affect local structures.

0010

Cache, TLB, and branch predictor operations affect structures according to shareability and defined behavior of instructions.

All other values are reserved.

In ARMv8-A the only permitted value is 0010.

BPMaint, bits [11:8]

Branch Predictor Maintenance. Indicates the supported branch predictor maintenance operations in an implementation with hierarchical cache maintenance operations. Defined values are:

BPMaintMeaning
0000

None supported.

0001

Supported branch predictor maintenance operations are:

  • Invalidate all branch predictors.
0010

As for 0001, and adds:

  • Invalidate branch predictors by VA.

All other values are reserved.

In ARMv8-A the only permitted value is 0010.

CMaintSW, bits [7:4]

Cache Maintenance by Set/Way. Indicates the supported cache maintenance operations by set/way, in an implementation with hierarchical caches. Defined values are:

CMaintSWMeaning
0000

None supported.

0001

Supported hierarchical cache maintenance instructions by set/way are:

  • Invalidate data cache by set/way.
  • Clean data cache by set/way.
  • Clean and invalidate data cache by set/way.

All other values are reserved.

In ARMv8-A the only permitted value is 0001.

In a unified cache implementation, the data cache maintenance operations apply to the unified caches.

CMaintVA, bits [3:0]

Cache Maintenance by Virtual Address. Indicates the supported cache maintenance operations by VA, in an implementation with hierarchical caches. Defined values are:

CMaintVAMeaning
0000

None supported.

0001

Supported hierarchical cache maintenance operations by VA are:

  • Invalidate data cache by VA.
  • Clean data cache by VA.
  • Clean and invalidate data cache by VA.
  • Invalidate instruction cache by VA.
  • Invalidate all instruction cache entries.

All other values are reserved.

In ARMv8-A the only permitted value is 0001.

In a unified cache implementation, data cache maintenance operations apply to the unified caches, and the instruction cache maintenance instructions are not implemented.

Accessing the ID_MMFR3_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
ID_MMFR3_EL11100000000001111

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RO n/a RO
x01 - RORORO
x11 - n/a RORO

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :




28/0907/2017 0816:2440

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