The PMXEVTYPER characteristics are:
When PMSELR.SEL selects an event counter, this accesses a PMEVTYPER<n> register. When PMSELR.SEL selects the cycle counter, this accesses PMCCFILTR.
This register is part of the Performance Monitors registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register PMXEVTYPER is architecturally mapped to AArch64 System register PMXEVTYPER_EL0.
When the value of PMSELR.SEL is 31, to select the cycle counter, RW fields in this register have defined reset values that apply only when the PE resets into an Exception level that is using AArch32. See PMCCFILTR for the reset values.
Otherwise, RW fields in this register reset to IMPLEMENTATION DEFINED values that might be UNKNOWN. This applies whenever PMSELR.SEL selects an event counter.
PMXEVTYPER is a 32-bit register.
The PMXEVTYPER bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Event type register or PMCCFILTR |
Event type register or PMCCFILTR.
When PMSELR.SEL == 31, this register accesses PMCCFILTR.
Otherwise, this register accesses PMEVTYPER<n> where n is the value in PMSELR.SEL.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c9, c13, 1 | 000 | 001 | 1001 | 1111 | 1101 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | RW | RW | n/a | RW |
x | 0 | 1 | RW | RW | RW | RW |
x | 1 | 1 | RW | n/a | RW | RW |
This table applies to all instructions that can access this register.
If PMSELR.SEL is greater than or equal to the number of accessible counters then reads and writes of PMXEVTYPER are CONSTRAINED UNPREDICTABLE, and the following behaviors are permitted:
In an implementation that includes EL2, in Non-secure state at EL0 and EL1:
Otherwise, the number of accessible counters is the number of implemented counters.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If PMUSERENR.EN==0, accesses to this register from EL0 are trapped to Undefined mode.
If PMUSERENR_EL0.EN==0, accesses to this register from EL0 are trapped to EL1.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HSTR_EL2.T9==1, Non-secure accesses to this register from EL0 and EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TPM==1, Non-secure accesses to this register from EL0 and EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T9==1, Non-secure accesses to this register from EL0 and EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HDCR.TPM==1, Non-secure accesses to this register from EL0 and EL1 are trapped to Hyp mode.
If HSTR.T9==1, Non-secure accesses to this register from EL0 and EL1 are trapped to Hyp mode.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TPM==1, accesses to this register from EL0, EL1, and EL2 are trapped to EL3.
28/09/2017 08:24
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