The RMR characteristics are:
If EL1 or EL3 is the highest implemented Exception level and this register is implemented:
This register is part of the Reset management registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register RMR is architecturally mapped to AArch64 System register RMR_EL1 when EL1 is highest implemented Exception level.
AArch32 System register RMR is architecturally mapped to AArch64 System register RMR_EL3 when EL3 is implemented.
Only implemented if EL1 or EL3 is the highest implemented Exception level. In this case:
See the field descriptions for the reset values. These apply whenever the register is implemented.
RMR is a 32-bit register.
The RMR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | RR | AA64 |
Reserved, RES0.
Reset Request. Setting this bit to 1 requests a Warm reset.
This field resets to 0 on a Warm or Cold reset.
When the highest implemented Exception level can use AArch64, determines which Execution state the PE boots into after a Warm reset:
AA64 | Meaning |
---|---|
0 |
AArch32. |
1 |
AArch64. |
On coming out of the Warm reset, execution starts at the IMPLEMENTATION DEFINED reset vector address of the specified Execution state.
If the highest implemented Exception level cannot use AArch64 this bit is RAZ/WI.
When implemented as a RW field, this field resets to 0 on a Cold reset.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c12, c0, 2 | 000 | 010 | 1100 | 1111 | 0000 |
The register is accessible as follows:
Configuration | Control | Accessibility | |||||
---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | |
EL1 is the highest implemented Exception level | x | x | x | - | RW | n/a | n/a |
EL2 is the highest implemented Exception level | x | 0 | 1 | - | - | - | n/a |
EL2 is the highest implemented Exception level | x | 1 | 1 | - | n/a | - | n/a |
EL3 is the highest implemented Exception level | x | x | 0 | - | - | n/a | RW |
EL3 is the highest implemented Exception level | x | 0 | 1 | - | - | - | RW |
EL3 is the highest implemented Exception level | x | 1 | 1 | - | n/a | - | RW |
This table applies to all instructions that can access this register.
The encoding for this register is UNDEFINED:
When EL3 is implemented, ARM deprecates accessing this register from any PE mode other than Monitor mode.
28/09/2017 08:24
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.