The GICC_NSAPR<n> characteristics are:
Provides information about Group 1 interrupt active priorities.
This register is part of the GIC physical CPU interface registers functional group.
This register is accessible as follows:
Security disabled | Secure | Non-secure |
---|---|---|
RW | RW | RW |
Some or all RW fields of this register have defined reset values.
The contents of these registers are IMPLEMENTATION DEFINED with the one architectural requirement that the value 0x00000000 is consistent with no interrupts being active.
When GICD_CTLR.DS==0, these registers are RAZ/WI to Non-secure accesses.
GICC_NSAPR1 is only implemented in implementations that support 6 or more bits of priority. GICC_NSAPR2 and GICC_NSAPR3 are only implemented in implementations that support 7 bits of priority.
GICC_NSAPR<n> is a 32-bit register.
The GICC_NSAPR<n> bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED |
IMPLEMENTATION DEFINED.
When this register has an architecturally-defined reset value, this field resets to 0.
GICC_NSAPR<n> can be accessed through its memory-mapped interface:
Component | Offset |
---|---|
GIC CPU interface | 0x00E0 + 4n |
28/09/2017 08:24
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