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PMCEID0, Performance Monitors Common Event Identification register 0

The PMCEID0 characteristics are:

Purpose

Defines which common architectural events and common microarchitectural events are implemented, or counted, using PMU events in the range 0x000 to 0x01F

When the value of a bit in the register is 1 the corresponding common event is implemented or counted.

Note

ARM recommends that, if a commoncomon event is never counted, the value of the corresponding register bit is 0.

For more information about the common events and the use of the PMCEIDn registers see The section describing 'Event numbers and common events' in chapter D5 'The Performance Monitors Extension' of the ARM Architecture Reference Manual, for ARMv8-A architecture profile.

Defines which common architectural events and common microarchitectural events are implemented, or counted, using PMU events in the range 0x000 to 0x01F.

Note

This register is part of the Performance Monitors registers functional group.

Usage constraints

This register is accessible as follows:

OffDLKOSLKEPMADSLKDefault
ErrorErrorErrorErrorRORO

Configuration

External register PMCEID0 is architecturally mapped to AArch64 System register PMCEID0_EL0[31:0] .

External register PMCEID0 bits [31:0] are architecturally mapped to AArch32 System register PMCEID0.

PMCEID0 is in the Core power domain.

Attributes

PMCEID0 is a 32-bit register.

Field descriptions

The PMCEID0 bit assignments are:

313029282726252423222120191817161514131211109876543210
ID[31:0]

ID[31:0], bits [31:0]

ID[n] corresponds to common event n.

For each bit:

ID[31:0]Meaning
0

The common event is not implemented, or not counted.

1

The common event is implemented.

A bit that corresponds to a reserved event number is reserved. The value might be used in a future revision of the architecture to identify an additionaladdional common event.

Note

Such an event might be added retrospectively to an earlier version of the PMU architecture, provided the event does not require any additional PMU features and has an event number that can be represented in the PMCEID<n> registers of that earlier version of the PMU architecture.

Accessing the PMCEID0

PMCEID0 can be accessed through the external debug interface:

ComponentOffset
PMU0xE20



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