VBAR_EL1, Vector Base Address Register (EL1)

The VBAR_EL1 characteristics are:

Purpose

Holds the vector base address for any exception that is taken to EL1.

This register is part of the Exception and fault handling registers functional group.

Configuration

AArch64 System register VBAR_EL1 bits [31:0] are architecturally mapped to AArch32 System register VBAR.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

VBAR_EL1 is a 64-bit register.

Field descriptions

The VBAR_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
Vector Base Address
Vector Base Address00000000000
313029282726252423222120191817161514131211109876543210

Bits [63:11]

Vector Base Address. Base address of the exception vectors for exceptions taken to EL1.

If the implementation does not support ARMv8.2-LVA, then:

If the implementation supports ARMv8.2-LVA, then:

Bits [10:0]

Reserved, RES0.

Accessing the VBAR_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
VBAR_EL11100011000000000
VBAR_EL121110111000000000

Accessibility

The register is accessible as follows:

<systemreg> Control Accessibility
E2HTGENSEL0EL1EL2EL3
VBAR_EL1xx0 - RW n/a RW
VBAR_EL1001 - RWRWRW
VBAR_EL1011 - n/a RWRW
VBAR_EL1101 - RW VBAR_EL2 RW
VBAR_EL1111 - n/a VBAR_EL2 RW
VBAR_EL12xx0 - - n/a -
VBAR_EL12001 - - - -
VBAR_EL12011 - n/a - -
VBAR_EL12101 - - RWRW
VBAR_EL12111 - n/a RWRW

When HCR_EL2.E2H is 1, without explicit synchronization, access from EL3 using the mnemonic VBAR_EL1 or VBAR_EL12 are not guaranteed to be ordered with respect to accesses using the other mnemonic.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :




28/09/2017 08:24

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