The TLBI ALLE2 characteristics are:
If EL2 is implemented, invalidate cached copies of translation table entries from TLBs that meet all the following requirements:
The invalidation only applies to the PE that executes this instruction.
This System instruction is part of the TLB maintenance instructions functional group.
There are no configuration notes.
TLBI ALLE2 is a 64-bit System instruction.
TLBI ALLE2 ignores the value in the register specified by the instruction encoding. Software does not have to write a value to the register before issuing this instruction.
This instruction is executed using TLBI with the following syntax:
TLBI <tlbi_op>
This syntax uses the following encoding in the System instruction encoding space:
<tlbi_op> | op0 | op1 | CRn | CRm | op2 | Rt |
---|---|---|---|---|---|---|
ALLE2 | 01 | 100 | 1000 | 0111 | 000 | 11111 |
The instruction is executable as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | - | n/a | - |
0 | 0 | 1 | - | - | WO | WO |
0 | 1 | 1 | - | n/a | WO | WO |
1 | 0 | 1 | - | - | WO | WO |
1 | 1 | 1 | - | n/a | WO | WO |
This table applies to all syntax that can be used to execute this instruction.
If EL2 is not implemented, this instruction is UNDEFINED.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when executing this System instruction.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.NV==1, Non-secure execution of this instruction at EL1 is trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.NV==1, Non-secure execution of this instruction at EL1 is trapped to EL2.
28/09/2017 08:24
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