System Register XML
for ARMv8.3
(00bet5)
28th September 2017
1. Introduction
This is the 00bet5 release
of the System Register XML for ARMv8.3, describing:
-
The AArch64 and AArch32 views of the System registers
(including Debug, PMU, Generic Timer, and GIC).
-
The AArch32 and AArch32 system control operations.
-
The memory-mapped Debug, CTI, PMU, GIC, and Generic Timer registers.
The Proprietary Notice
gives details of the terms and conditions under which this package
is provided.
If you have comments on the content of this package, please send
them by e-mail to
support-aarchv8@arm.com.
Give:
- The title, "System Register XML for ARMv8.3".
- The version, "00bet5".
- A concise explanation of your comments.
Please see the Documentation for
more information on the general structure of these descriptions.
2. Contents
3. Release notes
Change history
-
The traps that are generated by EDSCR.TDA are corrected to
indicate that they generate a Software Access debug event.
-
The traps and enables sections for PMCEID2 and PMCEID3 are
corrected to add the missing MDCR_EL2, HDCR, HSTR and HSTR_EL2
traps.
-
The EDPRSR field descriptions are corrected to split the
EDPRSR.OSLK or EDPRSR.R fields, as conditions under which the
value of these fields are UNKNOWN.
-
The SCR.TERR description is corrected to indicate that the
trap applies in modes other than Monitor mode, and also that
they generate a Monitor Trap exception.
-
The traps and enables sections for PMCCNTR, PMCNTENCLR,
PMCNTENSET, PMCR, PMINTENSET, PMINTENCLR, PMOVSR, PMOVSSET,
PMSELR, PMUSERENR, PMXEVCNTR, and PMXEVTYPER described the
HSTR_EL2.T9 traps as being only for write accesses. This trap
applies to read accesses too, and so is corrected.
-
The HCR_EL2.DC description is corrected to add description of
the behaviour of the field.
-
The SCTLR_ELx.IESB descriptions are updated to clarify which
Exception level the control affects in Debug state.
-
The NFD0 and NFD1 fields in TCR_EL1 and TCR_EL2 are updated to
show that this control only apply to accesses from EL0.
-
The SEL field in PMSELR_EL0 and PMSELR was incorrectly
asserting that the value of the field on a read is
UNKNOWN. This is corrected, and only applies when the field is
set to a value greater than or equal to the number of
implemented counters, but not equal to 31.
-
The registers for the Statistical Profiling Extension have
been added.
-
Many simple clarifications and corrections are also present,
but are too small to be listed here. These can be seen in the
Change Markup PDF provided.
Known issues
-
The FPEXC32_EL2.UFF field includes the statement
"POSSIBLE_ACCESS_RESTRICTION". This will be removed in the
next release.
-
The memory-mapped Generic Timer register descriptions have
incorrect information, and so must not be relied upon.
This will be corrected in a future release. The definitive
source for these registers is the ARM Architecture Reference
Manual ARMv8, for ARMv8-A architecture profile.
-
There are no RAS registers included in this XML package.
-
There are differences in the GIC registers in this XML package
when compared to the GIC register descriptions in the Generic
Interrupt Controller Architecture Specification document. The
definitive source for these registers is the document, and
there will be corrections to these registers in the next
release.
-
There are stylistic differences in the descriptions of some
areas (e.g. ID register fields) for ARMv8.3 when compared to
equivalent descriptions for earlier architectures. These
will be made consistent in a future release.
-
The "Traps and enables" for breakpoint and watchpoint
registers include a trap when EDSCR.TDA==1 and
OSLSR_EL1.OSLK==0. This trap description needs correcting to
only apply when halting is allowed, and the trap is actually a
Software Access debug event. This applies to the following
register descriptions:
- DBGBCR<n>_EL1
- DBGBVR<n>_EL1
- DBGWCR<n>_EL1
- DBGWVR<n>_EL1
- DBGBCR<n>
- DBGBVR<n>
- DBGBXVR<n>
- DBGWCR<n>
- DBGWVR<n>
-
The HCR(_EL2).TID3 on accesses to ID_MMFR4_EL1 and ID_MMFR4
needs correcting to indicate that this trap only applies if the
register value is not zero.
-
The "Traps and enables" for the following registers only
apply when the PE is in Non-debug state:
- DBGDTR_EL0
- DBGDTRRX_EL0
- DBGDTRTX_EL0
- DBGDTRRXint
- DBGDTRTXint
-
The PMPCSR bit[0] is corrected to be SBZ.
-
The references to Prince in the Pointer Authentication ID
fields are corrected to reference QARMA.
-
The CNTV_TVAL and CNTV_TVAL_EL0 registers are corrected to
reference the CNTVCT and CNTVCT_EL0 registers. The Generic
Timer *TVAL* and *CVAL* registers are corrected to indicate
that the timer condition is met when the value is greater than
or equal to zero.
-
The HPFAR_EL2.FIPA field description is corrected to indicate
the behavior for implementations with fewer than 48 bits of
physical address.
4. Documentation
General
A description within the XML contains the following sections:
- Purpose
-
A short description of the purpose of the register in the
ARMv8 Architecture.
- Configuration
-
How the register is architecturally mapped onto another System
register or a memory-mapped register. If the configuration of
the PE affects the implementation of the register, then
information about this is also included here. This section also
summarizes the behavior of the register on a reset.
- Attributes
-
The size of the register. For registers where the layouts of
the fields differ based on configuration, or other state
within the PE, this section also summarizes the different
layouts.
- Field descriptions
-
The register diagram, and a description of the behavior of
each field within the register.
Memory-mapped registers
A memory-mapped register description also contains the following
sections:
- Usage constraints
-
The accessibility of the memory-mapped register.
- Accessing the ...
-
The address or offset of the register in the memory map.
System registers
A System register description also contains an "Accessing the
..." section, that includes:
-
The assembler syntax for the instructions used to access the
register, and how the instruction is encoded.
-
The accessibility of the register when using these
instructions.
-
The traps and enables that apply on accesses to the register.
The accessibility of a System register is described in the
"Accessibility" sub-section. The first column of this table is
the same as the table describing the encoding of the
instructions used to access the register. The columns following
this are described below:
- Configuration
-
If present, this column describes other configuration
information (in addition to the Control fields) on which the
accessibility depends. If the entry for the row is empty or
the column is not present, there is no other configuration
information.
- Control
-
Every accessibility row include one or more control fields,
and the settings on which the accessibility depends. Each
setting is a binary value, and the value may include the
character 'x', which indicates that the bit at this position
in the value can be either '0' or '1'.
- Accessibility
-
The Accessibility columns describe the permission at each
Exception level for this row. Each value may be one of the
following, or a reference to another register:
- n/a
-
Access to the register at this Exception level is not
possible. This is used in the following cases:
-
EL2 when NS==0. Secure EL2 does not exist!
-
EL1 when NS==1 and TGE==1. In this case all exceptions
to EL1 are re-routed to EL2, so there is no execution
at EL1.
- RW
- Read and write access permitted.
- RO
- Read access permitted, but no write access.
- WO
- Write access permitted, but no read access.
- -
- Access to the register is UNDEFINED.
When the cell is a reference to another register, this
indicates that the attempt to access this register using the
instruction will result in access to the referenced register.
- Instance
-
Where the register is a banked register, this row describes
which banked register is accessed.