The GICC_RPR characteristics are:
This register indicates the running priority of the CPU interface.
This register is part of the GIC physical CPU interface registers functional group.
This register is accessible as follows:
Security disabled | Secure | Non-secure |
---|---|---|
RO | RO | RO |
If there is no active interrupt on the CPU interface, the idle priority value is returned.
If the GIC implementation supports two Security states, a Non-secure read of the Priority field returns:
See 'Priority control of Secure and Non-secure interrupts' in the GICv3 Architecture Specification for more information.
Software cannot determine the number of implemented priority bits from this register.
This register is available in all configurations of the GIC. If the GIC implementation supports two Security states this register is Common.
GICC_RPR is a 32-bit register.
The GICC_RPR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Priority |
Reserved, RES0.
The current running priority on the CPU interface. This is the group priority of the current active interrupt.
If there are no active interrupts on the CPU interface, or all active interrupts have undergone a priority drop, the value returned is the Idle priority.
The priority returned is the group priority as if the BPR was set to the minimum value.
GICC_RPR can be accessed through its memory-mapped interface:
Component | Offset |
---|---|
GIC CPU interface | 0x0014 |
28/09/2017 08:24
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