GICD_CLRSPI_SR, Clear Secure SPI Pending Register

The GICD_CLRSPI_SR characteristics are:

Purpose

Removes the pending state from a valid SPI.

A write to this register changes the state of a pending SPI to inactive, and the state of an active and pending SPI to active.

This register is part of the GIC Distributor registers functional group.

Usage constraints

This register is accessible as follows:

Security disabledSecureNon-secure
WIWOWI

Writes to this register have no effect if:

16-bit accesses to bits [15:0] of this register must be supported.

Configuration

If GICD_TYPER.MBIS == 0, this register is reserved.

When GICD_CTLR.DS==1, this register is WI.

Attributes

GICD_CLRSPI_SR is a 32-bit register.

Field descriptions

The GICD_CLRSPI_SR bit assignments are:

313029282726252423222120191817161514131211109876543210
0000000000000000000000INTID

Bits [31:10]

Reserved, RES0.

INTID, bits [9:0]

The INTID of the SPI.

The function of this register depends on whether the targeted SPI is configured to be an edge-triggered or level-sensitive interrupt:

Accessing the GICD_CLRSPI_SR

GICD_CLRSPI_SR can be accessed through its memory-mapped interface:

ComponentOffset
GIC Distributor 0x0058



28/09/2017 08:24

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