The ID_ISAR4 characteristics are:
Provides information about the instruction sets implemented by the PE in AArch32 state.
Must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR2, ID_ISAR3, and ID_ISAR5.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section G4.14.6.
This register is part of the Identification registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register ID_ISAR4 is architecturally mapped to AArch64 System register ID_ISAR4_EL1.
ID_ISAR4 is a 32-bit register.
The ID_ISAR4 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SWP_frac | PSR_M | SynchPrim_frac | Barrier | SMC | Writeback | WithShifts | Unpriv |
Indicates support for the memory system locking the bus for SWP or SWPB instructions. Defined values are:
SWP_frac | Meaning |
---|---|
0000 |
SWP or SWPB instructions not implemented. |
0001 |
SWP or SWPB implemented but only in a uniprocessor context. SWP and SWPB do not guarantee whether memory accesses from other masters can come between the load memory access and the store memory access of the SWP or SWPB. |
All other values are reserved. This field is valid only if the ID_ISAR0.Swap_instrs field is 0000.
In ARMv8-A the only permitted value is 0000.
Indicates the implemented M profile instructions to modify the PSRs. Defined values are:
PSR_M | Meaning |
---|---|
0000 |
None implemented. |
0001 |
Adds the M profile forms of the CPS, MRS, and MSR instructions. |
All other values are reserved.
In ARMv8-A the only permitted value is 0000.
Used in conjunction with ID_ISAR3.SynchPrim to indicate the implemented Synchronization Primitive instructions. Possible values are:
SynchPrim_frac | Meaning |
---|---|
0000 |
If SynchPrim == 0000, no Synchronization Primitives implemented. If SynchPrim == 0001, adds the LDREX and STREX instructions. If SynchPrim == 0010, also adds the CLREX, LDREXB, LDREXH, STREXB, STREXH, LDREXD, and STREXD instructions. |
0011 |
If SynchPrim == 0001, adds the LDREX, STREX, CLREX, LDREXB, LDREXH, STREXB, and STREXH instructions. |
All other combinations of SynchPrim and SynchPrim_frac are reserved.
In ARMv8-A the only permitted value is 0000.
Indicates the implemented Barrier instructions in the A32 and T32 instruction sets. Defined values are:
Barrier | Meaning |
---|---|
0000 |
None implemented. Barrier operations are provided only as System instructions in the (coproc==1111) encoding space. |
0001 |
Adds the DMB, DSB, and ISB barrier instructions. |
All other values are reserved.
In ARMv8-A the only permitted value is 0001.
Indicates the implemented SMC instructions. Defined values are:
SMC | Meaning |
---|---|
0000 |
None implemented. |
0001 |
Adds the SMC instruction. |
All other values are reserved.
In ARMv8-A the only permitted value is 0001.
Indicates the support for Writeback addressing modes. Defined values are:
Writeback | Meaning |
---|---|
0000 |
Basic support. Only the LDM, STM, PUSH, POP, SRS, and RFE instructions support writeback addressing modes. These instructions support all of their writeback addressing modes. |
0001 |
Adds support for all of the writeback addressing modes. |
All other values are reserved.
In ARMv8-A the only permitted value is 0001.
Indicates the support for instructions with shifts. Defined values are:
WithShifts | Meaning |
---|---|
0000 |
Nonzero shifts supported only in MOV and shift instructions. |
0001 |
Adds support for shifts of loads and stores over the range LSL 0-3. |
0011 |
As for 0001, and adds support for other constant shift options, both on load/store and other instructions. |
0100 |
As for 0011, and adds support for register-controlled shift options. |
All other values are reserved.
In ARMv8-A the only permitted value is 0100.
Indicates the implemented unprivileged instructions. Defined values are:
Unpriv | Meaning |
---|---|
0000 |
None implemented. No T variant instructions are implemented. |
0001 |
Adds the LDRBT, LDRT, STRBT, and STRT instructions. |
0010 |
As for 0001, and adds the LDRHT, LDRSBT, LDRSHT, and STRHT instructions. |
All other values are reserved.
In ARMv8-A the only permitted value is 0010.
This register can be read using MRC with the following syntax:
MRC <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c0, c2, 4 | 000 | 100 | 0000 | 1111 | 0010 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HSTR_EL2.T0==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HSTR_EL2.T0==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
28/09/2017 08:24
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