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CNTHP_TVAL, Counter-timer Hyp Physical Timer TimerValue register

The CNTHP_TVAL characteristics are:

Purpose

Holds the timer value for the Hyp mode physical timer.

This register is part of:

Configuration

AArch32 System register CNTHP_TVAL is architecturally mapped to AArch64 System register CNTHP_TVAL_EL2.

If EL2 is not implemented, this register is RES0 from EL3.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

CNTHP_TVAL is a 32-bit register.

Field descriptions

The CNTHP_TVAL bit assignments are:

313029282726252423222120191817161514131211109876543210
TimerValue

TimerValue, bits [31:0]

The TimerValue view of the EL2 physical timer.

On a read of this register:

On a write of this register, CNTHP_CVAL is set to (CNTPCT + TimerValue), where TimerValue is treated as a signed 32-bit integer.

When CNTHP_CTL.ENABLE is 1, the timer condition is met when (CNTPCT - CNTHP_CVAL) is greater than or equal to zero. This means that TimerValue acts like a 32-bit downcounter timer. When the timer condition is met:

When CNTHP_CTL.ENABLE is 0, the timer condition is not met, but CNTPCT continues to count, so the TimerValue view appears to continue to count down.

Accessing the CNTHP_TVAL

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 4, <Rt>, c14, c2, 0100000111011110010
p15, 0, <Rt>, c14, c2, 0000000111011110010

Accessibility

The register is accessible as follows:

<syntax> Control Accessibility
E2HTGENSEL0EL1EL2EL3
p15, 4, <Rt>, c14, c2, 0xx0 - - n/a -
p15, 4, <Rt>, c14, c2, 0x01 - - RWRW
p15, 4, <Rt>, c14, c2, 0x11 - n/a RWRW
p15, 0, <Rt>, c14, c2, 0xx0 CNTP_TVAL CNTP_TVAL n/a CNTP_TVAL
p15, 0, <Rt>, c14, c2, 0001 CNTP_TVAL CNTP_TVAL CNTP_TVAL CNTP_TVAL
p15, 0, <Rt>, c14, c2, 0011 CNTP_TVAL n/a CNTP_TVAL CNTP_TVAL
p15, 0, <Rt>, c14, c2, 0101 CNTP_TVAL CNTP_TVAL n/a n/a
p15, 0, <Rt>, c14, c2, 0111RW n/a n/a n/a

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==1 :




28/0907/2017 0816:2440

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