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ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0

The ID_AA64PFR0_EL1 characteristics are:

Purpose

Provides additional information about implemented PE features in AArch64 state.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.

This register is part of the Identification registers functional group.

Configuration

The external register EDPFR gives information from this register.

Attributes

ID_AA64PFR0_EL1 is a 64-bit register.

Field descriptions

The ID_AA64PFR0_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
0000000000000000000000000000SVE
RASGICAdvSIMDFPEL3EL2EL1EL0
313029282726252423222120191817161514131211109876543210

Bits [63:36]

Reserved, RES0.

SVE, bits [35:32]
In ARMv8.3 and ARMv8.2:

Scalable Vector Extension. Defined values are:

SVEMeaning
0000

SVE is not implemented.

0001

SVE is implemented.

All other values are reserved.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

RAS, bits [31:28]

RAS Extension version. The defined values of this field are:

RASMeaning
0000

No RAS Extension.

0001

Version 1 of the RAS Extension present.

All other values are reserved.

GIC, bits [27:24]

System register GIC interface support. Defined values are:

GICMeaning
0000

No System register interface to the GIC is supported.

0001

System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported.

All other values are reserved.

AdvSIMD, bits [23:20]

Advanced SIMD. Defined values are:

AdvSIMDMeaning
0000

Advanced SIMD is implemented, including support for the following SISD and SIMD operations:

  • Integer byte, halfword, word and doubleword element operations.
  • Single-precision and double-precision floating-point arithmetic.
  • Conversions between single-precision and half-precision data types, and double-precision and half-precision data types.
0001

As for 0000, and also includes support for half-precision floating-point arithmetic.

1111

Advanced SIMD is not implemented.

All other values are reserved.

This field must have the same value as the FP field.

The permitted values are:

FP, bits [19:16]

Floating-point. Defined values are:

FPMeaning
0000

Floating-point is implemented, and includes support for:

  • Single-precision and double-precision floating-point types.
  • Conversions between single-precision and half-precision data types, and double-precision and half-precision data types.
0001

As for 0000, and also includes support for half-precision floating-point arithmetic.

1111

Floating-point is not implemented.

All other values are reserved.

This field must have the same value as the AdvSIMD field.

The permitted values are:

EL3, bits [15:12]

EL3 Exception level handling. Defined values are:

EL3Meaning
0000

EL3 is not implemented.

0001

EL3 can be executed in AArch64 state only.

0010

EL3 can be executed in either AArch64 or AArch32 state.

All other values are reserved.

EL2, bits [11:8]

EL2 Exception level handling. Defined values are:

EL2Meaning
0000

EL2 is not implemented.

0001

EL2 can be executed in AArch64 state only.

0010

EL2 can be executed in either AArch64 or AArch32 state.

All other values are reserved.

EL1, bits [7:4]

EL1 Exception level handling. Defined values are:

EL1Meaning
0001

EL1 can be executed in AArch64 state only.

0010

EL1 can be executed in either AArch64 or AArch32 state.

All other values are reserved.

EL0, bits [3:0]

EL0 Exception level handling. Defined values are:

EL0Meaning
0001

EL0 can be executed in AArch64 state only.

0010

EL0 can be executed in either AArch64 or AArch32 state.

All other values are reserved.

Accessing the ID_AA64PFR0_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
ID_AA64PFR0_EL11100000000100000

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RO n/a RO
x01 - RORORO
x11 - n/a RORO

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :




28/0907/2017 0816:2440

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