The PMVIDSR characteristics are:
Contains the sampled VMID value that is captured on reading PMPCSR[31:0].
This register is part of the Performance Monitors registers functional group.
This register is accessible as follows:
Off | DLK | OSLK | SLK | Default |
---|---|---|---|---|
Error | Error | Error | RO | RO |
IMPLEMENTATION DEFINED extensions to external debug might make the value of this register UNKNOWN, see the section describing 'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN' in chapter H7 'The PC Sample-based Profiling Extension' of the ARM Architecture Reference Manual, for ARMv8-A architecture profile.
PMVIDSR is in the Core power domain.
Fields in this register reset to architecturally UNKNOWN values. These apply only on a Cold reset. The register is not affected by a Warm reset and is not affected by an External debug reset.
Implemented only when ARMv8.2-PCSample is implemented.
Before ARMv8.2, the PC Sample-based Profiling Extension can be implemented in the external debug register space, as indicated by the value of EDDEVID.PCSample.
If EL2 is not implemented, this register is RES0.
This register is introduced in ARMv8.2.
PMVIDSR is a 32-bit register.
The PMVIDSR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | VMID |
Reserved, RES0.
VMID sample. The VMID associated with the most recent PMPCSR sample.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
PMVIDSR can be accessed through the external debug interface:
Component | Offset |
---|---|
PMU | 0x20C |
28/09/2017 08:24
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