CPSR, Current Program Status Register

The CPSR characteristics are:

Purpose

Holds PE status and control information.

This register is part of the Process state registers functional group.

Usage constraints

The CPSR can be read using the MRS instruction and written using the MSR (immediate) or MSR (register) instructions. For more details on the instruction syntax, see 'PSTATE and banked register access instructions' in the ARMv8 ARM, section F1.5.

Traps and Enables

There are no traps or enables affecting this register.

Configuration

There is one instance of this register that is used in both Secure and Non-secure states.

Attributes

CPSR is a 32-bit register.

Field descriptions

The CPSR bit assignments are:

313029282726252423222120191817161514131211109876543210
NZCVQIT[1:0]J0PAN00GEIT[7:2]EAIFT1M[3:0]

N, bit [31]

Negative condition flag. Set to bit[31] of the result of the last flag-setting instruction. If the result is regarded as a two's complement signed integer, then N is set to 1 if the result was negative, and N is set to 0 if the result was positive or zero.

Z, bit [30]

Zero condition flag. Set to 1 if the result of the last flag-setting instruction was zero, and to 0 otherwise. A result of zero often indicates an equal result from a comparison.

C, bit [29]

Carry condition flag. Set to 1 if the last flag-setting instruction resulted in a carry condition, for example an unsigned overflow on an addition.

V, bit [28]

Overflow condition flag. Set to 1 if the last flag-setting instruction resulted in an overflow condition, for example a signed overflow on an addition.

Q, bit [27]

Cumulative saturation bit. Set to 1 to indicate that overflow or saturation occurred in some instructions.

IT[1:0], bits [26:25]

IT block state bits for the T32 IT (If-Then) instruction. See IT[7:2] for explanation of this field.

J, bit [24]

RES0.

In previous versions of the architecture, the {J, T} bits determined the AArch32 Instruction set state. ARMv8 does not support either Jazelle state or T32EE state, and the T bit determines the Instruction set state.

Bit [23]

Reserved, RES0.

PAN, bit [22]
In ARMv8.3, ARMv8.2 and ARMv8.1:

Privileged Access Never. When ARMv8.1-PAN is implemented, defined values are:

PANMeaning
0

The translation system is the same as ARMv8.0.

1

Disables privileged read and write accesses to addresses accessible at EL0.

The value of this bit is usually preserved on taking an exception, except in the following situations:

When ARMv8.1-PAN is not implemented, this bit is RES0.


In ARMv8.0:

Reserved, RES0.

Bits [21:20]

Reserved, RES0.

GE, bits [19:16]

Greater than or Equal flags, for parallel addition and subtraction.

IT[7:2], bits [15:10]

IT block state bits for the T32 IT (If-Then) instruction. This field must be interpreted in two parts.

The IT field is 0b00000000 when no IT block is active.

E, bit [9]

Endianness state bit. Controls the load and store endianness for data accesses:

EMeaning
0

Little-endian operation

1

Big-endian operation.

Instruction fetches ignore this bit.

When the reset value of the SCTLR.EE bit is defined by a configuration input signal, that value also applies to the CPSR.E bit on reset, and therefore applies to software execution from reset.

If an implementation does not provide Big-endian support, this bit is RES0. If it does not provide Little-endian support, this bit is RES1.

If an implementation provides Big-endian support but only at EL0, this bit is RES0 for an exception return to any Exception level other than EL0.

Likewise, if it provides Little-endian support only at EL0, this bit is RES1 for an exception return to any Exception level other than EL0.

A, bit [8]

SError interrupt mask bit. The possible values of this bit are:

AMeaning
0

Exception not masked.

1

Exception masked.

I, bit [7]

IRQ mask bit. The possible values of this bit are:

IMeaning
0

Exception not masked.

1

Exception masked.

F, bit [6]

FIQ mask bit. The possible values of this bit are:

FMeaning
0

Exception not masked.

1

Exception masked.

T, bit [5]

T32 Instruction set state bit. Indicates the AArch32 instruction set state. Possible values of this bit are:

TMeaning
0

A32 state.

1

T32 state.

Bit [4]

Reserved, RES1.

M[3:0], bits [3:0]

Current PE mode. Possible values are:

M[3:0] Mode
0b0000 User
0b0001 FIQ
0b0010 IRQ
0b0011 Supervisor
0b0110 Monitor
0b0111 Abort
0b1010 Hyp
0b1011 Undefined
0b1111 System

Other values are reserved.




28/09/2017 08:24

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