The EDPIDR3 characteristics are:
Provides information to identify an external debug component.
For more information see 'About the Peripheral identification scheme' in the ARMv8 ARM, section H8 (About the External Debug Registers).
This register is part of the Debug registers functional group.
This register is accessible as follows:
Default |
---|
RO |
EDPIDR3 is in the Debug power domain.
Implementation of this register is OPTIONAL.
This register is required for CoreSight compliance.
EDPIDR3 is a 32-bit register.
The EDPIDR3 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | REVAND | CMOD |
Reserved, RES0.
Part minor revision. Parts using EDPIDR2.REVISION as an extension to the Part number must use this field as a major revision number.
Customer modified. Indicates someone other than the Designer has modified the component.
EDPIDR3 can be accessed through the external debug interface:
Component | Offset |
---|---|
Debug | 0xFEC |
28/09/2017 08:24
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