TTBCR, Translation Table Base Control Register

The TTBCR characteristics are:

Purpose

The control register for stage 1 of the PL1&0 translation regime. Its controls include:

In ARMv8.2, when the value of TTBCR.{EAE, T2E} is {1, 1}, TTBCR is used with TTBCR2.

This register is part of the Virtual memory control registers functional group.

Configuration

AArch32 System register TTBCR is architecturally mapped to AArch64 System register TCR_EL1[31:0] .

The current translation table format determines which format of the register is used.

When EL3 is using AArch32, write access to TTBCR(S) is disabled when the CP15SDISABLE signal is asserted HIGH.

Some RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch32. If the PE resets into EL3 using AArch32 then:

Attributes

TTBCR is a 32-bit register.

Field descriptions

The TTBCR bit assignments are:

For all register layouts:

EAE, bit [31]

Extended Address Enable. The meanings of the possible values of this bit are:

EAEMeaning
0

Use the VMSAv8-32 translation system with the Short-descriptor translation table format.

1

Use the VMSAv8-32 translation system with the Long-descriptor translation table format.

When TTBCR.EAE==0:

313029282726252423222120191817161514131211109876543210
EAE0000000000000000000000000PD1PD00N

EAE, bit [31]

Extended Address Enable. The meanings of the possible values of this bit are:

EAEMeaning
0

Use the VMSAv8-32 translation system with the Short-descriptor translation table format.

When this register has an architecturally-defined reset value, this field resets to 0.

Bits [30:6]

Reserved, RES0.

PD1, bit [5]

Translation table walk disable for translations using TTBR1. This bit controls whether a translation table walk is performed on a TLB miss, for an address that is translated using TTBR1. The encoding of this bit is:

PD1Meaning
0

Perform translation table walks using TTBR1.

1

A TLB miss on an address that is translated using TTBR1 generates a Translation fault. No translation table walk is performed.

When this register has an architecturally-defined reset value, this field resets to 0.

PD0, bit [4]

Translation table walk disable for translations using TTBR0. This bit controls whether a translation table walk is performed on a TLB miss for an address that is translated using TTBR0. The encoding of this bit is:

PD0Meaning
0

Perform translation table walks using TTBR0.

1

A TLB miss on an address that is translated using TTBR0 generates a Translation fault. No translation table walk is performed.

When this register has an architecturally-defined reset value, this field resets to 0.

Bit [3]

Reserved, RES0.

N, bits [2:0]

Indicate the width of the base address held in TTBR0. In TTBR0, the base address field is bits[31:14-N]. The value of N also determines:

N can take any value from 0 to 7, that is, from 0b000 to 0b111.

When N has its reset value of 0, the translation table base is compatible with ARMv5 and ARMv6.

When this register has an architecturally-defined reset value, this field resets to 0.

When TTBCR.EAE==1:

313029282726252423222120191817161514131211109876543210
EAEIMP DEFSH1ORGN1IRGN1EPD1A1000T1SZ00SH0ORGN0IRGN0EPD0T2E000T0SZ

EAE, bit [31]

Extended Address Enable. The meanings of the possible values of this bit are:

EAEMeaning
1

Use the VMSAv8-32 translation system with the Long-descriptor translation table format.

When this register has an architecturally-defined reset value, this field resets to 0.

IMP DEF, bit [30]

IMPLEMENTATION DEFINED.

When this register has an architecturally-defined reset value, this field resets to 0.

SH1, bits [29:28]

Shareability attribute for memory associated with translation table walks using TTBR1. Defined values are:

SH1Meaning
00

Non-shareable

10

Outer Shareable

11

Inner Shareable

Other values are reserved. The effect of programming this field to a Reserved value is that behavior is CONSTRAINED UNPREDICTABLE, as described in 'Unallocated values in fields of AArch32 System registers and translation table entries' in the ARM ARM, section K1.1.11.

When this register has an architecturally-defined reset value, this field resets to 0.

ORGN1, bits [27:26]

Outer cacheability attribute for memory associated with translation table walks using TTBR1.

ORGN1Meaning
00

Normal memory, Outer Non-cacheable

01

Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable

10

Normal memory, Outer Write-Through Read-Allocate No Write-Allocate Cacheable

11

Normal memory, Outer Write-Back Read-Allocate No Write-Allocate Cacheable

When this register has an architecturally-defined reset value, this field resets to 0.

IRGN1, bits [25:24]

Inner cacheability attribute for memory associated with translation table walks using TTBR1.

IRGN1Meaning
00

Normal memory, Inner Non-cacheable

01

Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable

10

Normal memory, Inner Write-Through Read-Allocate No Write-Allocate Cacheable

11

Normal memory, Inner Write-Back Read-Allocate No Write-Allocate Cacheable

When this register has an architecturally-defined reset value, this field resets to 0.

EPD1, bit [23]

Translation table walk disable for translations using TTBR1. This bit controls whether a translation table walk is performed on a TLB miss, for an address that is translated using TTBR1. The encoding of this bit is:

EPD1Meaning
0

Perform translation table walks using TTBR1.

1

A TLB miss on an address that is translated using TTBR1 generates a Translation fault. No translation table walk is performed.

When this register has an architecturally-defined reset value, this field resets to 0.

A1, bit [22]

Selects whether TTBR0 or TTBR1 defines the ASID. The encoding of this bit is:

A1Meaning
0

TTBR0.ASID defines the ASID.

1

TTBR1.ASID defines the ASID.

When this register has an architecturally-defined reset value, this field resets to 0.

Bits [21:19]

Reserved, RES0.

T1SZ, bits [18:16]

See 'Selecting between TTBR0 and TTBR1, VMSAv8-32 Long-descriptor translation table format' in the ARMv8 ARM for how TTBCR.{T1SZ, T0SZ} determine the input address ranges and memory region sizes translated using TTBR0 and TTBR1.

When this register has an architecturally-defined reset value, this field resets to 0.

Bits [15:14]

Reserved, RES0.

SH0, bits [13:12]

Shareability attribute for memory associated with translation table walks using TTBR0.

SH0Meaning
00

Non-shareable

10

Outer Shareable

11

Inner Shareable

Other values are reserved. The effect of programming this field to a Reserved value is that behavior is CONSTRAINED UNPREDICTABLE, as described in 'Unallocated values in fields of AArch32 System registers and translation table entries' in the ARM ARM, section K1.1.11.

When this register has an architecturally-defined reset value, this field resets to 0.

ORGN0, bits [11:10]

Outer cacheability attribute for memory associated with translation table walks using TTBR0.

ORGN0Meaning
00

Normal memory, Outer Non-cacheable

01

Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable

10

Normal memory, Outer Write-Through Read-Allocate No Write-Allocate Cacheable

11

Normal memory, Outer Write-Back Read-Allocate No Write-Allocate Cacheable

When this register has an architecturally-defined reset value, this field resets to 0.

IRGN0, bits [9:8]

Inner cacheability attribute for memory associated with translation table walks using TTBR0.

IRGN0Meaning
00

Normal memory, Inner Non-cacheable

01

Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable

10

Normal memory, Inner Write-Through Read-Allocate No Write-Allocate Cacheable

11

Normal memory, Inner Write-Back Read-Allocate No Write-Allocate Cacheable

When this register has an architecturally-defined reset value, this field resets to 0.

EPD0, bit [7]

Translation table walk disable for translations using TTBR0. This bit controls whether a translation table walk is performed on a TLB miss, for an address that is translated using TTBR0. The encoding of this bit is:

EPD0Meaning
0

Perform translation table walks using TTBR0.

1

A TLB miss on an address that is translated using TTBR0 generates a Translation fault. No translation table walk is performed.

When this register has an architecturally-defined reset value, this field resets to 0.

T2E, bit [6]
In ARMv8.3 and ARMv8.2:

TTBCR2 Enable.

Defined values are:

T2EMeaning
0

TTBCR2 is disabled. The contents of TTBCR2 are treated as 0 for all purposes other than reading or writing the register.

1

TTBCR2 is enabled.

If TTBCR.EAE==0, then the behavior is as if the bit is 0.

This bit is RES0 if ARMv8.2-AA32HPD is not implemented.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

Bits [5:3]

Reserved, RES0.

T0SZ, bits [2:0]

See 'Selecting between TTBR0 and TTBR1, VMSAv8-32 Long-descriptor translation table format' in the ARMv8 ARM for how TTBCR.{T1SZ, T0SZ} determine the input address ranges and memory region sizes translated using TTBR0 and TTBR1.

When this register has an architecturally-defined reset value, this field resets to 0.

Accessing the TTBCR

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 0, <Rt>, c2, c0, 2000010001011110000

Accessibility

The register is accessible as follows:

Configuration Control Accessibility Instance
E2HTGENSEL0EL1EL2EL3
EL3 not implemented xx0 - RW n/a n/a TTBCR
EL3 not implemented x01 - RWRW n/a TTBCR
EL3 not implemented x11 - n/a RW n/a TTBCR
EL3 using AArch64xx0 - RW n/a n/a TTBCR
EL3 using AArch64x01 - RWRW n/a TTBCR
EL3 using AArch64x11 - n/a RW n/a TTBCR
EL3 using AArch32x01 - RWRWRWTTBCR_ns
EL3 using AArch32x11 - n/a RWRWTTBCR_ns
EL3 using AArch32xx0 - n/a n/a RWTTBCR_s

This table applies to all instructions that can access this register.

When EL3 is using AArch32, write access to TTBCR_s is UNDEFINED when the CP15SDISABLE signal is asserted HIGH.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :




28/09/2017 08:24

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