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The PMBIDR_EL1 characteristics are:
Provides information to software as to whether the buffer can be programmed at the current Exception level.
This register is part of the Statistical Profiling Extension registers functional group.
Present only if the Statistical Profiling Extension is implemented. Direct reads of PMBIDR_EL1 are UNDEFINED at EL0.
PMBIDR_EL1 is a 64-bit register.
The PMBIDR_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | F | P | Align | |||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Flag Updates. Defines whether the address translation performed by the Profiling Buffer manages the Access Flag and Dirty Bit
F | Meaning |
---|---|
0b0 | Accesses to pages not marked with Access Flag and not with Dirty Bit set will generate an Unsupported Access fault if hardware management of those flags is enabled |
0b1 | Profiling Buffer address translation manages the Access Flag and Dirty Bit in the same way as the MMU on this PE |
Prohibited. The Profiling Buffer is owned by the current or a lower Exception level in the current security state.
P | Meaning |
---|---|
0b0 | Profiling Buffer is owned by the current or a lower Exception level in the current security state. This does not mean an access will not be trapped to a higher Exception level |
0b1 | Profiling Buffer is owned by a higher Exception level or the other security state |
The value read from this field depends on the current Exception level and the values of MDCR_EL3.NSPB and MDCR_EL2.E2PB:
Defines the minimum alignment constraint for PMBPTR_EL1. If this field is non-zero, then the PE must pad every record up to a multiple of this size.
Align | Meaning |
---|---|
0b0000 | Byte |
0b0001 | Halfword. PMBPTR_EL1[0] is RES0 |
0b0010 | Word. PMBPTR_EL1[1:0] is RES0 |
0b0011 | Doubleword. PMBPTR_EL1[2:0] is RES0 |
0b0100 | 16 Bytes. PMBPTR_EL1[3:0] is RES0 |
0b0101 | 32 Bytes. PMBPTR_EL1[4:0] is RES0 |
0b0110 | 64 Bytes. PMBPTR_EL1[5:0] is RES0 |
0b0111 | 128 Bytes. PMBPTR_EL1[6:0] is RES0 |
0b1000 | 256 Bytes. PMBPTR_EL1[7:0] is RES0 |
0b1001 | 512 Bytes. PMBPTR_EL1[8:0] is RES0 |
0b1010 | 1KB. PMBPTR_EL1[9:0] is RES0 |
0b1011 | 2KB. PMBPTR_EL1[10:0] is RES0 |
All other values are reserved. Reserved values might be defined in a future version of the architecture.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | CRn | op0 | op1 | op2 | CRm |
---|---|---|---|---|---|
PMBIDR_EL1 | 1001 | 11 | 000 | 111 | 1010 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
12/09/2017 18:03
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.
no old file | htmldiff from-SysReg_v83A_xml-00bet4 | (new) SysReg_v83A_xml-00bet5 |