ID_DFR0_EL1, AArch32 Debug Feature Register 0

The ID_DFR0_EL1 characteristics are:

Purpose

Provides top level information about the debug system in AArch32 state.

Must be interpreted with the Main ID Register, MIDR_EL1.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.

This register is part of the Identification registers functional group.

Configuration

AArch64 System register ID_DFR0_EL1 is architecturally mapped to AArch32 System register ID_DFR0.

In an implementation that supports only AArch64 state, this register is UNKNOWN.

Attributes

ID_DFR0_EL1 is a 32-bit register.

Field descriptions

The ID_DFR0_EL1 bit assignments are:

313029282726252423222120191817161514131211109876543210
0000PerfMonMProfDbgMMapTrcCopTrcMMapDbgCopSDbgCopDbg

Bits [31:28]

Reserved, RES0.

PerfMon, bits [27:24]

Performance Monitors. Support for System registers-based ARM Performance Monitors Extension, using registers in the coproc == 1111 encoding space, for A and R profile processors. Defined values are:

PerfMonMeaning
0000

Performance Monitors Extension System registers not implemented.

0001

Support for Performance Monitors Extension version 1 (PMUv1) System registers.

0010

Support for Performance Monitors Extension version 2 (PMUv2) System registers.

0011

Support for Performance Monitors Extension version 3 (PMUv3) System registers.

0100

Support for Performance Monitors Extension version 3 (PMUv3) System registers, with a 16-bit evtCount field.

1111

IMPLEMENTATION DEFINED form of Performance Monitors System registers supported. PMUv3 not supported.

All other values are reserved.

ARMv8.1-PMU implements the functionality added by the value 0100.

In any ARMv8 implementation the values 0001 and 0010 are not permitted.

From ARMv8.1 the value 0011 is not permitted.

Note

In ARMv7, the value 0000 can mean that PMUv1 is implemented. PMUv1 is not permitted in an ARMv8 implementation.

MProfDbg, bits [23:20]

M Profile Debug. Support for memory-mapped debug model for M profile processors. Defined values are:

MProfDbgMeaning
0000

Not supported.

0001

Support for M profile Debug architecture, with memory-mapped access.

All other values are reserved.

In ARMv8-A the only permitted value is 0000.

MMapTrc, bits [19:16]

Memory Mapped Trace. Support for memory-mapped trace model. Defined values are:

MMapTrcMeaning
0000

Not supported.

0001

Support for ARM trace architecture, with memory-mapped access.

All other values are reserved.

In ARMv8-A the permitted values are 0000 and 0001.

In the Trace registers, the ETMIDR gives more information about the implementation.

CopTrc, bits [15:12]

Support for System registers-based trace model, using registers in the coproc == 1110 encoding space. Defined values are:

CopTrcMeaning
0000

Not supported.

0001

Support for ARM trace architecture, with System registers access.

All other values are reserved.

In ARMv8-A the permitted values are 0000 and 0001.

In the Trace registers, the ETMIDR gives more information about the implementation.

MMapDbg, bits [11:8]

Memory Mapped Debug. Support for v7 memory-mapped debug model, for A and R profile processors.

In ARMv8-A this field is RES0.

The optional memory map defined by ARMv8 is not compatible with ARMv7.

CopSDbg, bits [7:4]

Support for a System registers-based Secure debug model, using registers in the coproc = 1110 encoding space, for an A profile processor that includes EL3.

If EL3 is not implemented and the implemented Security state is Non-Secure state, this field is RES0. Otherwise, this field reads the same as bits [3:0].

CopDbg, bits [3:0]

Support for System registers-based debug model, using registers in the coproc == 1110 encoding space, for A and R profile processors. Defined values are:

CopDbgMeaning
0000

Not supported.

0010

Support for ARMv6, v6 Debug architecture, with System registers access.

0011

Support for ARMv6, v6.1 Debug architecture, with System registers access.

0100

Support for ARMv7, v7 Debug architecture, with System registers access.

0101

Support for ARMv7, v7.1 Debug architecture, with System registers access.

0110

Support for ARMv8 debug architecture, with System registers access.

0111

Support for ARMv8 debug architecture, with System registers access, and Virtualization Host extensions.

1000

Support for ARMv8.2 debug architecture.

All other values are reserved.

ARMv8.2-Debug adds the functionality indicated by the value 1000.

Accessing the ID_DFR0_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
ID_DFR0_EL11100000000001010

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RO n/a RO
x01 - RORORO
x11 - n/a RORO

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :




28/09/2017 08:24

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