The CNTP_CTL_EL0 characteristics are:
Control register for the EL1 physical timer.
This register is part of the Generic Timer registers functional group.
AArch64 System register CNTP_CTL_EL0 is architecturally mapped to AArch32 System register CNTP_CTL.
RW fields in this register reset to architecturally UNKNOWN values.
CNTP_CTL_EL0 is a 32-bit register.
The CNTP_CTL_EL0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ISTATUS | IMASK | ENABLE |
Reserved, RES0.
The status of the timer. This bit indicates whether the timer condition is met:
ISTATUS | Meaning |
---|---|
0 |
Timer condition is not met. |
1 |
Timer condition is met. |
When the value of the ENABLE bit is 1, ISTATUS indicates whether the timer condition is met. ISTATUS takes no account of the value of the IMASK bit. If the value of ISTATUS is 1 and the value of IMASK is 0 then the timer interrupt is asserted.
When the value of the ENABLE bit is 0, the ISTATUS field is UNKNOWN.
For more information see 'Operation of the CompareValue views of the timers' and 'Operation of the TimerValue views of the timers' in the ARM ARM, chapter D6.
This bit is read-only.
Timer interrupt mask bit. Permitted values are:
IMASK | Meaning |
---|---|
0 |
Timer interrupt is not masked by the IMASK bit. |
1 |
Timer interrupt is masked by the IMASK bit. |
For more information, see the description of the ISTATUS bit.
Enables the timer. Permitted values are:
ENABLE | Meaning |
---|---|
0 |
Timer disabled. |
1 |
Timer enabled. |
Setting this bit to 0 disables the timer output signal, but the timer value accessible from CNTP_TVAL_EL0 continues to count down.
Disabling the output signal might be a power-saving option.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
CNTP_CTL_EL0 | 11 | 011 | 1110 | 0010 | 001 |
CNTP_CTL_EL02 | 11 | 101 | 1110 | 0010 | 001 |
The register is accessible as follows:
<systemreg> | Control | Accessibility | |||||
---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | |
CNTP_CTL_EL0 | x | x | 0 | RW | RW | n/a | RW |
CNTP_CTL_EL0 | 0 | 0 | 1 | RW | RW | RW | RW |
CNTP_CTL_EL0 | 0 | 1 | 1 | RW | n/a | RW | RW |
CNTP_CTL_EL0 | 1 | 0 | 1 | RW | RW | CNTHP_CTL_EL2 | RW |
CNTP_CTL_EL0 | 1 | 1 | 1 | CNTHP_CTL_EL2 | n/a | CNTHP_CTL_EL2 | RW |
CNTP_CTL_EL02 | x | x | 0 | - | - | n/a | - |
CNTP_CTL_EL02 | 0 | 0 | 1 | - | - | - | - |
CNTP_CTL_EL02 | 0 | 1 | 1 | - | n/a | - | - |
CNTP_CTL_EL02 | 1 | 0 | 1 | - | - | RW | RW |
CNTP_CTL_EL02 | 1 | 1 | 1 | - | n/a | RW | RW |
When HCR_EL2.E2H is 1, without explicit synchronization, access from EL3 using the mnemonic CNTP_CTL_EL0 or CNTP_CTL_EL02 are not guaranteed to be ordered with respect to accesses using the other mnemonic.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When HCR_EL2.E2H==0 :
If CNTKCTL_EL1.EL0PTEN==0, accesses to this register from EL0 are trapped to EL1.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If CNTHCTL_EL2.EL1PCEN==0, Non-secure accesses to this register from EL1 are trapped to EL2.
If CNTHCTL_EL2.EL1PCEN==0, and CNTKCTL_EL1.EL0PTEN==1, Non-secure accesses to this register from EL0 are trapped to EL2.
If HCR_EL2.NV==1, Non-secure accesses to this register from EL1 using accessor CNTP_CTL_EL02 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If CNTHCTL_EL2.EL1PTEN==0, Non-secure accesses to this register from EL1 are trapped to EL2.
If CNTHCTL_EL2.EL1PTEN==0, and CNTKCTL_EL1.EL0PTEN==1, Non-secure accesses to this register from EL0 are trapped to EL2.
If CNTKCTL_EL1.EL0PTEN==0, Non-secure accesses to this register from EL0 are trapped to EL1.
If HCR_EL2.NV==1, Non-secure accesses to this register from EL1 using accessor CNTP_CTL_EL02 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==1 :
If CNTHCTL_EL2.EL0PTEN==0, Non-secure accesses to this register from EL0 are trapped to EL2.
28/09/2017 08:24
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