ICV_CTLR_EL1, Interrupt Controller Virtual Control Register

The ICV_CTLR_EL1 characteristics are:

Purpose

Controls aspects of the behavior of the GIC virtual CPU interface and provides information about the features implemented.

This register is part of:

Configuration

AArch64 System register ICV_CTLR_EL1 is architecturally mapped to AArch32 System register ICV_CTLR.

Attributes

ICV_CTLR_EL1 is a 32-bit register.

Field descriptions

The ICV_CTLR_EL1 bit assignments are:

313029282726252423222120191817161514131211109876543210
0000000000000RSS00A3VSEISIDbitsPRIbits000000EOImodeCBPR

Bits [31:19]

Reserved, RES0.

RSS, bit [18]

Range Selector Support. Possible values are:

RSSMeaning
0

Targeted SGIs with affinity level 0 values of 0 - 15 are supported.

1

Targeted SGIs with affinity level 0 values of 0 - 255 are supported.

This bit is read-only.

Bits [17:16]

Reserved, RES0.

A3V, bit [15]

Affinity 3 Valid. Read-only and writes are ignored. Possible values are:

A3VMeaning
0

The virtual CPU interface logic only supports zero values of Affinity 3 in SGI generation System registers.

1

The virtual CPU interface logic supports non-zero values of Affinity 3 in SGI generation System registers.

SEIS, bit [14]

SEI Support. Read-only and writes are ignored. Indicates whether the virtual CPU interface supports local generation of SEIs:

SEISMeaning
0

The virtual CPU interface logic does not support local generation of SEIs.

1

The virtual CPU interface logic supports local generation of SEIs.

IDbits, bits [13:11]

Identifier bits. Read-only and writes are ignored. The number of virtual interrupt identifier bits supported:

IDbitsMeaning
000

16 bits.

001

24 bits.

All other values are reserved.

PRIbits, bits [10:8]

Priority bits. Read-only and writes are ignored. The number of priority bits implemented, minus one.

An implementation must implement at least 32 levels of physical priority (5 priority bits).

Note

This field always returns the number of priority bits implemented.

The division between group priority and subpriority is defined in the binary point registers ICV_BPR0_EL1 and ICV_BPR1_EL1.

Bits [7:2]

Reserved, RES0.

EOImode, bit [1]

Virtual EOI mode. Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt:

EOImodeMeaning
0

ICV_EOIR0_EL1 and ICV_EOIR1_EL1 provide both priority drop and interrupt deactivation functionality. Accesses to ICV_DIR_EL1 are UNPREDICTABLE.

1

ICV_EOIR0_EL1 and ICV_EOIR1_EL1 provide priority drop functionality only. ICV_DIR_EL1 provides interrupt deactivation functionality.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

CBPR, bit [0]

Common Binary Point Register. Controls whether the same register is used for interrupt preemption of both virtual Group 0 and virtual Group 1 interrupts:

CBPRMeaning
0

ICV_BPR0_EL1 determines the preemption group for virtual Group 0 interrupts only.

ICV_BPR1_EL1 determines the preemption group for virtual Group 1 interrupts.

1

ICV_BPR0_EL1 determines the preemption group for both virtual Group 0 and virtual Group 1 interrupts.

Reads of ICV_BPR1_EL1 return ICV_BPR0_EL1 plus one, saturated to 0b111. Writes to ICV_BPR1_EL1 are ignored.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Accessing the ICV_CTLR_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
ICC_CTLR_EL11100011001100100

When HCR_EL2.{FMO, IMO} == {0, 0}, execution of this encoding at Non-secure EL1 results in an access to ICC_CTLR_EL1.

Accessibility

The register is accessible as follows:

Control Accessibility
FMOIMOTGENSEL0EL1EL2EL3
xxx0 - ICC_CTLR_EL1 n/a ICC_CTLR_EL1
xx11 - n/a ICC_CTLR_EL1 ICC_CTLR_EL1
x101 - RW ICC_CTLR_EL1 ICC_CTLR_EL1
1x01 - RW ICC_CTLR_EL1 ICC_CTLR_EL1
0001 - ICC_CTLR_EL1 ICC_CTLR_EL1 ICC_CTLR_EL1

This table applies to all instructions that can access this register.

ICV_CTLR_EL1 is only accessible at Non-secure EL1 when HCR_EL2.{FMO, IMO} != {0, 0}.

Note

When HCR_EL2.{FMO, IMO} == {0, 0}, at Non-secure EL1, the instruction encoding used to access ICV_CTLR_EL1 results in an access to ICC_CTLR_EL1.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When SCR_EL3.NS==1 :




28/09/2017 08:24

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