The VMPIDR_EL2 characteristics are:
Holds the value of the Virtualization Multiprocessor ID. This is the value returned by Non-secure EL1 reads of MPIDR_EL1.
This register is part of:
AArch64 System register VMPIDR_EL2 bits [31:0] are architecturally mapped to AArch32 System register VMPIDR.
If EL2 is not implemented, reads of this register return the value of the MPIDR_EL1, and writes to the register are ignored.
RW fields in this register reset to architecturally UNKNOWN values.
VMPIDR_EL2 is a 64-bit register.
The VMPIDR_EL2 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Aff3 | |||||||
1 | U | 0 | 0 | 0 | 0 | 0 | MT | Aff2 | Aff1 | Aff0 | |||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Affinity level 3. Highest level affinity field.
Reserved, RES1.
Indicates a Uniprocessor system, as distinct from PE 0 in a multiprocessor system. The possible values of this bit are:
U | Meaning |
---|---|
0 |
Processor is part of a multiprocessor system. |
1 |
Processor is part of a uniprocessor system. |
Reserved, RES0.
Indicates whether the lowest level of affinity consists of logical PEs that are implemented using a multithreading type approach. The possible values of this bit are:
MT | Meaning |
---|---|
0 |
Performance of PEs at the lowest affinity level is largely independent. |
1 |
Performance of PEs at the lowest affinity level is very interdependent. |
Affinity level 2. Second highest level affinity field.
Affinity level 1. Third highest level affinity field.
Affinity level 0. Lowest level affinity field.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
VMPIDR_EL2 | 11 | 100 | 0000 | 0000 | 101 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | - | n/a | RW |
x | 0 | 1 | - | - | RW | RW |
x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.NV==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.NV==1, Non-secure accesses to this register from EL1 are trapped to EL2.
28/09/2017 08:24
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