The AMAIR0 characteristics are:
When using the Long-descriptor format translation tables for stage 1 translations, provides IMPLEMENTATION DEFINED memory attributes for the memory regions specified by MAIR0.
This register is part of:
AArch32 System register AMAIR0 is architecturally mapped to AArch64 System register AMAIR_EL1[31:0] .
When EL3 is using AArch32, write access to AMAIR0(S) is disabled when the CP15SDISABLE signal is asserted HIGH.
RW fields in this register reset to architecturally UNKNOWN values.
AMAIR0 is a 32-bit register.
The AMAIR0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED |
This register is RES0 in the following cases:
If EL3 is implemented and is using AArch32:
Any IMPLEMENTATION DEFINED memory attributes are additional qualifiers for the memory locations and must not change the architected behavior specified by MAIR0 and MAIR1.
In a typical implementation, AMAIR0 and AMAIR1 split into eight one-byte fields, corresponding to the MAIRn.Attr<n> fields, but the architecture does not require them to do so.
IMPLEMENTATION DEFINED.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c10, c3, 0 | 000 | 000 | 1010 | 1111 | 0011 |
The register is accessible as follows:
Configuration | Control | Accessibility | Instance | |||||
---|---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | ||
EL3 not implemented | x | x | 0 | - | RW | n/a | n/a | AMAIR0 |
EL3 not implemented | x | 0 | 1 | - | RW | RW | n/a | AMAIR0 |
EL3 not implemented | x | 1 | 1 | - | n/a | RW | n/a | AMAIR0 |
EL3 using AArch64 | x | x | 0 | - | RW | n/a | n/a | AMAIR0 |
EL3 using AArch64 | x | 0 | 1 | - | RW | RW | n/a | AMAIR0 |
EL3 using AArch64 | x | 1 | 1 | - | n/a | RW | n/a | AMAIR0 |
EL3 using AArch32 | x | 0 | 1 | - | RW | RW | RW | AMAIR0_ns |
EL3 using AArch32 | x | 1 | 1 | - | n/a | RW | RW | AMAIR0_ns |
EL3 using AArch32 | x | x | 0 | - | n/a | n/a | RW | AMAIR0_s |
This table applies to all instructions that can access this register.
When EL3 is using AArch32, write access to AMAIR0_s is UNDEFINED when the CP15SDISABLE signal is asserted HIGH.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TVM==1, Non-secure write accesses to this register from EL1 are trapped to EL2.
If HCR_EL2.TRVM==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HSTR_EL2.T10==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TVM==1, Non-secure write accesses to this register from EL1 are trapped to EL2.
If HCR_EL2.TRVM==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HSTR_EL2.T10==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
28/09/2017 08:24
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