TTBR1, Translation Table Base Register 1

The TTBR1 characteristics are:

Purpose

Holds the base address of the translation table for the initial lookup for stage 1 of the translation of an address from the higher VA range in the PL1&0 translation regime, and other information for this translation regime.

This register is part of the Virtual memory control registers functional group.

Configuration

AArch32 System register TTBR1 is architecturally mapped to AArch64 System register TTBR1_EL1.

TTBCR.EAE determines which TTBR1 format is used:

EAE==0
32-bit format is used. TTBR1[63:32] are ignored.
EAE==1
64-bit format is used.

Used in conjunction with the TTBCR. When the 64-bit TTBR1 format is used, cacheability and shareability information is held in the TTBCR, not in TTBR1.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

TTBR1 is a 64-bit register that can also be accessed as a 32-bit value. If it is accessed as a 32-bit register, accesses read and write bits [31:0] and do not modify bits [63:32].

Field descriptions

The TTBR1 bit assignments are:

When TTBCR.EAE==0:

313029282726252423222120191817161514131211109876543210
TTB1IRGN[0]NOSRGNIMPSIRGN[1]

TTB1, bits [31:7]

Translation table base address, bits[31:14]. Register bits [13:7] are RES0, with the additional requirement that if these bits are not all zero, this is a misaligned translation table base address, with effects that are CONSTRAINED UNPREDICTABLE, and must be one of the following:

IRGN[0], bit [6]

See the IRGN[1] description.

NOS, bit [5]

Not Outer Shareable. When the value of TTBR1.S is 1, indicates whether the memory associated with a translation table walk is Inner Shareable or Outer Shareable:

NOSMeaning
0

Memory is Outer Shareable.

1

Memory is Inner Shareable.

This bit is ignored when the value of TTBR1.S is 0.

RGN, bits [4:3]

Region bits. Indicates the Outer cacheability attributes for the memory associated with the translation table walks:

RGNMeaning
00

Normal memory, Outer Non-cacheable.

01

Normal memory, Outer Write-Back Write-Allocate Cacheable.

10

Normal memory, Outer Write-Through Cacheable.

11

Normal memory, Outer Write-Back no Write-Allocate Cacheable.

IMP, bit [2]

The effect of this bit is IMPLEMENTATION DEFINED. If the translation table implementation does not include any IMPLEMENTATION DEFINED features this bit is UNK/SBZP.

S, bit [1]

Shareable. Indicates whether the memory associated with the translation table walks is Non-shareable:

SMeaning
0

Memory is Non-shareable.

1

Memory is shareable. The TTBR1.NOS field indicates whether the memory is Inner Shareable or Outer Shareable.

IRGN[1], bit [0]

Inner region bits. IRGN[1:0] indicate the Inner Cacheability attributes for the memory associated with the translation table walks. The possible values of IRGN[1:0] are:

IRGNMeaning
00

Normal memory, Inner Non-cacheable.

01

Normal memory, Inner Write-Back Write-Allocate Cacheable.

10

Normal memory, Inner Write-Through Cacheable.

11

Normal memory, Inner Write-Back no Write-Allocate Cacheable.

Note

The encoding of the IRGN bits is counter-intuitive, with register bit[6] being IRGN[0] and register bit[0] being IRGN[1]. This encoding is chosen to give a consistent encoding of memory region types and to ensure that software written for ARMv7 without the Multiprocessing Extensions can run unmodified on an implementation that includes the functionality introduced by the ARMv7 Multiprocessing Extensions.

When TTBCR.EAE==1:

6362616059585756555453525150494847464544434241403938373635343332
00000000ASIDBADDR
BADDRCnP
313029282726252423222120191817161514131211109876543210

Bits [63:56]

Reserved, RES0.

ASID, bits [55:48]

An ASID for the translation table base address. The TTBCR.A1 field selects either TTBR0.ASID or TTBR1.ASID.

BADDR, bits [47:1]

Translation table base address, bits[47:x], Bits [x-1:1] are RES0, with the additional requirement that if bits[x-1:3] are not all zero, this is a misaligned translation table base address, with effects that are CONSTRAINED UNPREDICTABLE, and must be one of the following:

x is determined from the value of TTBCR.T1SZ as follows:

If bits[47:40] of the translation table base address are not zero, an Address size fault is generated.

CnP, bit [0]
In ARMv8.3 and ARMv8.2:

Common not Private. In an implementation that includes ARMv8.2-TTCNP, when TTBCR.EAE ==1, indicates whether each entry that is pointed to by TTBR1 is a member of a common set that can be used by every PE in the Inner Shareable domain for which the value of TTBR1.CnP is 1.

CnPMeaning
0

The translation table entries pointed to by this instance of TTBR1, for the current ASID, are permitted to differ from corresponding entries for this instance of TTBR1 for other PEs in the Inner Shareable domain. This is not affected by:

  • The value of TTBR1.CnP on those other PEs.
  • The value of TTBCR.EAE on those other PEs.
  • The value of the current ASID or, for the Non-secure instance of TTBR1, the value of the current VMID.
1

The translation table entries pointed to by this instance of TTBR1 are the same as the translation table entries for every other PE in the Inner Shareable domain for which the value of TTBR1.CnP is 1 for this instance of TTBR1 and all of the following apply:

  • The translation table entries are pointed to by this instance of TTBR1.
  • The value of the applicable TTBCR.EAE field is 1.
  • The ASID is the same as the current ASID.
  • For the Non-secure instance of TTBR1, the VMID is the same as the current VMID.

When a TLB combines entries from stage 1 translation and stage 2 translation into a single entry, that entry can only be shared between different PEs if the value of the CnP bit is 1 for both stage 1 and stage 2.

Note

If the value of the TTBR1.CnP bit is 1 on multiple PEs in the same Inner Shareable domain and those TTBR1s do not point to the same translation table entries when the other conditions specified for the case when the value of CnP is 1 apply, then the results of translations are CONSTRAINED UNPREDICTABLE, see 'CONSTRAINED UNPREDICTABLE behaviors due to caching of control or data values' in the ARMv8-A ARM appendix K1.

In an implementation that does not include ARMv8.2-TTCNP this field is RES0.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

Accessing the TTBR1

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 0, <Rt>, c2, c0, 1000001001011110000

This register can be read using MRRC with the following syntax:

MRRC <syntax>

This register can be written using MCRR with the following syntax:

MCRR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1coprocCRm
p15, 1, <Rt>, <Rt2>, c2000111110010

Accessibility

The register is accessible as follows:

Configuration Control Accessibility Instance
E2HTGENSEL0EL1EL2EL3
EL3 not implemented xx0 - RW n/a n/a TTBR1
EL3 not implemented x01 - RWRW n/a TTBR1
EL3 not implemented x11 - n/a RW n/a TTBR1
EL3 using AArch64xx0 - RW n/a n/a TTBR1
EL3 using AArch64x01 - RWRW n/a TTBR1
EL3 using AArch64x11 - n/a RW n/a TTBR1
EL3 using AArch32x01 - RWRWRWTTBR1_ns
EL3 using AArch32x11 - n/a RWRWTTBR1_ns
EL3 using AArch32xx0 - n/a n/a RWTTBR1_s

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :




28/09/2017 08:24

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