CNTNSAR, Counter-timer Non-secure Access Register

The CNTNSAR characteristics are:

Purpose

Provides the highest-level control of whether frames CNTBaseN and CNTEL0BaseN are accessible by Non-secure accesses.

This register is part of the Generic Timer registers functional group.

Usage constraints

This register is accessible as follows:

Default
RW

In a system that recognizes two Security states, this register is only accessible by Secure accesses.

Configuration

The power domain of CNTNSAR is IMPLEMENTATION DEFINED.

On a reset of the reset domain in which it is implemented, RW fields in this register reset to UNKNOWN values. The register is not affected by a reset of any other reset domain. For more information see 'Power and reset domains for the system level implementation of the Generic Timer' in Chapter I1 of the ARMv8 ARM.

Attributes

CNTNSAR is a 32-bit register.

Field descriptions

The CNTNSAR bit assignments are:

313029282726252423222120191817161514131211109876543210
000000000000000000000000NS7NS6NS5NS4NS3NS2NS1NS0

Bits [31:8]

Reserved, RES0.

NS<n>, bit [n], for n = 0 to 7

Non-secure access to frame n. The possible values of this bit are:

NS<n>Meaning
0

Secure access only. Behaves as RES0 to Non-secure accesses.

1

Secure and Non-secure accesses permitted.

This bit also determines whether, in the CNTCTLBase frame, CNTACR<n> and CNTVOFF<n> are accessible to Non-secure accesses.

If frame CNTBase<n>:

Accessing the CNTNSAR

CNTNSAR can be accessed through its memory-mapped interface:

ComponentFrameOffset
TimerCNTCTLBase 0x004



28/09/2017 08:24

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