The PMSIDR_EL1 characteristics are:
Describes the Statistical Profiling implementation to software
This register is part of the Statistical Profiling Extension registers functional group.
Present only if the Statistical Profiling Extension is implemented. Direct reads of PMSIDR_EL1 are UNDEFINED otherwise.
PMSIDR_EL1 is a 64-bit register.
The PMSIDR_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CountSize | MaxSize | Interval | 0 | 0 | ERnd | LDS | ArchInst | FL | FT | FE | |||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Reserved, RES0.
Defines the size of the counters
CountSize | Meaning |
---|---|
0b0010 |
12-bit saturating counters |
All other values are reserved. Reserved values might be defined in a future version of the architecture.
Defines the largest size for a single record, rounded up to a power-of-two. If this is the same as the minimum alignment (PMBIDR_EL1.Align), then each record is exactly this size
MaxSize | Meaning |
---|---|
0b0100 |
16 bytes |
0b0101 |
32 bytes |
0b0110 |
64 bytes |
0b0111 |
128 bytes |
0b1000 |
256 bytes |
0b1001 |
512 bytes |
0b1010 |
1024 bytes |
0b1011 |
2KB |
All other values are reserved. Reserved values might be defined in a future version of the architecture.
Recommended minimum sampling interval. This provides guidance from the implementer to the smallest minimum sampling interval, N.
Interval | Meaning |
---|---|
0b0000 |
256 |
0b0010 |
512 |
0b0011 |
768 |
0b0100 |
1,024 |
0b0101 |
1,536 |
0b0110 |
2,048 |
0b0111 |
3,072 |
0b1000 |
4,096 |
All other values are reserved. Reserved values might be defined in a future version of the architecture.
Defines how the random number generator is used in determining the interval between samples, when enabled by PMSIRR_EL1.RND.
ERnd | Meaning |
---|---|
0b0 |
The random number is added at the start of the interval, and the sample is taken and a new interval started when the combined interval expires. |
0b1 |
The random number is added and the new interval started after the interval programmed in PMSIRR_EL1.INTERVAL expires, and the sample is taken when the random interval expires. |
Data source indicator for sampled load instructions
LDS | Meaning |
---|---|
0b0 |
Loaded data source not implemented |
0b1 |
Loaded data source implemented |
Architectural instruction profiling
ArchInst | Meaning |
---|---|
0b0 |
Micro-op sampling implemented |
0b1 |
Architecture instruction sampling implemented |
Filtering by latency. This bit is RAO.
Filtering by operation type. This bit is RAO.
Filtering by events. This bit is RAO.
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | CRn | op0 | op1 | op2 | CRm |
---|---|---|---|---|---|
PMSIDR_EL1 | 1001 | 11 | 000 | 111 | 1001 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RW | n/a | RW |
x | 0 | 1 | - | RW | RW | RW |
x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
If AArch64-MDCR_EL2.TPMS == 0b1 && AArch64-SCR_EL3.NS == 0b1, then access from EL1 traps to EL2
If AArch64-MDCR_EL3.NSPB != 0b01 && AArch64-SCR_EL3.NS == 0b0, then access from EL1 traps to EL3
If AArch64-MDCR_EL3.NSPB != 0b11 && AArch64-SCR_EL3.NS == 0b1, then access from EL2 or EL1 traps to EL3
12/09/2017 18:03
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