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CNTHV_TVAL_EL2, Counter-timer Virtual Timer TimerValue register (EL2)

The CNTHV_TVAL_EL2 characteristics are:

Purpose

Holds the timer value for the EL2 virtual timer.

This register is part of the Generic Timer registers functional group.

Configuration

AArch64 System register CNTHV_TVAL_EL2 is architecturally mapped to AArch32 System register CNTHV_TVAL.

If EL2 is not implemented, this register is RES0 from EL3.

RW fields in this register reset to architecturally UNKNOWN values.

This register is introduced in ARMv8.1.

Attributes

CNTHV_TVAL_EL2 is a 32-bit register.

Field descriptions

The CNTHV_TVAL_EL2 bit assignments are:

313029282726252423222120191817161514131211109876543210
TimerValue

TimerValue, bits [31:0]

The TimerValue view of the EL2 virtual timer.

On a read of this register:

On a write of this register, CNTHV_CVAL_EL2 is set to (CNTVCT_EL0 + TimerValue), where TimerValue is treated as a signed 32-bit integer.

When CNTHV_CTL_EL2.ENABLE is 1, the timer condition is met when ((CNTVCT_EL0 - CNTHV_CVAL_EL2) is greater than or equal to zero. This means that TimerValue acts like a 32-bit downcounter timer. When the timer condition is met:

When CNTHV_CTL_EL2.ENABLE is 0, the timer condition is not met, but CNTVCT_EL0 continues to count, so the TimerValue view appears to continue to count down.

Accessing the CNTHV_TVAL_EL2

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
CNTHV_TVAL_EL21110011100011000
CNTV_TVAL_EL01101111100011000

Accessibility

The register is accessible as follows:

<systemreg> Control Accessibility
E2HTGENSEL0EL1EL2EL3
CNTHV_TVAL_EL2xx0 - - n/a RW
CNTHV_TVAL_EL2001 - - RWRW
CNTHV_TVAL_EL2011 - n/a RWRW
CNTHV_TVAL_EL2101 - - RWRW
CNTHV_TVAL_EL2111 - n/a RWRW
CNTV_TVAL_EL0xx0 CNTV_TVAL_EL0 CNTV_TVAL_EL0 n/a CNTV_TVAL_EL0
CNTV_TVAL_EL0001 CNTV_TVAL_EL0 CNTV_TVAL_EL0 CNTV_TVAL_EL0 CNTV_TVAL_EL0
CNTV_TVAL_EL0011 CNTV_TVAL_EL0 n/a CNTV_TVAL_EL0 CNTV_TVAL_EL0
CNTV_TVAL_EL0101 CNTV_TVAL_EL0 CNTV_TVAL_EL0 RW CNTV_TVAL_EL0
CNTV_TVAL_EL0111RW n/a RW CNTV_TVAL_EL0

When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic CNTHV_TVAL_EL2 or CNTV_TVAL_EL0 are not guaranteed to be ordered with respect to accesses using the other mnemonic.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==1 :




28/0907/2017 0816:2440

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