The CONTEXTIDR_EL2 characteristics are:
When ARMv8.1-VHE is implemented and HCR_EL2.E2H is set to 1, identifies the current Process Identifier.
The value of the whole of this register is called the Context ID and is used by:
The significance of this register is for debug and trace use only.
In ARMv8.0, or when ARMv8.1-VHE is implemented and HCR_EL2.E2H is 0, CONTEXTIDR_EL1 is used.
This register is part of the Virtual memory control registers functional group.
If EL2 is not implemented, this register is RES0 from EL3.
RW fields in this register reset to architecturally UNKNOWN values.
This register is introduced in ARMv8.1.
CONTEXTIDR_EL2 is a 32-bit register.
The CONTEXTIDR_EL2 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PROCID |
Process Identifier. This field must be programmed with a unique value that identifies the current process.
In AArch32 state, when TTBCR.EAE is set to 0, CONTEXTIDR.ASID holds the ASID.
In AArch64 state, CONTEXTIDR_EL2 is independent of the ASID, and for the EL2&0 translation regime either TTBR0_EL2 or TTBR1_EL2 holds the ASID.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
CONTEXTIDR_EL2 | 11 | 100 | 1101 | 0000 | 001 |
CONTEXTIDR_EL1 | 11 | 000 | 1101 | 0000 | 001 |
The register is accessible as follows:
<systemreg> | Control | Accessibility | |||||
---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | |
CONTEXTIDR_EL2 | x | x | 0 | - | - | n/a | RW |
CONTEXTIDR_EL2 | 0 | 0 | 1 | - | - | RW | RW |
CONTEXTIDR_EL2 | 0 | 1 | 1 | - | n/a | RW | RW |
CONTEXTIDR_EL2 | 1 | 0 | 1 | - | - | RW | RW |
CONTEXTIDR_EL2 | 1 | 1 | 1 | - | n/a | RW | RW |
CONTEXTIDR_EL1 | x | x | 0 | - | CONTEXTIDR_EL1 | n/a | CONTEXTIDR_EL1 |
CONTEXTIDR_EL1 | 0 | 0 | 1 | - | CONTEXTIDR_EL1 | CONTEXTIDR_EL1 | CONTEXTIDR_EL1 |
CONTEXTIDR_EL1 | 0 | 1 | 1 | - | n/a | CONTEXTIDR_EL1 | CONTEXTIDR_EL1 |
CONTEXTIDR_EL1 | 1 | 0 | 1 | - | CONTEXTIDR_EL1 | RW | CONTEXTIDR_EL1 |
CONTEXTIDR_EL1 | 1 | 1 | 1 | - | n/a | RW | CONTEXTIDR_EL1 |
When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic CONTEXTIDR_EL2 or CONTEXTIDR_EL1 are not guaranteed to be ordered with respect to accesses using the other mnemonic.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.NV==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.NV==1, Non-secure accesses to this register from EL1 are trapped to EL2.
28/09/2017 08:24
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