The DBGOSLAR characteristics are:
Provides a lock for the debug registers. The OS lock also disables some debug exceptions and debug events.
This register is part of the Debug registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register DBGOSLAR is architecturally mapped to AArch64 System register OSLAR_EL1.
AArch32 System register DBGOSLAR is architecturally mapped to External register OSLAR_EL1.
DBGOSLAR is a 32-bit register.
The DBGOSLAR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OS Lock Access |
OS Lock Access. Writing the value 0xC5ACCE55 to the DBGOSLAR sets the OS lock to 1. Writing any other value sets the OS lock to 0.
Use DBGOSLSR.OSLK to check the current status of the lock.
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p14, 0, <Rt>, c1, c0, 4 | 000 | 100 | 0001 | 1110 | 0000 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | WO | n/a | WO |
x | 0 | 1 | - | WO | WO | WO |
x | 1 | 1 | - | n/a | WO | WO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TDOSA==1, Non-secure write accesses to this register from EL1 are trapped to EL2 using AArch64.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HDCR.TDOSA==1, Non-secure write accesses to this register from EL1 are trapped to Hyp mode.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TDOSA==1, write accesses to this register from EL1 and EL2 are trapped to EL3 using AArch64.
28/09/2017 08:24
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