DBGVCR, Debug Vector Catch Register

The DBGVCR characteristics are:

Purpose

Controls Vector Catch debug events.

This register is part of the Debug registers functional group.

Configuration

There is one instance of this register that is used in both Secure and Non-secure states.

AArch32 System register DBGVCR is architecturally mapped to AArch64 System register DBGVCR32_EL2.

This register is required in all implementations.

This register is in the Warm reset domain. On a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.

Attributes

DBGVCR is a 32-bit register.

Field descriptions

The DBGVCR bit assignments are:

When EL3 implemented and using AArch32:

313029282726252423222120191817161514131211109876543210
NSFNSI0NSDNSPNSSNSU000000000MFMI0MDMPMS00SFSI0SDSPSSSU0

NSF, bit [31]

FIQ vector catch enable in Non-secure state.

The exception vector offset is 0x1C.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

NSI, bit [30]

IRQ vector catch enable in Non-secure state.

The exception vector offset is 0x18.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bit [29]

Reserved, RES0.

NSD, bit [28]

Data Abort vector catch enable in Non-secure state.

The exception vector offset is 0x10.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

NSP, bit [27]

Prefetch Abort vector catch enable in Non-secure state.

The exception vector offset is 0x0C.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

NSS, bit [26]

Supervisor Call (SVC) vector catch enable in Non-secure state.

The exception vector offset is 0x08.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

NSU, bit [25]

Undefined Instruction vector catch enable in Non-secure state.

The exception vector offset is 0x04.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bits [24:16]

Reserved, RES0.

MF, bit [15]

FIQ vector catch enable in Monitor mode.

The exception vector offset is 0x1C.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

MI, bit [14]

IRQ vector catch enable in Monitor mode.

The exception vector offset is 0x18.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bit [13]

Reserved, RES0.

MD, bit [12]

Data Abort vector catch enable in Monitor mode.

The exception vector offset is 0x10.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

MP, bit [11]

Prefetch Abort vector catch enable in Monitor mode.

The exception vector offset is 0x0C.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

MS, bit [10]

Secure Monitor Call (SMC) vector catch enable in Monitor mode.

The exception vector offset is 0x08.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bits [9:8]

Reserved, RES0.

SF, bit [7]

FIQ vector catch enable in Secure state.

The exception vector offset is 0x1C.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

SI, bit [6]

IRQ vector catch enable in Secure state.

The exception vector offset is 0x18.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bit [5]

Reserved, RES0.

SD, bit [4]

Data Abort vector catch enable in Secure state.

The exception vector offset is 0x10.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

SP, bit [3]

Prefetch Abort vector catch enable in Secure state.

The exception vector offset is 0x0C.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

SS, bit [2]

Supervisor Call (SVC) vector catch enable in Secure state.

The exception vector offset is 0x08.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

SU, bit [1]

Undefined Instruction vector catch enable in Secure state.

The exception vector offset is 0x04.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bit [0]

Reserved, RES0.

When EL3 implemented and using AArch64:

313029282726252423222120191817161514131211109876543210
NSFNSI0NSDNSPNSSNSU00000000000000000SFSI0SDSPSSSU0

NSF, bit [31]

FIQ vector catch enable in Non-secure state.

The exception vector offset is 0x1C.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

NSI, bit [30]

IRQ vector catch enable in Non-secure state.

The exception vector offset is 0x18.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bit [29]

Reserved, RES0.

NSD, bit [28]

Data Abort vector catch enable in Non-secure state.

The exception vector offset is 0x10.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

NSP, bit [27]

Prefetch Abort vector catch enable in Non-secure state.

The exception vector offset is 0x0C.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

NSS, bit [26]

Supervisor Call (SVC) vector catch enable in Non-secure state.

The exception vector offset is 0x08.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

NSU, bit [25]

Undefined Instruction vector catch enable in Non-secure state.

The exception vector offset is 0x04.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bits [24:8]

Reserved, RES0.

SF, bit [7]

FIQ vector catch enable in Secure state.

The exception vector offset is 0x1C.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

SI, bit [6]

IRQ vector catch enable in Secure state.

The exception vector offset is 0x18.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bit [5]

Reserved, RES0.

SD, bit [4]

Data Abort vector catch enable in Secure state.

The exception vector offset is 0x10.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

SP, bit [3]

Prefetch Abort vector catch enable in Secure state.

The exception vector offset is 0x0C.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

SS, bit [2]

Supervisor Call (SVC) vector catch enable in Secure state.

The exception vector offset is 0x08.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

SU, bit [1]

Undefined Instruction vector catch enable in Secure state.

The exception vector offset is 0x04.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bit [0]

Reserved, RES0.

When EL3 not implemented:

313029282726252423222120191817161514131211109876543210
000000000000000000000000FI0DPSU0

Bits [31:8]

Reserved, RES0.

F, bit [7]

FIQ vector catch enable.

The exception vector offset is 0x1C.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

I, bit [6]

IRQ vector catch enable.

The exception vector offset is 0x18.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bit [5]

Reserved, RES0.

D, bit [4]

Data Abort vector catch enable.

The exception vector offset is 0x10.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

P, bit [3]

Prefetch Abort vector catch enable.

The exception vector offset 0x0C.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

S, bit [2]

Supervisor Call (SVC) vector catch enable.

The exception vector offset is 0x08.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

U, bit [1]

Undefined Instruction vector catch enable.

The exception vector offset is 0x04.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bit [0]

Reserved, RES0.

Accessing the DBGVCR

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p14, 0, <Rt>, c0, c7, 0000000000011100111

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RW n/a RW
x01 - RWRWRW
x11 - n/a RWRW

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :

When EL3 is implemented and is using AArch64 :




28/09/2017 08:24

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