The DBGWCR<n>_EL1 characteristics are:
Holds control information for a watchpoint. Forms watchpoint n together with value register DBGWVR<n>_EL1.
This register is part of the Debug registers functional group.
AArch64 System register DBGWCR<n>_EL1 is architecturally mapped to AArch32 System register DBGWCR<n>.
AArch64 System register DBGWCR<n>_EL1 is architecturally mapped to External register DBGWCR<n>_EL1.
If breakpoint n is not implemented then this register is unallocated.
This register is in the Cold reset domain. On a Cold reset RW fields in this register reset to architecturally UNKNOWN values. The register is not affected by a Warm reset.
DBGWCR<n>_EL1 is a 32-bit register.
The DBGWCR<n>_EL1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | MASK | 0 | 0 | 0 | WT | LBN | SSC | HMC | BAS | LSC | PAC | E |
Reserved, RES0.
Address mask. Only objects up to 2GB can be watched using a single mask.
MASK | Meaning |
---|---|
00000 |
No mask. |
00001 |
Reserved. |
00010 |
Reserved. |
If programmed with a reserved value, a watchpoint must behave as if either:
Software must not rely on this property because the behavior of reserved values might change in a future revision of the architecture.
Other values mask the corresponding number of address bits, from 0b00011 masking 3 address bits (0x00000007 mask for address) to 0b11111 masking 31 address bits (0x7FFFFFFF mask for address).
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Reserved, RES0.
Watchpoint type. Possible values are:
WT | Meaning |
---|---|
0 |
Unlinked data address match. |
1 |
Linked data address match. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Linked breakpoint number. For Linked data address watchpoints, this specifies the index of the Context-matching breakpoint linked to.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Security state control. Determines the Security states under which a Watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the HMC and PAC fields.
For more information on the operation of the SSC, HMC, and PAC fields, see 'Execution conditions for which a watchpoint generates Watchpoint exceptions' in the ARMv8 ARM, section D2 (AArch64 Self-hosted Debug).
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Higher mode control. Determines the debug perspective for deciding when a Watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and PAC fields.
For more information on the operation of the SSC, HMC, and PAC fields, see 'Execution conditions for which a watchpoint generates Watchpoint exceptions' in the ARMv8 ARM, section D2 (AArch64 Self-hosted Debug).
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Byte address select. Each bit of this field selects whether a byte from within the word or double-word addressed by DBGWVR<n>_EL1 is being watched.
BAS | Description |
---|---|
xxxxxxx1 | Match byte at DBGWVR<n>_EL1 |
xxxxxx1x | Match byte at DBGWVR<n>_EL1+1 |
xxxxx1xx | Match byte at DBGWVR<n>_EL1+2 |
xxxx1xxx | Match byte at DBGWVR<n>_EL1+3 |
In cases where DBGWVR<n>_EL1 addresses a double-word:
BAS | Description, if DBGWVR<n>_EL1[2] == 0 |
---|---|
xxx1xxxx | Match byte at DBGWVR<n>_EL1+4 |
xx1xxxxx | Match byte at DBGWVR<n>_EL1+5 |
x1xxxxxx | Match byte at DBGWVR<n>_EL1+6 |
1xxxxxxx | Match byte at DBGWVR<n>_EL1+7 |
If DBGWVR<n>_EL1[2] == 1, only BAS[3:0] are used and BAS[7:4] are ignored. ARM deprecates setting DBGWVR<n>_EL1[2] == 1.
The valid values for BAS are non-zero binary numbers all of whose set bits are contiguous. All other values are reserved and must not be used by software. See 'Reserved DBGWCR<n>_EL1.BAS values' in the ARMv8 ARM, section D2 (AArch64 Self-hosted Debug).
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Load/store control. This field enables watchpoint matching on the type of access being made. Possible values of this field are:
LSC | Meaning |
---|---|
01 |
Match instructions that load from a watchpointed address. |
10 |
Match instructions that store to a watchpointed address. |
11 |
Match instructions that load from or store to a watchpointed address. |
All other values are reserved, but must behave as if the watchpoint is disabled. Software must not rely on this property as the behavior of reserved values might change in a future revision of the architecture.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Privilege of access control. Determines the Exception level or levels at which a Watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and HMC fields.
For more information on the operation of the SSC, HMC, and PAC fields, see 'Execution conditions for which a watchpoint generates Watchpoint exceptions' in the ARMv8 ARM, section D2 (AArch64 Self-hosted Debug).
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Enable watchpoint n. Possible values are:
E | Meaning |
---|---|
0 |
Watchpoint disabled. |
1 |
Watchpoint enabled. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
DBGWCR<n>_EL1 | 10 | 000 | 0000 | n<3:0> | 111 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RW | n/a | RW |
x | 0 | 1 | - | RW | RW | RW |
x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If EDSCR.TDA==1, and OSLSR_EL1.OSLK==0, and halting is allowed, accesses to this register from EL1, EL2, and EL3 generate a Software Access debug event.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TDA==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TDA==1, accesses to this register from EL1 and EL2 are trapped to EL3.
28/09/2017 08:24
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.