The SDER32_EL3 characteristics are:
Allows access to the AArch32 register SDER from AArch64 state only. Its value has no effect on execution in AArch64 state.
This register is part of:
AArch64 System register SDER32_EL3 is architecturally mapped to AArch32 System register SDER.
If EL1 is AArch64 only, this register is UNDEFINED.
This register is in the Warm reset domain. On a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.
SDER32_EL3 is a 32-bit register.
The SDER32_EL3 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SUNIDEN | SUIDEN |
Reserved, RES0.
Secure User Non-Invasive Debug Enable:
SUNIDEN | Meaning |
---|---|
0 |
Performance Monitors event counting prohibited in Secure EL0 unless allowed by MDCR_EL3.SPME or the IMPLEMENTATION DEFINED authentication interface ExternalSecureNoninvasiveDebugEnabled(). |
1 |
Performance Monitors event counting allowed in Secure EL0. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Secure User Invasive Debug Enable:
SUIDEN | Meaning |
---|---|
0 |
Debug exceptions other than Breakpoint Instruction exceptions from Secure EL0 are disabled, unless enabled by MDCR_EL3.SPD32. |
1 |
Debug exceptions from Secure EL0 are enabled. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
SDER_EL3 | 11 | 110 | 0001 | 0001 | 001 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | - | n/a | RW |
x | 0 | 1 | - | - | - | RW |
x | 1 | 1 | - | n/a | - | RW |
This table applies to all instructions that can access this register.
28/09/2017 08:24
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