The AT S1E2W characteristics are:
Performs stage 1 address translation as defined for EL2, with permissions as if writing to the given virtual address.
This System instruction is part of the Address translation instructions functional group.
There are no configuration notes.
AT S1E2W is a 64-bit System instruction.
The AT S1E2W input value bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
Input address for translation | |||||||||||||||||||||||||||||||
Input address for translation | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Input address for translation. The resulting address can be read from the PAR_EL1.
If the address translation instructions are targeting a translation regime that is using AArch32, and so has a VA of only 32 bits, then VA[63:32] is RES0.
This instruction is executed using AT with the following syntax:
AT <at_op>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<at_op> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
S1E2W | 01 | 100 | 0111 | 1000 | 001 |
The instruction is executable as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | - | n/a | - |
0 | 0 | 1 | - | - | WO | WO |
0 | 1 | 1 | - | n/a | WO | WO |
1 | 0 | 1 | - | - | WO | WO |
1 | 1 | 1 | - | n/a | WO | WO |
This table applies to all syntax that can be used to execute this instruction.
If EL2 is not implemented, this instruction is UNDEFINED at EL3.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when executing this System instruction.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.NV==1, Non-secure execution of this instruction at EL1 is trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.NV==1, Non-secure execution of this instruction at EL1 is trapped to EL2.
28/09/2017 08:24
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