ID_AA64ISAR1_EL1, AArch64 Instruction Set Attribute Register 1

The ID_AA64ISAR1_EL1 characteristics are:

Purpose

Provides information about the features and instructions implemented in AArch64 state.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.

This register is part of the Identification registers functional group.

Configuration

There are no configuration notes.

Attributes

ID_AA64ISAR1_EL1 is a 64-bit register.

Field descriptions

The ID_AA64ISAR1_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
00000000000000000000000000000000
GPIGPALRCPCFCMAJSCVTAPIAPADPB
313029282726252423222120191817161514131211109876543210

Bits [63:32]

Reserved, RES0.

GPI, bits [31:28]
In ARMv8.3:

Indicates whether an IMPLEMENTATION DEFINED algorithm is implemented in the PE for generic code authentication, in AArch64 state. Defined values are:

GPIMeaning
0000

Generic Authentication using an IMPLEMENTATION DEFINED algorithm is not implemented.

0001

Generic Authentication using an IMPLEMENTATION DEFINED algorithm is implemented. This involves the PACGA instruction.

All other values are reserved.


In ARMv8.2, ARMv8.1 and ARMv8.0:

Reserved, RES0.

GPA, bits [27:24]
In ARMv8.3:

Indicates whether QARMA or Architected algorithm is implemented in the PE for generic code authentication, in AArch64 state. Defined values are:

GPAMeaning
0000

Generic Authentication using an Architected algorithm is not implemented.

0001

Generic Authentication using the QARMA algorithm is implemented. This involves the PACGA instruction.

All other values are reserved.


In ARMv8.2, ARMv8.1 and ARMv8.0:

Reserved, RES0.

LRCPC, bits [23:20]
In ARMv8.3:

Indicates support for weaker release consistency, RCpc based model. Defined values are:

LRCPCMeaning
0000

The LDAPRB, LDAPRH and LDAPR instructions are not implemented.

0001

The LDAPRB, LDAPRH and LDAPR instructions are implemented.

All other values are reserved.

In ARMv8.0, ARMv8.1 and ARMv8.2 the only permitted value is 0000.

From ARMv8.3 the only permitted value is 0001. This feature is identified as ARMv8.3-RCPC.


In ARMv8.2, ARMv8.1 and ARMv8.0:

Reserved, RES0.

FCMA, bits [19:16]
In ARMv8.3:

Indicates support for complex number addition and multiplication where numbers are stored in vectors. Defined values are:

FCMAMeaning
0000

The FCMLA and FCADD instructions are not implemented.

0001

The FCMLA and FCADD instructions are implemented.

All other values are reserved.

In ARMv8.0, ARMv8.1 and ARMv8.2 the only permitted value is 0000.

From ARMv8.3 the only permitted value is 0001. This feature is identified as ARMv8.3-CompNum.


In ARMv8.2, ARMv8.1 and ARMv8.0:

Reserved, RES0.

JSCVT, bits [15:12]
In ARMv8.3:

Indicates support for javascript conversion from double precision floating point values to integers in AArch64 state. Defined values are:

JSCVTMeaning
0000

The FJCVTZS instruction is not implemented.

0001

The FJCVTZS instruction is implemented.

All other values are reserved.

In ARMv8.0, ARMv8.1 and ARMv8.2 the only permitted value is 0000.

From ARMv8.3 the only permitted value is 0001. This feature is identified as ARMv8.3-JSConv.


In ARMv8.2, ARMv8.1 and ARMv8.0:

Reserved, RES0.

API, bits [11:8]
In ARMv8.3:

Indicates whether an IMPLEMENTATION DEFINED algorithm is implemented in the PE for address authentication, in AArch64 state. Defined values are:

APIMeaning
0000

Address Authentication using an IMPLEMENTATION DEFINED algorithm is not implemented.

0001

Address Authentication using an IMPLEMENTATION DEFINED algorithm is implemented. This involves all Pointer Authentication instructions other than the PACGA instruction.

All other values are reserved.


In ARMv8.2, ARMv8.1 and ARMv8.0:

Reserved, RES0.

APA, bits [7:4]
In ARMv8.3:

Indicates whether QARMA or Architected algorithm is implemented in the PE for address authentication, in AArch64 state. Defined values are:

APAMeaning
0000

Address Authentication using an Architected algorithm is not implemented.

0001

Address Authentication using the QARMA algorithm is implemented. This involves all Pointer Authentication instructions other than the PACGA instruction.

All other values are reserved.


In ARMv8.2, ARMv8.1 and ARMv8.0:

Reserved, RES0.

DPB, bits [3:0]
In ARMv8.3 and ARMv8.2:

Indicates support for the DC CVAP instruction in AArch64 state. Defined values are:

DPBMeaning
0000

DC CVAP not supported.

0001

DC CVAP supported.

All other values are reserved.

ARMv8.2-DCPoP implements the functionality identified by the value 0001.

From ARMv8.2 the only permitted value is 0001.


In ARMv8.1 and ARMv8.0:

Reserved, RES0.

If API == 0000 and APA == 0000, then:

If API == 0000 and APA == 0000 and GPI == 0000 and GPA == 0000, then:

Accessing the ID_AA64ISAR1_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
ID_AA64ISAR1_EL11100000000110001

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RO n/a RO
x01 - RORORO
x11 - n/a RORO

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :




28/09/2017 08:24

Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.