EDPRCR, External Debug Power/Reset Control Register

The EDPRCR characteristics are:

Purpose

Controls the PE functionality related to powerup, reset, and powerdown.

This register is part of the Debug registers functional group.

Usage constraints

This register is accessible as follows:

SLKDefault
RORW

On permitted accesses to the register, other access controls affect the behavior of some fields. See the field descriptions for more information.

Configuration

EDPRCR contains fields that are in the Core power domain and fields that are in the Debug power domain.

For RW fields see the field description for a description of the behavior of the field on a reset that applies to its power domain. However:

CORENPDRQ is the only field that is mapped between the EDPRCR and DBGPRCR and DBGPRCR_EL1.

Attributes

EDPRCR is a 32-bit register.

Field descriptions

The EDPRCR bit assignments are:

313029282726252423222120191817161514131211109876543210
0000000000000000000000000000COREPURQ0CWRRCORENPDRQ

Bits [31:4]

Reserved, RES0.

COREPURQ, bit [3]

Core powerup request. Allows a debugger to request that the power controller power up the core, enabling access to the debug register in the Core power domain. The actions on writing to this bit are:

COREPURQMeaning
0

Do not request power up of the Core power domain.

1

Request power up of the Core power domain, and emulation of powerdown.

In an implementation that includes the recommended external debug interface, this bit drives the DBGPWRUPREQ signal.

Typically, this request is passed to an external power controller. This means that whether a request causes power up is dependent on the IMPLEMENTATION DEFINED nature of the system.

This field is in the Debug power domain and can be read and written when the Core power domain is powered off. On an External debug reset this field resets to 0.

The power controller must not allow the Core power domain to switch off while this bit is 1.

When this register has an architecturally-defined reset value, this field resets to 0.

This field resets to its defined reset value on External debug reset.

This table summarizes the effect of the register access controls on the behavior of this field:

SLKDefault
RORW

'Access permissions for the External debug interface registers' in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile, section H8.6.1 describes the conditions shown in this table. These conditions are prioritized, with the leftmost condition having the highest priority and priority decreasing from left to right.

Bit [2]

Reserved, RES0.

CWRR, bit [1]

Warm reset request. Write only bit that reads as zero. The actions on writing to this bit are:

CWRRMeaning
0

No action.

1

Request Warm reset.

The PE ignores writes to this bit if any of the following are true:

In an implementation that includes the recommended external debug interface, this bit drives the DBGRSTREQ signal.

The extent of the reset is IMPLEMENTATION DEFINED, but must be one of:

Note

Although the ARM architecture permits the first option from the above list, ARM recommends that either of the other options is implemented.

When this register has an architecturally-defined reset value, this field resets to 0.

This field resets to its defined reset value on Warm reset.

This table summarizes the effect of the register access controls on the behavior of this field:

OffDLKOSLKSLKDefault
WIWIWIWIWO

'Access permissions for the External debug interface registers' in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile, section H8.6.1 describes the conditions shown in this table. These conditions are prioritized, with the leftmost condition having the highest priority and priority decreasing from left to right.

CORENPDRQ, bit [0]

Core no powerdown request. Requests emulation of powerdown. Possible values of this bit are:

CORENPDRQMeaning
0

If the system responds to a powerdown request, it powers down Core power domain.

1

If the system responds to a powerdown request, it does not powerdown the Core power domain, but instead emulates a powerdown of that domain.

This bit is UNKNOWN, and the PE ignores writes to this bit if any of the following are true:

Permitted accesses to this field map to the DBGPRCR.CORENPDRQ and DBGPRCR_EL1.CORENPDRQ fields.

This field is in the Core reset domain. See the descriptions of the DBGPRCR.CORENPDRQ and DBGPRCR_EL1.CORENPDRQ fields for information about the effect of a Cold reset on the value returned by a permitted read of this field.

This table summarizes the effect of the register access controls on the behavior of this field:

OffDLKOSLKSLKDefault
WIWIWIRORW

'Access permissions for the External debug interface registers' in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile, section H8.6.1 describes the conditions shown in this table. These conditions are prioritized, with the leftmost condition having the highest priority and priority decreasing from left to right.

Accessing the EDPRCR

EDPRCR can be accessed through the external debug interface:

ComponentOffset
Debug 0x310



28/09/2017 08:24

Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.