CSSELR, Cache Size Selection Register

The CSSELR characteristics are:

Purpose

Selects the current Cache Size ID Register, CCSIDR, by specifying the required cache level and the cache type (either instruction or data cache).

This register is part of the Identification registers functional group.

Configuration

AArch32 System register CSSELR is architecturally mapped to AArch64 System register CSSELR_EL1.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

CSSELR is a 32-bit register.

Field descriptions

The CSSELR bit assignments are:

313029282726252423222120191817161514131211109876543210
0000000000000000000000000000LevelInD

Bits [31:4]

Reserved, RES0.

Level, bits [3:1]

Cache level of required cache. Permitted values are:

LevelMeaning
000

Level 1 cache

001

Level 2 cache

010

Level 3 cache

011

Level 4 cache

100

Level 5 cache

101

Level 6 cache

110

Level 7 cache

All other values are reserved.

If CSSELR.Level is programmed to a cache level that is not implemented, then the value for this field on a read of CSSELR is UNKNOWN.

InD, bit [0]

Instruction not Data bit. Permitted values are:

InDMeaning
0

Data or unified cache.

1

Instruction cache.

If CSSELR.Level is programmed to a cache level that is not implemented, then the value for this field on a read of CSSELR is UNKNOWN.

Accessing the CSSELR

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 2, <Rt>, c0, c0, 0010000000011110000

Accessibility

The register is accessible as follows:

Configuration Control Accessibility Instance
E2HTGENSEL0EL1EL2EL3
EL3 not implemented xx0 - RW n/a n/a CSSELR
EL3 not implemented x01 - RWRW n/a CSSELR
EL3 not implemented x11 - n/a RW n/a CSSELR
EL3 using AArch64xx0 - RW n/a n/a CSSELR
EL3 using AArch64x01 - RWRW n/a CSSELR
EL3 using AArch64x11 - n/a RW n/a CSSELR
EL3 using AArch32xx0 - n/a n/a RWCSSELR_s
EL3 using AArch32x01 - RWRWRWCSSELR_ns
EL3 using AArch32x11 - n/a RWRWCSSELR_ns

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :




28/09/2017 08:24

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