ICH_LR<n>, Interrupt Controller List Registers, n = 0 - 15

The ICH_LR<n> characteristics are:

Purpose

Provides interrupt context information for the virtual CPU interface.

This register is part of:

Configuration

AArch32 System register ICH_LR<n> is architecturally mapped to AArch64 System register ICH_LR<n>_EL2[31:0] .

If EL2 is not implemented, this register is RES0 from EL3.

Attributes

ICH_LR<n> is a 32-bit register.

Field descriptions

The ICH_LR<n> bit assignments are:

313029282726252423222120191817161514131211109876543210
vINTID

vINTID, bits [31:0]

Virtual INTID of the interrupt.

If the value of vINTID is 1020-1023 and ICH_LRC<n>.State!=0b00 (Inactive), behavior is UNPREDICTABLE.

Behavior is UNPREDICTABLE if two or more List Registers specify the same vINTID when:

It is IMPLEMENTATION DEFINED how many bits are implemented, though at least 16 bits must be implemented. Unimplemented bits are RES0. The number of implemented bits can be discovered from ICH_VTR.IDbits.

Note

When a VM is using memory-mapped access to the GIC, software must ensure that the correct source PE ID is provided in bits[12:10].

When this register has an architecturally-defined reset value, this field resets to 0.

Accessing the ICH_LR<n>

This register can be read using MRC with the following syntax:

MRC <syntax>

This register can be written using MCR with the following syntax:

MCR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1opc2CRncoprocCRm
p15, 4, <Rt>, c12, <CRm>, <opc2>100n<2:0> 11001111110:n<3>

Accessibility

The register is accessible as follows:

Control Accessibility
TGENSEL0EL1EL2EL3
x0 - - n/a -
01 - - RWRW
11 - n/a RWRW

This table applies to all instructions that can access this register.

ICH_LR<n> and ICH_LRC<n> can be updated independently.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

In both Security states, and not dependent on other configuration bits:

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :




28/09/2017 08:24

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