The GICH_ELRSR characteristics are:
Indicates which List registers contain valid interrupts.
This register is part of the GIC virtualised guest interface control registers functional group.
This register is accessible as follows:
Security disabled | Secure | Non-secure |
---|---|---|
RO | RO | RO |
This register is used only when System register access is not enabled. When System register access is enabled:
Bits corresponding to unimplemented List registers are RES0.
Some or all RW fields of this register have defined reset values.
This register is available when the GIC implementation supports interrupt virtualization.
GICH_ELRSR is a 32-bit register.
The GICH_ELRSR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Status<n>, bit [n], for n = 0 to 15 |
Reserved, RES0.
Status bit for List register <n>:
Status<n> | Meaning |
---|---|
0 |
GICH_LR<n>, if implemented, contains a valid interrupt. Using this List register can result in overwriting a valid interrupt. |
1 |
GICH_LR<n> does not contain a valid interrupt. The List register is empty and can be used without overwriting a valid interrupt or losing an EOI maintenance interrupt. |
For any GICH_LR<n> register, the corresponding status bit is set to 1 if GICH_LR<n>.State is 0b00 and either:
When this register has an architecturally-defined reset value, this field resets to 1.
GICH_ELRSR can be accessed through its memory-mapped interface:
Component | Offset |
---|---|
GIC Virtual interface control | 0x0030 |
28/09/2017 08:24
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