GICH_VMCR, Virtual Machine Control Register

The GICH_VMCR characteristics are:

Purpose

Enables the hypervisor to save and restore the virtual machine view of the GIC state. This register is updated when a virtual machine updates the virtual CPU interface registers.

This register is part of the GIC virtualised guest interface control registers functional group.

Usage constraints

This register is accessible as follows:

Security disabledSecureNon-secure
RWRWRW

This register is used only when System register access is not enabled. When System register access is enabled:

Configuration

RW fields in this register reset to architecturally UNKNOWN values.

This register is available when the GIC implementation supports interrupt virtualization.

Attributes

GICH_VMCR is a 32-bit register.

Field descriptions

The GICH_VMCR bit assignments are:

313029282726252423222120191817161514131211109876543210
VPMRVBPR0VBPR100000000VEOIM0000VCBPRVFIQEnVAckCtlVENG1VENG0

VPMR, bits [31:24]

Virtual priority mask. The priority mask level for the CPU interface. If the priority of an interrupt is higher than the value indicated by this field, the interface signals the interrupt to the PE.

This alias field is updated when a VM updates GICV_PMR.Priority.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

VBPR0, bits [23:21]

Virtual Binary Point Register, Group 0. Defines the point at which the priority value fields split into two parts, the Group priority field and the subpriority field. The Group priority field determines Group 0 interrupt preemption, and also determines Group 1 interrupt preemption if GICH_VMCR.VCBPR == 1.

This alias field is updated when a VM updates GICV_BPR.Binary_Point.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

VBPR1, bits [20:18]

Virtual Binary Point Register, Group 1. Defines the point at which the priority value fields split into two parts, the Group priority field and the subpriority field. The Group priority field determines Group 1 interrupt preemption if GICH_VMCR.VCBPR == 0.

This alias field is updated when a VM updates GICV_ABPR.Binary_Point.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Bits [17:10]

Reserved, RES0.

VEOIM, bit [9]

Virtual EOImode. Possible values of this bit are:

VEOIMMeaning
0

A write of an INTID to GICV_EOIR or GICV_AEOIR drops the priority of the interrupt with that INTID, and also deactivates that interrupt.

1

A write of an INTID to GICV_EOIR or GICV_AEOIR only drops the priority of the interrupt with that INTID. Software must write to GICV_DIR to deactivate the interrupt.

This alias field is updated when a VM updates GICV_CTLR.EOImode.

When this register has an architecturally-defined reset value, if this field is implemented as an RW field, it resets to a value that is architecturally UNKNOWN.

Bits [8:5]

Reserved, RES0.

VCBPR, bit [4]

Virtual Common Binary Point Register. Possible values of this bit are:

VCBPRMeaning
0

GICV_ABPR determines the preemption group for Group 1 interrupts.

1

GICV_BPR determines the preemption group for Group 1 interrupts.

This alias field is updated when a VM updates GICV_CTLR.CBPR.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

VFIQEn, bit [3]

Virtual FIQ enable. Possible values of this bit are:

VFIQEnMeaning
0

Group 0 virtual interrupts are presented as virtual IRQs.

1

Group 0 virtual interrupts are presented as virtual FIQs.

This alias field is updated when a VM updates GICV_CTLR.FIQEn.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

VAckCtl, bit [2]

Virtual AckCtl. Possible values of this bit are:

VAckCtlMeaning
0

If the highest priority pending interrupt is Group 1, a read of GICV_IAR or GICV_HPPIR returns an INTID of 1022.

1

If the highest priority pending interrupt is Group 1, a read of GICV_IAR or GICV_HPPIR returns the INTID of the corresponding interrupt.

This alias field is updated when a VM updates GICV_CTLR.AckCtl.

This field is supported for backwards compatibility with GICv2. ARM deprecates the use of this field.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

VENG1, bit [1]

Virtual interrupt enable, Group 1. Possible values of this bit are:

VENG1Meaning
0

Group 1 virtual interrupts are disabled.

1

Group 1 virtual interrupts are enabled.

This alias field is updated when a VM updates GICV_CTLR.EnableGrp1.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

VENG0, bit [0]

Virtual interrupt enable, Group 0. Possible values of this bit are:

VENG0Meaning
0

Group 0 virtual interrupts are disabled.

1

Group 0 virtual interrupts are enabled.

This alias field is updated when a VM updates GICV_CTLR.EnableGrp0.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.

Note

A List register is in the pending state only if the corresponding GICH_LR<n> value is 01, that is, pending. The active and pending state is not included.

Accessing the GICH_VMCR

GICH_VMCR can be accessed through its memory-mapped interface:

ComponentOffset
GIC Virtual interface control 0x0008



28/09/2017 08:24

Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.