The ESR_EL2 characteristics are:
Holds syndrome information for an exception taken to EL2.
This register is part of:
AArch64 System register ESR_EL2 is architecturally mapped to AArch32 System register HSR.
If EL2 is not implemented, this register is RES0 from EL3.
RW fields in this register reset to architecturally UNKNOWN values.
ESR_EL2 is a 32-bit register.
See ESR_ELx.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
ESR_EL2 | 11 | 100 | 0101 | 0010 | 000 |
ESR_EL1 | 11 | 000 | 0101 | 0010 | 000 |
The register is accessible as follows:
<systemreg> | Control | Accessibility | |||||
---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | |
ESR_EL2 | x | x | 0 | - | - | n/a | RW |
ESR_EL2 | 0 | 0 | 1 | - | - | RW | RW |
ESR_EL2 | 0 | 1 | 1 | - | n/a | RW | RW |
ESR_EL2 | 1 | 0 | 1 | - | - | RW | RW |
ESR_EL2 | 1 | 1 | 1 | - | n/a | RW | RW |
ESR_EL1 | x | x | 0 | - | ESR_EL1 | n/a | ESR_EL1 |
ESR_EL1 | 0 | 0 | 1 | - | ESR_EL1 | ESR_EL1 | ESR_EL1 |
ESR_EL1 | 0 | 1 | 1 | - | n/a | ESR_EL1 | ESR_EL1 |
ESR_EL1 | 1 | 0 | 1 | - | ESR_EL1 | RW | ESR_EL1 |
ESR_EL1 | 1 | 1 | 1 | - | n/a | RW | ESR_EL1 |
When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic ESR_EL2 or ESR_EL1 are not guaranteed to be ordered with respect to accesses using the other mnemonic.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.NV==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.NV==1, Non-secure accesses to this register from EL1 are trapped to EL2.
28/09/2017 08:24
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