The CTIOUTEN<n> characteristics are:
Defines which input channels generate output trigger n.
This register is part of the Cross-Trigger Interface registers functional group.
This register is accessible as follows:
SLK | Default |
---|---|
RO | RW |
CTIOUTEN<n> is in the Debug power domain. RW fields in this register reset to architecturally UNKNOWN values. These apply only on an External debug reset. The register is not affected by a Warm reset and is not affected by a Cold reset.
If output trigger n is not connected, the behavior of CTIOUTEN<n> is IMPLEMENTATION DEFINED.
CTIOUTEN<n> is a 32-bit register.
The CTIOUTEN<n> bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OUTEN<x>, bit [x] |
Input channel <x> to output trigger <n> enable.
Bits [31:N] are RAZ/WI. N is the number of ECT channels implemented as defined by the CTIDEVID.NUMCHAN field.
Possible values of this bit are:
OUTEN<x> | Meaning |
---|---|
0 |
An event on input channel <x> will not cause output trigger <n> to be asserted. |
1 |
An event on input channel <x> will cause output trigger <n> to be asserted. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
CTIOUTEN<n> can be accessed through the external debug interface:
Component | Offset |
---|---|
CTI | 0x0A0 + 4n |
28/09/2017 08:24
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