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CNTP_CVAL, Counter-timer Physical Timer CompareValue register

The CNTP_CVAL characteristics are:

Purpose

Holds the compare value for the EL1 physical timer.

This register is part of the Generic Timer registers functional group.

Configuration

AArch32 System register CNTP_CVAL is architecturally mapped to AArch64 System register CNTP_CVAL_EL0.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

CNTP_CVAL is a 64-bit register.

Field descriptions

The CNTP_CVAL bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
CompareValue
CompareValue
313029282726252423222120191817161514131211109876543210

CompareValue, bits [63:0]

Holds the EL1 physical timer CompareValue.

When CNTP_CTL.ENABLE is 1, the timer condition is met when (CNTPCT - CompareValue) is greater than or equal to zero. This means that CompareValue acts like a 64-bit upcounter timer. When the timer condition is met:

When CNTP_CTL.ENABLE is 0, the timer condition is not met, but CNTPCT continues to count.

Accessing the CNTP_CVAL

This register can be read using MRRC with the following syntax:

MRRC <syntax>

This register can be written using MCRR with the following syntax:

MCRR <syntax>

This syntax uses the following encoding in the System instruction encoding space:

<syntax> opc1coprocCRm
p15, 2, <Rt>, <Rt2>, c14001011111110

Accessibility

The register is accessible as follows:

Configuration Control Accessibility Instance
E2HTGENSEL0EL1EL2EL3
EL3 using AArch32xx0RW n/a n/a RWCNTP_CVAL_s
EL3 using AArch32x01RWRWRWRWCNTP_CVAL_ns
EL3 using AArch32x11RW n/a RWRWCNTP_CVAL_ns
EL3 not implemented xx0RWRW n/a n/a CNTP_CVAL
EL3 not implemented 001RWRWRW n/a CNTP_CVAL
EL3 not implemented 011RW n/a RW n/a CNTP_CVAL
EL3 not implemented 101RWRW n/a n/a CNTP_CVAL
EL3 not implemented 111 CNTHP_CVAL n/a n/a n/a -
EL3 using AArch64xx0RWRW n/a n/a CNTP_CVAL
EL3 using AArch64001RWRWRW n/a CNTP_CVAL
EL3 using AArch64011RW n/a RW n/a CNTP_CVAL
EL3 using AArch64101RWRW n/a n/a CNTP_CVAL
EL3 using AArch64111 CNTHP_CVAL n/a n/a n/a -

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==1 :

When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :




28/0907/2017 0816:2440

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