ID_AA64MMFR2_EL1, AArch64 Memory Model Feature Register 2

The ID_AA64MMFR2_EL1 characteristics are:

Purpose

Provides information about the implemented memory model and memory management support in AArch64 state.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section D7.1.3.

This register is part of the Identification registers functional group.

Configuration

This register is introduced in ARMv8.2.

Attributes

ID_AA64MMFR2_EL1 is a 64-bit register.

Field descriptions

The ID_AA64MMFR2_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
00000000000000000000000000000000
0000NVCCIDXVARangeIESBLSMUAOCnP
313029282726252423222120191817161514131211109876543210

Bits [63:28]

Reserved, RES0.

NV, bits [27:24]
In ARMv8.3:

If EL2 is implemented, indicates support for the use of Nested Virtualization. Defined values are:

NVMeaning
0000

Nested Virtualization is not supported.

0001

The HCR_EL2.NV, HCR_EL2.NV1, HCR_EL2.AT bits are implemented.

All other values are reserved.

In ARMv8.2 the only permitted value is 0000.

From ARMv8.3 the permitted values are:


In ARMv8.2:

Reserved, RES0.

CCIDX, bits [23:20]
In ARMv8.3:

Support for the use of revised CCSIDR_EL1 register format. Defined values are:

CCIDXMeaning
0000

32-bit format implemented for all levels of the CCSIDR_EL1.

0001

64-bit format implemented for all levels of the CCSIDR_EL1.

All other values are reserved.

From ARMv8.3, the permitted values are 0000 and 0001. This feature is identified by the name ARMv8.3-CCIDX.


In ARMv8.2:

Reserved, RES0.

VARange, bits [19:16]

Indicates support for a larger virtual address. Defined values are:

VARangeMeaning
0000

VMSAv8-64 supports 48-bit VAs.

0001

VMSAv8-64 supports 52-bit VAs when using the 64KB translation granule. The other translation granules support 48-bit VAs.

All other values are reserved.

ARMv8.2-LVA implements the functionality identified by the value 0001.

IESB, bits [15:12]

Indicates support for the IESB bit in the SCTLR_ELx registers. Defined values are:

IESBMeaning
0000

IESB bit in the SCTLR_ELx registers is not supported.

0001

IESB bit in the SCTLR_ELx registers is supported.

All other values are reserved.

ARMv8.2-IESB implements the functionality identified by the value 0001.

From ARMv8.2 the only permitted value is 0001.

LSM, bits [11:8]

Indicates support for LSMAOE and nTLSMD bits in SCTLR_EL1 and SCTLR_EL2. Defined values are:

LSMMeaning
0000

LSMAOE and nTLSMD bits not supported.

0001

LSMAOE and nTLSMD bits supported.

All other values are reserved.

ARMv8.2-LSMAOC implements the functionality identified by the value 0001.

UAO, bits [7:4]

User Access Override. Defined values are:

UAOMeaning
0000

UAO not supported.

0001

UAO supported.

All other values are reserved.

ARMv8.2-UAO implements the functionality identified by the value 0001.

From ARMv8.2 the only permitted value is 0001.

CnP, bits [3:0]

Common not Private translations. Defined values are:

CnPMeaning
0000

Common not Private translations not supported.

0001

Common not Private translations supported.

All other values are reserved.

ARMv8.2-TTCNP implements the functionality identified by the value 0001.

From ARMv8.2, the only permitted value is 0001.

Accessing the ID_AA64MMFR2_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
ID_AA64MMFR2_EL11100000000111010

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RO n/a RO
x01 - RORORO
x11 - n/a RORO

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :




28/09/2017 08:24

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