PMBPTR_EL1, Profiling Buffer Write Pointer Register

The PMBPTR_EL1 characteristics are:

Purpose

Defines the current write pointer for the profiling buffer.

This register is part of the Statistical Profiling Extension registers functional group.

Configuration

Present only if the Statistical Profiling Extension is implemented. Direct reads and writes of PMBPTR_EL1 are UNDEFINED otherwise.

Attributes

PMBPTR_EL1 is a 64-bit register.

Field descriptions

The PMBPTR_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
PTR
PTR
313029282726252423222120191817161514131211109876543210

PTR, bits [63:0]

Current write address. Defines the virtual address of the next entry to be written to the buffer.

Software must treat bits [M:0] of this register as RES0, where M is defined by PMBIDR_EL1.Align. If synchronous reporting of external aborts is not supported, then hardware also treats these bits as RES0. Otherwise, bits [M:0] might contain part of a fault address on a synchronous external abort.

On a management interrupt, PMBPTR_EL1 is frozen

Accessing the PMBPTR_EL1

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> CRnop0op1op2CRm
PMBPTR_EL11001110000011010

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RW n/a RW
x01 - RWRWRW
x11 - n/a RWRW

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.




12/09/2017 18:03

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