The DACR32_EL2 characteristics are:
Allows access to the AArch32 DACR register from AArch64 state only. Its value has no effect on execution in AArch64 state.
This register is part of the Virtual memory control registers functional group.
AArch64 System register DACR32_EL2 is architecturally mapped to AArch32 System register DACR.
If EL1 does not support AArch32, this register is UNDEFINED.
If EL2 is not implemented but EL3 is implemented, and EL1 is capable of using AArch32, then this register is not RES0.
RW fields in this register reset to architecturally UNKNOWN values.
DACR32_EL2 is a 32-bit register.
The DACR32_EL2 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
Domain n access permission, where n = 0 to 15. Permitted values are:
D<n> | Meaning |
---|---|
00 |
No access. Any access to the domain generates a Domain fault. |
01 |
Client. Accesses are checked against the permission bits in the translation tables. |
11 |
Manager. Accesses are not checked against the permission bits in the translation tables. |
The value 10 is reserved.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
DACR32_EL2 | 11 | 100 | 0011 | 0000 | 000 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | - | n/a | RW |
x | 0 | 1 | - | - | RW | RW |
x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.NV==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.NV==1, Non-secure accesses to this register from EL1 are trapped to EL2.
28/09/2017 08:24
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