The PMCNTENCLR_EL0 characteristics are:
Disables the Cycle Count Register, PMCCNTR_EL0, and any implemented event counters PMEVCNTR<n>. Reading this register shows which counters are enabled.
This register is part of the Performance Monitors registers functional group.
This register is accessible as follows:
Off | DLK | OSLK | EPMAD | SLK | Default |
---|---|---|---|---|---|
Error | Error | Error | Error | RO | RW |
External register PMCNTENCLR_EL0 is architecturally mapped to AArch64 System register PMCNTENCLR_EL0.
External register PMCNTENCLR_EL0 is architecturally mapped to AArch32 System register PMCNTENCLR.
PMCNTENCLR_EL0 is in the Core power domain. RW fields in this register reset to architecturally UNKNOWN values. These apply on a Warm or Cold reset. The register is not affected by an External debug reset.
PMCNTENCLR_EL0 is a 32-bit register.
The PMCNTENCLR_EL0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
C | P<n>, bit [n] |
PMCCNTR_EL0 disable bit. Disables the cycle counter register. Possible values are:
C | Meaning |
---|---|
0 |
When read, means the cycle counter is disabled. When written, has no effect. |
1 |
When read, means the cycle counter is enabled. When written, disables the cycle counter. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Event counter disable bit for PMEVCNTR<n>_EL0.
Bits [30:N] are RAZ/WI. N is the value in PMCFGR.N.
Possible values of each bit are:
P<n> | Meaning |
---|---|
0 |
When read, means that PMEVCNTR<n>_EL0 is disabled. When written, has no effect. |
1 |
When read, means that PMEVCNTR<n>_EL0 is enabled. When written, disables PMEVCNTR<n>_EL0. |
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
PMCNTENCLR_EL0 can be accessed through the external debug interface:
Component | Offset |
---|---|
PMU | 0xC20 |
28/09/2017 08:24
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