The ID_DFR0 characteristics are:
Provides top level information about the debug system in AArch32 state.
Must be interpreted with the Main ID Register, MIDR.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the ARMv8 ARM, section G4.14.6.
This register is part of the Identification registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register ID_DFR0 is architecturally mapped to AArch64 System register ID_DFR0_EL1.
ID_DFR0 is a 32-bit register.
The ID_DFR0 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | PerfMon | MProfDbg | MMapTrc | CopTrc | MMapDbg | CopSDbg | CopDbg |
Reserved, RES0.
Performance Monitors. Support for System registers-based ARM Performance Monitors Extension, using registers in the coproc == 1111 encoding space, for A and R profile processors. Defined values are:
PerfMon | Meaning |
---|---|
0000 |
Performance Monitors Extension System registers not implemented. |
0001 |
Support for Performance Monitors Extension version 1 (PMUv1) System registers. |
0010 |
Support for Performance Monitors Extension version 2 (PMUv2) System registers. |
0011 |
Support for Performance Monitors Extension version 3 (PMUv3) System registers. |
0100 |
Support for Performance Monitors Extension version 3 (PMUv3) System registers, with a 16-bit evtCount field. |
1111 |
IMPLEMENTATION DEFINED form of Performance Monitors System registers supported. PMUv3 not supported. |
All other values are reserved.
ARMv8.1-PMU implements the functionality added by the value 0100.
In any ARMv8 implementation the values 0001 and 0010 are not permitted.
From ARMv8.1 the value 0011 is not permitted.
In ARMv7, the value 0000 can mean that PMUv1 is implemented. PMUv1 is not permitted in an ARMv8 implementation.
M Profile Debug. Support for memory-mapped debug model for M profile processors. Defined values are:
MProfDbg | Meaning |
---|---|
0000 |
Not supported. |
0001 |
Support for M profile Debug architecture, with memory-mapped access. |
All other values are reserved.
In ARMv8-A the only permitted value is 0000.
Memory Mapped Trace. Support for memory-mapped trace model. Defined values are:
MMapTrc | Meaning |
---|---|
0000 |
Not supported. |
0001 |
Support for ARM trace architecture, with memory-mapped access. |
All other values are reserved.
In ARMv8-A the permitted values are 0000 and 0001.
In the Trace registers, the ETMIDR gives more information about the implementation.
Support for System registers-based trace model, using registers in the coproc == 1110 encoding space. Defined values are:
CopTrc | Meaning |
---|---|
0000 |
Not supported. |
0001 |
Support for ARM trace architecture, with System registers access. |
All other values are reserved.
In ARMv8-A the permitted values are 0000 and 0001.
In the Trace registers, the ETMIDR gives more information about the implementation.
Memory Mapped Debug. Support for v7 memory-mapped debug model, for A and R profile processors.
In ARMv8-A this field is RES0.
The optional memory map defined by ARMv8 is not compatible with ARMv7.
Support for a System registers-based Secure debug model, using registers in the coproc = 1110 encoding space, for an A profile processor that includes EL3.
If EL3 is not implemented and the implemented Security state is Non-Secure state, this field is RES0. Otherwise, this field reads the same as bits [3:0].
Support for System registers-based debug model, using registers in the coproc == 1110 encoding space, for A and R profile processors. Defined values are:
CopDbg | Meaning |
---|---|
0000 |
Not supported. |
0010 |
Support for ARMv6, v6 Debug architecture, with System registers access. |
0011 |
Support for ARMv6, v6.1 Debug architecture, with System registers access. |
0100 |
Support for ARMv7, v7 Debug architecture, with System registers access. |
0101 |
Support for ARMv7, v7.1 Debug architecture, with System registers access. |
0110 |
Support for ARMv8 debug architecture, with System registers access. |
0111 |
Support for ARMv8 debug architecture, with System registers access, and Virtualization Host extensions. |
1000 |
Support for ARMv8.2 debug architecture. |
All other values are reserved.
ARMv8.2-Debug adds the functionality indicated by the value 1000.
This register can be read using MRC with the following syntax:
MRC <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c0, c1, 2 | 000 | 010 | 0000 | 1111 | 0001 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RO | n/a | RO |
x | 0 | 1 | - | RO | RO | RO |
x | 1 | 1 | - | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HSTR_EL2.T0==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TID3==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
If HSTR_EL2.T0==1, Non-secure read accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
28/09/2017 08:24
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.