The CounterID<n> characteristics are:
IMPLEMENTATION DEFINED identification registers 0 to 11 for the memory-mapped Generic Timer.
This register is part of the Generic Timer registers functional group.
This register is accessible as follows:
Default |
---|
RO |
These registers must be implemented, as RO registers, in every implemented Generic Timer memory-mapped frame.
For the CNTCTLBase frame, in a system that recognizes two Security states these registers are accessible by both Secure and Non-secure accesses.
For the CNTControlBase frame, in a system that supports Secure and Non-secure memory maps the frame is implemented only in the Secure memory map, meaning these registers are implemented only in the Secure memory map.
For the CNTBaseN frames, 'CNTCTLBase status and control fields for the CNTBaseN and CNTEL0BaseN frames' in Chapter I1 of the ARMv8 ARM describes the status fields that identify whether a frame is implemented, and for an implemented frame:
The power domain of CounterID<n> is IMPLEMENTATION DEFINED.
For more information see 'Power and reset domains for the system level implementation of the Generic Timer' in Chapter I1 of the ARMv8 ARM.
These registers are implemented independently in each of the implemented Generic Timer memory-mapped frames.
If the implementation of the Counter ID registers requires an architecture version, the value for this version of the ARM Generic Timer is version 0.
The Counter ID registers can be implemented as a set of CoreSight ID registers, comprising Peripheral ID Registers and Component ID Registers. An implementation of these registers for the Generic Timer must use a Component class value of 0xF.
CounterID<n> is a 32-bit register.
The CounterID<n> bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED |
IMPLEMENTATION DEFINED.
CounterID<n> can be accessed through its memory-mapped interface:
Component | Frame | Offset |
---|---|---|
Timer | CNTControlBase | 0xFD0 + 4n |
Timer | CNTReadBase | 0xFD0 + 4n |
Timer | CNTBaseN | 0xFD0 + 4n |
Timer | CNTEL0BaseN | 0xFD0 + 4n |
Timer | CNTCTLBase | 0xFD0 + 4n |
28/09/2017 08:24
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