The PMCEID1 characteristics are:
Defines which common architectural events and common microarchitectural events are implemented, or counted, using PMU events in the range 0x020 to 0x03F.
When the value of a bit in the register is 1 the corresponding common event is implemented or counted.
ARM recommends that, if a common event is never counted, the value of the corresponding register bit is 0.
For more information about the common events and the use of the PMCEIDn registers see The section describing 'Event numbers and common events' in chapter D5 'The Performance Monitors Extension' of the ARM Architecture Reference Manual, for ARMv8-A architecture profile.
This register is part of the Performance Monitors registers functional group.
There is one instance of this register that is used in both Secure and Non-secure states.
AArch32 System register PMCEID1 is architecturally mapped to AArch64 System register PMCEID1_EL0[31:0] .
AArch32 System register PMCEID1 is architecturally mapped to External register PMCEID1[31:0] .
PMCEID1 is a 32-bit register.
The PMCEID1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ID[63:32] |
ID[n] corresponds to common event n.
For each bit:
ID[63:32] | Meaning |
---|---|
0 |
The common event is not implemented, or not counted. |
1 |
The common event is implemented. |
A bit that corresponds to a reserved event number is reserved. The value might be used in a future revision of the architecture to identify an additional common event.
Such an event might be added retrospectively to an earlier version of the PMU architecture, provided the event does not require any additional PMU features and has an event number that can be represented in the PMCEID<n> registers of that earlier version of the PMU architecture.
This register can be read using MRC with the following syntax:
MRC <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c9, c12, 7 | 000 | 111 | 1001 | 1111 | 1100 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | RO | RO | n/a | RO |
x | 0 | 1 | RO | RO | RO | RO |
x | 1 | 1 | RO | n/a | RO | RO |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If PMUSERENR.EN==0, read accesses to this register from EL0 are trapped to Undefined mode.
If PMUSERENR_EL0.EN==0, read accesses to this register from EL0 are trapped to EL1.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HSTR_EL2.T9==1, Non-secure read accesses to this register from EL0 are trapped to EL2.
If HSTR_EL2.T9==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 :
If MDCR_EL2.TPM==1, Non-secure read accesses to this register from EL0 and EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HSTR_EL2.T9==1, Non-secure read accesses to this register from EL0 are trapped to EL2.
If HSTR_EL2.T9==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If HDCR.TPM==1, Non-secure read accesses to this register from EL0 and EL1 are trapped to Hyp mode.
If HSTR.T9==1, Non-secure read accesses to this register from EL0 are trapped to Hyp mode.
If HSTR.T9==1, Non-secure accesses to this register from EL1 are trapped to Hyp mode.
When EL3 is implemented and is using AArch64 :
If MDCR_EL3.TPM==1, read accesses to this register from EL0, EL1, and EL2 are trapped to EL3.
28/09/2017 08:24
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