The RVBAR_EL3 characteristics are:
If EL3 is the highest Exception level implemented, contains the IMPLEMENTATION DEFINED address that execution starts from after reset when executing in AArch64 state.
This register is part of the Reset management registers functional group.
Only implemented if the highest Exception level implemented is EL3.
RVBAR_EL3 is a 64-bit register.
The RVBAR_EL3 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
Reset Address | |||||||||||||||||||||||||||||||
Reset Address | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset Address. The IMPLEMENTATION DEFINED address that execution starts from after reset when executing in 64-bit state. Bits[1:0] of this register are 00, as this address must be aligned, and the address must be within the physical address size supported by the PE.
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
RVBAR_EL3 | 11 | 110 | 1100 | 0000 | 001 |
The register is accessible as follows:
Configuration | Control | Accessibility | |||||
---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | |
EL3 is the highest implemented Exception level | x | x | 0 | - | - | n/a | RO |
EL3 is the highest implemented Exception level | x | 0 | 1 | - | - | - | RO |
EL3 is the highest implemented Exception level | x | 1 | 1 | - | n/a | - | RO |
This table applies to all instructions that can access this register.
When EL3 is not the highest implemented Exception level, the encoding for this register is UNDEFINED.
28/09/2017 08:24
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