The CNTP_CTL characteristics are:
Control register for the EL1 physical timer.
This register is part of the Generic Timer registers functional group.
AArch32 System register CNTP_CTL is architecturally mapped to AArch64 System register CNTP_CTL_EL0.
Some or all RW fields of this register have defined reset values. These apply only if the PE resets into an Exception level that is using AArch32. If the PE resets into EL3 using AArch32 they apply only to the Secure instance of the register. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.
CNTP_CTL is a 32-bit register.
The CNTP_CTL bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ISTATUS | IMASK | ENABLE |
Reserved, RES0.
The status of the timer. This bit indicates whether the timer condition is met:
ISTATUS | Meaning |
---|---|
0 |
Timer condition is not met. |
1 |
Timer condition is met. |
When the value of the ENABLE bit is 1, ISTATUS indicates whether the timer condition is met. ISTATUS takes no account of the value of the IMASK bit. If the value of ISTATUS is 1 and the value of IMASK is 0 then the timer interrupt is asserted.
When the value of the ENABLE bit is 0, the ISTATUS field is UNKNOWN.
For more information see 'Operation of the CompareValue views of the timers' and 'Operation of the TimerValue views of the timers' in the ARM ARM, chapter D6.
This bit is read-only.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Timer interrupt mask bit. Permitted values are:
IMASK | Meaning |
---|---|
0 |
Timer interrupt is not masked by the IMASK bit. |
1 |
Timer interrupt is masked by the IMASK bit. |
For more information, see the description of the ISTATUS bit.
When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN.
Enables the timer. Permitted values are:
ENABLE | Meaning |
---|---|
0 |
Timer disabled. |
1 |
Timer enabled. |
Setting this bit to 0 disables the timer output signal, but the timer value accessible from CNTP_TVAL continues to count down.
Disabling the output signal might be a power-saving option.
When this register has an architecturally-defined reset value, this field resets to 0.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c14, c2, 1 | 000 | 001 | 1110 | 1111 | 0010 |
The register is accessible as follows:
Configuration | Control | Accessibility | Instance | |||||
---|---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | ||
EL3 not implemented | x | x | 0 | RW | RW | n/a | n/a | CNTP_CTL |
EL3 not implemented | 0 | 0 | 1 | RW | RW | RW | n/a | CNTP_CTL |
EL3 not implemented | 0 | 1 | 1 | RW | n/a | RW | n/a | CNTP_CTL |
EL3 not implemented | 1 | 0 | 1 | RW | RW | n/a | n/a | CNTP_CTL |
EL3 not implemented | 1 | 1 | 1 | CNTHP_CTL | n/a | n/a | n/a | - |
EL3 using AArch64 | x | x | 0 | RW | RW | n/a | n/a | CNTP_CTL |
EL3 using AArch64 | 0 | 0 | 1 | RW | RW | RW | n/a | CNTP_CTL |
EL3 using AArch64 | 0 | 1 | 1 | RW | n/a | RW | n/a | CNTP_CTL |
EL3 using AArch64 | 1 | 0 | 1 | RW | RW | n/a | n/a | CNTP_CTL |
EL3 using AArch64 | 1 | 1 | 1 | CNTHP_CTL | n/a | n/a | n/a | - |
EL3 using AArch32 | x | x | 0 | RW | n/a | n/a | RW | CNTP_CTL_s |
EL3 using AArch32 | x | 0 | 1 | RW | RW | RW | RW | CNTP_CTL_ns |
EL3 using AArch32 | x | 1 | 1 | RW | n/a | RW | RW | CNTP_CTL_ns |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When HCR_EL2.E2H==0 :
If CNTKCTL_EL1.EL0PTEN==0, accesses to this register from EL0 are trapped to EL1.
If CNTKCTL.PL0PTEN==0, accesses to this register from EL0 are trapped to Undefined mode.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If CNTHCTL_EL2.EL1PCEN==0, Non-secure accesses to this register from EL1 are trapped to EL2.
If CNTHCTL_EL2.EL1PCEN==0, and CNTKCTL_EL1.EL0PTEN==1, Non-secure accesses to this register from EL0 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If CNTHCTL_EL2.EL1PTEN==0, Non-secure accesses to this register from EL1 are trapped to EL2.
If CNTHCTL_EL2.EL1PTEN==0, and CNTKCTL_EL1.EL0PTEN==1, Non-secure accesses to this register from EL0 are trapped to EL2.
If CNTKCTL_EL1.EL0PTEN==0, Non-secure accesses to this register from EL0 are trapped to EL1.
If CNTKCTL.PL0PTEN==0, Non-secure accesses to this register from EL0 are trapped to Undefined mode.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==1 :
If CNTHCTL_EL2.EL0PTEN==0, Non-secure accesses to this register from EL0 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
If CNTHCTL.PL1PCEN==0, Non-secure accesses to this register from EL0 and EL1 are trapped to Hyp mode.
28/09/2017 08:24
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