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The PMSIRR_EL1 characteristics are:
Defines the interval between samples
This register is part of the Statistical Profiling Extension registers functional group.
Present only if the Statistical Profiling Extension is implemented. Direct reads and writes of PMSIRR_EL1 are UNDEFINED otherwise.
PMSIRR_EL1 is a 64-bit register.
The PMSIRR_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
INTERVAL | 0 | 0 | 0 | 0 | 0 | 0 | 0 | RND | |||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved, RES0.
Reserved, RES0.
Bits [31:8] of the PMSICR_EL1 interval counter reload value. Software must set this to a non-zero value. If software sets this to zero, an UNKNOWN sampling interval is used. Software should set this to a value greater than the minimum indicated by PMSIDR_EL1.Interval
Controls randomization of the sampling interval
RND | Meaning |
---|---|
0b0 | Disable randomization of sampling interval |
0b1 | Add (pseudo-)random jitter to sampling interval |
The random number generator is not architected.
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | CRn | op0 | op1 | op2 | CRm |
---|---|---|---|---|---|
PMSIRR_EL1 | 1001 | 11 | 000 | 000 | 1010 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RW | n/a | RW |
x | 0 | 1 | - | RW | RW | RW |
x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
If AArch64-MDCR_EL2.TPMS == 0b1 && AArch64-SCR_EL3.NS == 0b1, then access from EL1 traps to EL2
If AArch64-MDCR_EL3.NSPB != 0b01 && AArch64-SCR_EL3.NS == 0b0, then access from EL1 traps to EL3
If AArch64-MDCR_EL3.NSPB != 0b11 && AArch64-SCR_EL3.NS == 0b1, then access from EL2 or EL1 traps to EL3
12/09/2017 18:03
Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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