The ACTLR characteristics are:
Provides IMPLEMENTATION DEFINED configuration and control options for execution at EL1 and EL0.
This register is part of:
AArch32 System register ACTLR is architecturally mapped to AArch64 System register ACTLR_EL1[31:0] .
Some bits might define global configuration settings, and be common to the Secure and Non-secure instances of the register.
RW fields in this register reset to architecturally UNKNOWN values.
ACTLR is a 32-bit register.
The ACTLR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED |
IMPLEMENTATION DEFINED.
This register can be read using MRC with the following syntax:
MRC <syntax>
This register can be written using MCR with the following syntax:
MCR <syntax>
This syntax uses the following encoding in the System instruction encoding space:
<syntax> | opc1 | opc2 | CRn | coproc | CRm |
---|---|---|---|---|---|
p15, 0, <Rt>, c1, c0, 1 | 000 | 001 | 0001 | 1111 | 0000 |
The register is accessible as follows:
Configuration | Control | Accessibility | Instance | |||||
---|---|---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 | ||
EL3 using AArch32 | x | x | 0 | - | n/a | n/a | RW | ACTLR_s |
EL3 using AArch32 | x | 0 | 1 | - | RW | RW | RW | ACTLR_ns |
EL3 using AArch32 | x | 1 | 1 | - | n/a | RW | RW | ACTLR_ns |
EL3 not implemented | x | x | 0 | - | RW | n/a | n/a | ACTLR |
EL3 not implemented | x | 0 | 1 | - | RW | RW | n/a | ACTLR |
EL3 not implemented | x | 1 | 1 | - | n/a | RW | n/a | ACTLR |
EL3 using AArch64 | x | x | 0 | - | RW | n/a | n/a | ACTLR |
EL3 using AArch64 | x | 0 | 1 | - | RW | RW | n/a | ACTLR |
EL3 using AArch64 | x | 1 | 1 | - | n/a | RW | n/a | ACTLR |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :
If HCR_EL2.TACR==1, Non-secure accesses to this register from EL1 are trapped to EL2 using AArch64.
If HSTR_EL2.T1==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :
If HCR_EL2.TACR==1, Non-secure accesses to this register from EL1 are trapped to EL2 using AArch64.
If HSTR_EL2.T1==1, Non-secure accesses to this register from EL1 are trapped to EL2.
When EL2 is implemented and is using AArch32 and SCR_EL3.NS==1 :
28/09/2017 08:24
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