no old filehtmldiff from-SysReg_v83A_xml-00bet4(new) SysReg_v83A_xml-00bet5

PMBLIMITR_EL1, Profiling Buffer Limit Address Register

The PMBLIMITR_EL1 characteristics are:

Purpose

Defines the upper limit for the profiling buffer, and enables the profiling buffer

This register is part of the Statistical Profiling Extension registers functional group.

Configuration

Present only if the Statistical Profiling Extension is implemented. Direct reads and writes of PMBLIMITR_EL1 are UNDEFINED at EL0.

Attributes

PMBLIMITR_EL1 is a 64-bit register.

Field descriptions

The PMBLIMITR_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
LIMIT
LIMIT000000000FME
313029282726252423222120191817161514131211109876543210

LIMIT, bits [63:12]

Limit address, plus one. Read/write. Defines the limit of the buffer. If the smallest implemented translation granule is not 4KB, then bits [N-1:12] are RES0, where N is the IMPLEMENTATION DEFINED value, Log2(smallest implemented translation granule).

Bits [11:3]

Reserved, RES0.

FM, bits [2:1]

Fill mode

FMMeaning
0b00

Stop collection and raise maintenance interrupt on buffer fill

All other values are reserved. If this field is programmed with a reserved value, the PE behaves as if this field has a defined value, other than for a direct read of the register. Software must not rely on the behavior of reserved values, as they might change in a future version of the architecture.

E, bit [0]

Profiling Buffer enable

EMeaning
0b0

All output is discarded

0b1

Enabled

When this register has an architecturally-defined reset value, this field resets to 0 on Warm or Cold reset.

Accessing the PMBLIMITR_EL1

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> CRnop0op1op2CRm
PMBLIMITR_EL11001110000001010

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RW n/a RW
x01 - RWRWRW
x11 - n/a RWRW

This table applies to all instructions that can access this register.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.




12/09/2017 18:03

Copyright © 2010-2017 ARM Limited or its affiliates. All rights reserved. This document is Non-Confidential.

no old filehtmldiff from-SysReg_v83A_xml-00bet4(new) SysReg_v83A_xml-00bet5