The PMSEVFR_EL1 characteristics are:
Controls sample filtering by events. The overall filter is the logical AND of these filters. For example, if E[3] and E[5] are both set to 1, only samples that have both event 3 (Level 1 unified or data cache refill) and event 5 set (TLB walk) are recorded
This register is part of the Statistical Profiling Extension registers functional group.
Present only if the Statistical Profiling Extension is implemented. Direct reads and writes of PMSEVFR_EL1 are UNDEFINED otherwise.
PMSEVFR_EL1 is a 64-bit register.
The PMSEVFR_EL1 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
E | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||||||||||||
E | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | E | 0 | 0 | 0 | 0 | E[7] | 0 | E[5] | 0 | E[3] | 0 | E[1] | 0 | ||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
E[n] is the event filter for event n. If event n is not implemented, or filtering on event n is not supported, the corresponding bit is RES0.
E | Meaning |
---|---|
0b0 |
Event n is ignored. |
0b1 |
Record samples that have event n == 1 |
An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, if the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.
This field is ignored by the PE when PMSFCR_EL1.FE == 0b0
E[n] is the event filter for event n. If event n is not implemented, or filtering on event n is not supported, the corresponding bit is RES0.
E | Meaning |
---|---|
0b0 |
Event n is ignored. |
0b1 |
Record samples that have event n == 1 |
An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, if the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.
This field is ignored by the PE when PMSFCR_EL1.FE == 0b0
E[n] is the event filter for event n. If event n is not implemented, or filtering on event n is not supported, the corresponding bit is RES0.
E | Meaning |
---|---|
0b0 |
Event n is ignored. |
0b1 |
Record samples that have event n == 1 |
An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, if the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.
This field is ignored by the PE when PMSFCR_EL1.FE == 0b0
Reserved, RES0.
Reserved, RES0.
Reserved, RES0.
Reserved, RES0.
Reserved, RES0.
Reserved, RES0.
Reserved, RES0.
Mispredicted
E[7] | Meaning |
---|---|
0b0 |
Mispredicted event is ignored. |
0b1 |
Record samples that have event 7 (Mispredicted) == 1 |
This bit is ignored by the PE when PMSFCR_EL1.FE == 0.
TLB walk
E[5] | Meaning |
---|---|
0b0 |
TLB walk event is ignored. |
0b1 |
Record samples that have event 5 (TLB walk) == 1 |
This bit is ignored by the PE when PMSFCR_EL1.FE == 0.
Level 1 data or unified cache refill
E[3] | Meaning |
---|---|
0b0 |
Level 1 data or unified cache refill event is ignored. |
0b1 |
Record samples that have event 3 (Level 1 data or unified cache refill) == 1 |
This bit is ignored by the PE when PMSFCR_EL1.FE == 0.
Architecturally retired
E[1] | Meaning |
---|---|
0b0 |
Architecturally retired event is ignored. |
0b1 |
Record samples that have event 1 (Architecturally retired) == 1 |
This bit is ignored by the PE when PMSFCR_EL1.FE == 0.
If the PE does not support sampling of speculative instructions this bit is RES1.
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This register can be read using MRS with the following syntax:
MRS <Xt>, <systemreg>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | CRn | op0 | op1 | op2 | CRm |
---|---|---|---|---|---|
PMSEVFR_EL1 | 1001 | 11 | 000 | 101 | 1001 |
The register is accessible as follows:
Control | Accessibility | |||||
---|---|---|---|---|---|---|
E2H | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | 0 | - | RW | n/a | RW |
x | 0 | 1 | - | RW | RW | RW |
x | 1 | 1 | - | n/a | RW | RW |
This table applies to all instructions that can access this register.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
If AArch64-MDCR_EL2.TPMS == 0b1 && AArch64-SCR_EL3.NS == 0b1, then access from EL1 traps to EL2
If AArch64-MDCR_EL2.NSPB != 0b01 && AArch64-SCR_EL3.NS == 0b0, then access from EL1 traps to EL3
If AArch64-MDCR_EL2.NSPB != 0b11 && AArch64-SCR_EL3.NS == 0b1, then access from EL2 or EL1 traps to EL3
12/09/2017 18:03
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