The ICC_EOIR0_EL1 characteristics are:
A PE writes to this register to inform the CPU interface that it has completed the processing of the specified Group 0 interrupt.
This register is part of:
AArch64 System register ICC_EOIR0_EL1 performs the same function as AArch32 System register ICC_EOIR0.
ICC_EOIR0_EL1 is a 32-bit register.
The ICC_EOIR0_EL1 bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | INTID |
Reserved, RES0.
The INTID from the corresponding ICC_IAR0_EL1 access.
This field has either 16 or 24 bits implemented. The number of implemented bits can be found in ICC_CTLR_EL1.IDbits and ICC_CTLR_EL3.IDbits. If only 16 bits are implemented, bits [23:16] of this register are RES0.
If the EOImode bit for the current Exception level and Security state is 0, a write to this register drops the priority for the interrupt, and also deactivates the interrupt.
If the EOImode bit for the current Exception level and Security state is 1, a write to this register only drops the priority for the interrupt. Software must write to ICC_DIR_EL1 to deactivate the interrupt.
The EOImode bit for the current Exception level and Security state is determined as follows:
This register can be written using MSR (register) with the following syntax:
MSR <systemreg>, <Xt>
This syntax uses the following encoding in the System instruction encoding space:
<systemreg> | op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|---|
ICC_EOIR0_EL1 | 11 | 000 | 1100 | 1000 | 001 |
When HCR_EL2.FMO is set to 1, execution of this encoding at Non-secure EL1 results in an access to ICV_EOIR0_EL1.
The register is accessible as follows:
Control | Accessibility | ||||||
---|---|---|---|---|---|---|---|
FMO | IMO | TGE | NS | EL0 | EL1 | EL2 | EL3 |
x | x | x | 0 | - | WO | n/a | WO |
x | x | 1 | 1 | - | n/a | WO | WO |
0 | x | 0 | 1 | - | WO | WO | WO |
1 | x | 0 | 1 | - | ICV_EOIR0_EL1 | WO | WO |
This table applies to all instructions that can access this register.
ICC_EOIR0_EL1 is only accessible at Non-secure EL1 when HCR_EL2.FMO is set to 0.
When HCR_EL2.FMO is set to 1, at Non-secure EL1, the instruction encoding used to access ICC_EOIR0_EL1 results in an access to ICV_EOIR0_EL1.
A write to this register must correspond to the most recent valid read by this PE from an Interrupt Acknowledge Register, and must correspond to the INTID that was read from ICC_IAR0_EL1, otherwise the system behavior is UNPREDICTABLE. A valid read is a read that returns a valid INTID that is not a special INTID.
A write of a Special INTID is ignored. See Special INTIDs, for more information.
For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.
In both Security states, and not dependent on other configuration bits:
If ICC_SRE_EL1.SRE==0, write accesses to this register from EL1 are trapped to EL1.
If ICC_SRE_EL2.SRE==0, write accesses to this register from EL2 are trapped to EL2.
If ICC_SRE_EL3.SRE==0, write accesses to this register from EL3 are trapped to EL3.
When SCR_EL3.NS==1 :
If ICH_HCR_EL2.TALL0==1, Non-secure write accesses to this register from EL1 are trapped to EL2.
When EL3 is implemented and is using AArch64 and SCR_EL3.NS==0 :
If SCR_EL3.FIQ==1, Secure write accesses to this register from EL1 are trapped to EL3.
When EL3 is implemented and is using AArch64 :
If SCR_EL3.FIQ==1, write accesses to this register from EL2 are trapped to EL3.
When EL3 is implemented and is using AArch64 and SCR_EL3.NS==1 :
28/09/2017 08:24
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