MAIR_EL1, Memory Attribute Indirection Register (EL1)

The MAIR_EL1 characteristics are:

Purpose

Provides the memory attribute encodings corresponding to the possible AttrIndx values in a Long-descriptor format translation table entry for stage 1 translations at EL1.

This register is part of the Virtual memory control registers functional group.

Configuration

AArch64 System register MAIR_EL1 bits [31:0] are architecturally mapped to AArch32 System register PRRR when TTBCR.EAE==0.

AArch64 System register MAIR_EL1 bits [31:0] are architecturally mapped to AArch32 System register MAIR0 when TTBCR.EAE==1.

AArch64 System register MAIR_EL1 bits [63:32] are architecturally mapped to AArch32 System register NMRR when TTBCR.EAE==0.

AArch64 System register MAIR_EL1 bits [63:32] are architecturally mapped to AArch32 System register MAIR1 when TTBCR.EAE==1.

RW fields in this register reset to architecturally UNKNOWN values.

Attributes

MAIR_EL1 is a 64-bit register.

Field descriptions

The MAIR_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
Attr7Attr6Attr5Attr4
Attr3Attr2Attr1Attr0
313029282726252423222120191817161514131211109876543210

MAIR_EL1 is permitted to be cached in a TLB.

Attr<n>, bits [8n+7:8n], for n = 0 to 7

The memory attribute encoding for an AttrIndx[2:0] entry in a Long descriptor format translation table entry, where AttrIndx[2:0] gives the value of <n> in Attr<n>.

Bits [7:4] are encoded as follows:

Attr<n>[7:4] Meaning
0000 Device memory. See encoding of Attr<n>[3:0] for the type of Device memory.
00RW, RW not 00 Normal memory, Outer Write-Through Transient
0100 Normal memory, Outer Non-cacheable
01RW, RW not 00 Normal memory, Outer Write-Back Transient
10RW Normal memory, Outer Write-Through Non-transient
11RW Normal memory, Outer Write-Back Non-transient

R = Outer Read-Allocate policy, W = Outer Write-Allocate policy.

The meaning of bits [3:0] depends on the value of bits [7:4]:

Attr<n>[3:0] Meaning when Attr<n>[7:4] is 0000 Meaning when Attr<n>[7:4] is not 0000
0000 Device-nGnRnE memory UNPREDICTABLE
00RW, RW not 00 UNPREDICTABLE Normal memory, Inner Write-Through Transient
0100 Device-nGnRE memory Normal memory, Inner Non-cacheable
01RW, RW not 00 UNPREDICTABLE Normal memory, Inner Write-Back Transient
1000 Device-nGRE memory Normal memory, Inner Write-Through Non-transient (RW=00)
10RW, RW not 00 UNPREDICTABLE Normal memory, Inner Write-Through Non-transient
1100 Device-GRE memory Normal memory, Inner Write-Back Non-transient (RW=00)
11RW, RW not 00 UNPREDICTABLE Normal memory, Inner Write-Back Non-transient

R = Inner Read-Allocate policy, W = Inner Write-Allocate policy.

The R and W bits in some Attr<n> fields have the following meanings:

R or W Meaning
0 No Allocate
1 Allocate

Accessing the MAIR_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This register can be written using MSR (register) with the following syntax:

MSR <systemreg>, <Xt>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> op0op1CRnCRmop2
MAIR_EL11100010100010000
MAIR_EL121110110100010000

Accessibility

The register is accessible as follows:

<systemreg> Control Accessibility
E2HTGENSEL0EL1EL2EL3
MAIR_EL1xx0 - RW n/a RW
MAIR_EL1001 - RWRWRW
MAIR_EL1011 - n/a RWRW
MAIR_EL1101 - RW MAIR_EL2 RW
MAIR_EL1111 - n/a MAIR_EL2 RW
MAIR_EL12xx0 - - n/a -
MAIR_EL12001 - - - -
MAIR_EL12011 - n/a - -
MAIR_EL12101 - - RWRW
MAIR_EL12111 - n/a RWRW

When HCR_EL2.E2H is 1, without explicit synchronization, access from EL3 using the mnemonic MAIR_EL1 or MAIR_EL12 are not guaranteed to be ordered with respect to accesses using the other mnemonic.

Traps and enables

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules, the following traps and enables are applicable when accessing this register.

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==0 :

When EL2 is implemented and is using AArch64 and SCR_EL3.NS==1 && HCR_EL2.E2H==1 && HCR_EL2.TGE==0 :




28/09/2017 08:24

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