PMBIDR_EL1, Profiling Buffer ID Register

The PMBIDR_EL1 characteristics are:

Purpose

Provides information to software as to whether the buffer can be programmed at the current Exception level.

This register is part of the Statistical Profiling Extension registers functional group.

Configuration

Present only if the Statistical Profiling Extension is implemented. Direct reads of PMBIDR_EL1 are UNDEFINED at EL0.

Attributes

PMBIDR_EL1 is a 64-bit register.

Field descriptions

The PMBIDR_EL1 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
00000000000000000000000000000000
00000000000000000000000000FPAlign
313029282726252423222120191817161514131211109876543210

Bits [63:6]

Reserved, RES0.

F, bit [5]

Flag Updates. Defines whether the address translation performed by the Profiling Buffer manages the Access Flag and Dirty Bit

FMeaning
0b0

Accesses to pages not marked with Access Flag and not with Dirty Bit set will generate an Unsupported Access fault if hardware management of those flags is enabled

0b1

Profiling Buffer address translation manages the Access Flag and Dirty Bit in the same way as the MMU on this PE

P, bit [4]

Prohibited. The Profiling Buffer is owned by the current or a lower Exception level in the current security state.

PMeaning
0b0

Profiling Buffer is owned by the current or a lower Exception level in the current security state. This does not mean an access will not be trapped to a higher Exception level

0b1

Profiling Buffer is owned by a higher Exception level or the other security state

The value read from this field depends on the current Exception level and the values of MDCR_EL3.NSPB and MDCR_EL2.E2PB:

Align, bits [3:0]

Defines the minimum alignment constraint for PMBPTR_EL1. If this field is non-zero, then the PE must pad every record up to a multiple of this size.

AlignMeaning
0b0000

Byte

0b0001

Halfword. PMBPTR_EL1[0] is RES0

0b0010

Word. PMBPTR_EL1[1:0] is RES0

0b0011

Doubleword. PMBPTR_EL1[2:0] is RES0

0b0100

16 Bytes. PMBPTR_EL1[3:0] is RES0

0b0101

32 Bytes. PMBPTR_EL1[4:0] is RES0

0b0110

64 Bytes. PMBPTR_EL1[5:0] is RES0

0b0111

128 Bytes. PMBPTR_EL1[6:0] is RES0

0b1000

256 Bytes. PMBPTR_EL1[7:0] is RES0

0b1001

512 Bytes. PMBPTR_EL1[8:0] is RES0

0b1010

1KB. PMBPTR_EL1[9:0] is RES0

0b1011

2KB. PMBPTR_EL1[10:0] is RES0

All other values are reserved. Reserved values might be defined in a future version of the architecture.

Accessing the PMBIDR_EL1

This register can be read using MRS with the following syntax:

MRS <Xt>, <systemreg>

This syntax uses the following encoding in the System instruction encoding space:

<systemreg> CRnop0op1op2CRm
PMBIDR_EL11001110001111010

Accessibility

The register is accessible as follows:

Control Accessibility
E2HTGENSEL0EL1EL2EL3
xx0 - RO n/a RO
x01 - RORORO
x11 - n/a RORO

This table applies to all instructions that can access this register.




12/09/2017 18:03

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