no old file | htmldiff from- | (new) |
The ALLINT characteristics are:
Allows access to the all interrupt mask bit.
This register is present only when FEAT_NMI is implemented. Otherwise, direct accesses to ALLINT are UNDEFINED.
ALLINT is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | ALLINT | RES0 |
Reserved, RES0.
All interrupt mask.
ALLINT | Meaning |
---|---|
0b0 | When SCTLR_ELx.NMI is 1 and execution is at ELx, an IRQ or FIQ interrupt with Superpriority that is targeted to ELx is not masked by PSTATE.I or PSTATE.F, respectively, unless both PSTATE.SP and SCTLR_ELx.SPINTMASK are 1. An IRQ or FIQ interrupt without Superpriority that is targeted to ELx is masked. |
0b1 | When SCTLR_ELx.NMI is 1 and execution is at ELx, an IRQ or FIQ interrupt that is targeted to ELx is masked by PSTATE.I or PSTATE.F, respectively, regardless of Superpriority. |
When executing at EL0 and SCTLR_ELx.NMI is 1, if an IRQ or FIQ interrupt targeted to ELx is masked by PSTATE.I or PSTATE.F, the mask applies only to IRQ or FIQ interrupts without Superpriority. IRQ or FIQ interrupts with Superpriority are not masked.
The value of this bit is set to the inverse value in the SCTLR_ELx.SPINTMASK field on taking an exception to ELx.
The reset behavior of this field is:
Reserved, RES0.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0100 | 0b0011 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then return Zeros(50):PSTATE.ALLINT:Zeros(13); elsif PSTATE.EL == EL2 then return Zeros(50):PSTATE.ALLINT:Zeros(13); elsif PSTATE.EL == EL3 then return Zeros(50):PSTATE.ALLINT:Zeros(13);
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0100 | 0b0011 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsHCRXEL2Enabled() && HCRX_EL2.TALLINT == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else PSTATE.ALLINT = X[t]<13>; elsif PSTATE.EL == EL2 then PSTATE.ALLINT = X[t]<13>; elsif PSTATE.EL == EL3 then PSTATE.ALLINT = X[t]<13>;
op0 | op1 | CRn | op2 |
---|---|---|---|
0b00 | 0b001 | 0b0100 | 0b000 |
30/09/2021 14:52; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
no old file | htmldiff from- | (new) |