CNTP_CTL, Counter-timer Physical Timer Control

The CNTP_CTL characteristics are:

Purpose

Control register for the EL1 physical timer.

Configuration

The power domain of CNTP_CTL is IMPLEMENTATION DEFINED.

For more information, see 'Power and reset domains for the system level implementation of the Generic Timer'.

Attributes

CNTP_CTL is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
RES0ISTATUSIMASKENABLE

Bits [31:3]

Reserved, RES0.

ISTATUS, bit [2]

The status of the timer. This bit indicates whether the timer condition is met:

ISTATUSMeaning
0b0

Timer condition is not met.

0b1

Timer condition is met.

When the value of the ENABLE bit is 1, ISTATUS indicates whether the timer condition is met. ISTATUS takes no account of the value of the IMASK bit. If the value of ISTATUS is 1 and the value of IMASK is 0 then the timer interrupt is asserted.

When the value of the ENABLE bit is 0, the ISTATUS field is UNKNOWN.

The reset behavior of this field is:

Access to this field is RO.

IMASK, bit [1]

Timer interrupt mask bit. Permitted values are:

IMASKMeaning
0b0

Timer interrupt is not masked by the IMASK bit.

0b1

Timer interrupt is masked by the IMASK bit.

For more information, see the description of the ISTATUS bit.

The reset behavior of this field is:

ENABLE, bit [0]

Enables the timer. Permitted values are:

ENABLEMeaning
0b0

Timer disabled.

0b1

Timer enabled.

Setting this bit to 0 disables the timer output signal, but the timer value accessible from CNTP_TVAL continues to count down.

Note

Disabling the output signal might be a power-saving option.

The reset behavior of this field is:

Accessing CNTP_CTL

CNTP_CTL can be implemented in any implemented CNTBaseN frame, and in the corresponding CNTEL0BaseN frame.

'CNTCTLBase status and control fields for the CNTBaseN and CNTEL0BaseN frames' describes the status fields that identify whether a CNTBaseN frame is implemented, and for an implemented frame:

For an implemented CNTBaseN frame:

For an implemented CNTEL0BaseN frame:

CNTP_CTL can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
TimerCNTBaseN0x02CCNTP_CTL

Accesses on this interface are RW.

ComponentFrameOffsetInstance
TimerCNTEL0BaseN0x02CCNTP_CTL

Accesses on this interface are RW.


20/09/2021 12:37; d4a233ffbdfb36e47856c443a7ce9a85f5e501ca

Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.