The TRCCNTVR<n> characteristics are:
This sets or returns the value of Counter <n>.
External register TRCCNTVR<n> bits [31:0] are architecturally mapped to AArch64 System register TRCCNTVR<n>[31:0].
This register is present only when FEAT_ETE is implemented and TRCIDR5.NUMCNTR > n. Otherwise, direct accesses to TRCCNTVR<n> are RES0.
TRCCNTVR<n> is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | VALUE |
Reserved, RES0.
Contains the count value of Counter.
The reset behavior of this field is:
Must be programmed if TRCRSCTLR<a>.GROUP == 0b0010 and TRCRSCTLR<a>.COUNTERS[n] == 1.
Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.
Reads from this register might return an UNKNOWN value if the trace unit is not in either of the Idle or Stable states.
Component | Offset | Instance |
---|---|---|
ETE | 0x160 + (4 * n) | TRCCNTVR<n> |
This interface is accessible as follows:
20/09/2021 12:37; d4a233ffbdfb36e47856c443a7ce9a85f5e501ca
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.