The TRBSR_EL1 characteristics are:
Provides syndrome information to software for a trace buffer management event.
This register is present only when FEAT_TRBE is implemented. Otherwise, direct accesses to TRBSR_EL1 are UNDEFINED.
TRBSR_EL1 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
EC | RES0 | IRQ | TRG | WRAP | RES0 | EA | S | RES0 | MSS |
Reserved, RES0.
Event class. Top-level description of the cause of the trace buffer management event.
EC | Meaning | MSS | Applies when |
---|---|---|---|
0b000000 |
Other trace buffer management event. All trace buffer management events other than those described by the other defined Event class codes. | MSS encoding for other trace buffer management events | |
0b011110 |
Granule Protection Check fault, other than GPF, on write to trace buffer. | MSS encoding for Granule Protection Check fault | When FEAT_RME is implemented |
0b011111 |
Buffer management event for IMPLEMENTATION DEFINED reason. | MSS encoding for Buffer management event for IMPLEMENTATION DEFINED reason | |
0b100100 |
Stage 1 Data Abort on write to trace buffer. | MSS encoding for stage 1 or stage 2 Data Aborts on write to trace buffer | |
0b100101 |
Stage 2 Data Abort on write to trace buffer. | MSS encoding for stage 1 or stage 2 Data Aborts on write to trace buffer |
All other values are reserved.
The reset behavior of this field is:
Reserved, RES0.
Maintenance interrupt status.
IRQ | Meaning |
---|---|
0b0 |
Maintenance interrupt is not asserted. |
0b1 |
Maintenance interrupt is asserted. |
The reset behavior of this field is:
Triggered.
TRG | Meaning |
---|---|
0b0 |
No Detected Trigger has been observed since this field was last cleared to zero. |
0b1 |
A Detected Trigger has been observed since this field was last cleared to zero. |
The reset behavior of this field is:
Wrapped.
WRAP | Meaning |
---|---|
0b0 |
The current write pointer has not wrapped since this field was last cleared to zero. |
0b1 |
The current write pointer has wrapped since this field was last cleared to zero. |
For each byte of trace the Trace Buffer Unit Accepts and writes to the trace buffer at the address in the current write pointer, if the current write pointer is equal to the Limit pointer minus one, the current write pointer is wrapped by setting it to the Base pointer, and this field is set to 1.
The reset behavior of this field is:
Reserved, RES0.
External Abort.
EA | Meaning |
---|---|
0b0 |
An External Abort has not been asserted. |
0b1 |
An External Abort has been asserted and detected by the Trace Buffer Unit. |
The reset behavior of this field is:
Accessing this field has the following behavior:
Stopped.
S | Meaning |
---|---|
0b0 |
Collection has not been stopped. |
0b1 |
Collection is stopped. |
The reset behavior of this field is:
Reserved, RES0.
Management Event Specific Syndrome. Contains syndrome specific to the management event.
The syndrome contents for each management event are described in the following sections.
The reset behavior of this field is:
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | BSC |
Reserved, RES0.
Trace buffer status code.
BSC | Meaning |
---|---|
0b000000 |
Collection not stopped. |
0b000001 |
Trace buffer filled. Collection stopped because the current write pointer wrapped to the base pointer and the trace buffer mode is Fill mode. |
0b000010 |
Trigger Event. Collection stopped because of a Trigger Event. See TRBTRG_EL1 for more information. |
All other values are reserved.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED |
IMPLEMENTATION DEFINED.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 |
Reserved, RES0.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | FSC |
Reserved, RES0.
Fault status code.
FSC | Meaning | Applies when |
---|---|---|
0b000000 |
Address size fault, level 0 of translation or translation table base register. | |
0b000001 |
Address size fault, level 1. | |
0b000010 |
Address size fault, level 2. | |
0b000011 |
Address size fault, level 3. | |
0b000100 |
Translation fault, level 0. | |
0b000101 |
Translation fault, level 1. | |
0b000110 |
Translation fault, level 2. | |
0b000111 |
Translation fault, level 3. | |
0b001001 |
Access flag fault, level 1. | |
0b001010 |
Access flag fault, level 2. | |
0b001011 |
Access flag fault, level 3. | |
0b001000 |
Access flag fault, level 0. | When FEAT_LPA2 is implemented |
0b001100 |
Permission fault, level 0. | When FEAT_LPA2 is implemented |
0b001101 |
Permission fault, level 1. | |
0b001110 |
Permission fault, level 2. | |
0b001111 |
Permission fault, level 3. | |
0b010000 |
Synchronous External abort, not on translation table walk or hardware update of translation table. | |
0b010001 |
Asynchronous External abort. | |
0b010011 |
Synchronous External abort on translation table walk or hardware update of translation table, level -1. | When FEAT_LPA2 is implemented |
0b010100 |
Synchronous External abort on translation table walk or hardware update of translation table, level 0. | |
0b010101 |
Synchronous External abort on translation table walk or hardware update of translation table, level 1. | |
0b010110 |
Synchronous External abort on translation table walk or hardware update of translation table, level 2. | |
0b010111 |
Synchronous External abort on translation table walk or hardware update of translation table, level 3. | |
0b011011 |
Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level -1. | When FEAT_LPA2 is implemented and FEAT_RAS is not implemented |
0b100001 |
Alignment fault. | |
0b100011 |
Granule Protection Fault on translation table walk or hardware update of translation table, level -1. | When FEAT_RME is implemented and FEAT_LPA2 is implemented |
0b100100 |
Granule Protection Fault on translation table walk or hardware update of translation table, level 0. | When FEAT_RME is implemented |
0b100101 |
Granule Protection Fault on translation table walk or hardware update of translation table, level 1. | When FEAT_RME is implemented |
0b100110 |
Granule Protection Fault on translation table walk or hardware update of translation table, level 2. | When FEAT_RME is implemented |
0b100111 |
Granule Protection Fault on translation table walk or hardware update of translation table, level 3. | When FEAT_RME is implemented |
0b101000 |
Granule Protection Fault, not on translation table walk or hardware update of translation table. | When FEAT_RME is implemented |
0b101001 |
Address size fault, level -1. | When FEAT_LPA2 is implemented |
0b101011 |
Translation fault, level -1. | When FEAT_LPA2 is implemented |
0b110000 |
TLB conflict abort. | |
0b110001 |
Unsupported atomic hardware update fault. | When FEAT_HAFDBS is implemented |
All other values are reserved.
The PE might ignore a direct write to TRBSR_EL1 if TRBLIMITR_EL1.E == 1.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1001 | 0b1011 | 0b011 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then UNDEFINED; elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.TRBSR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.E2TB == 'x0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return TRBSR_EL1; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return TRBSR_EL1; elsif PSTATE.EL == EL3 then return TRBSR_EL1;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1001 | 0b1011 | 0b011 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then UNDEFINED; elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.TRBSR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.E2TB == 'x0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else TRBSR_EL1 = X[t]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else TRBSR_EL1 = X[t]; elsif PSTATE.EL == EL3 then TRBSR_EL1 = X[t];
30/09/2021 14:53; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f
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