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MPAMSM_EL1, MPAM Streaming Mode Register

The MPAMSM_EL1 characteristics are:

Purpose

Holds information to generate MPAM labels for memory requests issued by SME, SVE, and SIMD&FP load and store instructions and, when the PE is in Streaming SVE mode, by SVE and SIMD&FP load and store instructions.mode. For those requests, the MPAM labels in this register have precedence over the labels in MPAM0_EL1, MPAM1_EL1, MPAM2_EL2, and MPAM3_EL3.

It is IMPLEMENTATION DEFINED whether the MPAM labels in this register are used for memory requests due to hardware page table walks orand page table updates performed as a result of SME, loadSVE, and SIMD&FP load/store instructions, and SVE prefetch instructions, when the PE is in Streaming SVE mode, SVE and SIMD&FP load and store instructions, and SVE prefetch instructions.mode.

The MPAM labels in this register are only used if MPAM1_EL1.MPAMEN is 1.

For memory requests issued from EL0, the MPAM PARTID in this register is virtual and mapped into a physical PARTID when all of the following are true:

For memory requests issued from EL1, the MPAM PARTID in this register is virtual and mapped into a physical PARTID when all of the following are true:

Configuration

This register is present only when FEAT_MPAM is implemented and FEAT_SME is implemented. Otherwise, direct accesses to MPAMSM_EL1 are UNDEFINED.

Attributes

MPAMSM_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0PMG_DRES0
PARTID_DRES0

Bits [63:48]

Reserved, RES0.

PMG_D, bits [47:40]

Performance monitoring group property for PARTID_D.

The reset behavior of this field is:

Bits [39:32]

Reserved, RES0.

PARTID_D, bits [31:16]

Partition ID for requestsdata issuedaccesses due to the execution atof anySME, ExceptionSVE, leveland ofSIMD&FP SME load and store instructions and,performed when the PE is in Streaming SVE mode, SVEat andany SIMD&FPException load and store instructions and SVE prefetch instructions.level.

The reset behavior of this field is:

Bits [15:0]

Reserved, RES0.

Accessing MPAMSM_EL1

None of the fields in this register are permitted to be cached in a TLB.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, MPAMSM_EL1

op0op1CRnCRmop2
0b110b0000b10100b01010b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && MPAM2_EL2.EnMPAMSM == '0' then AArch64.SystemAccessTrap(EL2, 0x18); else return MPAMSM_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return MPAMSM_EL1; elsif PSTATE.EL == EL3 then return MPAMSM_EL1;

MSR MPAMSM_EL1, <Xt>

op0op1CRnCRmop2
0b110b0000b10100b01010b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && MPAM2_EL2.EnMPAMSM == '0' then AArch64.SystemAccessTrap(EL2, 0x18); else MPAMSM_EL1 = X[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else MPAMSM_EL1 = X[t]; elsif PSTATE.EL == EL3 then MPAMSM_EL1 = X[t];


3020/09/2021 1412:5337; 092b4e1bbfbb45a293b198f9330c5f529ead2b0fd4a233ffbdfb36e47856c443a7ce9a85f5e501ca

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