TRBIDR_EL1, Trace Buffer ID Register

The TRBIDR_EL1 characteristics are:

Purpose

Describes constraints on using the Trace Buffer Unit to software, including whether the Trace Buffer Unit can be programmed at the current Exception level.

Configuration

This register is present only when FEAT_TRBE is implemented. Otherwise, direct accesses to TRBIDR_EL1 are UNDEFINED.

Attributes

TRBIDR_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0FPAlign

Bits [63:6]

Reserved, RES0.

F, bit [5]

Flag Updates. Defines whether the address translation performed by the Trace Buffer Unit manages the Access Flag and dirty state. Defined values are:

FMeaning
0b0

Trace buffer address translation does not manage the Access flag and dirty state in translation tables.

0b1

Trace buffer address translation manages the Access Flag and dirty state in the same way as the MMU on this PE.

P, bit [4]

Programming not allowed. When read at EL3, this field reads as zero. Otherwise, indicates that the trace buffer is owned by a higher Exception level or another Security state. Defined values are:

PMeaning
0b0

Programming is allowed.

0b1

Programming not allowed.

The value read from this field depends on the current Exception level and the Effective values of MDCR_EL3.NSTB, MDCR_EL3.NSTBE, and MDCR_EL2.E2TB:

Align, bits [3:0]

Defines the minimum alignment constraint for writes to TRBPTR_EL1 and TRBTRG_EL1. Defined values are:

AlignMeaning
0b0000

Byte.

0b0001

Halfword.

0b0010

Word.

0b0011

Doubleword.

0b0100

16 bytes.

0b0101

32 bytes.

0b0110

64 bytes.

0b0111

128 bytes.

0b1000

256 bytes.

0b1001

512 bytes.

0b1010

1KB.

0b1011

2KB.

All other values are reserved.

Accessing TRBIDR_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, TRBIDR_EL1

op0op1CRnCRmop2
0b110b0000b10010b10110b111

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.TRBIDR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return TRBIDR_EL1; elsif PSTATE.EL == EL2 then return TRBIDR_EL1; elsif PSTATE.EL == EL3 then return TRBIDR_EL1;


20/09/2021 12:37; d4a233ffbdfb36e47856c443a7ce9a85f5e501ca

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