The EDPIDR1 characteristics are:
Provides information to identify an external debug component.
For more information, see 'About the Peripheral identification scheme'.
Implementation of this register is OPTIONAL.
If FEAT_DoPD is implemented, this register is in the Core power domain. If FEAT_DoPD is not implemented, this register is in the Debug power domain.
This register is required for CoreSight compliance.
EDPIDR1 is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | DES_0 | PART_1 |
Reserved, RES0.
Designer, least significant nibble of JEP106 ID code. For Arm Limited, this field is 0b1011.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Part number, most significant nibble.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Component | Offset | Instance |
---|---|---|
Debug | 0xFE4 | EDPIDR1 |
This interface is accessible as follows:
20/09/2021 12:37; d4a233ffbdfb36e47856c443a7ce9a85f5e501ca
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.