The TRCIDR2 characteristics are:
Returns the tracing capabilities of the trace unit.
AArch64 System register TRCIDR2 bits [31:0] are architecturally mapped to External register TRCIDR2[31:0].
This register is present only when FEAT_ETE is implemented. Otherwise, direct accesses to TRCIDR2 are UNDEFINED.
TRCIDR2 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
WFXMODE | VMIDOPT | CCSIZE | DVSIZE | DASIZE | VMIDSIZE | CIDSIZE | IASIZE |
Reserved, RES0.
Indicates whether WFI and WFE instructions are classified as P0 instructions:
WFXMODE | Meaning |
---|---|
0b0 |
WFI and WFE instructions are not classified as P0 instructions. |
0b1 |
WFI and WFE instructions are classified as P0 instructions. |
Indicates the options for Virtual context identifier selection.
VMIDOPT | Meaning |
---|---|
0b00 |
Virtual context identifier selection not supported. TRCCONFIGR.VMIDOPT is RES0. |
0b01 |
Virtual context identifier selection supported. TRCCONFIGR.VMIDOPT is implemented. |
0b10 |
Virtual context identifier selection not supported. TRCCONFIGR.VMIDOPT is RES1. |
All other values are reserved.
If TRCIDR2.VMIDSIZE == 0b00000 then this field is 0b00.
If TRCIDR2.VMIDSIZE != 0b00000 then this field is 0b10.
Indicates the size of the cycle counter.
CCSIZE | Meaning |
---|---|
0b0000 |
The cycle counter is 12 bits in length. |
0b0001 |
The cycle counter is 13 bits in length. |
0b0010 |
The cycle counter is 14 bits in length. |
0b0011 |
The cycle counter is 15 bits in length. |
0b0100 |
The cycle counter is 16 bits in length. |
0b0101 |
The cycle counter is 17 bits in length. |
0b0110 |
The cycle counter is 18 bits in length. |
0b0111 |
The cycle counter is 19 bits in length. |
0b1000 |
The cycle counter is 20 bits in length. |
All other values are reserved.
Reserved, RES0.
Indicates the data value size in bytes. Data tracing is not implemented in ETE and this field is reserved for other trace architectures. Allocated in other trace architectures.
DVSIZE | Meaning |
---|---|
0b00000 |
Data value tracing not implemented. |
0b00100 |
Data value tracing has a maximum of 32-bit data values. |
0b01000 |
Data value tracing has a maximum of 64-bit data values. |
All other values are reserved.
Reserved, RES0.
Indicates the data address size in bytes. Data tracing is not implemented in ETE and this field is reserved for other trace architectures. Allocated in other trace architectures.
DASIZE | Meaning |
---|---|
0b00000 |
Data address tracing not implemented. |
0b00100 |
Data address tracing has a maximum of 32-bit data addresses. |
0b01000 |
Data address tracing has a maximum of 64-bit data addresses. |
All other values are reserved.
Reserved, RES0.
Indicates the trace unit Virtual context identifier size.
VMIDSIZE | Meaning |
---|---|
0b00000 |
Virtual context identifier tracing is not supported. |
0b00001 |
8-bit Virtual context identifier size. |
0b00010 |
16-bit Virtual context identifier size. |
0b00100 |
32-bit Virtual context identifier size. |
All other values are reserved.
If the PE does not implement EL2 then this field is 0b00000.
If the PE implements EL2 then this field is 0b00100.
Indicates the Context identifier size.
CIDSIZE | Meaning |
---|---|
0b00000 |
Context identifier tracing is not supported. |
0b00100 |
32-bit Context identifier size. |
All other values are reserved.
This field reads as 0b00100.
Virtual instruction address size.
IASIZE | Meaning |
---|---|
0b00100 |
Maximum of 32-bit instruction address size. |
0b01000 |
Maximum of 64-bit instruction address size. |
All other values are reserved.
This field reads as 0b01000.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b001 | 0b0000 | 0b1010 | 0b111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TTA == '1' then UNDEFINED; elsif CPACR_EL1.TTA == '1' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.TRCID == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return TRCIDR2; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TTA == '1' then UNDEFINED; elsif CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return TRCIDR2; elsif PSTATE.EL == EL3 then if CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return TRCIDR2;
20/09/2021 12:37; d4a233ffbdfb36e47856c443a7ce9a85f5e501ca
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