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TRBSR_EL1, Trace Buffer Status/syndrome Register

The TRBSR_EL1 characteristics are:

Purpose

Provides syndrome information to software for a trace buffer management event.

Configuration

This register is present only when FEAT_TRBE is implemented. Otherwise, direct accesses to TRBSR_EL1 are UNDEFINED.

Attributes

TRBSR_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
ECRES0IRQTRGWRAPRES0EASRES0MSS

Bits [63:32]

Reserved, RES0.

EC, bits [31:26]

Event class. Top-level description of the cause of the trace buffer management event.

ECMeaningMSSApplies when
0b000000

Other trace buffer management event. All trace buffer management events other than those described by the other defined Event class codes.

MSS encoding for other trace buffer management events
0b011110

Granule Protection Check fault, other than GPF, on write to trace buffer.

MSS encoding for Granule Protection Check faultMSS encoding for other trace buffer management eventsWhen FEAT_RME is implemented
0b011111

Buffer management event for IMPLEMENTATION DEFINED reason.

MSS encoding for Buffer management event for IMPLEMENTATION DEFINED reason
0b100100

Stage 1 Data Abort on write to trace buffer.

MSS encoding for stage 1 or stage 2 Data Aborts on write to trace buffer
0b100101

Stage 2 Data Abort on write to trace buffer.

MSS encoding for stage 1 or stage 2 Data Aborts on write to trace buffer

All other values are reserved.

The reset behavior of this field is:

Bits [25:23]

Reserved, RES0.

IRQ, bit [22]

Maintenance interrupt status.

IRQMeaning
0b0

Maintenance interrupt is not asserted.

0b1

Maintenance interrupt is asserted.

The reset behavior of this field is:

TRG, bit [21]

Triggered.

TRGMeaning
0b0

No Detected Trigger has been observed since this field was last cleared to zero.

0b1

A Detected Trigger has been observed since this field was last cleared to zero.

The reset behavior of this field is:

WRAP, bit [20]

Wrapped.

WRAPMeaning
0b0

The current write pointer has not wrapped since this field was last cleared to zero.

0b1

The current write pointer has wrapped since this field was last cleared to zero.

For each byte of trace the Trace Buffer Unit Accepts and writes to the trace buffer at the address in the current write pointer, if the current write pointer is equal to the Limit pointer minus one, the current write pointer is wrapped by setting it to the Base pointer, and this field is set to 1.

The reset behavior of this field is:

Bit [19]

Reserved, RES0.

EA, bit [18]

External Abort.

EAMeaning
0b0

An External Abort has not been asserted.

0b1

An External Abort has been asserted and detected by the Trace Buffer Unit.

The reset behavior of this field is:

Accessing this field has the following behavior:

S, bit [17]

Stopped.

SMeaning
0b0

Collection has not been stopped.

0b1

Collection is stopped.

The reset behavior of this field is:

Bit [16]

Reserved, RES0.

MSS, bits [15:0]

Management Event Specific Syndrome. Contains syndrome specific to the management event.

The syndrome contents for each management event are described in the following sections.

The reset behavior of this field is:

MSS encoding for other trace buffer management events

1514131211109876543210
RES0BSC

Bits [15:6]

Reserved, RES0.

BSC, bits [5:0]

Trace buffer status code.

BSCMeaning
0b000000

Collection not stopped.

0b000001

Trace buffer filled. Collection stopped because the current write pointer wrapped to the base pointer and the trace buffer mode is Fill mode.

0b000010

Trigger Event. Collection stopped because of a Trigger Event. See TRBTRG_EL1 for more information.

All other values are reserved.

MSS encoding for Buffer management event for IMPLEMENTATION DEFINED reason

1514131211109876543210
IMPLEMENTATION DEFINED

IMPLEMENTATION DEFINED, bits [15:0]

IMPLEMENTATION DEFINED.

MSS encoding for Granule Protection Check fault

1514131211109876543210
RES0

Bits [15:0]

Reserved, RES0.

MSS encoding for stage 1 or stage 2 Data Aborts on write to trace buffer

1514131211109876543210
RES0FSC

Bits [15:6]

Reserved, RES0.

FSC, bits [5:0]

Fault status code.

FSCMeaningApplies when
0b000000

Address size fault, level 0 of translation or translation table base register.

0b000001

Address size fault, level 1.

0b000010

Address size fault, level 2.

0b000011

Address size fault, level 3.

0b000100

Translation fault, level 0.

0b000101

Translation fault, level 1.

0b000110

Translation fault, level 2.

0b000111

Translation fault, level 3.

0b001001

Access flag fault, level 1.

0b001010

Access flag fault, level 2.

0b001011

Access flag fault, level 3.

0b001000

Access flag fault, level 0.

When FEAT_LPA2 is implemented
0b001100

Permission fault, level 0.

When FEAT_LPA2 is implemented
0b001101

Permission fault, level 1.

0b001110

Permission fault, level 2.

0b001111

Permission fault, level 3.

0b010000

Synchronous External abort, not on translation table walk or hardware update of translation table.

0b010001

Asynchronous External abort.

0b010011

Synchronous External abort on translation table walk or hardware update of translation table, level -1.

When FEAT_LPA2 is implemented
0b010100

Synchronous External abort on translation table walk or hardware update of translation table, level 0.

0b010101

Synchronous External abort on translation table walk or hardware update of translation table, level 1.

0b010110

Synchronous External abort on translation table walk or hardware update of translation table, level 2.

0b010111

Synchronous External abort on translation table walk or hardware update of translation table, level 3.

0b011011

Synchronous parity or ECC error on memory access on translation table walk or hardware update of translation table, level -1.

When FEAT_LPA2 is implemented and FEAT_RAS is not implemented
0b100001

Alignment fault.

0b100011

Granule Protection Fault on translation table walk or hardware update of translation table, level -1.

When FEAT_RME is implemented and FEAT_LPA2 is implemented
0b100100

Granule Protection Fault on translation table walk or hardware update of translation table, level 0.

When FEAT_RME is implemented
0b100101

Granule Protection Fault on translation table walk or hardware update of translation table, level 1.

When FEAT_RME is implemented
0b100110

Granule Protection Fault on translation table walk or hardware update of translation table, level 2.

When FEAT_RME is implemented
0b100111

Granule Protection Fault on translation table walk or hardware update of translation table, level 3.

When FEAT_RME is implemented
0b101000

Granule Protection Fault, not on translation table walk or hardware update of translation table.

When FEAT_RME is implemented
0b101001

Address size fault, level -1.

When FEAT_LPA2 is implemented
0b101011

Translation fault, level -1.

When FEAT_LPA2 is implemented
0b110000

TLB conflict abort.

0b110001

Unsupported atomic hardware update fault.

When FEAT_HAFDBS is implemented

All other values are reserved.

Accessing TRBSR_EL1

The PE might ignore a direct write to TRBSR_EL1 if TRBLIMITR_EL1.E == 1.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, TRBSR_EL1

op0op1CRnCRmop2
0b110b0000b10010b10110b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then UNDEFINED; elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.TRBSR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.E2TB == 'x0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return TRBSR_EL1; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return TRBSR_EL1; elsif PSTATE.EL == EL3 then return TRBSR_EL1;

MSR TRBSR_EL1, <Xt>

op0op1CRnCRmop2
0b110b0000b10010b10110b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then UNDEFINED; elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.TRBSR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.E2TB == 'x0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else TRBSR_EL1 = X[t]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else TRBSR_EL1 = X[t]; elsif PSTATE.EL == EL3 then TRBSR_EL1 = X[t];


3020/09/2021 1412:5337; 092b4e1bbfbb45a293b198f9330c5f529ead2b0fd4a233ffbdfb36e47856c443a7ce9a85f5e501ca

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