ID_AA64SMFR0_EL1, SME Feature ID register 0

The ID_AA64SMFR0_EL1 characteristics are:

Purpose

Provides information about the implemented features of the AArch64 Scalable Matrix Extension, when the ID_AA64PFR1_EL1.SME field is not zero.

For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'.

Configuration

Note

Prior to the introduction of the features described by this register, this register was unnamed and reserved, RES0 from EL1, EL2, and EL3.

Attributes

ID_AA64SMFR0_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
FA64RES0SMEverI16I64RES0F64F64RES0I8I32F16F32B16F32RES0F32F32
RES0

FA64, bit [63]

Indicates support for execution of the full A64 instruction set when the PE is in Streaming SVE mode. Defined values are:

FA64Meaning
0b0

Only those A64 instructions defined as being legal can be executed in Streaming SVE mode.

0b1

All implemented A64 instructions can be executed in Streaming SVE mode, when enabled at the current Exception level by SMCR_EL1.FA64, SMCR_EL2.FA64, and SMCR_EL3.FA64.

FEAT_SME_FA64 implements the functionality identified by the value 0b1.

Bits [62:60]

Reserved, RES0.

SMEver, bits [59:56]

Indicates support for SME instructions when ID_AA64PFR1_EL1.SME is not zero. Defined values are:

SMEverMeaning
0b0000

The non-optional SME instructions are implemented.

All other values are reserved.

FEAT_SME implements the functionality identified by the value 0b0000, when ID_AA64PFR1_EL1.SME is not zero.

From Armv9.2, the only permitted value is 0b0000.

I16I64, bits [55:52]

Indicates SME support for instructions that accumulate into 64-bit integer elements in the ZA array. Defined values are:

I16I64Meaning
0b0000

Instructions that accumulate into 64-bit integer elements in the ZA array are not implemented.

0b1111

The variants of the ADDHA, ADDVA, SMOPA, SMOPS, SUMOPA, SUMOPS, UMOPA, UMOPS, USMOPA, and USMOPS instructions that accumulate into 64-bit integer element tiles are implemented.

All other values are reserved.

The only permitted values are 0b0000 and 0b1111.

Bits [51:49]

Reserved, RES0.

F64F64, bit [48]

Indicates SME support for instructions that accumulate into double-precision floating-point elements in the ZA array. Defined values are:

F64F64Meaning
0b0

Instructions that accumulate into double-precision floating-point elements in the ZA array are not implemented.

0b1

The variants of the FMOPA and FMOPS instructions that accumulate into double-precision element tiles are implemented.

Bits [47:40]

Reserved, RES0.

I8I32, bits [39:36]

Indicates SME support for accumulating 8-bit integer outer products into 32-bit integer tiles. Defined values are:

I8I32Meaning
0b0000

Instructions that accumulate 8-bit outer products into 32-bit tiles are not implemented.

0b1111

The SMOPA, SMOPS, SUMOPA, SUMOPS, UMOPA, UMOPS, USMOPA, and USMOPS instructions that accumulate 8-bit outer products into 32-bit tiles are implemented.

All other values are reserved.

If FEAT_SME is implemented, the only permitted value is 0b1111.

F16F32, bit [35]

Indicates SME support for accumulating half-precision floating-point outer products into single-precision floating-point tiles. Defined values are:

F16F32Meaning
0b0

Instructions that accumulate FP16 outer products into FP32 tiles are not implemented.

0b1

The FMOPA and FMOPS instructions that accumulate half-precision outer products into single-precision tiles are implemented.

If FEAT_SME is implemented, the only permitted value is 0b1.

B16F32, bit [34]

Indicates SME support for accumulating BFloat16 outer products into single-precision floating-point tiles. Defined values are:

B16F32Meaning
0b0

Instructions that accumulate BFloat16 outer products into single-precision tiles are not implemented.

0b1

The BFMOPA and BFMOPS instructions that accumulate BFloat16 outer products into single-precision tiles are implemented.

If FEAT_SME is implemented, the only permitted value is 0b1.

Bit [33]

Reserved, RES0.

F32F32, bit [32]

Indicates SME support for accumulating single-precision floating-point outer products into single-precision floating-point tiles. Defined values are:

F32F32Meaning
0b0

Instructions that accumulate single-precision outer products into single-precision tiles are not implemented.

0b1

The FMOPA and FMOPS instructions that accumulate single-precision outer products into single-precision tiles are implemented.

If FEAT_SME is implemented, the only permitted value is 0b1.

Bits [31:0]

Reserved, RES0.

Accessing ID_AA64SMFR0_EL1

This register is read-only and can be accessed from EL1 and higher.

This register is only accessible from the AArch64 state.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, ID_AA64SMFR0_EL1

op0op1CRnCRmop2
0b110b0000b00000b01000b101

if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_AA64SMFR0_EL1; elsif PSTATE.EL == EL2 then return ID_AA64SMFR0_EL1; elsif PSTATE.EL == EL3 then return ID_AA64SMFR0_EL1;


30/09/2021 14:53; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f

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