The PMDEVARCH characteristics are:
Identifies the programmers' model architecture of the Performance Monitor component.
If FEAT_DoPD is implemented, this register is in the Core power domain. If FEAT_DoPD is not implemented, this register is in the Debug power domain.
PMDEVARCH is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ARCHITECT | PRESENT | REVISION | ARCHID |
Defines the architecture of the component. For Performance Monitors, this is Arm Limited.
Bits [31:28] are the JEP106 continuation code, 0x4.
Bits [27:21] are the JEP106 ID code, 0x3B.
Reads as 0b01000111011.
Access to this field is RO.
Indicates that the DEVARCH is present.
Reads as 0b1.
Access to this field is RO.
Defines the architecture revision. For architectures defined by Arm this is the minor revision.
For Performance Monitors, the revision defined by Armv8 is 0x0.
All other values are reserved.
Reads as 0b0000.
Access to this field is RO.
Defines this part to be an Armv8 debug component. For architectures defined by Arm this is further subdivided.
For Performance Monitors:
This corresponds to Performance Monitors architecture version PMUv3.
Component | Offset | Instance |
---|---|---|
PMU | 0xFBC | PMDEVARCH |
This interface is accessible as follows:
20/09/2021 12:37; d4a233ffbdfb36e47856c443a7ce9a85f5e501ca
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.