The MPAMCFG_CPBM<n> characteristics are:
The MPAMCFG_CPBM<n> register array gives access to the cache portion bitmap. Each register in the array is a read/write register that configures the cache portions numbered from <n * 32> to <31 + (n * 32)> that a PARTID is allowed to allocate.
After setting MPAMCFG_PART_SEL with a PARTID, software writes to the MPAMCFG_CPBM<n> register to configure which cache portions the PARTID is allowed to allocate.
The MPAMCFG_CPBM<n> register that contains the bitmap bit corresponding to cache portion p has n equal to p[15:5]. The field, P<x>, of that MPAMCFG_CPBM<n> register that contains the bitmap bit corresponding to cache portion p has x equal to p[4:0].
MPAMCFG_CPBM<n>_s controls cache portions for the Secure PARTID selected by the Secure instance of MPAMCFG_PART_SEL. MPAMCFG_CPBM<n>_ns controls the cache portions for the Non-secure PARTID selected by the Non-secure instance of MPAMCFG_PART_SEL. MPAMCFG_CPBM<n>_rt controls cache portions for the Root PARTID selected by the Root instance of MPAMCFG_PART_SEL. MPAMCFG_CPBM<n>_rl controls the cache portions for the Realm PARTID selected by the Non-secure instance of MPAMCFG_PART_SEL.
If MPAMF_IDR.HAS_RIS is 1, the control settings accessed are those of the resource instance currently selected by MPAMCFG_PART_SEL.RIS and the PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL.
The power domain of MPAMCFG_CPBM<n> is IMPLEMENTATION DEFINED.
This register is present only when FEAT_MPAM is implemented and MPAMF_IDR.HAS_CPOR_PART == 1. Otherwise, direct accesses to MPAMCFG_CPBM<n> are RES0.
The power and reset domain of each MSC component is specific to that component.
MPAMCFG_CPBM<n> is a 32-bit register.
Portion allocation control bit. Each cache portion allocation control bit, MPAMCFG_CPBM<n>.P<x>, grants permission to the PARTID selected by MPAMCFG_PART_SEL to allocate cache lines within cache portion <x + (n * 32)>.
P<x + (n * 32)> | Meaning |
---|---|
0b0 |
The PARTID is not permitted to allocate into cache portion <x + (n * 32)>. |
0b1 |
The PARTID is permitted to allocate within cache portion <x + (n * 32)>. |
The number of bits in the cache portion partitioning bit map of this component is given in MPAMF_CPOR_IDR.CPBM_WD. CPBM_WD contains a value from 1 to 215, inclusive. Values of CPBM_WD greater than 32 require an array of 32-bit MPAMCFG_CPBM<n> registers to access the cache portion bitmap, up to 1024 registers.
Bits MPAMCFG_CPBM<n>.P<<x + (n * 32)>>, where <x + (n * 32)> is greater than or equal to CPBM_WD, are RES0:
If n > MPAMF_CPOR_IDR.CPBM_WD[15:5], the entire 32 P<x> are RES0.
If n == MPAMF_CPOR_IDR.CPBM_WD[15:5], bits [31: CPBM_WD[4:0]] are RES0 and the remaining bits are valid.
If n < MPAMF_CPOR_IDR.CPBM_WD[15:5], the entire 32 P<x> are valid.
This register is within the MPAM feature page memory frames.
In a system that supports Secure, Non-secure, Root, and Realm memory maps, there must be MPAM feature pages in all four address maps.
MPAMCFG_CPBM<n>_s, MPAMCFG_CPBM<n>_ns, MPAMCFG_CPBM<n>_rt, and MPAMCFG_CPBM<n>_rl must be separate registers.
When RIS is implemented, loads and stores to MPAMCFG_CPBM<n> access the cache portion bitmap configuration settings for the cache resource instance selected by MPAMCFG_PART_SEL.RIS and the PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL.
When RIS is not implemented, loads and stores to MPAMCFG_CPBM<n> access the cache portion bitmap configuration settings for the PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL.
When PARTID narrowing is implemented, loads and stores to MPAMCFG_CPBM<n> access the cache portion bitmap configuration settings for the internal PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL, and MPAMCFG_PART_SEL.INTERNAL must be 1.
When PARTID narrowing is not implemented, loads and stores to MPAMCFG_CPBM<n> access the cache portion bitmap configuration settings for the request PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL, and MPAMCFG_PART_SEL.INTERNAL must be 0.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_s | 0x1000 + (4 * n) | MPAMCFG_CPBM<n>_s |
Accesses on this interface are RW.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_ns | 0x1000 + (4 * n) | MPAMCFG_CPBM<n>_ns |
Accesses on this interface are RW.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_rt | 0x1000 + (4 * n) | MPAMCFG_CPBM<n>_rt |
When FEAT_RME is implemented access on this interface are RW.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_rl | 0x1000 + (4 * n) | MPAMCFG_CPBM<n>_rl |
When FEAT_RME is implemented access on this interface are RW.
20/09/2021 12:37; d4a233ffbdfb36e47856c443a7ce9a85f5e501ca
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