The MSMON_CFG_MBWU_CTL characteristics are:
Controls the MBWU monitor selected by MSMON_CFG_MON_SEL.
MSMON_CFG_MBWU_CTL_s controls the Secure memory bandwidth usage monitor instance selected by the Secure instance of MSMON_CFG_MON_SEL. MSMON_CFG_MBWU_CTL_ns controls Non-secure memory bandwidth usage monitor instance selected by the Non-secure instance of MSMON_CFG_MON_SEL. MSMON_CFG_MBWU_CTL_rt controls the monitor configuration for the Root PARTID selected by the Root instance of MSMON_CFG_MON_SEL. MSMON_CFG_MBWU_CTL_rl controls the monitor configuration for the Realm PARTID selected by the Realm instance of MSMON_CFG_MON_SEL.
If MPAMF_IDR.HAS_RIS is 1, the monitor instance configuration accessed is for the resource instance currently selected by MSMON_CFG_MON_SEL.RIS and the monitor instance of that resource instance selected by MSMON_CFG_MON_SEL.MON_SEL.
The power domain of MSMON_CFG_MBWU_CTL is IMPLEMENTATION DEFINED.
This register is present only when FEAT_MPAM is implemented, MPAMF_IDR.HAS_MSMON == 1 and MPAMF_MSMON_IDR.MSMON_MBWU == 1. Otherwise, direct accesses to MSMON_CFG_MBWU_CTL are RES0.
The power and reset domain of each MSC component is specific to that component.
MSMON_CFG_MBWU_CTL is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EN | CAPT_EVNT | CAPT_RESET | OFLOW_STATUS | OFLOW_INTR | OFLOW_FRZ | OFLOW_CAPT | SUBTYPE | SCLEN | CEVNT_OFLW | MATCH_PMG | MATCH_PARTID | OFLOW_STATUS_L | OFLOW_INTR_L | OFLOW_CAPT_L | RES0 | OFLOW_CAPT_L | TYPE |
Enabled.
EN | Meaning |
---|---|
0b0 |
The monitor instance is disabled and must not collect any information. |
0b1 |
The monitor instance is enabled to collect information according to the configuration of the instance. |
Capture event selector.
When the selected capture event occurs, MSMON_MBWU of the monitor instance is copied to MSMON_MBWU_CAPTURE of the same instance. If the long counter is also implemented, MSMON_MBWU_L is also copied to MSMON_MBWU_L_CAPTURE.
Select the event that triggers capture from the following:
CAPT_EVNT | Meaning |
---|---|
0b000 |
No capture event is triggered. |
0b001 |
External capture event 1 (optional, but recommended) |
0b010 |
External capture event 2 (optional) |
0b011 |
External capture event 3 (optional) |
0b100 |
External capture event 4 (optional) |
0b101 |
External capture event 5 (optional) |
0b110 |
External capture event 6 (optional) |
0b111 |
Capture occurs when a MSMON_CAPT_EVNT register in this MSC is written and causes a capture event for the Security state of this monitor. (optional) |
The values marked as optional indicate capture event sources that can be omitted in an implementation. Those values representing non-implemented event sources must not trigger a capture event.
If capture is not implemented for the MBWU monitor type as indicated by MPAMF_MBWUMON_IDR.HAS_CAPTURE = 0, this field is RAZ/WI.
Reset MSMON_MBWU.VALUE after capture.
Controls whether the VALUE field of the monitor instance is reset to zero immediately after being copied to the corresponding capture register.
CAPT_RESET | Meaning |
---|---|
0b0 |
MSMON_MBWU.VALUE field of the monitor instance is not reset on capture. |
0b1 |
MSMON_MBWU.VALUE field of the monitor instance is reset on capture. |
If capture is not implemented for the MBWU monitor type as indicated by MPAMF_MBWUMON_IDR.HAS_CAPTURE = 0, this field is RAZ/WI.
This control bit affects both MSMON_MBWU and MSMON_MBWU_L in implementations that include MSMON_MBWU_L.
Overflow status.
Indicates whether the value of MSMON_MBWU has overflowed.
OFLOW_STATUS | Meaning |
---|---|
0b0 |
MSMON_MBWU.VALUE has not overflowed. |
0b1 |
MSMON_MBWU.VALUE has overflowed at least once since this bit was last written to zero. |
If overflow is not possible for an MBWU monitor in the MSC implementation, this field is RAZ/WI.
Overflow status for MSMON_MBWU_L.VALUE is reported in MSMON_CFG_MBWU_CTL.OFLOW_STATUS_L.
If MPAMF_MBWUMON_IDR.HAS_OFLOW_CAPT is 1 or MPAMF_MBWUMON_IDR.HAS_OFLOW_LNKG is 1, then a store to MSMON_MBWU when this field is 1 resets this field to 0.
Enable interrupt on overflow of MSMON_MBWU.VALUE.
OFLOW_INTR | Meaning |
---|---|
0b0 |
No interrupt is signaled on an overflow of MSMON_MBWU.VALUE. |
0b1 |
An implementation-specific interrupt is signaled on an overflow of MSMON_MBWU.VALUE. |
If overflow is not possible for an MBWU monitor in the MSC implementation, this field is RAZ/WI.
If overflow interrupt is not supported by the MSC implementation, this field is RAZ/WI.
Interrupt enable for overflow of MSMON_MBWU_L.VALUE is controlled by MSMON_CFG_MBWU_CTL.OFLOW_INTR_L.
Freeze monitor instance on overflow.
Controls whether MSMON_MBWU.VALUE field of the monitor instance freezes on an overflow.
OFLOW_FRZ | Meaning |
---|---|
0b0 |
MSMON_MBWU.VALUE field of the monitor instance wraps on overflow. |
0b1 |
MSMON_MBWU.VALUE field of the monitor instance freezes on overflow. If the increment that caused the overflow was 1, the frozen value is the post-increment value of 0. If the increment that caused the overflow was larger than 1, the frozen value of the monitor might be 0 or a larger value less than the final increment. |
If overflow is not possible for the instance of the MBWU monitor in the implementation, this field is RAZ/WI.
This control bit affects both MSMON_MBWU and MSMON_MBWU_L in implementations that include MSMON_MBWU_L.
Capture Monitor on Overflow.
Controls whether the value of MSMON_MBWU is captured on an overflow or an overflow linkage event.
OFLOW_CAPT | Meaning |
---|---|
0b0 |
Monitor register MSMON_MBWU is not captured on an overflow or when affected by an overflow linkage event. |
0b1 |
Monitor register MSMON_MBWU is captured on an overflow or when affected by an overflow linkage event. If OFLOW_FRZ is 1, the monitor does not continue to count after the overflow or overflow linkage event. If CAPT_RESET is 1, the monitor instance resets to 0. |
If this bit is 1, this monitor instance treats an overflow of this monitor instance as a private capture event.
If this bit is 1, this monitor instance also treats overflow linkage events for which it qualifies as a private capture event.
Reserved, RES0.
Subtype. Type of bandwidth counted by this monitor.
This field is not currently used for MBWU monitors, but reserved for future use.
This field is RAZ/WI.
MSMON_MBWU.VALUE Scaling Enable.
Enables scaling of MSMON_MBWU.VALUE by MPAMF_MBWUMON_IDR.SCALE.
SCLEN | Meaning |
---|---|
0b0 |
MSMON_MBWU.VALUE has bytes counted by the monitor instance. |
0b1 |
MSMON_MBWU.VALUE has bytes counted by the monitor instance, shifted right by MPAMF_MBWUMON_IDR.SCALE. |
Capture Event performs overflow behavior.
Selects whether a capture event matching the CAPT_EVNT field perform the overflow behavior or the capture behavior.
CEVNT_OFLW | Meaning |
---|---|
0b0 |
On a capture event matching the CAPT_EVNT field the capture behaviors are performed. |
0b1 |
On a capture event matching the CAPT_EVNT field the overflow behaviors are performed. |
Reserved, RES0.
Match PMG.
Controls whether the monitor instance only counts data transferred with PMG matching MSMON_CFG_MBWU_FLT.PMG.
MATCH_PMG | Meaning |
---|---|
0b0 |
The monitor instance counts data transferred with any PMG value. |
0b1 |
The monitor instance only counts data transferred with the PMG value matching MSMON_CFG_MBWU_FLT.PMG. |
Match PARTID.
Controls whether the monitor instance counts only data transferred with PARTID matching MSMON_CFG_MBWU_FLT.PARTID.
MATCH_PARTID | Meaning |
---|---|
0b0 |
The monitor instance counts data transferred with any PARTID value. |
0b1 |
The monitor instance only counts data transferred with the PARTID value matching MSMON_CFG_MBWU_FLT.PARTID. |
Overflow Status of MSMON_MBWU_L.VALUE of the monitor instance.
Indicates whether MSMON_MBWU_L.VALUE has overflowed.
OFLOW_STATUS_L | Meaning |
---|---|
0b0 |
MSMON_MBWU_L.VALUE has not overflowed. |
0b1 |
MSMON_MBWU_L.VALUE has overflowed at least once since this bit was last written to zero. |
If MPAMF_MBWUMON_IDR.HAS_LONG == 0, this bit is RES0.
Overflow status of MSMON_MBWU.VALUE is reported in MSMON_CFG_MBWU_CTL.OFLOW_STATUS.
If MPAMF_MBWUMON_IDR.HAS_OFLOW_CAPT is 1 or MPAMF_MBWUMON_IDR.HAS_OFLOW_LNKG is 1, then a store to MSMON_MBWU_L when this field is 1 resets this field to 0.
Reserved, RES0.
Overflow Interrupt for MSMON_MBWU_L.
Controls whether an MPAM overflow interrupt is generated when MSMON_MBWU_L.VALUE overflows.
OFLOW_INTR_L | Meaning |
---|---|
0b0 |
No interrupt is signaled on an overflow of MSMON_MBWU_L.VALUE. |
0b1 |
An implementation-specific interrupt is signaled on overflow of MSMON_MBWU_L.VALUE. |
If overflow is not possible for an MBWU monitor in the MSC implementation, this field is RAZ/WI.
If the overflow interrupt is not supported by the MSC implementation, this field is RAZ/WI.
Reserved, RES0.
Capture Long Monitor on Overflow.
Controls whether MSMON_MBWU_L is captured on an overflow or an overflow linkage event.
OFLOW_CAPT_L | Meaning |
---|---|
0b0 |
Monitor register MSMON_MBWU_L is not captured on an overflow or when affected by an overflow linkage event. |
0b1 |
Monitor register MSMON_MBWU_L is captured on an overflow or when affected by an overflow linkage event. If OFLOW_FRZ is 1, the monitor does not continue to count after the overflow or overflow linkage event. If CAPT_RESET is 1, the monitor instance resets to 0. |
If this bit is 1, this monitor instance treats an overflow of this monitor instance as a private capture event.
If this bit is 1, this monitor instance also treats overflow linkage events for which it qualifies as a private capture event.
Reserved, RES0.
Reserved, RES0.
Overflow linkage event.
Controls signaling of a capture event on overflow of this monitor instance.
OFLOW_CAPT_L | Meaning |
---|---|
0b000 |
Overflow of the monitor instance only affects this monitor instance. |
0b001 |
Overflow of this monitor instance signals Capture Event 1. |
0b010 |
Overflow of this monitor instance signals Capture Event 2. |
0b011 |
Overflow of this monitor instance signals Capture Event 3. |
0b100 |
Overflow of this monitor instance signals Capture Event 4. |
0b101 |
Overflow of this monitor instance signals Capture Event 5. |
0b110 |
Overflow of this monitor instance signals Capture Event 6. |
0b111 |
Reserved. |
Reserved, RES0.
Monitor Type Code. The MBWU monitor is TYPE = 0x42.
TYPE is a read-only constant indicating the type of the monitor.
Reads as 0x42.
Access to this field is RO.
This register is within the MPAM feature page memory frames.
In a system that supports Secure, Non-secure, Root, and Realm memory maps, there must be MPAM feature pages in all four address maps:
MSMON_CFG_MBWU_CTL_s, MSMON_CFG_MBWU_CTL_ns, MSMON_CFG_MBWU_CTL_rt, and MSMON_CFG_MBWU_CTL_rl must be separate registers:
When RIS is implemented, loads and stores to MSMON_CFG_MBWU_CTL access the monitor configuration settings for the bandwidth resource instance selected by MSMON_CFG_MON_SEL.RIS and the memory bandwidth usage monitor instance selected by MSMON_CFG_MON_SEL.MON_SEL.
When RIS is not implemented, loads and stores to MSMON_CFG_MBWU_CTL access the monitor configuration settings for the memory bandwidth usage monitor instance selected by MSMON_CFG_MON_SEL.MON_SEL.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_s | 0x0828 | MSMON_CFG_MBWU_CTL_s |
Accesses on this interface are RW.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_ns | 0x0828 | MSMON_CFG_MBWU_CTL_ns |
Accesses on this interface are RW.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_rt | 0x0828 | MSMON_CFG_MBWU_CTL_rt |
When FEAT_RME is implemented access on this interface are RW.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_rl | 0x0828 | MSMON_CFG_MBWU_CTL_rl |
When FEAT_RME is implemented access on this interface are RW.
30/09/2021 14:53; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f
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