The PMCIDR0 characteristics are:
Provides information to identify a Performance Monitor component.
For more information, see 'About the Component Identification scheme'.
Implementation of this register is OPTIONAL.
If FEAT_DoPD is implemented, this register is in the Core power domain. If FEAT_DoPD is not implemented, this register is in the Debug power domain.
This register is required for CoreSight compliance.
PMCIDR0 is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | PRMBL_0 |
Reserved, RES0.
Preamble.
Reads as 0x0D.
Access to this field is RO.
Component | Offset | Instance |
---|---|---|
PMU | 0xFF0 | PMCIDR0 |
This interface is accessible as follows:
30/09/2021 14:52; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f
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