The GICC_RPR characteristics are:
This register indicates the running priority of the CPU interface.
This register is present only when FEAT_GICv3_LEGACY is implemented. Otherwise, direct accesses to GICC_RPR are RES0.
This register is available in all configurations of the GIC. If the GIC implementation supports two Security states this register is Common.
GICC_RPR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | Priority |
Reserved, RES0.
The current running priority on the CPU interface. This is the group priority of the current active interrupt.
If there are no active interrupts on the CPU interface, or all active interrupts have undergone a priority drop, the value returned is the Idle priority.
The priority returned is the group priority as if the BPR was set to the minimum value.
If there is no active interrupt on the CPU interface, the idle priority value is returned.
If the GIC implementation supports two Security states, a Non-secure read of the Priority field returns:
For more information, see 'Interrupt prioritization' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
Software cannot determine the number of implemented priority bits from this register.
Component | Offset | Instance |
---|---|---|
GIC CPU interface | 0x0014 | GICC_RPR |
This interface is accessible as follows:
30/09/2021 14:53; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f
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