ICC_AP1R<n>_EL1, Interrupt Controller Active Priorities Group 1 Registers, n = 0 - 3

The ICC_AP1R<n>_EL1 characteristics are:

Purpose

Provides information about Group 1 active priorities.

Configuration

AArch64 System register ICC_AP1R<n>_EL1 bits [31:0] (S) are architecturally mapped to AArch32 System register ICC_AP1R<n>[31:0] (S).

AArch64 System register ICC_AP1R<n>_EL1 bits [31:0] (NS) are architecturally mapped to AArch32 System register ICC_AP1R<n>[31:0] (NS).

This register is present only when FEAT_GICv3 is implemented. Otherwise, direct accesses to ICC_AP1R<n>_EL1 are UNDEFINED.

Attributes

ICC_AP1R<n>_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
IMPLEMENTATION DEFINED

Bits [63:32]

Reserved, RES0.

IMPLEMENTATION DEFINED, bits [31:0]

IMPLEMENTATION DEFINED.

The reset behavior of this field is:

The contents of these registers are IMPLEMENTATION DEFINED with the one architectural requirement that the value 0x00000000 is consistent with no interrupts being active.

Accessing ICC_AP1R<n>_EL1

Writing to these registers with any value other than the last read value of the register (or 0x00000000 when there are no Group 1 active priorities) might result in UNPREDICTABLE behavior of the interrupt prioritization system, causing:

ICC_AP1R1_EL1 is only implemented in implementations that support 6 or more bits of priority. ICC_AP1R2_EL1 and ICC_AP1R3_EL1 are only implemented in implementations that support 7 or more bits of priority. Unimplemented registers are UNDEFINED.

Note

The number of bits of preemption is indicated by ICH_VTR_EL2.PREbits.

Writing to the active priority registers in any order other than the following order will result in UNPREDICTABLE behavior:

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, ICC_AP1R<n>_EL1

op0op1CRnCRmop2
0b110b0000b11000b10010b0:n[1:0]

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.IRQ == '1' then UNDEFINED; elsif ICC_SRE_EL1.SRE == '0' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && ICH_HCR_EL2.TALL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.IMO == '1' then return ICV_AP1R_EL1[UInt(op2<1:0>)]; elsif HaveEL(EL3) && SCR_EL3.IRQ == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) then if SCR_EL3.NS == '0' then return ICC_AP1R_EL1_S[UInt(op2<1:0>)]; else return ICC_AP1R_EL1_NS[UInt(op2<1:0>)]; else return ICC_AP1R_EL1[UInt(op2<1:0>)]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.IRQ == '1' then UNDEFINED; elsif ICC_SRE_EL2.SRE == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.IRQ == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) then if SCR_EL3.NS == '0' then return ICC_AP1R_EL1_S[UInt(op2<1:0>)]; else return ICC_AP1R_EL1_NS[UInt(op2<1:0>)]; else return ICC_AP1R_EL1[UInt(op2<1:0>)]; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3.SRE == '0' then AArch64.SystemAccessTrap(EL3, 0x18); else if SCR_EL3.NS == '0' then return ICC_AP1R_EL1_S[UInt(op2<1:0>)]; else return ICC_AP1R_EL1_NS[UInt(op2<1:0>)];

MSR ICC_AP1R<n>_EL1, <Xt>

op0op1CRnCRmop2
0b110b0000b11000b10010b0:n[1:0]

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.IRQ == '1' then UNDEFINED; elsif ICC_SRE_EL1.SRE == '0' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && ICH_HCR_EL2.TALL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.IMO == '1' then ICV_AP1R_EL1[UInt(op2<1:0>)] = X[t]; elsif HaveEL(EL3) && SCR_EL3.IRQ == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) then if SCR_EL3.NS == '0' then ICC_AP1R_EL1_S[UInt(op2<1:0>)] = X[t]; else ICC_AP1R_EL1_NS[UInt(op2<1:0>)] = X[t]; else ICC_AP1R_EL1[UInt(op2<1:0>)] = X[t]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.IRQ == '1' then UNDEFINED; elsif ICC_SRE_EL2.SRE == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.IRQ == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) then if SCR_EL3.NS == '0' then ICC_AP1R_EL1_S[UInt(op2<1:0>)] = X[t]; else ICC_AP1R_EL1_NS[UInt(op2<1:0>)] = X[t]; else ICC_AP1R_EL1[UInt(op2<1:0>)] = X[t]; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3.SRE == '0' then AArch64.SystemAccessTrap(EL3, 0x18); else if SCR_EL3.NS == '0' then ICC_AP1R_EL1_S[UInt(op2<1:0>)] = X[t]; else ICC_AP1R_EL1_NS[UInt(op2<1:0>)] = X[t];


20/09/2021 12:37; d4a233ffbdfb36e47856c443a7ce9a85f5e501ca

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