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GICR_SYNCR, Redistributor Synchronize Register

The GICR_SYNCR characteristics are:

Purpose

Indicates completion of register based invalidate operations.

Configuration

A copy of this register is provided for each Redistributor.

Attributes

GICR_SYNCR is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
RES0Busy

Bits [31:1]

Reserved, RES0.

Busy, bit [0]

Indicates completion of invalidation operations

BusyMeaning
0b0

No operations are in progress.

0b1

A write is in progress to one or more of the following registers:

This field tracks operations initiated on the same Redistributor.

Accessing GICR_SYNCR

When this register is accessed, it is optional that an implementation might wait until all operations are complete before returning a value, in which case GICR_SYNCR.Busy is always 0.

This register is mandatory when any of the following are true:

Otherwise, the functionality is IMPLEMENTATION DEFINED.

GICR_SYNCR can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
GIC RedistributorRD_base0x00C0GICR_SYNCR

AccessesThis oninterface thisis interfaceaccessible areas follows: RO.


3020/09/2021 1412:5237; 092b4e1bbfbb45a293b198f9330c5f529ead2b0fd4a233ffbdfb36e47856c443a7ce9a85f5e501ca

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