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The CNTHCTL characteristics are:
Controls the generation of an event stream from the physical counter, and access from Non-secure EL1 modes to the physical counter and the Non-secure EL1 physical timer.
AArch32 System register CNTHCTL bits [31:0] are architecturally mapped to AArch64 System register CNTHCTL_EL2[31:0].
This register is present only when AArch32 is supported. Otherwise, direct accesses to CNTHCTL are UNDEFINED.
If EL2 is not implemented, this register is RES0 from EL3.
CNTHCTL is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | EVNTIS | RES0 | EVNTI | EVNTDIR | EVNTEN | PL1PCEN | PL1PCTEN |
Reserved, RES0.
Controls the scale of the generation of the event stream.
EVNTIS | Meaning |
---|---|
0b0 | The CNTHCTL.EVNTI field applies to CNTPCT[15:0]. |
0b1 | The CNTHCTL.EVNTI field applies to CNTPCT[23:8]. |
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Selects which bit of the counter register CNTPCT, as seen from EL2, is the trigger for the event stream generated from that counter, when that stream is enabled.
If FEAT_ECV is implemented, and CNTHCTL.EVNTIS is 1, this field selects a trigger bit in the range 8 to 23 of the counter register CNTPCT.is the trigger.
Otherwise, this field selects a trigger bit in the range 0 to 15 of the counter register. CNTPCT.
The reset behavior of this field is:
Controls which transition of the counter register CNTPCT trigger bit, as seen from EL2 and defined by EVNTI, generates an event when the event stream is enabled.enabled:
EVNTDIR | Meaning |
---|---|
0b0 | A 0 to 1 transition of the trigger bit triggers an event. |
0b1 | A 1 to 0 transition of the trigger bit triggers an event. |
The reset behavior of this field is:
Enables the generation of an event stream from the counter register CNTPCT as seen from EL2.:
EVNTEN | Meaning |
---|---|
0b0 | Disables the event stream. |
0b1 | Enables the event stream. |
The reset behavior of this field is:
Traps Non-secure EL0 and EL1 accesses to the physical timer registers to Hyp mode.
PL1PCEN | Meaning |
---|---|
0b0 | Non-secure EL0 and EL1 accesses to the CNTP_CTL, CNTP_CVAL, and CNTP_TVAL are trapped to Hyp mode, unless the it is trapped by CNTKCTL.PL0PTEN. |
0b1 | This control does not cause any instructions to be trapped. |
If EL3 is implemented and EL2 is not implemented, behavior is as if this bit is 1 other than for the purpose of a direct read.
The reset behavior of this field is:
Traps Non-secure EL0 and EL1 accesses to the physical counter register to Hyp mode.
PL1PCTEN | Meaning |
---|---|
0b0 | Non-secure EL0 and EL1 accesses to the CNTPCT are trapped to Hyp mode, unless it is trapped by CNTKCTL.PL0PCTEN. |
0b1 | This control does not cause any instructions to be trapped. |
If EL3 is implemented and EL2 is not implemented, behavior is as if this bit is 1 other than for the purpose of a direct read.
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b100 | 0b1110 | 0b0001 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then return CNTHCTL; elsif PSTATE.EL == EL3 then if SCR.NS == '0' then UNDEFINED; else return CNTHCTL;
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b100 | 0b1110 | 0b0001 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then CNTHCTL = R[t]; elsif PSTATE.EL == EL3 then if SCR.NS == '0' then UNDEFINED; else CNTHCTL = R[t];
3020/09/2021 1412:5337; 092b4e1bbfbb45a293b198f9330c5f529ead2b0fd4a233ffbdfb36e47856c443a7ce9a85f5e501ca
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