The DBGWCR<n>_EL1 characteristics are:
Holds control information for a watchpoint. Forms watchpoint n together with value register DBGWVR<n>_EL1.
AArch64 System register DBGWCR<n>_EL1 bits [31:0] are architecturally mapped to AArch32 System register DBGWCR<n>[31:0].
AArch64 System register DBGWCR<n>_EL1 bits [31:0] are architecturally mapped to External register DBGWCR<n>_EL1[31:0].
If watchpoint n is not implemented then accesses to this register are UNDEFINED.
DBGWCR<n>_EL1 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | SSCE | MASK | RES0 | WT | LBN | SSC | HMC | BAS | LSC | PAC | E |
Reserved, RES0.
Security State Control Extended.
The fields that indicate when the watchpoint can be generated are: HMC, PAC, SSC, and SSCE. These fields must be considered in combination, and the values that are permitted for these fields are constrained.
The reset behavior of this field is:
Reserved, RES0.
Address mask. Only objects up to 2GB can be watched using a single mask.
MASK | Meaning |
---|---|
0b00000 |
No mask. |
0b00001 |
Reserved. |
0b00010 |
Reserved. |
If programmed with a reserved value, a watchpoint must behave as if either:
Software must not rely on this property because the behavior of reserved values might change in a future revision of the architecture.
Other values mask the corresponding number of address bits, from 0b00011 masking 3 address bits (0x00000007 mask for address) to 0b11111 masking 31 address bits (0x7FFFFFFF mask for address).
The reset behavior of this field is:
Reserved, RES0.
Watchpoint type. Possible values are:
WT | Meaning |
---|---|
0b0 |
Unlinked data address match. |
0b1 |
Linked data address match. |
The reset behavior of this field is:
Linked breakpoint number. For Linked data address watchpoints, this specifies the index of the Context-matching breakpoint linked to.
The reset behavior of this field is:
Security state control. Determines the Security states under which a Watchpoint debug event for watchpoint n is generated.
The fields that indicate when the watchpoint can be generated are: HMC, PAC, SSC, and SSCE. These fields must be considered in combination, and the values that are permitted for these fields are constrained.
For more information on the operation of these fields, see 'Execution conditions for which a watchpoint generates Watchpoint exceptions'.
For more information on the effect of programming the fields to a reserved value, see 'Reserved DBGWCR<n>_EL1.{SSC, HMC, PAC} values'.
The reset behavior of this field is:
Higher mode control. Determines the debug perspective for deciding when a Watchpoint debug event for watchpoint n is generated.
The fields that indicate when the watchpoint can be generated are: HMC, PAC, SSC, and SSCE. These fields must be considered in combination, and the values that are permitted for these fields are constrained.
For more information on the operation of these fields, see 'Execution conditions for which a watchpoint generates Watchpoint exceptions'.
The reset behavior of this field is:
Byte address select. Each bit of this field selects whether a byte from within the word or double-word addressed by DBGWVR<n>_EL1 is being watched.
BAS | Description |
---|---|
xxxxxxx1 | Match byte at DBGWVR<n>_EL1 |
xxxxxx1x | Match byte at DBGWVR<n>_EL1 + 1 |
xxxxx1xx | Match byte at DBGWVR<n>_EL1 + 2 |
xxxx1xxx | Match byte at DBGWVR<n>_EL1 + 3 |
In cases where DBGWVR<n>_EL1 addresses a double-word:
BAS | Description, if DBGWVR<n>_EL1[2] == 0 |
---|---|
xxx1xxxx | Match byte at DBGWVR<n>_EL1 + 4 |
xx1xxxxx | Match byte at DBGWVR<n>_EL1 + 5 |
x1xxxxxx | Match byte at DBGWVR<n>_EL1 + 6 |
1xxxxxxx | Match byte at DBGWVR<n>_EL1 + 7 |
If DBGWVR<n>_EL1[2] == 1, only BAS[3:0] are used and BAS[7:4] are ignored. Arm deprecates setting DBGWVR<n>_EL1[2] == 1.
The valid values for BAS are non-zero binary numbers all of whose set bits are contiguous. All other values are reserved and must not be used by software. See 'Reserved DBGWCR<n>_EL1.BAS values'.
The reset behavior of this field is:
Load/store control. This field enables watchpoint matching on the type of access being made. Possible values of this field are:
LSC | Meaning |
---|---|
0b01 |
Match instructions that load from a watchpointed address. |
0b10 |
Match instructions that store to a watchpointed address. |
0b11 |
Match instructions that load from or store to a watchpointed address. |
All other values are reserved, but must behave as if the watchpoint is disabled. Software must not rely on this property as the behavior of reserved values might change in a future revision of the architecture.
The reset behavior of this field is:
Privilege of access control. Determines the Exception level or levels at which a Watchpoint debug event for watchpoint n is generated.
The fields that indicate when the watchpoint can be generated are: HMC, PAC, SSC, and SSCE. These fields must be considered in combination, and the values that are permitted for these fields are constrained.
For more information on the operation of these fields, see 'Execution conditions for which a watchpoint generates Watchpoint exceptions'.
The reset behavior of this field is:
Enable watchpoint n. Possible values are:
E | Meaning |
---|---|
0b0 |
Watchpoint disabled. |
0b1 |
Watchpoint enabled. |
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b000 | 0b0000 | n[3:0] | 0b111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TDA == '1' then UNDEFINED; elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.DBGWCRn_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.<TDE,TDA> != '00' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TDA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else return DBGWCR_EL1[UInt(CRm<3:0>)]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TDA == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TDA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else return DBGWCR_EL1[UInt(CRm<3:0>)]; elsif PSTATE.EL == EL3 then if OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else return DBGWCR_EL1[UInt(CRm<3:0>)];
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b000 | 0b0000 | n[3:0] | 0b111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TDA == '1' then UNDEFINED; elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.DBGWCRn_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.<TDE,TDA> != '00' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TDA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else DBGWCR_EL1[UInt(CRm<3:0>)] = X[t]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TDA == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TDA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else DBGWCR_EL1[UInt(CRm<3:0>)] = X[t]; elsif PSTATE.EL == EL3 then if OSLSR_EL1.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else DBGWCR_EL1[UInt(CRm<3:0>)] = X[t];
20/09/2021 12:37; d4a233ffbdfb36e47856c443a7ce9a85f5e501ca
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