The DSPSR_EL0 characteristics are:
Holds the saved process state for Debug state. On entering Debug state, PSTATE information is written to this register. On exiting Debug state, values are copied from this register to PSTATE.
AArch64 System register DSPSR_EL0 bits [31:0] are architecturally mapped to AArch32 System register DSPSR[31:0].
DSPSR_EL0 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
N | Z | C | V | Q | IT[1:0] | DIT | SSBS | PAN | SS | IL | GE | IT[7:2] | E | A | I | F | T | M[4] | M[3:0] |
Reserved, RES0.
Negative Condition flag. Copied to PSTATE.N on exiting Debug state.
The reset behavior of this field is:
Zero Condition flag. Copied to PSTATE.Z on exiting Debug state.
The reset behavior of this field is:
Carry Condition flag. Copied to PSTATE.C on exiting Debug state.
The reset behavior of this field is:
Overflow Condition flag. Copied to PSTATE.V on exiting Debug state.
The reset behavior of this field is:
Overflow or saturation flag. Copied to PSTATE.Q on exiting Debug state.
The reset behavior of this field is:
If-Then. Copied to PSTATE.IT on exiting Debug state.
DSPSR_EL0.IT must contain a value that is valid for the instruction being returned to.
The IT field is split as follows:
The reset behavior of this field is:
Data Independent Timing. Copied to PSTATE.DIT on exiting Debug state.
The reset behavior of this field is:
Reserved, RES0.
Speculative Store Bypass. Copied to PSTATE.SSBS on exiting Debug state.
The reset behavior of this field is:
Reserved, RES0.
Privileged Access Never. Copied to PSTATE.PAN on exiting Debug state.
The reset behavior of this field is:
Reserved, RES0.
Software Step. Copied to PSTATE.SS on exiting Debug state.
The reset behavior of this field is:
Illegal Execution state. Copied to PSTATE.IL on exiting Debug state.
The reset behavior of this field is:
Greater than or Equal flags. Copied to PSTATE.GE on exiting Debug state.
The reset behavior of this field is:
Endianness. Copied to PSTATE.E on exiting Debug state.
If the implementation does not support big-endian operation, DSPSR_EL0.E is RES0. If the implementation does not support little-endian operation, DSPSR_EL0.E is RES1. On exiting Debug state, if the implementation does not support big-endian operation at the Exception level being returned to, DSPSR_EL0.E is RES0, and if the implementation does not support little-endian operation at the Exception level being returned to, DSPSR_EL0.E is RES1.
The reset behavior of this field is:
SError interrupt mask. Copied to PSTATE.A on exiting Debug state.
The reset behavior of this field is:
IRQ interrupt mask. Copied to PSTATE.I on exiting Debug state.
The reset behavior of this field is:
FIQ interrupt mask. Copied to PSTATE.F on exiting Debug state.
The reset behavior of this field is:
T32 Instruction set state. Copied to PSTATE.T on exiting Debug state.
The reset behavior of this field is:
Execution state. Copied to PSTATE.nRW on exiting Debug state.
M[4] | Meaning |
---|---|
0b1 |
AArch32 execution state. |
The reset behavior of this field is:
AArch32 Mode. Copied to PSTATE.M[3:0] on exiting Debug state.
M[3:0] | Meaning |
---|---|
0b0000 |
User. |
0b0001 |
FIQ. |
0b0010 |
IRQ. |
0b0011 |
Supervisor. |
0b0110 |
Monitor. |
0b0111 |
Abort. |
0b1010 |
Hyp. |
0b1011 |
Undefined. |
0b1111 |
System. |
Other values are reserved. If DSPSR_EL0.M[3:0] has a Reserved value, or a value for an unimplemented Exception level, exiting Debug state is an illegal return event, as described in 'Illegal return events from AArch64 state'.
The reset behavior of this field is:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
N | Z | C | V | RES0 | TCO | DIT | UAO | PAN | SS | IL | RES0 | SSBS | BTYPE | D | A | I | F | RES0 | M[4] | M[3:0] |
Reserved, RES0.
Negative Condition flag. Set to the value of PSTATE.N on entering Debug state, and copied to PSTATE.N on exiting Debug state.
The reset behavior of this field is:
Zero Condition flag. Set to the value of PSTATE.Z on entering Debug state, and copied to PSTATE.Z on exiting Debug state.
The reset behavior of this field is:
Carry Condition flag. Set to the value of PSTATE.C on entering Debug state, and copied to PSTATE.C on exiting Debug state.
The reset behavior of this field is:
Overflow Condition flag. Set to the value of PSTATE.V on entering Debug state, and copied to PSTATE.V on exiting Debug state.
The reset behavior of this field is:
Reserved, RES0.
Tag Check Override. Set to the value of PSTATE.TCO on entering Debug state, and copied to PSTATE.TCO on exiting Debug state.
When FEAT_MTE2 is not implemented, it is CONSTRAINED UNPREDICTABLE whether this field is RES0 or behaves as if FEAT_MTE is implemented.
The reset behavior of this field is:
Reserved, RES0.
Data Independent Timing. Set to the value of PSTATE.DIT on entering Debug state, and copied to PSTATE.DIT on exiting Debug state.
The reset behavior of this field is:
Reserved, RES0.
User Access Override. Set to the value of PSTATE.UAO on entering Debug state, and copied to PSTATE.UAO on exiting Debug state.
The reset behavior of this field is:
Reserved, RES0.
Privileged Access Never. Set to the value of PSTATE.PAN on entering Debug state, and copied to PSTATE.PAN on exiting Debug state.
The reset behavior of this field is:
Reserved, RES0.
Software Step. Set to the value of PSTATE.SS on entering Debug state, and conditionally copied to PSTATE.SS on exiting Debug state.
The reset behavior of this field is:
Illegal Execution state. Set to the value of PSTATE.IL on entering Debug state, and copied to PSTATE.IL on exiting Debug state.
The reset behavior of this field is:
Reserved, RES0.
Speculative Store Bypass. Set to the value of PSTATE.SSBS on entering Debug state, and copied to PSTATE.SSBS on exiting Debug state.
The reset behavior of this field is:
Reserved, RES0.
Branch Type Indicator. Set to the value of PSTATE.BTYPE on entering Debug state, and copied to PSTATE.BTYPE on exiting Debug state.
The reset behavior of this field is:
Reserved, RES0.
Debug exception mask. Set to the value of PSTATE.D on entering Debug state, and copied to PSTATE.D on exiting Debug state.
The reset behavior of this field is:
SError interrupt mask. Set to the value of PSTATE.A on entering Debug state, and copied to PSTATE.A on exiting Debug state.
The reset behavior of this field is:
IRQ interrupt mask. Set to the value of PSTATE.I on entering Debug state, and copied to PSTATE.I on exiting Debug state.
The reset behavior of this field is:
FIQ interrupt mask. Set to the value of PSTATE.F on entering Debug state, and copied to PSTATE.F on exiting Debug state.
The reset behavior of this field is:
Reserved, RES0.
Execution state. Set to 0b0, the value of PSTATE.nRW, on entering Debug state from AArch64 state, and copied to PSTATE.nRW on exiting Debug state.
M[4] | Meaning |
---|---|
0b0 |
AArch64 execution state. |
The reset behavior of this field is:
AArch64 Exception level and selected Stack Pointer.
M[3:0] | Meaning |
---|---|
0b0000 |
EL0t. |
0b0100 |
EL1t. |
0b0101 |
EL1h. |
0b1000 |
EL2t. |
0b1001 |
EL2h. |
0b1100 |
EL3t. |
0b1101 |
EL3h. |
Other values are reserved. If DSPSR_EL0.M[3:0] has a Reserved value, or a value for an unimplemented Exception level, exiting Debug state is an illegal return event, as described in 'Illegal return events from AArch64 state'.
The bits in this field are interpreted as follows:
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b011 | 0b0100 | 0b0101 | 0b000 |
if !Halted() then UNDEFINED; else return DSPSR_EL0;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b011 | 0b0100 | 0b0101 | 0b000 |
if !Halted() then UNDEFINED; else DSPSR_EL0 = X[t];
20/09/2021 12:37; d4a233ffbdfb36e47856c443a7ce9a85f5e501ca
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