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The ID_AA64MMFR1_EL1 characteristics are:
Provides information about the implemented memory model and memory management support in AArch64 state.
For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'.
There are no configuration notes.
ID_AA64MMFR1_EL1 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | CMOW | TIDCP1 | nTLBPA | AFP | HCX | ETS | TWED | ||||||||||||||||||||||||
XNX | SpecSEI | PAN | LO | HPDS | VH | VMIDBits | HAFDBS |
Reserved, RES0.
Indicates support for cache maintenance instruction permission. Defined values are:
CMOW | Meaning |
---|---|
0b0000 | SCTLR_EL1.CMOW, SCTLR_EL2.CMOW, and HCRX_EL2.CMOW bits are not implemented. |
0b0001 | SCTLR_EL1.CMOW is implemented. If EL2 is implemented, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are implemented. |
All other values are reserved.
FEAT_CMOW implements the functionality identified by the value 0b0001.
From Armv8.8, the only permitted value is 0b0001.
Indicates whether SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP are implemented in AArch64 state. Defined values are:
TIDCP1 | Meaning |
---|---|
0b0000 | SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are not implemented and are RES0. |
0b0001 | SCTLR_EL1.TIDCP bit is implemented. If EL2 is implemented, SCTLR_EL2.TIDCP bit is implemented. |
All other values are reserved.
FEAT_TIDCP1 implements the functionality identified by the value 0b0001.
From Armv8.8, the only permitted value is 0b0001.
Indicates support for intermediate caching of translation table walks. Defined values are:
nTLBPA | Meaning |
---|---|
0b0000 | The intermediate caching of translation table walks might include non-coherent caches of previous valid translation table entries since the last completed relevant TLBI applicable to the PE where either:
|
0b0001 | The intermediate caching of translation table walks does not include non-coherent caches of previous valid translation table entries since the last completed TLBI applicable to the PE where either:
|
All other values are reserved.
FEAT_nTLBPA implements the functionality identified by the value 0b0001.
From Armv8.0, the permitted values are 0b0000 and 0b0001.
Indicates support for FPCR.{AH, FIZ, NEP}. Defined values are:
AFP | Meaning |
---|---|
0b0000 | The FPCR.{AH, FIZ, NEP} fields are not supported. |
0b0001 | The FPCR.{AH, FIZ, NEP} fields are supported. |
All other values are reserved.
FEAT_AFP implements the functionality identified by the value 0b0001.
From Armv8.7, if Advanced SIMD and floating-point is implemented, the only permitted value is 0b0001.
Indicates support for HCRX_EL2 and its associated EL3 trap. Defined values are:
HCX | Meaning |
---|---|
0b0000 | HCRX_EL2 and its associated EL3 trap are not supported. |
0b0001 | HCRX_EL2 and its associated EL3 trap are supported. |
All other values are reserved.
FEAT_HCX implements the functionality identified by the value 0b0001.
From Armv8.7, if EL2 is implemented, the only permitted value is 0b0001.
Indicates support for Enhanced Translation Synchronization. Defined values are:
ETS | Meaning |
---|---|
0b0000 | Enhanced Translation Synchronization is not supported. |
0b0001 | Enhanced Translation Synchronization is supported. |
All other values are reserved.
FEAT_ETS implements the functionality identified by the value 0b0001.
In Armv8.0, the permitted values are 0b0000 and 0b0001.
From Armv8.7, the only permitted value is 0b0001.
Indicates support for the configurable delayed trapping of WFE. Defined values are:
TWED | Meaning |
---|---|
0b0000 | Configurable delayed trapping of WFE is not supported. |
0b0001 | Configurable delayed trapping of WFE is supported. |
All other values are reserved.
FEAT_TWED implements the functionality identified by the value 0b0001.
From Armv8.6, the permitted values are 0b0000 and 0b0001.
Indicates support for execute-never control distinction by Exception level at stage 2. Defined values are:
XNX | Meaning |
---|---|
0b0000 | Distinction between EL0 and EL1 execute-never control at stage 2 not supported. |
0b0001 | Distinction between EL0 and EL1 execute-never control at stage 2 supported. |
All other values are reserved.
FEAT_XNX implements the functionality identified by the value 0b0001.
From Armv8.2, the only permitted value is 0b0001.
Describes whether the PE can generate SError interrupt exceptions from speculative reads of memory, including speculative instruction fetches. The defined values of this field are:
SpecSEI | Meaning |
---|---|
0b0000 | The PE never generates an SError interrupt due to an External abort on a speculative read. |
0b0001 | The PE might generate an SError interrupt due to an External abort on a speculative read. |
All other values are reserved.
Privileged Access Never. Indicates support for the PAN bit in PSTATE, SPSR_EL1, SPSR_EL2, SPSR_EL3, and DSPSR_EL0. Defined values are:
PAN | Meaning |
---|---|
0b0000 | PAN not supported. |
0b0001 | PAN supported. |
0b0010 | PAN supported and AT S1E1RP and AT S1E1WP instructions supported. |
0b0011 | PAN supported, AT S1E1RP and AT S1E1WP instructions supported, and SCTLR_EL1.EPAN and SCTLR_EL2.EPAN bits supported. |
All other values are reserved.
FEAT_PAN implements the functionality identified by the value 0b0001.
FEAT_PAN2 implements the functionality added by the value 0b0010.
FEAT_PAN3 implements the functionality added by the value 0b0011.
In Armv8.1, the permitted values are 0b0001, 0b0010, and 0b0011.
From Armv8.2, the permitted values are 0b0010 and 0b0011.
From Armv8.7, the only permitted value is 0b0011.
LORegions. Indicates support for LORegions. Defined values are:
LO | Meaning |
---|---|
0b0000 | LORegions not supported. |
0b0001 | LORegions supported. |
All other values are reserved.
FEAT_LOR implements the functionality identified by the value 0b0001.
From Armv8.1, the only permitted value is 0b0001.
Hierarchical Permission Disables. Indicates support for disabling hierarchical controls in translation tables. Defined values are:
HPDS | Meaning |
---|---|
0b0000 | Disabling of hierarchical controls not supported. |
0b0001 | Disabling of hierarchical controls supported with the TCR_EL1.{HPD1, HPD0}, TCR_EL2.HPD or TCR_EL2.{HPD1, HPD0}, and TCR_EL3.HPD bits. |
0b0010 | As for value 0b0001, and adds possible hardware allocation of bits[62:59] of the translation table descriptors from the final lookup level for IMPLEMENTATION DEFINED use. |
All other values are reserved.
FEAT_HPDS implements the functionality identified by the value 0b0001.
FEAT_HPDS2 implements the functionality identified by the value 0b0010.
From Armv8.1, the value 0b0000 is not permitted.
Virtualization Host Extensions. Defined values are:
VH | Meaning |
---|---|
0b0000 | Virtualization Host Extensions not supported. |
0b0001 | Virtualization Host Extensions supported. |
All other values are reserved.
FEAT_VHE implements the functionality identified by the value 0b0001.
From Armv8.1, the only permitted value is 0b0001.
Number of VMID bits. Defined values are:
VMIDBits | Meaning |
---|---|
0b0000 | 8 bits |
0b0010 | 16 bits |
All other values are reserved.
FEAT_VMID16 implements the functionality identified by the value 0b0010.
From Armv8.1, the permitted values are 0b0000 and 0b0010.
Hardware updates to Access flag and Dirty state in translation tables. Defined values are:
HAFDBS | Meaning |
---|---|
0b0000 | Hardware update of the Access flag and dirty state are not supported. |
0b0001 | Hardware update of the Access flag is supported. |
0b0010 | Hardware update of both the Access flag and dirty state is supported. |
All other values are reserved.
FEAT_HAFDBS implements the functionality identified by the values 0b0001 and 0b0010.
From Armv8.1, the permitted values are 0b0000, 0b0001, and 0b0010.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0000 | 0b0111 | 0b001 |
if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return ID_AA64MMFR1_EL1; elsif PSTATE.EL == EL2 then return ID_AA64MMFR1_EL1; elsif PSTATE.EL == EL3 then return ID_AA64MMFR1_EL1;
3020/09/2021 1412:5237; 092b4e1bbfbb45a293b198f9330c5f529ead2b0fd4a233ffbdfb36e47856c443a7ce9a85f5e501ca
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