The ERRCRICR1 characteristics are:
Critical Error Interrupt configuration register.
This register is present only when (the Critical Error Interrupt is implemented or the implementation does not use the recommended layout for the ERRIRQCR<n> registers) and interrupt configuration registers are implemented. Otherwise, direct accesses to ERRCRICR1 are RES0.
ERRCRICR1 is implemented only as part of a memory-mapped group of error records.
ERRCRICR1 is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA |
Payload for the message signaled interrupt.
The reset behavior of this field is:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED |
IMPLEMENTATION DEFINED.
Component | Offset | Instance |
---|---|---|
RAS | 0xEA8 | ERRCRICR1 |
Accesses on this interface are RW.
30/09/2021 14:53; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f
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