The GICV_IIDR characteristics are:
Provides information about the implementer and revision of the virtual CPU interface.
This register is present only when FEAT_GICv3_LEGACY is implemented and EL2 is implemented. Otherwise, direct accesses to GICV_IIDR are RES0.
This register is available in all configurations of the GIC. If the GIC implementation supports two Security states this register is Common.
GICV_IIDR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ProductID | Architecture_version | Revision | Implementer |
Product Identifier.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
The version of the GIC architecture that is implemented.
Architecture_version | Meaning |
---|---|
0b0001 |
GICv1. |
0b0010 |
GICv2. |
0b0011 |
GICv3 memory-mapped interface supported. Support for the System register interface is discoverable from PE registers ID_PFR1 and ID_AA64PFR0_EL1. |
0b0100 |
GICv4 memory-mapped interface supported. Support for the System register interface is discoverable from PE registers ID_PFR1 and ID_AA64PFR0_EL1. |
Other values are reserved.
Revision number for the CPU interface.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Contains the JEP106 code of the company that implemented the CPU interface.
Component | Offset | Instance |
---|---|---|
GIC Virtual CPU interface | 0x00FC | GICV_IIDR |
This interface is accessible as follows:
20/09/2021 12:37; d4a233ffbdfb36e47856c443a7ce9a85f5e501ca
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