GICR_INMIR0, Non-maskable Interrupt Register for PPIs.

The GICR_INMIR0 characteristics are:

Purpose

Controls whether the corresponding PPI has the non-maskable property.

Configuration

This register is present only when FEAT_GICv3_NMI is implemented. Otherwise, direct accesses to GICR_INMIR0 are RES0.

When GICD_TYPER.NMI is 0, this register is RES0.

A copy of this register is provided for each Redistributor.

Attributes

GICR_INMIR0 is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
nmi31nmi30nmi29nmi28nmi27nmi26nmi25nmi24nmi23nmi22nmi21nmi20nmi19nmi18nmi17nmi16nmi15nmi14nmi13nmi12nmi11nmi10nmi9nmi8nmi7nmi6nmi5nmi4nmi3nmi2nmi1nmi0

nmi<x>, bit [x], for x = 31 to 0

Non-maskable property.

nmi<x>Meaning
0b0

Interrupt does not have the non-maskable property.

0b1

Interrupt has the non-maskable property.

The reset behavior of this field is:

If affinity routing is disabled for the Security state of an interrupt, the bit is RES0.

Accessing GICR_INMIR0

Bits corresponding to unimplemented interrupts are RAZ/WI.

GICR_INMIR0 can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
GIC RedistributorSGI_base0x0F80GICR_INMIR0

Accesses on this interface are RW.


30/09/2021 14:53; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f

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