The CNTNSAR characteristics are:
Provides the highest-level control of whether frames CNTBaseN and CNTEL0BaseN are accessible by Non-secure accesses.
The power domain of CNTNSAR is IMPLEMENTATION DEFINED.
For more information, see 'Power and reset domains for the system level implementation of the Generic Timer'.
CNTNSAR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | NS7 | NS6 | NS5 | NS4 | NS3 | NS2 | NS1 | NS0 |
Reserved, RES0.
Non-secure access to frame n.
NS<n> | Meaning |
---|---|
0b0 |
Secure access only. Behaves as RES0 to Non-secure accesses. |
0b1 |
Secure and Non-secure accesses permitted. |
This bit also determines whether, in the CNTCTLBase frame, CNTACR<n> and CNTVOFF<n> are accessible to Non-secure accesses.
If frame CNTBase<n>:
The reset behavior of this field is:
In a system that recognizes two Security states, this register is only accessible by Secure accesses.
Component | Frame | Offset | Instance |
---|---|---|---|
Timer | CNTCTLBase | 0x004 | CNTNSAR |
Accesses on this interface are RW.
30/09/2021 14:53; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.