DCCIMVAC, Data Cache line Clean and Invalidate by VA to PoC

The DCCIMVAC characteristics are:

Purpose

Clean and Invalidate data or unified cache line by virtual address to PoC.

Configuration

AArch32 System instruction DCCIMVAC performs the same function as AArch64 System instruction DC CIVAC.

This instruction is present only when AArch32 is supported. Otherwise, direct accesses to DCCIMVAC are UNDEFINED.

Attributes

DCCIMVAC is a 32-bit System instruction.

Field descriptions

313029282726252423222120191817161514131211109876543210
Virtual address to use

Bits [31:0]

Virtual address to use. No alignment restrictions apply to this VA.

Executing the DCCIMVAC instruction

Execution of this instruction might require an address translation from VA to PA, and that translation might fault.

If FEAT_CMOW is implemented, HCRX_EL2.CMOW is 1, and EL1 or EL0 access is enabled, when executed at EL1 or EL0, the instruction has stage 2 read permission to the VA but does not have stage 2 write permission to the VA, the instruction generates a stage 2 Permission fault.

For more information, see 'AArch32 data cache maintenance instructions (DC*)'.

Accesses to this instruction use the following encodings in the System instruction encoding space:

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coprocopc1CRnCRmopc2
0b11110b0000b01110b11100b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T7 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T7 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TPCP == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TPC == '1' then AArch32.TakeHypTrapException(0x03); else AArch32.DC(R[t], CacheOp_CleanInvalidate, CacheOpScope_PoC); elsif PSTATE.EL == EL2 then AArch32.DC(R[t], CacheOp_CleanInvalidate, CacheOpScope_PoC); elsif PSTATE.EL == EL3 then AArch32.DC(R[t], CacheOp_CleanInvalidate, CacheOpScope_PoC);


30/09/2021 14:53; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f

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