PMSNEVFR_EL1, Sampling Inverted Event Filter Register

The PMSNEVFR_EL1 characteristics are:

Purpose

Controls sample filtering by events. The overall filter is the logical AND of these filters. For example, if E[3] and E[5] are both set to 1, only samples that have both event 3 (Level 1 unified or data cache refill) and event 5 (TLB walk) clear are recorded.

Configuration

This register is present only when FEAT_SPEv1p2 is implemented. Otherwise, direct accesses to PMSNEVFR_EL1 are UNDEFINED.

Attributes

PMSNEVFR_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
E[63]E[62]E[61]E[60]E[59]E[58]E[57]E[56]E[55]E[54]E[53]E[52]E[51]E[50]E[49]E[48]RAZ/WI
E[31]E[30]E[29]E[28]E[27]E[26]E[25]E[24]RAZ/WIE[18]E[17]E[16]E[15]E[14]E[13]E[12]E[11]RAZ/WIE[7]E[6]E[5]RAZ/WIE[3]RAZ/WIE[1]RAZ/WI

E[<x>], bit [x], for x = 63 to 48, 31 to 24, 15 to 12

E[<x>] is the event filter for IMPLEMENTATION DEFINED event <x>.

E[<x>]Meaning
0b0

Event <x> is ignored.

0b1

Do not record samples that have event <x> == 1.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSNEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This bit is ignored by the PE when PMSFCR_EL1.FnE == 0.

The reset behavior of this field is:

When event <x> is not implemented, or filtering on event <x> is not supported, access to this field is RAZ/WI.

Bits [47:32]

Reserved, RAZ/WI.

Bits [23:19]

Reserved, RAZ/WI.

E[18], bit [18]
When FEAT_SVE is implemented and FEAT_SPEv1p1 is implemented:

Not empty predicate.

E[18]Meaning
0b0

Empty predicate event is ignored.

0b1

Do not record samples that have the Empty predicate event == 1.

This field is ignored by the PE when PMSFCR_EL1.FnE == 0.

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[17], bit [17]
When FEAT_SVE is implemented and FEAT_SPEv1p1 is implemented:

Not partial predicate.

E[17]Meaning
0b0

Partial predicate event is ignored.

0b1

Do not record samples that have the Partial predicate event == 1.

This field is ignored by the PE when PMSFCR_EL1.FnE == 0.

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[16], bit [16]
When FEAT_TME is implemented:

Not transactional.

E[16]Meaning
0b0

Transactional event is ignored.

0b1

Do not record samples that have the Transactional event == 1.

This field is ignored by the PE when PMSFCR_EL1.FnE == 0.

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[11], bit [11]
When FEAT_SPEv1p1 is implemented:

Aligned.

E[11]Meaning
0b0

Misalignment event is ignored.

0b1

Do not record samples that have the Misalignment event == 1.

This field is ignored by the PE when PMSFCR_EL1.FnE == 0.

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

Bits [10:8]

Reserved, RAZ/WI.

E[7], bit [7]

Correctly predicted.

E[7]Meaning
0b0

Mispredicted event is ignored.

0b1

Do not record samples that have the Mispredicted event == 1.

This field is ignored by the PE when PMSFCR_EL1.FnE == 0.

The reset behavior of this field is:

E[6], bit [6]

Taken.

E[6]Meaning
0b0

Not taken event is ignored.

0b1

Do not record samples that have the Not taken event == 1.

This field is ignored by the PE when PMSFCR_EL1.FnE == 0.

The reset behavior of this field is:

E[5], bit [5]

TLB hit.

E[5]Meaning
0b0

TLB walk event is ignored.

0b1

Do not record samples that have the TLB walk event == 1.

This field is ignored by the PE when PMSFCR_EL1.FnE == 0.

The reset behavior of this field is:

Bit [4]

Reserved, RAZ/WI.

E[3], bit [3]

Level 1 data or unified cache hit.

E[3]Meaning
0b0

Level 1 data or unified cache refill event is ignored.

0b1

Do not record samples that have the Level 1 data or unified cache refill event == 1.

This field is ignored by the PE when PMSFCR_EL1.FnE == 0.

The reset behavior of this field is:

Bit [2]

Reserved, RAZ/WI.

E[1], bit [1]
When the PE supports sampling of speculative instructions:

Speculative.

E[1]Meaning
0b0

Architecturally executed event is ignored.

0b1

Do not record samples that have the Architecturally executed event == 1.

This field is ignored by the PE when PMSFCR_EL1.FnE == 0.

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

Bit [0]

Reserved, RAZ/WI.

Accessing PMSNEVFR_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PMSNEVFR_EL1

op0op1CRnCRmop2
0b110b0000b10010b10010b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.EnPMSN == '0' then UNDEFINED; elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.nPMSNEVFR_EL1 == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPMS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.EnPMSN == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '1x1' then return NVMem[0x850]; else return PMSNEVFR_EL1; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.EnPMSN == '0' then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.EnPMSN == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return PMSNEVFR_EL1; elsif PSTATE.EL == EL3 then return PMSNEVFR_EL1;

MSR PMSNEVFR_EL1, <Xt>

op0op1CRnCRmop2
0b110b0000b10010b10010b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.EnPMSN == '0' then UNDEFINED; elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.nPMSNEVFR_EL1 == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPMS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.EnPMSN == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '1x1' then NVMem[0x850] = X[t]; else PMSNEVFR_EL1 = X[t]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.EnPMSN == '0' then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3.EnPMSN == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMSNEVFR_EL1 = X[t]; elsif PSTATE.EL == EL3 then PMSNEVFR_EL1 = X[t];


20/09/2021 12:37; d4a233ffbdfb36e47856c443a7ce9a85f5e501ca

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