The TRBMAR_EL1 characteristics are:
Controls Trace Buffer Unit accesses to memory.
If the trace buffer pointers specify virtual addresses, the address properties are defined by the translation tables and this register is ignored.
This register is present only when FEAT_TRBE is implemented. Otherwise, direct accesses to TRBMAR_EL1 are UNDEFINED.
TRBMAR_EL1 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | SH | Attr[7:4] | Attr[3:0] |
Reserved, RES0.
Trace buffer shareability domain. Defines the shareability domain for Normal memory used by the trace buffer.
SH | Meaning |
---|---|
0b00 |
Non-shareable. |
0b10 |
Outer Shareable. |
0b11 |
Inner Shareable. |
All other values are reserved.
This field is ignored when TRBMAR_EL1.Attr specifies any of the following memory types:
All Device and Normal Inner Non-cacheable Outer Non-cacheable memory regions are always treated as Outer Shareable.
The reset behavior of this field is:
Trace buffer memory type and attributes. Defines the memory type and, for Normal memory, the cacheability attributes, for memory addressed by the trace buffer.
Attr[7:4] | Meaning | Applies when |
---|---|---|
0b0000 |
Device-nGnRnE memory. | |
0b0100 |
Normal memory, Inner Non-cacheable, Outer Non-cacheable with the XS attribute set to 0. | When FEAT_XS is implemented |
0b1010 |
Normal memory, Inner Write-through Cacheable, Outer Write-through Cacheable, Non-transient, Read-Allocate with the XS attribute set to 0. | When FEAT_XS is implemented |
0b1111 |
Tagged Normal memory, Outer Write-Back Non-transient, Read-allocate Write-allocate. | When FEAT_MTE2 is implemented |
All other values are reserved.
The reset behavior of this field is:
Trace buffer memory type and attributes. Defines the memory type and, for Normal memory, the Outer cacheability attributes, for memory addressed by the trace buffer.
Attr[7:4] | Meaning |
---|---|
0b0000 |
Device memory. The Device memory type is defined by TRBMAR_EL1.Attr[3:0]. |
0b0001 |
Normal memory, Outer Write-Through Transient, Write-allocate. |
0b0010 |
Normal memory, Outer Write-Through Transient, Read-allocate. |
0b0011 |
Normal memory, Outer Write-Through Transient, Read-allocate Write-allocate. |
0b0100 |
Normal memory, Outer Non-cacheable. |
0b0101 |
Normal memory, Outer Write-Back Transient, Write-allocate. |
0b0110 |
Normal memory, Outer Write-Back Transient, Read-allocate. |
0b0111 |
Normal memory, Outer Write-Back Transient, Read-allocate Write-allocate. |
0b1000 |
Normal memory, Outer Write-Through Non-transient, No allocate. |
0b1001 |
Normal memory, Outer Write-Through Non-transient, Write-allocate. |
0b1010 |
Normal memory, Outer Write-Through Non-transient, Read-allocate. |
0b1011 |
Normal memory, Outer Write-Through Non-transient, Read-allocate Write-allocate. |
0b1100 |
Normal memory, Outer Write-Back Non-transient, No allocate. |
0b1101 |
Normal memory, Outer Write-Back Non-transient, Write-allocate. |
0b1110 |
Normal memory, Outer Write-Back Non-transient, Read-allocate. |
0b1111 |
Normal memory, Outer Write-Back Non-transient, Read-allocate Write-allocate. |
The reset behavior of this field is:
Trace buffer memory attributes. Defines the Device memory attributes for memory addressed by the trace buffer.
Attr[3:0] | Meaning | Applies when |
---|---|---|
0b0000 |
Device-nGnRnE memory. | |
0b0100 |
Device-nGnRE memory. | |
0b1000 |
Device-nGRE memory. | |
0b1100 |
Device-GRE memory. | |
0b0001 |
Device-nGnRnE memory with the XS attribute set to 0. | When FEAT_XS is implemented |
0b0101 |
Device-nGnRE memory with the XS attribute set to 0. | When FEAT_XS is implemented |
0b1001 |
Device-nGRE memory with the XS attribute set to 0. | When FEAT_XS is implemented |
0b1101 |
Device-GRE memory with the XS attribute set to 0. | When FEAT_XS is implemented |
All other values are reserved.
The reset behavior of this field is:
Trace buffer memory attributes. Defines the Inner cacheability attributes for memory addressed by the trace buffer.
Attr[3:0] | Meaning | Applies when |
---|---|---|
0b0000 |
The memory type is defined by TRBMAR_EL1.Attr[7:4]. | When FEAT_MTE is implemented or FEAT_XS is implemented |
0b0001 |
Normal memory, Inner Write-Through Transient, Write-allocate. | |
0b0010 |
Normal memory, Inner Write-Through Transient, Read-allocate. | |
0b0011 |
Normal memory, Inner Write-Through Transient, Read-allocate Write-allocate. | |
0b0100 |
Normal memory, Inner Non-cacheable. | |
0b0101 |
Normal memory, Inner Write-Back Transient, Write-allocate. | |
0b0110 |
Normal memory, Inner Write-Back Transient, Read-allocate. | |
0b0111 |
Normal memory, Inner Write-Back Transient, Read-allocate Write-allocate. | |
0b1000 |
Normal memory, Inner Write-Through Non-transient, No allocate. | |
0b1001 |
Normal memory, Inner Write-Through Non-transient, Write-allocate. | |
0b1010 |
Normal memory, Inner Write-Through Non-transient, Read-allocate. | |
0b1011 |
Normal memory, Inner Write-Through Non-transient, Read-allocate Write-allocate. | |
0b1100 |
Normal memory, Inner Write-Back Non-transient, No allocate. | |
0b1101 |
Normal memory, Inner Write-Back Non-transient, Write-allocate. | |
0b1110 |
Normal memory, Inner Write-Back Non-transient, Read-allocate. | |
0b1111 |
Normal memory, Inner Write-Back Non-transient, Read-allocate Write-allocate. |
All other values are reserved.
The reset behavior of this field is:
The PE might ignore a direct write to TRBMAR_EL1 if TRBLIMITR_EL1.E == 1.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1001 | 0b1011 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then UNDEFINED; elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.TRBMAR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.E2TB == 'x0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return TRBMAR_EL1; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return TRBMAR_EL1; elsif PSTATE.EL == EL3 then return TRBMAR_EL1;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1001 | 0b1011 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then UNDEFINED; elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.TRBMAR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.E2TB == 'x0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else TRBMAR_EL1 = X[t]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSTB[0] == '0' || MDCR_EL3.NSTB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSTBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else TRBMAR_EL1 = X[t]; elsif PSTATE.EL == EL3 then TRBMAR_EL1 = X[t];
20/09/2021 12:37; d4a233ffbdfb36e47856c443a7ce9a85f5e501ca
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