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SMIDR_EL1, Streaming Mode Identification Register

The SMIDR_EL1 characteristics are:

Purpose

Provides additional identification mechanisms for scheduling purposes, for a PE that supports Streaming SVE mode.

Configuration

This register is present only when FEAT_SME is implemented. Otherwise, direct accesses to SMIDR_EL1 are UNDEFINED.

Attributes

SMIDR_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
ImplementerRevisionSMPSRES0Affinity

Bits [63:32]

Reserved, RES0.

Implementer, bits [31:24]

The Implementer code. This field must hold an implementer code that has been assigned by Arm. Assigned codes include the following:

ImplementerMeaning
0x00

Reserved for software use.

0x41

Arm Limited.

0x42

Broadcom Corporation.

0x43

Cavium Inc.

0x44

Digital Equipment Corporation.

0x46

Fujitsu Ltd.

0x49

Infineon Technologies AG.

0x4D

Motorola or Freescale Semiconductor Inc.

0x4E

NVIDIA Corporation.

0x50

Applied Micro Circuits Corporation.

0x51

Qualcomm Inc.

0x56

Marvell International Ltd.

0x69

Intel Corporation.

0xC0

Ampere Computing.

Arm can assign codes that are not published in this manual. All values not assigned by Arm are reserved and must not be used.

It is not required that this value is the same as the value of MIDR_EL1.Implementer.

Access to this field is RO.

Revision, bits [23:16]

Revision number for the Streaming Mode Compute Unit (SMCU).

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

SMPS, bit [15]

Indicates support for Streaming SVE mode execution priority.

SMPSMeaning
0b0

Priority control not supported.

0b1

Priority control supported.

Bits [14:12]

Reserved, RES0.

Affinity, bits [11:0]

The SMCU affinity of the accessing PE.

Accessing SMIDR_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, SMIDR_EL1

op0op1CRnCRmop2
0b110b0010b00000b00000b110

if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TID1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return SMIDR_EL1; elsif PSTATE.EL == EL2 then return SMIDR_EL1; elsif PSTATE.EL == EL3 then return SMIDR_EL1;


3020/09/2021 1412:5337; 092b4e1bbfbb45a293b198f9330c5f529ead2b0fd4a233ffbdfb36e47856c443a7ce9a85f5e501ca

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