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GICD_ICPENDR<n>, Interrupt Clear-Pending Registers, n = 0 - 31

The GICD_ICPENDR<n> characteristics are:

Purpose

Removes the pending state from the corresponding interrupt.

Configuration

These registers are available in all GIC configurations. If GICD_CTLR.DS==0, these registers are Common.

The number of implemented GICD_ICPENDR<n> registers is (GICD_TYPER.ITLinesNumber+1). Registers are numbered from 0.

GICD_ICPENDR0 is Banked for each connected PE with GICR_TYPER.Processor_Number < 8.

Accessing GICD_ICPENDR0 from a PE with GICR_TYPER.Processor_Number > 7 is CONSTRAINED UNPREDICTABLE:

Attributes

GICD_ICPENDR<n> is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
Clear_pending_bit31Clear_pending_bit30Clear_pending_bit29Clear_pending_bit28Clear_pending_bit27Clear_pending_bit26Clear_pending_bit25Clear_pending_bit24Clear_pending_bit23Clear_pending_bit22Clear_pending_bit21Clear_pending_bit20Clear_pending_bit19Clear_pending_bit18Clear_pending_bit17Clear_pending_bit16Clear_pending_bit15Clear_pending_bit14Clear_pending_bit13Clear_pending_bit12Clear_pending_bit11Clear_pending_bit10Clear_pending_bit9Clear_pending_bit8Clear_pending_bit7Clear_pending_bit6Clear_pending_bit5Clear_pending_bit4Clear_pending_bit3Clear_pending_bit2Clear_pending_bit1Clear_pending_bit0

Clear_pending_bit<x>, bit [x], for x = 31 to 0

For SPIs and PPIs, removes the pending state from interrupt number 32n + x. Reads and writes have the following behavior:

Clear_pending_bit<x>Meaning
0b0

If read, indicates that the corresponding interrupt is not pending on any PE.

If written, has no effect.

0b1
  • On this PE if the interrupt is an SGI or PPI.
  • On at least one PE if the interrupt is an SPI.

If read, indicates that the corresponding interrupt is pending, or active and pending.pending:

If written, changes the state of the corresponding interrupt from pending to inactive, or from active and pending to active. This has no effect in the following cases:

  • If the interrupt is an SGI. In this case, the write is ignored. The pending state of an SGI can be cleared using GICD_CPENDSGIR<n>.
  • If the interrupt is not pending and is not active and pending.
  • If the interrupt is a level-sensitive interrupt that is pending or active and pending for a reason other than a write to GICD_ISPENDR<n>. In this case, if the interrupt signal continues to be asserted, the interrupt remains pending or active and pending.

The reset behavior of this field is:

For INTID m, when DIV and MOD are the integer division and modulo operations:

Accessing GICD_ICPENDR<n>

Clear-pending bits for SGIs are RO/WI.

When affinity routing is enabled for the Security state of an interrupt:

Bits corresponding to unimplemented interrupts are RAZ/WI.

If GICD_CTLR.DS==0, unless the GICD_NSACR<n> registers permit Non-secure software to control Group 0 and Secure Group 1 interrupts, any bits that correspond to Group 0 or Secure Group 1 interrupts are accessible only by Secure accesses and are RAZ/WI to Non-secure accesses.

GICD_ICPENDR<n> can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
GIC DistributorDist_base0x0280 + (4 * n)GICD_ICPENDR<n>

AccessesThis oninterface thisis interfaceaccessible areas follows: RW.


3020/09/2021 1412:5337; 092b4e1bbfbb45a293b198f9330c5f529ead2b0fd4a233ffbdfb36e47856c443a7ce9a85f5e501ca

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