(old) htmldiff from-(new)

ATS1CPR, Address Translate Stage 1 Current state PL1 Read

The ATS1CPR characteristics are:

Purpose

Performs stage 1 address translation as defined for PL1 and the current Security state, with permissions as if reading from the given virtual address.

Configuration

This instruction is present only when AArch32 is supported. Otherwise, direct accesses to ATS1CPR are UNDEFINED.

Attributes

ATS1CPR is a 32-bit System instruction.

Field descriptions

313029282726252423222120191817161514131211109876543210
Input address for translation

Bits [31:0]

Input address for translation. The resulting address can be read from the PAR.

This System instruction takes a VA as input. If EL2 is implemented and enabled in the current Security state, the resulting address is the IPA that is the output address of the stage 1 translation. Otherwise, the resulting address is a PA.

Executing the ATS1CPR instruction

Accesses to this instruction use the following encodings in the System instruction encoding space:

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coprocopc1CRnCRmopc2
0b11110b0000b01110b10000b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T7 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T7 == '1' then AArch32.TakeHypTrapException(0x03); else AArch32.ATATS1CPR(R[t], TranslationStage_1, EL1, ATAccess_Read);]); elsif PSTATE.EL == EL2 then AArch32.ATATS1CPR(R[t], TranslationStage_1, EL1, ATAccess_Read);]); elsif PSTATE.EL == EL3 then if SCR.NS == '0' then AArch32.ATATS1CPR(R[t], TranslationStage_1, EL3, ATAccess_Read); else AArch32.AT(R[t], TranslationStage_1, EL1, ATAccess_Read);]);


3020/09/2021 1412:5337; 092b4e1bbfbb45a293b198f9330c5f529ead2b0fd4a233ffbdfb36e47856c443a7ce9a85f5e501ca

Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

(old) htmldiff from-(new)