The RMR characteristics are:
If EL1 or EL3 is the highest implemented Exception level and this register is implemented:
AArch32 System register RMR bits [31:0] are architecturally mapped to AArch64 System register RMR_EL1[31:0] when the highest implemented Exception level is EL1.
AArch32 System register RMR bits [31:0] are architecturally mapped to AArch64 System register RMR_EL3[31:0] when EL3 is implemented.
This register is present only when AArch32 is supported. Otherwise, direct accesses to RMR are UNDEFINED.
Only implemented if EL1 or EL3 is the highest implemented Exception level. In this case:
RMR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | RR | AA64 |
Reserved, RES0.
Reset Request. Setting this bit to 1 requests a Warm reset.
The reset behavior of this field is:
When the highest implemented Exception level can use AArch64, determines which Execution state the PE boots into after a Warm reset:
AA64 | Meaning |
---|---|
0b0 |
AArch32. |
0b1 |
AArch64. |
On coming out of the Warm reset, execution starts at the IMPLEMENTATION DEFINED reset vector address of the specified Execution state.
If the highest implemented Exception level cannot use AArch64 this bit is RAZ/WI.
When implemented as a RW field, this field resets to 0 on a Cold reset.
When EL3 is implemented, Arm deprecates accessing this register from any PE mode other than Monitor mode.
Accesses to this register use the following encodings in the System register encoding space:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b1100 | 0b0000 | 0b010 |
if PSTATE.EL IN {EL1, EL3} && IsHighestEL(PSTATE.EL) then return RMR; else UNDEFINED;
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b1100 | 0b0000 | 0b010 |
if PSTATE.EL IN {EL1, EL3} && IsHighestEL(PSTATE.EL) then RMR = R[t]; else UNDEFINED;
20/09/2021 12:37; d4a233ffbdfb36e47856c443a7ce9a85f5e501ca
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