The TRCIDR1 characteristics are:
Returns the tracing capabilities of the trace unit.
AArch64 System register TRCIDR1 bits [31:0] are architecturally mapped to External register TRCIDR1[31:0].
This register is present only when FEAT_ETE is implemented. Otherwise, direct accesses to TRCIDR1 are UNDEFINED.
TRCIDR1 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
DESIGNER | RES0 | RES1 | TRCARCHMAJ | TRCARCHMIN | REVISION |
Reserved, RES0.
Indicates which company designed the trace unit. The permitted values of this field are the same as MIDR_EL1.Implementer.
Reserved, RES0.
Reserved, RES1.
Major architecture version.
TRCARCHMAJ | Meaning |
---|---|
0b1111 |
If both TRCARCHMAJ and TRCARCHMIN == 0xF then refer to TRCDEVARCH. |
All other values are reserved.
This field reads as 0b1111.
Minor architecture version.
TRCARCHMIN | Meaning |
---|---|
0b1111 |
If both TRCARCHMAJ and TRCARCHMIN == 0xF then refer to TRCDEVARCH. |
All other values are reserved.
This field reads as 0b1111.
Implementation revision.
Returns an IMPLEMENTATION DEFINED value that identifies the revision of the trace unit.
Arm deprecates any use of this field and recommends that implementations set this field to zero.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b001 | 0b0000 | 0b1001 | 0b111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TTA == '1' then UNDEFINED; elsif CPACR_EL1.TTA == '1' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.TRCID == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return TRCIDR1; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TTA == '1' then UNDEFINED; elsif CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return TRCIDR1; elsif PSTATE.EL == EL3 then if CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else return TRCIDR1;
30/09/2021 14:53; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.