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The DC CIGVAC characteristics are:
Clean and Invalidate Allocation Tags in data cache by address to Point of Coherency.
This instruction is present only when FEAT_MTE is implemented. Otherwise, direct accesses to DC CIGVAC are UNDEFINED.
DC CIGVAC is a 64-bit System instruction.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Virtual address to use | |||||||||||||||||||||||||||||||
Virtual address to use |
Virtual address to use. No alignment restrictions apply to this VA.
Execution of this instruction might require an address translation from VA to PA, and that translation might fault. For more information, see 'The data cache maintenance instruction (DC)'.
If EL0 access is enabled, when executed at EL0, this instruction requires read access permission to the VA, otherwise it generates a Permission fault.
If EL0 access is enabled, when executed at EL0, this instruction requires read access permission to the VA, otherwise it generates a Permission fault, subject to the constraints described in 'Permission fault'.
If FEAT_CMOW is implemented, HCR_EL2.{E2H, TGE} is not {1, 1}, SCTLR_EL1.CMOW is 1, and EL0 access is enabled, when executed at EL0, the instruction has stage 1 read permission to the VA, but does not have stage 1 write permission to the VA, the instruction generates a stage 1 Permission fault.
If FEAT_CMOW is implemented, HCR_EL2.E2H is 1, SCTLR_EL2.CMOW is 1, and EL0 access is enabled, when executed at EL0, the instruction has stage 1 read permission to the VA but does not have stage 1 write permission to the VA, the instruction generates a stage 1 Permission fault.
If FEAT_CMOW is implemented, HCRX_EL2.CMOW is 1, and EL1 or EL0 access is enabled, when executed at EL1 or EL0, the instruction has stage 2 read permission to the VA but does not have stage 2 write permission to the VA, the instruction generates a stage 2 Permission fault.
For more information, see 'Permission fault'.
Accesses to this instruction use the following encodings in the System instruction encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b01 | 0b011 | 0b0111 | 0b1110 | 0b011 |
if PSTATE.EL == EL0 then if !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && SCTLR_EL1.UCI == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && HCR_EL2.TPCP == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.DCCIVAC == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && SCTLR_EL2.UCI == '0' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.DC(X[t], CacheType_Tag, CacheOp_CleanInvalidate, CacheOpScope_PoC); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TPCP == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.DCCIVAC == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.DC(X[t], CacheType_Tag, CacheOp_CleanInvalidate, CacheOpScope_PoC); elsif PSTATE.EL == EL2 then AArch64.DC(X[t], CacheType_Tag, CacheOp_CleanInvalidate, CacheOpScope_PoC); elsif PSTATE.EL == EL3 then AArch64.DC(X[t], CacheType_Tag, CacheOp_CleanInvalidate, CacheOpScope_PoC);
3020/09/2021 1412:5337; 092b4e1bbfbb45a293b198f9330c5f529ead2b0fd4a233ffbdfb36e47856c443a7ce9a85f5e501ca
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