The PMSEVFR_EL1 characteristics are:
Controls sample filtering by events. The overall filter is the logical AND of these filters. For example, if E[3] and E[5] are both set to 1, only samples that have both event 3 (Level 1 unified or data cache refill) and event 5 set (TLB walk) are recorded.
This register is present only when FEAT_SPE is implemented. Otherwise, direct accesses to PMSEVFR_EL1 are UNDEFINED.
PMSEVFR_EL1 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
E[63] | E[62] | E[61] | E[60] | E[59] | E[58] | E[57] | E[56] | E[55] | E[54] | E[53] | E[52] | E[51] | E[50] | E[49] | E[48] | RAZ/WI | |||||||||||||||
E[31] | E[30] | E[29] | E[28] | E[27] | E[26] | E[25] | E[24] | RAZ/WI | E[18] | E[17] | E[16] | E[15] | E[14] | E[13] | E[12] | E[11] | RAZ/WI | E[7] | E[6] | E[5] | RAZ/WI | E[3] | RAZ/WI | E[1] | RAZ/WI |
E[<x>] is the event filter for event <x>. If event <x> is not implemented, or filtering on event <x> is not supported, the corresponding bit is RAZ/WI.
E[<x>] | Meaning |
---|---|
0b0 |
Event <x> is ignored. |
0b1 |
Do not record samples that have event <x> == 0. |
An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, if the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.
This field is ignored by the PE when PMSFCR_EL1.FE == 0
The reset behavior of this field is:
Reserved, RAZ/WI.
Reserved, RAZ/WI.
Empty predicate.
E[18] | Meaning |
---|---|
0b0 |
Empty predicate event is ignored. |
0b1 |
Do not record samples that have the Empty predicate event == 0. |
This bit is ignored by the PE when PMSFCR_EL1.FE == 0.
The reset behavior of this field is:
Reserved, RAZ/WI.
Partial predicate.
E[17] | Meaning |
---|---|
0b0 |
Partial predicate event is ignored. |
0b1 |
Do not record samples that have the Partial predicate event == 0. |
This bit is ignored by the PE when PMSFCR_EL1.FE == 0.
The reset behavior of this field is:
Reserved, RAZ/WI.
Transactional
E[16] | Meaning |
---|---|
0b0 |
Transactional event is ignored. |
0b1 |
Do not record samples that have the Transactional event == 0. |
This bit is ignored by the PE when PMSFCR_EL1.FE == 0.
The reset behavior of this field is:
Reserved, RAZ/WI.
Alignment.
E[11] | Meaning |
---|---|
0b0 |
Alignment event is ignored. |
0b1 |
Do not record samples that have the Alignment event == 0. |
This bit is ignored by the PE when PMSFCR_EL1.FE == 0.
The reset behavior of this field is:
Reserved, RAZ/WI.
Reserved, RAZ/WI.
Mispredicted.
E[7] | Meaning |
---|---|
0b0 |
Mispredicted event is ignored. |
0b1 |
Do not record samples that have the Mispredicted event == 0. |
This bit is ignored by the PE when PMSFCR_EL1.FE == 0.
The reset behavior of this field is:
Not taken.
E[6] | Meaning |
---|---|
0b0 |
Not taken event is ignored. |
0b1 |
Do not record samples that have the Not taken event == 0. |
This field is ignored by the PE when PMSFCR_EL1.FE == 0.
The reset behavior of this field is:
Reserved, RAZ/WI.
TLB walk.
E[5] | Meaning |
---|---|
0b0 |
TLB walk event is ignored. |
0b1 |
Do not record samples that have the TLB walk event == 0. |
This bit is ignored by the PE when PMSFCR_EL1.FE == 0.
The reset behavior of this field is:
Reserved, RAZ/WI.
Level 1 data or unified cache refill.
E[3] | Meaning |
---|---|
0b0 |
Level 1 data or unified cache refill event is ignored. |
0b1 |
Do not record samples that have the Level 1 data or unified cache refill event == 0. |
This bit is ignored by the PE when PMSFCR_EL1.FE == 0.
The reset behavior of this field is:
Reserved, RAZ/WI.
Architecturally executed.
When the PE supports sampling of speculative instructions:
E[1] | Meaning |
---|---|
0b0 |
Architecturally executed event is ignored. |
0b1 |
Do not record samples that have the Architecturally executed event == 0. |
This bit is ignored by the PE when PMSFCR_EL1.FE == 0.
If the PE does not support the sampling of speculative instructions, or always discards the sample record for speculative instructions, this bit reads as an UNKNOWN value and the PE ignores its value.
The reset behavior of this field is:
Reserved, UNKNOWN.
Reserved, RAZ/WI.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1001 | 0b1001 | 0b101 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMSEVFR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPMS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '1x1' then return NVMem[0x830]; else return PMSEVFR_EL1; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return PMSEVFR_EL1; elsif PSTATE.EL == EL3 then return PMSEVFR_EL1;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1001 | 0b1001 | 0b101 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.PMSEVFR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPMS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '1x1' then NVMem[0x830] = X[t]; else PMSEVFR_EL1 = X[t]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMSEVFR_EL1 = X[t]; elsif PSTATE.EL == EL3 then PMSEVFR_EL1 = X[t];
30/09/2021 14:53; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f
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