The SVCR characteristics are:
Controls Streaming SVE mode and SME behavior.
This register is present only when FEAT_SME is implemented. Otherwise, direct accesses to SVCR are UNDEFINED.
SVCR is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | ZA | SM |
Reserved, RES0.
Enables ZA array storage. The possible values of this bit are:
ZA | Meaning |
---|---|
0b0 |
SME ZA array storage is invalid and not accessible. SME instructions that access the ZA array are illegal. |
0b1 |
SME ZA array storage is valid and accessible. If SME instructions are not trapped, SME instructions that access the ZA array are legal. |
When PSTATE.ZA is changed by any means from 0 to 1, the contents of the SME ZA storage are set to zero.
When PSTATE.ZA is changed by any means from 1 to 0, there is no observable change to SME ZA storage.
When PSTATE.ZA is changed by any means from 1 to 0 or from 0 to 1, there is no effect on the Streaming SVE vector and predicate registers and FPSR if PSTATE.SM remains set to 1.
A direct or indirect read of ZA appears to occur in program order relative to a direct write of SVCR, and to MSR SVCRZA and MSR SVCRSMZA instructions, without the need for explicit synchronization.
The reset behavior of this field is:
Enables Streaming SVE mode. The possible values of this bit are:
SM | Meaning |
---|---|
0b0 |
The PE is not in Streaming SVE mode. |
0b1 |
The PE is in Streaming SVE mode. |
When the effective value of PSTATE.SM is changed by any means from 0 to 1, an entry to Streaming SVE mode is performed, and each implemented bit of the SVE registers Z0-Z31 and P0-P15 in the new mode is set to an IMPLEMENTATION DEFINED choice of one of the following values:
When the effective value of PSTATE.SM is changed by any means from 1 to 0, an exit from Streaming SVE mode is performed, and each implemented bit of the SVE registers Z0-Z31 and P0-P15 in the new mode is set to an IMPLEMENTATION DEFINED choice of one of the following values:
When the effective value of PSTATE.SM is changed by any means from from 1 to 0, each implemented bit of the FFR predicate register in the new mode is set to zero.
When the effective value of PSTATE.SM is changed by any means from 0 to 1 or from 1 to 0, the FPSR in the new mode is set to an IMPLEMENTATION DEFINED choice of one of the following values:
A direct or indirect read of SM appears to occur in program order relative to a direct write of SVCR, and to MSR SVCRSM and MSR SVCRSMZA instructions, without the need for explicit synchronization.
The reset behavior of this field is:
SVCR is read/write and can be accessed from any Exception level.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b011 | 0b0100 | 0b0010 | 0b010 |
if PSTATE.EL == EL0 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.ESM == '0' then UNDEFINED; elsif !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && CPACR_EL1.SMEN != '11' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); else AArch64.SystemAccessTrap(EL1, 0x1D); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && CPTR_EL2.SMEN != '11' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif EL2Enabled() && HCR_EL2.E2H == '1' && CPTR_EL2.SMEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif EL2Enabled() && HCR_EL2.E2H == '0' && CPTR_EL2.TSM == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HaveEL(EL3) && CPTR_EL3.ESM == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x1D); else return Zeros(62):PSTATE.<ZA,SM>; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.ESM == '0' then UNDEFINED; elsif CPACR_EL1.SMEN == 'x0' then AArch64.SystemAccessTrap(EL1, 0x1D); elsif EL2Enabled() && HCR_EL2.E2H == '0' && CPTR_EL2.TSM == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif EL2Enabled() && HCR_EL2.E2H == '1' && CPTR_EL2.SMEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HaveEL(EL3) && CPTR_EL3.ESM == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x1D); else return Zeros(62):PSTATE.<ZA,SM>; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.ESM == '0' then UNDEFINED; elsif HCR_EL2.E2H == '0' && CPTR_EL2.TSM == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HCR_EL2.E2H == '1' && CPTR_EL2.SMEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HaveEL(EL3) && CPTR_EL3.ESM == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x1D); else return Zeros(62):PSTATE.<ZA,SM>; elsif PSTATE.EL == EL3 then if CPTR_EL3.ESM == '0' then AArch64.SystemAccessTrap(EL3, 0x1D); else return Zeros(62):PSTATE.<ZA,SM>;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b011 | 0b0100 | 0b0010 | 0b010 |
if PSTATE.EL == EL0 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.ESM == '0' then UNDEFINED; elsif !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && CPACR_EL1.SMEN != '11' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); else AArch64.SystemAccessTrap(EL1, 0x1D); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && CPTR_EL2.SMEN != '11' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif EL2Enabled() && HCR_EL2.E2H == '1' && CPTR_EL2.SMEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif EL2Enabled() && HCR_EL2.E2H == '0' && CPTR_EL2.TSM == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HaveEL(EL3) && CPTR_EL3.ESM == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x1D); else PSTATE.<ZA,SM> = X[t]<1:0>; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.ESM == '0' then UNDEFINED; elsif CPACR_EL1.SMEN == 'x0' then AArch64.SystemAccessTrap(EL1, 0x1D); elsif EL2Enabled() && HCR_EL2.E2H == '0' && CPTR_EL2.TSM == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif EL2Enabled() && HCR_EL2.E2H == '1' && CPTR_EL2.SMEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HaveEL(EL3) && CPTR_EL3.ESM == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x1D); else PSTATE.<ZA,SM> = X[t]<1:0>; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.ESM == '0' then UNDEFINED; elsif HCR_EL2.E2H == '0' && CPTR_EL2.TSM == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HCR_EL2.E2H == '1' && CPTR_EL2.SMEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HaveEL(EL3) && CPTR_EL3.ESM == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x1D); else PSTATE.<ZA,SM> = X[t]<1:0>; elsif PSTATE.EL == EL3 then if CPTR_EL3.ESM == '0' then AArch64.SystemAccessTrap(EL3, 0x1D); else PSTATE.<ZA,SM> = X[t]<1:0>;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b00 | 0b011 | 0b0100 | 0b001x | 0b011 |
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b00 | 0b011 | 0b0100 | 0b010x | 0b011 |
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b00 | 0b011 | 0b0100 | 0b011x | 0b011 |
20/09/2021 12:37; d4a233ffbdfb36e47856c443a7ce9a85f5e501ca
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