DAIF, Interrupt Mask Bits

The DAIF characteristics are:

Purpose

Allows access to the interrupt mask bits.

Configuration

There are no configuration notes.

Attributes

DAIF is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0DAIFRES0

Bits [63:10]

Reserved, RES0.

D, bit [9]

Process state D mask. The possible values of this bit are:

DMeaning
0b0

Watchpoint, Breakpoint, and Software Step exceptions targeted at the current Exception level are not masked.

0b1

Watchpoint, Breakpoint, and Software Step exceptions targeted at the current Exception level are masked.

When the target Exception level of the debug exception is higher than the current Exception level, the exception is not masked by this bit.

The reset behavior of this field is:

A, bit [8]

SError interrupt mask bit. The possible values of this bit are:

AMeaning
0b0

Exception not masked.

0b1

Exception masked.

The reset behavior of this field is:

I, bit [7]

IRQ mask bit. The possible values of this bit are:

IMeaning
0b0

Exception not masked.

0b1

Exception masked.

The reset behavior of this field is:

F, bit [6]

FIQ mask bit. The possible values of this bit are:

FMeaning
0b0

Exception not masked.

0b1

Exception masked.

The reset behavior of this field is:

Bits [5:0]

Reserved, RES0.

Accessing DAIF

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, DAIF

op0op1CRnCRmop2
0b110b0110b01000b00100b001

if PSTATE.EL == EL0 then if (EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') || SCTLR_EL1.UMA == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else return Zeros(54):PSTATE.<D,A,I,F>:Zeros(6); elsif PSTATE.EL == EL1 then return Zeros(54):PSTATE.<D,A,I,F>:Zeros(6); elsif PSTATE.EL == EL2 then return Zeros(54):PSTATE.<D,A,I,F>:Zeros(6); elsif PSTATE.EL == EL3 then return Zeros(54):PSTATE.<D,A,I,F>:Zeros(6);

MSR DAIF, <Xt>

op0op1CRnCRmop2
0b110b0110b01000b00100b001

if PSTATE.EL == EL0 then if (EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') || SCTLR_EL1.UMA == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else PSTATE.<D,A,I,F> = X[t]<9:6>; elsif PSTATE.EL == EL1 then PSTATE.<D,A,I,F> = X[t]<9:6>; elsif PSTATE.EL == EL2 then PSTATE.<D,A,I,F> = X[t]<9:6>; elsif PSTATE.EL == EL3 then PSTATE.<D,A,I,F> = X[t]<9:6>;

MSR DAIFSet, #<imm>

op0op1CRnop2
0b000b0110b01000b110

MSR DAIFClr, #<imm>

op0op1CRnop2
0b000b0110b01000b111

20/09/2021 12:37; d4a233ffbdfb36e47856c443a7ce9a85f5e501ca

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