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SVCR, Streaming Vector Control Register

The SVCR characteristics are:

Purpose

Controls Streaming SVE mode and SME behavior.

Configuration

This register is present only when FEAT_SME is implemented. Otherwise, direct accesses to SVCR are UNDEFINED.

Attributes

SVCR is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0ZASM

Bits [63:2]

Reserved, RES0.

ZA, bit [1]

Enables ZA array storage. The possible values of this bit are:

ZAMeaning
0b0

SME ZA array storage is invalid and not accessible. SME instructions that access the ZA array are illegal.

0b1

SME ZA array storage is valid and accessible. If SME instructions are not trapped, SME instructions that access the ZA array are legal.

When thePSTATE.ZA valueis ofchanged PSTATE.ZAby isany changedmeans from 0 to 1, the followingcontents applies:of the SME ZA storage are set to zero.

When PSTATE.ZA is changed by any means from 1 to 0, there is no observable change to SME ZA storage.

When PSTATE.ZA is changed by any means from 1 to 0 or from 0 to 1, there is no effect on the Streaming SVE vector and predicate registers and FPSR if PSTATE.SM remains set to 1.

A direct or indirect read of ZA appears to occur in program order relative to a direct write of SVCR, and to MSR SVCRZA and MSR SVCRSMZA instructions, without the need for explicit synchronization.

The reset behavior of this field is:

SM, bit [0]

Enables Streaming SVE mode. The possible values of this bit are:

SMMeaning
0b0

The PE is not in Streaming SVE mode.

0b1

The PE is in Streaming SVE mode.

When the effective value of PSTATE.SM is changed by any means from 1 to 0, an exit from Streaming SVE mode is performed, and each implemented bit of the SVE registers Z0-Z31 and P0-P15 in the new mode is set to an IMPLEMENTATION DEFINED choice of one of the following values:

When the effective value of PSTATE.SM is changed by any means from from 1 to 0, each implemented bit of the FFR predicate register in the new mode is set to zero.

When the effective value of PSTATE.SM is changed by any means from 0 to 1 or from 1 to 0, the FPSR in the new mode is set to an IMPLEMENTATION DEFINED choice of one of the following values:

When the value of PSTATE.SM is changed, the following applies:

When the effective value of PSTATE.SM is changed by any means from 0 to 1, an entry to Streaming SVE mode is performed, and each implemented bit of the SVE registers Z0-Z31 and P0-P15 in the new mode is set to an IMPLEMENTATION DEFINED choice of one of the following values:

A direct or indirect read of SM appears to occur in program order relative to a direct write of SVCR, and to MSR SVCRSM and MSR SVCRSMZA instructions, without the need for explicit synchronization.

The reset behavior of this field is:

Accessing SVCR

SVCR is read/write and can be accessed from any Exception level.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, SVCR

op0op1CRnCRmop2
0b110b0110b01000b00100b010

if PSTATE.EL == EL0 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.ESM == '0' then UNDEFINED; elsif !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && CPACR_EL1.SMEN != '11' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); else AArch64.SystemAccessTrap(EL1, 0x1D); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && CPTR_EL2.SMEN != '11' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif EL2Enabled() && HCR_EL2.E2H == '1' && CPTR_EL2.SMEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif EL2Enabled() && HCR_EL2.E2H == '0' && CPTR_EL2.TSM == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HaveEL(EL3) && CPTR_EL3.ESM == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x1D); else return Zeros(62):PSTATE.<ZA,SM>; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.ESM == '0' then UNDEFINED; elsif CPACR_EL1.SMEN == 'x0' then AArch64.SystemAccessTrap(EL1, 0x1D); elsif EL2Enabled() && HCR_EL2.E2H == '0' && CPTR_EL2.TSM == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif EL2Enabled() && HCR_EL2.E2H == '1' && CPTR_EL2.SMEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HaveEL(EL3) && CPTR_EL3.ESM == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x1D); else return Zeros(62):PSTATE.<ZA,SM>; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.ESM == '0' then UNDEFINED; elsif HCR_EL2.E2H == '0' && CPTR_EL2.TSM == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HCR_EL2.E2H == '1' && CPTR_EL2.SMEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HaveEL(EL3) && CPTR_EL3.ESM == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x1D); else return Zeros(62):PSTATE.<ZA,SM>; elsif PSTATE.EL == EL3 then if CPTR_EL3.ESM == '0' then AArch64.SystemAccessTrap(EL3, 0x1D); else return Zeros(62):PSTATE.<ZA,SM>;

MSR SVCR, <Xt>

op0op1CRnCRmop2
0b110b0110b01000b00100b010

if PSTATE.EL == EL0 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.ESM == '0' then UNDEFINED; elsif !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && CPACR_EL1.SMEN != '11' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); else AArch64.SystemAccessTrap(EL1, 0x1D); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && CPTR_EL2.SMEN != '11' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif EL2Enabled() && HCR_EL2.E2H == '1' && CPTR_EL2.SMEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif EL2Enabled() && HCR_EL2.E2H == '0' && CPTR_EL2.TSM == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HaveEL(EL3) && CPTR_EL3.ESM == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x1D); else bits(64)PSTATE.<ZA,SM> v = X[t]; SetPSTATE_SM(v<]<1:0>); SetPSTATE_ZA(v<1>);>; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.ESM == '0' then UNDEFINED; elsif CPACR_EL1.SMEN == 'x0' then AArch64.SystemAccessTrap(EL1, 0x1D); elsif EL2Enabled() && HCR_EL2.E2H == '0' && CPTR_EL2.TSM == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif EL2Enabled() && HCR_EL2.E2H == '1' && CPTR_EL2.SMEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HaveEL(EL3) && CPTR_EL3.ESM == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x1D); else bits(64)PSTATE.<ZA,SM> v = X[t]; SetPSTATE_SM(v<]<1:0>); SetPSTATE_ZA(v<1>);>; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.ESM == '0' then UNDEFINED; elsif HCR_EL2.E2H == '0' && CPTR_EL2.TSM == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HCR_EL2.E2H == '1' && CPTR_EL2.SMEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HaveEL(EL3) && CPTR_EL3.ESM == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x1D); else bits(64)PSTATE.<ZA,SM> v = X[t]; SetPSTATE_SM(v<]<1:0>); SetPSTATE_ZA(v<1>);>; elsif PSTATE.EL == EL3 then if CPTR_EL3.ESM == '0' then AArch64.SystemAccessTrap(EL3, 0x1D); else bits(64)PSTATE.<ZA,SM> v = X[t]; SetPSTATE_SM(v<]<1:0>); SetPSTATE_ZA(v<1>);>;

MSR SVCRSM, #<imm>

op0op1CRnCRmop2
0b000b0110b01000b001x0b011

MSR SVCRZA, #<imm>

op0op1CRnCRmop2
0b000b0110b01000b010x0b011

MSR SVCRSMZA, #<imm>

op0op1CRnCRmop2
0b000b0110b01000b011x0b011

3020/09/2021 1412:5337; 092b4e1bbfbb45a293b198f9330c5f529ead2b0fd4a233ffbdfb36e47856c443a7ce9a85f5e501ca

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