VDISR_EL2, Virtual Deferred Interrupt Status Register

The VDISR_EL2 characteristics are:

Purpose

Records that a virtual SError interrupt has been consumed by an ESB instruction executed at EL1.

An indirect write to VDISR_EL2 made by an ESB instruction does not require an explicit synchronization operation for the value written to be observed by a direct read of DISR_EL1 or DISR occurring in program order after the ESB instruction.

Configuration

AArch64 System register VDISR_EL2 bits [31:0] are architecturally mapped to AArch32 System register VDISR[31:0].

This register is present only when FEAT_RAS is implemented. Otherwise, direct accesses to VDISR_EL2 are UNDEFINED.

If EL2 is not implemented, this register is RES0 from EL3.

This register has no effect if EL2 is not enabled in the current Security state.

Attributes

VDISR_EL2 is a 64-bit register.

Field descriptions

When EL1 is using AArch64:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
ARES0IDSISS

Bits [63:32]

Reserved, RES0.

A, bit [31]

Set to 1 when an ESB instruction defers a virtual SError interrupt.

The reset behavior of this field is:

Bits [30:25]

Reserved, RES0.

IDS, bit [24]

The value copied from VSESR_EL2.IDS.

The reset behavior of this field is:

ISS, bits [23:0]

The value copied from VSESR_EL2.ISS.

The reset behavior of this field is:

When EL1 is using AArch32 and VDISR_EL2.LPAE == 0:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
ARES0AETRES0ExTRES0FS[4]LPAERES0FS[3:0]

Bits [63:32]

Reserved, RES0.

A, bit [31]

Set to 1 when an ESB instruction defers a virtual SError interrupt.

The reset behavior of this field is:

Bits [30:16]

Reserved, RES0.

AET, bits [15:14]

The value copied from VSESR_EL2.AET.

The reset behavior of this field is:

Bit [13]

Reserved, RES0.

ExT, bit [12]

The value copied from VSESR_EL2.ExT.

The reset behavior of this field is:

Bit [11]

Reserved, RES0.

FS, bits [10, 3:0]

Fault status code. Set to 0b10110 when an ESB instruction defers a virtual SError interrupt.

FSMeaning
0b10110

Asynchronous SError interrupt.

All other values are reserved.

The FS field is split as follows:

The reset behavior of this field is:

LPAE, bit [9]

Format.

Set to TTBCR.EAE when an ESB instruction defers a virtual SError interrupt.

LPAEMeaning
0b0

Using the Short-descriptor translation table format.

The reset behavior of this field is:

Bits [8:4]

Reserved, RES0.

When EL1 is using AArch32 and VDISR_EL2.LPAE == 1:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
ARES0AETRES0ExTRES0LPAERES0STATUS

Bits [63:32]

Reserved, RES0.

A, bit [31]

Set to 1 when an ESB instruction defers a virtual SError interrupt.

The reset behavior of this field is:

Bits [30:16]

Reserved, RES0.

AET, bits [15:14]

The value copied from VSESR_EL2.AET.

The reset behavior of this field is:

Bit [13]

Reserved, RES0.

ExT, bit [12]

The value copied from VSESR_EL2.ExT.

The reset behavior of this field is:

Bits [11:10]

Reserved, RES0.

LPAE, bit [9]

Format.

Set to TTBCR.EAE when an ESB instruction defers a virtual SError interrupt.

LPAEMeaning
0b1

Using the Long-descriptor translation table format.

The reset behavior of this field is:

Bits [8:6]

Reserved, RES0.

STATUS, bits [5:0]

Fault status code. Set to 0b010001 when an ESB instruction defers a virtual SError interrupt.

STATUSMeaning
0b010001

Asynchronous SError interrupt.

All other values are reserved.

The reset behavior of this field is:

Accessing VDISR_EL2

An indirect write to VDISR_EL2 made by an ESB instruction does not require an explicit synchronization operation for the value that is written to be observed by a direct read of DISR_EL1 or DISR occurring in program order after the ESB instruction.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, VDISR_EL2

op0op1CRnCRmop2
0b110b1000b11000b00010b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then return NVMem[0x500]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then return VDISR_EL2; elsif PSTATE.EL == EL3 then return VDISR_EL2;

MSR VDISR_EL2, <Xt>

op0op1CRnCRmop2
0b110b1000b11000b00010b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then NVMem[0x500] = X[t]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then VDISR_EL2 = X[t]; elsif PSTATE.EL == EL3 then VDISR_EL2 = X[t];

MRS <Xt>, DISR_EL1

op0op1CRnCRmop2
0b110b0000b11000b00010b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.AMO == '1' then return VDISR_EL2; elsif HaveEL(EL3) && !Halted() && SCR_EL3.EA == '1' then return Zeros(); else return DISR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !Halted() && SCR_EL3.EA == '1' then return Zeros(); else return DISR_EL1; elsif PSTATE.EL == EL3 then return DISR_EL1;

MSR DISR_EL1, <Xt>

op0op1CRnCRmop2
0b110b0000b11000b00010b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.AMO == '1' then VDISR_EL2 = X[t]; elsif HaveEL(EL3) && !Halted() && SCR_EL3.EA == '1' then //no operation else DISR_EL1 = X[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && !Halted() && SCR_EL3.EA == '1' then //no operation else DISR_EL1 = X[t]; elsif PSTATE.EL == EL3 then DISR_EL1 = X[t];


20/09/2021 12:37; d4a233ffbdfb36e47856c443a7ce9a85f5e501ca

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