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SMCR_EL2, SME Control Register (EL2)

The SMCR_EL2 characteristics are:

Purpose

This register controls aspects of Streaming SVE that are visible at Exception levels EL2, EL1, and EL0.

Configuration

This register is present only when FEAT_SME is implemented. Otherwise, direct accesses to SMCR_EL2 are UNDEFINED.

This register has no effect if the PE is not in Streaming SVE mode, or if EL2 is not enabled in the current Security state.

If EL2 is not implemented, this register is RES0 from EL3.

Attributes

SMCR_EL2 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
FA64RES0RES0RAZ/WIRAZ/WILENLEN

Bits [63:329]

Reserved, RES0.

FA64, bit [31]
When FEAT_SME_FA64 is implemented:

Controls whether execution of an A64 instruction is considered legal when the PE is in Streaming SVE mode.

FA64Meaning
0b0

This control does not cause any instruction to be treated as legal in Streaming SVE mode.

0b1

This control causes all implemented A64 instructions to be treated as legal in Streaming SVE mode at EL2, if they are treated as legal at EL3.

Arm recommends that portable SME software should not rely on this optional feature, and that operating systems should provide a means to test for compliance with this recommendation.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Bits [30:9]

Reserved, RES0.

Bits [8:4]

Reserved, RAZ/WI.

LEN, bits [3:0]

Effective Streaming SVE Vector Length (SVL).

Constrains the effective Streaming SVE vector register length for EL2, EL1, and EL0 to (LEN+1)*128 bits when EL2 is enabled in the current Security state. SVLstate onlyand takes effect when the PE is in Streaming SVE mode.

An implementation is permitted to include any set of Streaming SVE vector lengths that are powers of two, from 128 bits to 2048 bits inclusive.

For all purposes other than returning the result of a direct read of SMCR_EL2, this field selects the effective vector length as follows:

An indirect read of SMCR_EL2.LEN appears to occur in program order relative to a direct write of the same register, without the need for explicit synchronization.

The reset behavior of this field is:

Accessing SMCR_EL2

When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic SMCR_EL2 or SMCR_EL1 are not guaranteed to be ordered with respect to accesses using the other mnemonic.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, SMCR_EL2

op0op1CRnCRmop2
0b110b1000b00010b00100b110

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.ESM == '0' then UNDEFINED; elsif HCR_EL2.E2H == '0' && CPTR_EL2.TSM == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HCR_EL2.E2H == '1' && CPTR_EL2.SMEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HaveEL(EL3) && CPTR_EL3.ESM == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x1D); else return SMCR_EL2; elsif PSTATE.EL == EL3 then if CPTR_EL3.ESM == '0' then AArch64.SystemAccessTrap(EL3, 0x1D); else return SMCR_EL2;

MSR SMCR_EL2, <Xt>

op0op1CRnCRmop2
0b110b1000b00010b00100b110

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.ESM == '0' then UNDEFINED; elsif HCR_EL2.E2H == '0' && CPTR_EL2.TSM == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HCR_EL2.E2H == '1' && CPTR_EL2.SMEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HaveEL(EL3) && CPTR_EL3.ESM == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x1D); else SMCR_EL2 = X[t]; elsif PSTATE.EL == EL3 then if CPTR_EL3.ESM == '0' then AArch64.SystemAccessTrap(EL3, 0x1D); else SMCR_EL2 = X[t];

MRS <Xt>, SMCR_EL1

op0op1CRnCRmop2
0b110b0000b00010b00100b110

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.ESM == '0' then UNDEFINED; elsif CPACR_EL1.SMEN == 'x0' then AArch64.SystemAccessTrap(EL1, 0x1D); elsif EL2Enabled() && HCR_EL2.E2H == '0' && CPTR_EL2.TSM == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif EL2Enabled() && HCR_EL2.E2H == '1' && CPTR_EL2.SMEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HaveEL(EL3) && CPTR_EL3.ESM == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x1D); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then return NVMem[0x1F0]; else return SMCR_EL1; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.ESM == '0' then UNDEFINED; elsif HCR_EL2.E2H == '0' && CPTR_EL2.TSM == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HCR_EL2.E2H == '1' && CPTR_EL2.SMEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HaveEL(EL3) && CPTR_EL3.ESM == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x1D); elsif HCR_EL2.E2H == '1' then return SMCR_EL2; else return SMCR_EL1; elsif PSTATE.EL == EL3 then if CPTR_EL3.ESM == '0' then AArch64.SystemAccessTrap(EL3, 0x1D); else return SMCR_EL1;

MSR SMCR_EL1, <Xt>

op0op1CRnCRmop2
0b110b0000b00010b00100b110

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.ESM == '0' then UNDEFINED; elsif CPACR_EL1.SMEN == 'x0' then AArch64.SystemAccessTrap(EL1, 0x1D); elsif EL2Enabled() && HCR_EL2.E2H == '0' && CPTR_EL2.TSM == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif EL2Enabled() && HCR_EL2.E2H == '1' && CPTR_EL2.SMEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HaveEL(EL3) && CPTR_EL3.ESM == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x1D); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then NVMem[0x1F0] = X[t]; else SMCR_EL1 = X[t]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.ESM == '0' then UNDEFINED; elsif HCR_EL2.E2H == '0' && CPTR_EL2.TSM == '1' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HCR_EL2.E2H == '1' && CPTR_EL2.SMEN == 'x0' then AArch64.SystemAccessTrap(EL2, 0x1D); elsif HaveEL(EL3) && CPTR_EL3.ESM == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x1D); elsif HCR_EL2.E2H == '1' then SMCR_EL2 = X[t]; else SMCR_EL1 = X[t]; elsif PSTATE.EL == EL3 then if CPTR_EL3.ESM == '0' then AArch64.SystemAccessTrap(EL3, 0x1D); else SMCR_EL1 = X[t];


3020/09/2021 1412:5337; 092b4e1bbfbb45a293b198f9330c5f529ead2b0fd4a233ffbdfb36e47856c443a7ce9a85f5e501ca

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