The TRCIMSPEC<n> characteristics are:
These registers might return information that is specific to an implementation, or enable features specific to an implementation to be programmed. The product Technical Reference Manual describes these registers.
External register TRCIMSPEC<n> bits [31:0] are architecturally mapped to AArch64 System register TRCIMSPEC<n>[31:0].
This register is present only when the trace unit implements this OPTIONAL register and FEAT_ETE is implemented. Otherwise, direct accesses to TRCIMSPEC<n> are RES0.
TRCIMSPEC<n> is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED |
IMPLEMENTATION DEFINED.
This field reads as an IMPLEMENTATION DEFINED value and writes to this field have IMPLEMENTATION DEFINED behavior.
Component | Offset | Instance |
---|---|---|
ETE | 0x1C0 + (4 * n) | TRCIMSPEC<n> |
This interface is accessible as follows:
30/09/2021 14:53; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f
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