The EDACR characteristics are:
Allows implementations to support IMPLEMENTATION DEFINED controls.
It is IMPLEMENTATION DEFINED whether EDACR is implemented in the Core power domain or in the Debug power domain.
If FEAT_DoPD is implemented, this register is implemented in the Core power domain.
If FEAT_DoPD is not implemented, the power domain that this register is implemented in is IMPLEMENTATION DEFINED.
Changing this register from its reset value causes IMPLEMENTATION DEFINED behavior, including possible deviation from the architecturally-defined behavior.
If the EDACR contains any control bits that must be preserved over power down, then these bits must be accessible by the external debug interface when the OS Lock is locked, OSLSR_EL1.OSLK == 1, and when the Core is powered off.
EDACR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED |
IMPLEMENTATION DEFINED.
The following resets apply:
If the register is implemented in the Core power domain:
On a Cold reset, this field resets to an architecturally UNKNOWN value.
On an External debug reset, the value of this field is unchanged.
On a Warm reset, the value of this field is unchanged.
If the register is implemented in the External debug power domain:
On a Cold reset, the value of this field is unchanged.
On an External debug reset, this field resets to an architecturally UNKNOWN value.
On a Warm reset, the value of this field is unchanged.
Component | Offset | Instance |
---|---|---|
Debug | 0x094 | EDACR |
This interface is accessible as follows:
30/09/2021 14:53; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f
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