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The TRBIDR_EL1 characteristics are:
Describes constraints on using the Trace Buffer Unit to software, including whether the Trace Buffer Unit can be programmed at the current Exception level.
This register is present only when FEAT_TRBE is implemented. Otherwise, direct accesses to TRBIDR_EL1 are UNDEFINED.
TRBIDR_EL1 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | EA | RES0 | F | P | Align |
Reserved, RES0.
External Abort handling. Describes how the PE manages External aborts on writes made by the Trace Buffer Unit to the trace buffer.
EA | Meaning |
---|---|
0b0000 | Not described. |
0b0001 | The PE ignores External aborts on writes made by the Trace Buffer Unit. |
0b0010 | The External abort generates an SError interrupt at the PE. |
All other values are reserved.
From Armv9.3, the value 0b0000 is not permitted.
Access to this field is RO.
Reserved, RES0.
Reserved, RES0.
Flag updates.Updates. DescribesDefines howwhether the address translationstranslation performed by the Trace Buffer Unit managemanages the Access flagFlag and dirty state. Defined values are:
F | Meaning |
---|---|
0b0 | Hardware |
0b1 | Hardware |
If hardware management of the Access flag is disabled for a stage of translation, an access to a Page or Block with the Access flag bit not set in the descriptor will generate an Access Flag fault.
If hardware management of the dirty state is disabled for a stage of translation, an access to a Page or Block will ignore the Dirty Bit Modifier in the descriptor and might generate a Permission fault, depending on the values of the access permission bits in the descriptor.
From Armv9.3, the value 0 is not permitted.
Access to this field is RO.
Programming not allowed. When read at EL3, this field reads as zero. Otherwise, indicates that the trace buffer is owned by a higher Exception level or another Security state. Defined values are:
P | Meaning |
---|---|
0b0 | Programming is allowed. |
0b1 | Programming not allowed. |
The value read from this field depends on the current Exception level and the Effective values of MDCR_EL3.NSTB, MDCR_EL3.NSTBE, and MDCR_EL2.E2TB:
Defines the minimum alignment constraint for writes to TRBPTR_EL1 and TRBTRG_EL1. Defined values are:
Align | Meaning |
---|---|
0b0000 | Byte. |
0b0001 | Halfword. |
0b0010 | Word. |
0b0011 | Doubleword. |
0b0100 | 16 bytes. |
0b0101 | 32 bytes. |
0b0110 | 64 bytes. |
0b0111 | 128 bytes. |
0b1000 | 256 bytes. |
0b1001 | 512 bytes. |
0b1010 | 1KB. |
0b1011 | 2KB. |
All other values are reserved.
Access to this field is RO.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1001 | 0b1011 | 0b111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.TRBIDR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return TRBIDR_EL1; elsif PSTATE.EL == EL2 then return TRBIDR_EL1; elsif PSTATE.EL == EL3 then return TRBIDR_EL1;
3020/09/2021 1412:5337; 092b4e1bbfbb45a293b198f9330c5f529ead2b0fd4a233ffbdfb36e47856c443a7ce9a85f5e501ca
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