The CNTCR characteristics are:
Enables the counter, controls the counter frequency setting, and controls counter behavior during debug.
The power domain of CNTCR is IMPLEMENTATION DEFINED.
For more information, see 'Power and reset domains for the system level implementation of the Generic Timer'.
CNTCR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | FCREQ | RES0 | SCEN | HDBG | EN |
Reserved, RES0.
Frequency change request. Indicates the number of the entry in the Frequency modes table to select.
Selecting an unimplemented entry, or an entry that contains 0, has no effect on the counter.
The maximum number of entries in the Frequency modes table is IMPLEMENTATION DEFINED up to a maximum of 1004 entries, see 'The Frequency modes table'. An implementation is only required to implement an FCREQ field that can hold values from 0 to the highest supported Frequency modes table entry. Any unrequired most-significant bits of FCREQ can be implemented as RES0.
The reset behavior of this field is:
Reserved, RES0.
Scale Enable.
SCEN | Meaning |
---|---|
0b0 |
Scaling is not enabled. The counter value is incremented by 0x1.0000000 for each counter tick. |
0b1 |
Scaling is enabled. The counter is incremented by CNTSCR.ScaleVal for each counter tick. |
The SCEN bit can only be changed when the counter is disabled, when CNTCR.EN == 0.
If the value of CNTCR.SCEN changes when CNTCR.EN == 1 then:
When the CNTCV register in the CNTControlBase frame of the memory mapped counter module is written to, the accumulated fraction information is reset to zero.
The reset behavior of this field is:
Reserved, RES0.
Halt-on-debug. Controls whether a Halt-on-debug signal halts the system counter:
HDBG | Meaning |
---|---|
0b0 |
System counter ignores Halt-on-debug. |
0b1 |
Asserted Halt-on-debug signal halts system counter update. |
The reset behavior of this field is:
Enables the counter:
EN | Meaning |
---|---|
0b0 |
System counter disabled. |
0b1 |
System counter enabled. |
The reset behavior of this field is:
In a system that supports Secure and Non-secure memory maps the CNTControlBase frame, that includes this register, is implemented only in the Secure memory map.
Component | Frame | Offset | Instance |
---|---|---|---|
Timer | CNTControlBase | 0x000 | CNTCR |
Accesses on this interface are RW.
30/09/2021 14:53; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f
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