The PMPIDR3 characteristics are:
Provides information to identify a Performance Monitor component.
For more information, see 'About the Peripheral identification scheme'.
Implementation of this register is OPTIONAL.
If FEAT_DoPD is implemented, this register is in the Core power domain. If FEAT_DoPD is not implemented, this register is in the Debug power domain.
This register is required for CoreSight compliance.
PMPIDR3 is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | REVAND | CMOD |
Reserved, RES0.
Part minor revision. Parts using PMPIDR2.REVISION as an extension to the Part number must use this field as a major revision number.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Customer modified. Indicates someone other than the Designer has modified the component.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Component | Offset | Instance |
---|---|---|
PMU | 0xFEC | PMPIDR3 |
This interface is accessible as follows:
20/09/2021 12:37; d4a233ffbdfb36e47856c443a7ce9a85f5e501ca
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