The TPIDRPRW characteristics are:
Provides a location where software executing at EL1 or higher can store thread identifying information that is not visible to software executing at EL0, for OS management purposes.
The PE makes no use of this register.
AArch32 System register TPIDRPRW bits [31:0] are architecturally mapped to AArch64 System register TPIDR_EL1[31:0].
This register is present only when AArch32 is supported. Otherwise, direct accesses to TPIDRPRW are UNDEFINED.
The PE never updates this register.
TPIDRPRW is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Thread ID |
Thread ID. Thread identifying information stored by software running at this Exception level.
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b1101 | 0b0000 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T13 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T13 == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) then return TPIDRPRW_NS; else return TPIDRPRW; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && ELUsingAArch32(EL3) then return TPIDRPRW_NS; else return TPIDRPRW; elsif PSTATE.EL == EL3 then if SCR.NS == '0' then return TPIDRPRW_S; else return TPIDRPRW_NS;
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b1101 | 0b0000 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T13 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T13 == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) then TPIDRPRW_NS = R[t]; else TPIDRPRW = R[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && ELUsingAArch32(EL3) then TPIDRPRW_NS = R[t]; else TPIDRPRW = R[t]; elsif PSTATE.EL == EL3 then if SCR.NS == '0' then TPIDRPRW_S = R[t]; else TPIDRPRW_NS = R[t];
30/09/2021 14:53; 092b4e1bbfbb45a293b198f9330c5f529ead2b0f
Copyright © 2010-2021 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.