Introduction

This is the 2022-03 release of the AArch32 ISA XML for Arm A-profile architecture.

The Proprietary Notice gives details of the terms and conditions under which this package is provided.

If you have comments on the content of this package, please send them by e-mail to support@arm.com. Give:

• The title, "AArch32 ISA XML for Arm A-profile architecture.".
• The version, "2022-03".
• A concise explanation of your comments.

Contents

Product Status

This release covers multiple versions of the architecture. The content relating to different versions is given different quality ratings.

The information relating to all Armv9-A features (including FEAT_RME and FEAT_SME) and the Armv8-A features, except for Optional 64-bit external interface to the Performance Monitors, is at Beta quality. Beta quality means that all major features of the specification are described, some details might be missing.

The information relating to the Optional 64-bit external interface to the Performance Monitors is at Alpha quality. Alpha quality means that most major features of the specification are described in the manual, some features and details might be missing.

Release notes

Change history

• In the operation for all encodings for DSB instruction, the check for options with value '0x00' are removed.
• The comment for TSB CSYNC now references the correct instruction.
• CONSTRAINT UNPREDICTABLE checks moved to decode stage of UBFX, SBFX, BFC and BFI instructions.
• The dependency of CMPP on FEAT_MTE is added. The dependency of SB on FEAT_SB is added.

Many simple clarifications and corrections are also present, but are too small to be listed here.

Known issues

All issues identified in the below list will be fixed in a future release.

• The execution Pseudocode for the AArch32 LDC and STC instructions do not show possible traps to Hyp mode.
• There is a mismatch between the encoding for VMOVL and some other instructions and the conditions defined for the groups they appear in. The encoding is correct. The group conditions for affected instructions will be clarified.
• The behavior for unallocated encodings will be clarified.
• Illegal Exception return behavior will be aligned with illegal Debug Exit.
• IsSecure() is replaced with IsCurrentSecurityState(SS_Secure).
• The common pseudocode in the A32/T32 XML does not show the v9A architecture and SVE. For a more complete version see the A64 XML. Future releases will provide a consistent view.
• In the browsable XML, hyperlinking with some Pseudocode functions do not link correctly.
• Some architectural features have limited or no descriptions in Pseudocode and are not fully covered by the functional testing. Affected features are listed below:
  • Address translation, Instruction Cache, Data Cache System instructions.
  • Ordering of memory accesses.
  • Self-hosted and halting debug.
  • Self-hosted trace and external trace.
  • RAS architecture.
  • Statistical Profiling Extension.
  • Performance Monitors Extension.
  • Activity Monitors Extension.
  • Generic Timers.
  • Generic Interrupt Controller.
  • Multi-processing.