(old) htmldiff from-(new)

Top-level encodings for A32

313029282726252423222120191817161514131211109876543210
condop0op1
Decode fields Instruction details
condop0op1
!= 1111 00x Data-processing and miscellaneous instructions
!= 1111 010 Load/Store Word, Unsigned Byte (immediate, literal)
!= 1111 011 0 Load/Store Word, Unsigned Byte (register)
!= 1111 011 1 Media instructions
10x Branch, branch with link, and block data transfer
11x System register access, Advanced SIMD, floating-point, and Supervisor call
1111 0xx Unconditional instructions

Data-processing and miscellaneous instructions

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
!= 111100op0op1op2op3op4
Decode fields Instruction details
op0op1op2op3op4
0 1 != 00 1 Extra load/store
0 0xxxx 1 00 1 Multiply and Accumulate
0 1xxxx 1 00 1 Synchronization primitives and Load-Acquire/Store-Release
0 10xx0 0 Miscellaneous
0 10xx0 1 0 Halfword Multiply and Accumulate
0 != 10xx0 0 Data-processing register (immediate shift)
0 != 10xx0 0 1 Data-processing register (register shift)
1 Data-processing immediate

Extra load/store

These instructions are under Data-processing and miscellaneous instructions.

313029282726252423222120191817161514131211109876543210
!= 1111000op01!= 001
Decode fields Instruction details
op0
0 Load/Store Dual, Half, Signed Byte (register)
1 Load/Store Dual, Half, Signed Byte (immediate, literal)

Load/Store Dual, Half, Signed Byte (register)

These instructions are under Extra load/store.

313029282726252423222120191817161514131211109876543210
!= 1111000PU0Wo1RnRt(0)(0)(0)(0)1!= 001Rm
condop2

The following constraints also apply to this encoding: cond != 1111 && op2 != 00 && cond != 1111 && op2 != 00

Decode fields Instruction Details
PWo1op2
00001STRH (register)post-indexed
00010LDRD (register)post-indexed
00011STRD (register)post-indexed
00101LDRH (register)post-indexed
00110LDRSB (register)post-indexed
00111LDRSH (register)post-indexed
01001STRHT
01010UNALLOCATED
01011UNALLOCATED
01101LDRHT
01110LDRSBT
01111LDRSHT
1001STRH (register)pre-indexed
1010LDRD (register)pre-indexed
1011STRD (register)pre-indexed
1101LDRH (register)pre-indexed
1110LDRSB (register)pre-indexed
1111LDRSH (register)pre-indexed

Load/Store Dual, Half, Signed Byte (immediate, literal)

These instructions are under Extra load/store.

313029282726252423222120191817161514131211109876543210
!= 1111000PU1Wo1RnRtimm4H1!= 001imm4L
condop2

The following constraints also apply to this encoding: cond != 1111 && op2 != 00 && cond != 1111 && op2 != 00

Decode fields Instruction Details
P:Wo1Rnop2
0111110LDRD (literal)
!= 011111101LDRH (literal)
!= 011111110LDRSB (literal)
!= 011111111LDRSH (literal)
000!= 111110LDRD (immediate)post-indexed
00001STRH (immediate)post-indexed
00011STRD (immediate)post-indexed
001!= 111101LDRH (immediate)post-indexed
001!= 111110LDRSB (immediate)post-indexed
001!= 111111LDRSH (immediate)post-indexed
010!= 111110UNALLOCATED
01001STRHT
01011UNALLOCATED
01101LDRHT
01110LDRSBT
01111LDRSHT
100!= 111110LDRD (immediate)offset
10001STRH (immediate)offset
10011STRD (immediate)offset
101!= 111101LDRH (immediate)offset
101!= 111110LDRSB (immediate)offset
101!= 111111LDRSH (immediate)offset
110!= 111110LDRD (immediate)pre-indexed
11001STRH (immediate)pre-indexed
11011STRD (immediate)pre-indexed
111!= 111101LDRH (immediate)pre-indexed
111!= 111110LDRSB (immediate)pre-indexed
111!= 111111LDRSH (immediate)pre-indexed

Multiply and Accumulate

These instructions are under Data-processing and miscellaneous instructions.

313029282726252423222120191817161514131211109876543210
!= 11110000opcSRdHiRdLoRm1001Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opcS
000MUL, MULS
001MLA, MLAS
0100UMAAL
0101UNALLOCATED
0110MLS
0111UNALLOCATED
100UMULL, UMULLS
101UMLAL, UMLALS
110SMULL, SMULLS
111SMLAL, SMLALS

Synchronization primitives and Load-Acquire/Store-Release

These instructions are under Data-processing and miscellaneous instructions.

313029282726252423222120191817161514131211109876543210
!= 11110001op0111001
Decode fields Instruction details
op0
0 UNALLOCATED
1 Load/Store Exclusive and Load-Acquire/Store-Release

Load/Store Exclusive and Load-Acquire/Store-Release

These instructions are under Synchronization primitives and Load-Acquire/Store-Release.

313029282726252423222120191817161514131211109876543210
!= 111100011sizeLRnxRd(1)(1)exord1001xRt
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
sizeLexord
00000STL
00001UNALLOCATED
00010STLEX
00011STREX
00100LDA
00101UNALLOCATED
00110LDAEX
00111LDREX
0100UNALLOCATED
01010STLEXD
01011STREXD
0110UNALLOCATED
01110LDAEXD
01111LDREXD
10000STLB
10001UNALLOCATED
10010STLEXB
10011STREXB
10100LDAB
10101UNALLOCATED
10110LDAEXB
10111LDREXB
11000STLH
11001UNALLOCATED
11010STLEXH
11011STREXH
11100LDAH
11101UNALLOCATED
11110LDAEXH
11111LDREXH

Miscellaneous

These instructions are under Data-processing and miscellaneous instructions.

313029282726252423222120191817161514131211109876543210
!= 111100010op000op1
Decode fields Instruction details
op0op1
00 001 UNALLOCATED
00 010 UNALLOCATED
00 011 UNALLOCATED
00 110 UNALLOCATED
01 001 BX
01 010 BXJ
01 011 BLX (register)
01 110 UNALLOCATED
10 001 UNALLOCATED
10 010 UNALLOCATED
10 011 UNALLOCATED
10 110 UNALLOCATED
11 001 CLZ
11 010 UNALLOCATED
11 011 UNALLOCATED
11 110 ERET
111 Exception Generation
000 Move special register (register)
100 Cyclic Redundancy Check
101 Integer Saturating Arithmetic

Exception Generation

These instructions are under Miscellaneous.

313029282726252423222120191817161514131211109876543210
!= 111100010opc0imm120111imm4
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc
00HLT
01BKPT
10HVC
11SMC

Move special register (register)

These instructions are under Miscellaneous.

313029282726252423222120191817161514131211109876543210
!= 111100010opc0maskRd(0)(0)Bm0000Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opcB
x00MRS
x01MRS (Banked register)
x10MSR (register)
x11MSR (Banked register)

Cyclic Redundancy Check

These instructions are under Miscellaneous.

313029282726252423222120191817161514131211109876543210
!= 111100010sz0RnRd(0)(0)C(0)0100Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
szC
000CRC32CRC32B
001CRC32CCRC32CB
010CRC32CRC32H
011CRC32CCRC32CH
100CRC32CRC32W
101CRC32CCRC32CW
11CONSTRAINED UNPREDICTABLE

The behavior of the CONSTRAINED UNPREDICTABLE encodings in this table is described in CONSTRAINED UNPREDICTABLE behavior for A32 and T32 instruction encodings


Integer Saturating Arithmetic

These instructions are under Miscellaneous.

313029282726252423222120191817161514131211109876543210
!= 111100010opc0RnRd(0)(0)(0)(0)0101Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc
00QADD
01QSUB
10QDADD
11QDSUB

Halfword Multiply and Accumulate

These instructions are under Data-processing and miscellaneous instructions.

313029282726252423222120191817161514131211109876543210
!= 111100010opc0RdRaRm1MN0Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opcMN
00SMLABB, SMLABT, SMLATB, SMLATT
0100SMLAWB, SMLAWTSMLAWB
0101SMULWB, SMULWTSMULWB
0110SMLAWB, SMLAWTSMLAWT
0111SMULWB, SMULWTSMULWT
10SMLALBB, SMLALBT, SMLALTB, SMLALTT
11SMULBB, SMULBT, SMULTB, SMULTT

Data-processing register (immediate shift)

These instructions are under Data-processing and miscellaneous instructions.

313029282726252423222120191817161514131211109876543210
!= 1111000op0op10

The following constraints also apply to this encoding: op0:op1 != 100

Decode fields Instruction details
op0op1
0x Integer Data Processing (three register, immediate shift)
10 1 Integer Test and Compare (two register, immediate shift)
11 Logical Arithmetic (three register, immediate shift)

Integer Data Processing (three register, immediate shift)

These instructions are under Data-processing register (immediate shift).

313029282726252423222120191817161514131211109876543210
!= 11110000opcSRnRdimm5stype0Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opcSRnimm5:stype
000!= 0000011AND, ANDS (register)shift or rotate by value
0000000011AND, ANDS (register)rotate right with extend
001!= 0000011EOR, EORS (register)shift or rotate by value
0010000011EOR, EORS (register)rotate right with extend
0100!= 1101!= 0000011SUB, SUBS (register)SUB, shift or rotate by value
0100!= 11010000011SUB, SUBS (register)SUB, rotate right with extend
01001101!= 0000011SUB, SUBS (SP minus register)SUB, shift or rotate by value
010011010000011SUB, SUBS (SP minus register)SUB, rotate right with extend
0101!= 1101!= 0000011SUB, SUBS (register)SUBS, shift or rotate by value
0101!= 11010000011SUB, SUBS (register)SUBS, rotate right with extend
01011101!= 0000011SUB, SUBS (SP minus register)SUBS, shift or rotate by value
010111010000011SUB, SUBS (SP minus register)SUBS, rotate right with extend
011!= 0000011RSB, RSBS (register)shift or rotate by value
0110000011RSB, RSBS (register)rotate right with extend
1000!= 1101!= 0000011ADD, ADDS (register)ADD, shift or rotate by value
1000!= 11010000011ADD, ADDS (register)ADD, rotate right with extend
10001101!= 0000011ADD, ADDS (SP plus register)ADD, shift or rotate by value
100011010000011ADD, ADDS (SP plus register)ADD, rotate right with extend
1001!= 1101!= 0000011ADD, ADDS (register)ADDS, shift or rotate by value
1001!= 11010000011ADD, ADDS (register)ADDS, rotate right with extend
10011101!= 0000011ADD, ADDS (SP plus register)ADDS, shift or rotate by value
100111010000011ADD, ADDS (SP plus register)ADDS, rotate right with extend
101!= 0000011ADC, ADCS (register)shift or rotate by value
1010000011ADC, ADCS (register)rotate right with extend
110!= 0000011SBC, SBCS (register)shift or rotate by value
1100000011SBC, SBCS (register)rotate right with extend
111!= 0000011RSC, RSCS (register)shift or rotate by value
1110000011RSC, RSCS (register)rotate right with extend

Integer Test and Compare (two register, immediate shift)

These instructions are under Data-processing register (immediate shift).

313029282726252423222120191817161514131211109876543210
!= 111100010opc1Rn(0)(0)(0)(0)imm5stype0Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opcimm5:stype
00!= 0000011TST (register)shift or rotate by value
000000011TST (register)rotate right with extend
01!= 0000011TEQ (register)shift or rotate by value
010000011TEQ (register)rotate right with extend
10!= 0000011CMP (register)shift or rotate by value
100000011CMP (register)rotate right with extend
11!= 0000011CMN (register)shift or rotate by value
110000011CMN (register)rotate right with extend

Logical Arithmetic (three register, immediate shift)

These instructions are under Data-processing register (immediate shift).

313029282726252423222120191817161514131211109876543210
!= 111100011opcSRnRdimm5stype0Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opcimm5:stype
00!= 0000011ORR, ORRS (register)shift or rotate by value
000000011ORR, ORRS (register)rotate right with extend
01!= 0000011MOV, MOVS (register)shift or rotate by value
010000011MOV, MOVS (register)rotate right with extend
10!= 0000011BIC, BICS (register)shift or rotate by value
100000011BIC, BICS (register)rotate right with extend
11!= 0000011MVN, MVNS (register)shift or rotate by value
110000011MVN, MVNS (register)rotate right with extend

Data-processing register (register shift)

These instructions are under Data-processing and miscellaneous instructions.

313029282726252423222120191817161514131211109876543210
!= 1111000op0op101

The following constraints also apply to this encoding: op0:op1 != 100

Decode fields Instruction details
op0op1
0x Integer Data Processing (three register, register shift)
10 1 Integer Test and Compare (two register, register shift)
11 Logical Arithmetic (three register, register shift)

Integer Data Processing (three register, register shift)

These instructions are under Data-processing register (register shift).

313029282726252423222120191817161514131211109876543210
!= 11110000opcSRnRdRs0stype1Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc
000AND, ANDS (register-shifted register)
001EOR, EORS (register-shifted register)
010SUB, SUBS (register-shifted register)
011RSB, RSBS (register-shifted register)
100ADD, ADDS (register-shifted register)
101ADC, ADCS (register-shifted register)
110SBC, SBCS (register-shifted register)
111RSC, RSCS (register-shifted register)

Integer Test and Compare (two register, register shift)

These instructions are under Data-processing register (register shift).

313029282726252423222120191817161514131211109876543210
!= 111100010opc1Rn(0)(0)(0)(0)Rs0stype1Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc
00TST (register-shifted register)
01TEQ (register-shifted register)
10CMP (register-shifted register)
11CMN (register-shifted register)

Logical Arithmetic (three register, register shift)

These instructions are under Data-processing register (register shift).

313029282726252423222120191817161514131211109876543210
!= 111100011opcSRnRdRs0stype1Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc
00ORR, ORRS (register-shifted register)
01MOV, MOVS (register-shifted register)
10BIC, BICS (register-shifted register)
11MVN, MVNS (register-shifted register)

Data-processing immediate

These instructions are under Data-processing and miscellaneous instructions.

313029282726252423222120191817161514131211109876543210
!= 1111001op0op1
Decode fields Instruction details
op0op1
0x Integer Data Processing (two register and immediate)
10 00 Move Halfword (immediate)
10 10 Move Special Register and Hints (immediate)
10 x1 Integer Test and Compare (one register and immediate)
11 Logical Arithmetic (two register and immediate)

Integer Data Processing (two register and immediate)

These instructions are under Data-processing immediate.

313029282726252423222120191817161514131211109876543210
!= 11110010opcSRnRdimm12
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opcSRn
000AND, ANDS (immediate)
001EOR, EORS (immediate)
0100!= 11x1SUB, SUBS (immediate)SUB
01001101SUB, SUBS (SP minus immediate)SUB
01001111ADRA2
0101!= 1101SUB, SUBS (immediate)SUBS
01011101SUB, SUBS (SP minus immediate)SUBS
011RSB, RSBS (immediate)
1000!= 11x1ADD, ADDS (immediate)ADD
10001101ADD, ADDS (SP plus immediate)ADD
10001111ADRA1
1001!= 1101ADD, ADDS (immediate)ADDS
10011101ADD, ADDS (SP plus immediate)ADDS
101ADC, ADCS (immediate)
110SBC, SBCS (immediate)
111RSC, RSCS (immediate)

Move Halfword (immediate)

These instructions are under Data-processing immediate.

313029282726252423222120191817161514131211109876543210
!= 111100110H00imm4Rdimm12
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
H
0MOV, MOVS (immediate)
1MOVT

Move Special Register and Hints (immediate)

These instructions are under Data-processing immediate.

313029282726252423222120191817161514131211109876543210
!= 111100110R10imm4(1)(1)(1)(1)imm12
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details Feature
R:imm4imm12
!= 00000MSR (immediate)-
00000xxxx00000000NOP-
00000xxxx00000001YIELD-
00000xxxx00000010WFE-
00000xxxx00000011WFI-
00000xxxx00000100SEV-
00000xxxx00000101SEVL-
00000xxxx0000011xReserved hint, behaves as NOP-
00000xxxx00001xxxReserved hint, behaves as NOP-
00000xxxx00010000ESBFEAT_RAS
00000xxxx00010001Reserved hint, behaves as NOP-
00000xxxx00010010TSB CSYNCFEAT_TRF
00000xxxx00010011Reserved hint, behaves as NOP-
00000xxxx00010100CSDB-
00000xxxx00010101Reserved hint, behaves as NOP-
00000xxxx0001011xReserved hint, behaves as NOP-
00000xxxx00011xxxReserved hint, behaves as NOP-
00000xxxx001xxxxxReserved hint, behaves as NOP-
00000xxxx01xxxxxxReserved hint, behaves as NOP-
00000xxxx10xxxxxxReserved hint, behaves as NOP-
00000xxxx110xxxxxReserved hint, behaves as NOP-
00000xxxx1110xxxxReserved hint, behaves as NOP-
00000xxxx1111xxxxDBG-

Integer Test and Compare (one register and immediate)

These instructions are under Data-processing immediate.

313029282726252423222120191817161514131211109876543210
!= 111100110opc1Rn(0)(0)(0)(0)imm12
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc
00TST (immediate)
01TEQ (immediate)
10CMP (immediate)
11CMN (immediate)

Logical Arithmetic (two register and immediate)

These instructions are under Data-processing immediate.

313029282726252423222120191817161514131211109876543210
!= 111100111opcSRnRdimm12
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc
00ORR, ORRS (immediate)
01MOV, MOVS (immediate)
10BIC, BICS (immediate)
11MVN, MVNS (immediate)

Load/Store Word, Unsigned Byte (immediate, literal)

313029282726252423222120191817161514131211109876543210
!= 1111010PUo2Wo1RnRtimm12
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111


Load/Store Word, Unsigned Byte (register)

313029282726252423222120191817161514131211109876543210
!= 1111011PUo2Wo1RnRtimm5stype0Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111


Media instructions

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
!= 1111011op0op11
Decode fields Instruction details
op0op1
00xxx Parallel Arithmetic
01000 101 SEL
01000 001 UNALLOCATED
01000 xx0 PKHBT, PKHTB
01001 x01 UNALLOCATED
01001 xx0 UNALLOCATED
0110x x01 UNALLOCATED
0110x xx0 UNALLOCATED
01x10 001 Saturate 16-bit
01x10 101 UNALLOCATED
01x11 x01 Reverse Bit/Byte
01x1x xx0 Saturate 32-bit
01xxx 111 UNALLOCATED
01xxx 011 Extend and Add
10xxx Signed multiply, Divide
11000 000 Unsigned Sum of Absolute Differences
11000 100 UNALLOCATED
11001 x00 UNALLOCATED
1101x x00 UNALLOCATED
110xx 111 UNALLOCATED
1110x 111 UNALLOCATED
1110x x00 Bitfield Insert
11110 111 UNALLOCATED
11111 111 Permanently UNDEFINED
1111x x00 UNALLOCATED
11x0x x10 UNALLOCATED
11x1x x10 Bitfield Extract
11xxx 011 UNALLOCATED
11xxx x01 UNALLOCATED

Parallel Arithmetic

These instructions are under Media instructions.

313029282726252423222120191817161514131211109876543210
!= 111101100op1RnRd(1)(1)(1)(1)Bop21Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
op1Bop2
000UNALLOCATED
001000SADD16
001001SASX
001010SSAX
001011SSUB16
001100SADD8
001101UNALLOCATED
001110UNALLOCATED
001111SSUB8
010000QADD16
010001QASX
010010QSAX
010011QSUB16
010100QADD8
010101UNALLOCATED
010110UNALLOCATED
010111QSUB8
011000SHADD16
011001SHASX
011010SHSAX
011011SHSUB16
011100SHADD8
011101UNALLOCATED
011110UNALLOCATED
011111SHSUB8
100UNALLOCATED
101000UADD16
101001UASX
101010USAX
101011USUB16
101100UADD8
101101UNALLOCATED
101110UNALLOCATED
101111USUB8
110000UQADD16
110001UQASX
110010UQSAX
110011UQSUB16
110100UQADD8
110101UNALLOCATED
110110UNALLOCATED
110111UQSUB8
111000UHADD16
111001UHASX
111010UHSAX
111011UHSUB16
111100UHADD8
111101UNALLOCATED
111110UNALLOCATED
111111UHSUB8

Saturate 16-bit

These instructions are under Media instructions.

313029282726252423222120191817161514131211109876543210
!= 111101101U10sat_immRd(1)(1)(1)(1)0011Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
U
0SSAT16
1USAT16

Reverse Bit/Byte

These instructions are under Media instructions.

313029282726252423222120191817161514131211109876543210
!= 111101101o111(1)(1)(1)(1)Rd(1)(1)(1)(1)o2011Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
o1o2
00REV
01REV16
10RBIT
11REVSH

Saturate 32-bit

These instructions are under Media instructions.

313029282726252423222120191817161514131211109876543210
!= 111101101U1sat_immRdimm5sh01Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
U
0SSAT
1USAT

Extend and Add

These instructions are under Media instructions.

313029282726252423222120191817161514131211109876543210
!= 111101101UopRnRdrotate(0)(0)0111Rm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
UopRn
000!= 1111SXTAB16
0001111SXTB16
010!= 1111SXTAB
0101111SXTB
011!= 1111SXTAH
0111111SXTH
100!= 1111UXTAB16
1001111UXTB16
110!= 1111UXTAB
1101111UXTB
111!= 1111UXTAH
1111111UXTH

Signed multiply, Divide

These instructions are under Media instructions.

313029282726252423222120191817161514131211109876543210
!= 111101110op1RdRaRmop21Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
op1Raop2
000!= 1111000SMLAD, SMLADXSMLAD
000!= 1111001SMLAD, SMLADXSMLADX
000!= 1111010SMLSD, SMLSDXSMLSD
000!= 1111011SMLSD, SMLSDXSMLSDX
0001xxUNALLOCATED
0001111000SMUAD, SMUADXSMUAD
0001111001SMUAD, SMUADXSMUADX
0001111010SMUSD, SMUSDXSMUSD
0001111011SMUSD, SMUSDXSMUSDX
001000SDIV
001!= 000UNALLOCATED
010UNALLOCATED
011000UDIV
011!= 000UNALLOCATED
100000SMLALD, SMLALDXSMLALD
100001SMLALD, SMLALDXSMLALDX
100010SMLSLD, SMLSLDXSMLSLD
100011SMLSLD, SMLSLDXSMLSLDX
1001xxUNALLOCATED
101!= 1111000SMMLA, SMMLARSMMLA
101!= 1111001SMMLA, SMMLARSMMLAR
10101xUNALLOCATED
10110xUNALLOCATED
101110SMMLS, SMMLSRSMMLS
101111SMMLS, SMMLSRSMMLSR
1011111000SMMUL, SMMULRSMMUL
1011111001SMMUL, SMMULRSMMULR
11xUNALLOCATED

Unsigned Sum of Absolute Differences

These instructions are under Media instructions.

313029282726252423222120191817161514131211109876543210
!= 111101111000RdRaRm0001Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
Ra
!= 1111USADA8
1111USAD8

Bitfield Insert

These instructions are under Media instructions.

313029282726252423222120191817161514131211109876543210
!= 11110111110msbRdlsb001Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
Rn
!= 1111BFI
1111BFC

Permanently UNDEFINED

These instructions are under Media instructions.

313029282726252423222120191817161514131211109876543210
!= 111101111111imm121111imm4
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
cond
0xxxUNALLOCATED
10xxUNALLOCATED
110xUNALLOCATED
1110UDF

Bitfield Extract

These instructions are under Media instructions.

313029282726252423222120191817161514131211109876543210
!= 111101111U1widthm1Rdlsb101Rn
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
U
0SBFX
1UBFX

Branch, branch with link, and block data transfer

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
cond10op0
Decode fields Instruction details
condop0
1111 0 Exception Save/Restore
!= 1111 0 Load/Store Multiple
1 Branch (immediate)

Exception Save/Restore

These instructions are under Branch, branch with link, and block data transfer.

313029282726252423222120191817161514131211109876543210
1111100PUSWLRnopmode
Decode fields Instruction Details
PUSL
00UNALLOCATED
0001RFE, RFEDA, RFEDB, RFEIA, RFEIBDecrement After
0010SRS, SRSDA, SRSDB, SRSIA, SRSIBDecrement After
0101RFE, RFEDA, RFEDB, RFEIA, RFEIBIncrement After
0110SRS, SRSDA, SRSDB, SRSIA, SRSIBIncrement After
1001RFE, RFEDA, RFEDB, RFEIA, RFEIBDecrement Before
1010SRS, SRSDA, SRSDB, SRSIA, SRSIBDecrement Before
11UNALLOCATED
1101RFE, RFEDA, RFEDB, RFEIA, RFEIBIncrement Before
1110SRS, SRSDA, SRSDB, SRSIA, SRSIBIncrement Before

Load/Store Multiple

These instructions are under Branch, branch with link, and block data transfer.

313029282726252423222120191817161514131211109876543210
!= 1111100PUopWLRnregister_list
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
PUopLregister_list
0000STMDA, STMED
0001LDMDA, LDMFA
0100STM, STMIA, STMEA
0101LDM, LDMIA, LDMFD
10STM (User registers)
1000STMDB, STMFD
1001LDMDB, LDMEA
110xxxxxxxxxxxxxxxLDM (User registers)
1100STMIB, STMFA
1101LDMIB, LDMED
111xxxxxxxxxxxxxxxLDM (exception return)

Branch (immediate)

These instructions are under Branch, branch with link, and block data transfer.

313029282726252423222120191817161514131211109876543210
cond101Himm24
Decode fields Instruction Details
condH
!= 11110B
!= 11111BL, BLX (immediate)A1
1111BL, BLX (immediate)A2

System register access, Advanced SIMD, floating-point, and Supervisor call

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
cond11op0op1op2
Decode fields Instruction details
condop0op1op2
0x 0x UNALLOCATED
10 0x UNALLOCATED
11 Supervisor call
1111 != 11 1x Unconditional Advanced SIMD and floating-point instructions
!= 1111 0x 1x Advanced SIMD and System register load/store and 64-bit move
!= 1111 10 1x 1 Advanced SIMD and System register 32-bit move
!= 1111 10 10 0 Floating-point data-processing
!= 1111 10 11 0 UNALLOCATED

Supervisor call

These instructions are under System register access, Advanced SIMD, floating-point, and Supervisor call.

313029282726252423222120191817161514131211109876543210
cond1111
Decode fields Instruction details
cond
1111 UNALLOCATED
!= 1111 SVC

Unconditional Advanced SIMD and floating-point instructions

These instructions are under System register access, Advanced SIMD, floating-point, and Supervisor call.

313029282726252423222120191817161514131211109876543210
111111op0op11op2op3op4op5

The following constraints also apply to this encoding: op0<2:1> != 11

Decode fields Instruction details
op0op1op2op3op4op5
0xx 0x Advanced SIMD three registers of the same length extension
100 0 != 00 0 0 Floating-point conditional select
101 00xxxx 0 != 00 0 Floating-point minNum/maxNum
101 110000 0 != 00 1 0 Floating-point extraction and insertion
101 111xxx 0 != 00 1 0 Floating-point directed convert to integer
10x 0 00 Advanced SIMD and floating-point multiply with accumulate
10x 1 0x Advanced SIMD and floating-point dot product

Advanced SIMD three registers of the same length extension

These instructions are under Unconditional Advanced SIMD and floating-point instructions.

313029282726252423222120191817161514131211109876543210
1111110op1Dop2VnVd1op30op4NQMUVm
Decode fields Instruction Details Feature
op1op2op3op4QU
x10x0000VCADD64-bit SIMD vectorFEAT_FCMA
x10x0001UNALLOCATED-
x10x0010VCADD128-bit SIMD vectorFEAT_FCMA
x10x0011UNALLOCATED-
000x00UNALLOCATED-
000x01UNALLOCATED-
00001000UNALLOCATED-
00001001UNALLOCATED-
00001010VMMLAFEAT_AA32BF16
00001011UNALLOCATED-
00001100VDOT (vector)64-bit SIMD vectorFEAT_AA32BF16
00001101UNALLOCATED-
00001110VDOT (vector)128-bit SIMD vectorFEAT_AA32BF16
00001111UNALLOCATED-
000110UNALLOCATED-
000111UNALLOCATED-
0010001VFMAL (vector)FEAT_FHM
001001UNALLOCATED-
0010100UNALLOCATED-
00101010VSMMLAFEAT_AA32I8MM
00101011VUMMLAFEAT_AA32I8MM
00101100VSDOT (vector)64-bit SIMD vectorFEAT_DotProd
00101101VUDOT (vector)64-bit SIMD vectorFEAT_DotProd
00101110VSDOT (vector)128-bit SIMD vectorFEAT_DotProd
00101111VUDOT (vector)128-bit SIMD vectorFEAT_DotProd
0011001VFMAB, VFMAT (BFloat16, vector)FEAT_AA32BF16
001101UNALLOCATED-
001110UNALLOCATED-
001111UNALLOCATED-
0110001VFMSL (vector)FEAT_FHM
011001UNALLOCATED-
0110100UNALLOCATED-
01101010VUSMMLAFEAT_AA32I8MM
01101011UNALLOCATED-
01101100VUSDOT (vector)64-bit SIMD vectorFEAT_AA32I8MM
0110111UNALLOCATED-
01101110VUSDOT (vector)128-bit SIMD vectorFEAT_AA32I8MM
011101UNALLOCATED-
011110UNALLOCATED-
011111UNALLOCATED-
1x000VCMLAFEAT_FCMA
101101UNALLOCATED-
101110UNALLOCATED-
101111UNALLOCATED-
111101UNALLOCATED-
111110UNALLOCATED-
111111UNALLOCATED-

Floating-point conditional select

These instructions are under Unconditional Advanced SIMD and floating-point instructions.

313029282726252423222120191817161514131211109876543210
111111100DccVnVd10!= 00N0M0Vm
size

The following constraints also apply to this encoding: size != 00 && size != 00

Decode fields Instruction Details Feature
size
01VSELEQ, VSELGE, VSELGT, VSELVShalf-precision scalarFEAT_FP16
10VSELEQ, VSELGE, VSELGT, VSELVSsingle-precision scalar-
11VSELEQ, VSELGE, VSELGT, VSELVSdouble-precision scalar-

Floating-point minNum/maxNum

These instructions are under Unconditional Advanced SIMD and floating-point instructions.

313029282726252423222120191817161514131211109876543210
111111101D00VnVd10!= 00NopM0Vm
size

The following constraints also apply to this encoding: size != 00 && size != 00

Decode fields Instruction Details Feature
sizeop
010VMAXNMhalf-precision scalarFEAT_FP16
011VMINNMhalf-precision scalarFEAT_FP16
100VMAXNMsingle-precision scalar-
101VMINNMsingle-precision scalar-
110VMAXNMdouble-precision scalar-
111VMINNMdouble-precision scalar-

Floating-point extraction and insertion

These instructions are under Unconditional Advanced SIMD and floating-point instructions.

313029282726252423222120191817161514131211109876543210
111111101D110000Vd10!= 00op1M0Vm
size

The following constraints also apply to this encoding: size != 00 && size != 00

Decode fields Instruction Details Feature
sizeop
01UNALLOCATED-
100VMOVXFEAT_FP16
101VINSFEAT_FP16
11UNALLOCATED-

Floating-point directed convert to integer

These instructions are under Unconditional Advanced SIMD and floating-point instructions.

313029282726252423222120191817161514131211109876543210
111111101D111o1RMVd10!= 00op1M0Vm
size

The following constraints also apply to this encoding: size != 00 && size != 00

Decode fields Instruction Details Feature
o1RMsizeop
0!= 001UNALLOCATED-
000010VRINTA (floating-point)half-precision scalarFEAT_FP16
000100VRINTA (floating-point)single-precision scalar-
000110VRINTA (floating-point)double-precision scalar-
001010VRINTN (floating-point)half-precision scalarFEAT_FP16
001100VRINTN (floating-point)single-precision scalar-
001110VRINTN (floating-point)double-precision scalar-
010010VRINTP (floating-point)half-precision scalarFEAT_FP16
010100VRINTP (floating-point)single-precision scalar-
010110VRINTP (floating-point)double-precision scalar-
011010VRINTM (floating-point)half-precision scalarFEAT_FP16
011100VRINTM (floating-point)single-precision scalar-
011110VRINTM (floating-point)double-precision scalar-
10001VCVTA (floating-point)half-precision scalarFEAT_FP16
10010VCVTA (floating-point)single-precision scalar-
10011VCVTA (floating-point)double-precision scalar-
10101VCVTN (floating-point)half-precision scalarFEAT_FP16
10110VCVTN (floating-point)single-precision scalar-
10111VCVTN (floating-point)double-precision scalar-
11001VCVTP (floating-point)half-precision scalarFEAT_FP16
11010VCVTP (floating-point)single-precision scalar-
11011VCVTP (floating-point)double-precision scalar-
11101VCVTM (floating-point)half-precision scalarFEAT_FP16
11110VCVTM (floating-point)single-precision scalar-
11111VCVTM (floating-point)double-precision scalar-

Advanced SIMD and floating-point multiply with accumulate

These instructions are under Unconditional Advanced SIMD and floating-point instructions.

313029282726252423222120191817161514131211109876543210
11111110op1Dop2VnVd1000NQMUVm
Decode fields Instruction Details Feature
op1op2QU
00VCMLA (by element)128-bit SIMD vector of half-precision floating-pointFEAT_FCMA
0001VFMAL (by scalar)FEAT_FHM
0011VFMSL (by scalar)FEAT_FHM
0101UNALLOCATED-
0111VFMAB, VFMAT (BFloat16, by scalar)FEAT_AA32BF16
100VCMLA (by element)64-bit SIMD vector of single-precision floating-pointFEAT_FCMA
11UNALLOCATED-
110VCMLA (by element)128-bit SIMD vector of single-precision floating-pointFEAT_FCMA

Advanced SIMD and floating-point dot product

These instructions are under Unconditional Advanced SIMD and floating-point instructions.

313029282726252423222120191817161514131211109876543210
11111110op1Dop2VnVd110op4NQMUVm
Decode fields Instruction Details Feature
op1op2op4QU
0000UNALLOCATED-
000100VDOT (by element)64-bit SIMD vectorFEAT_AA32BF16
00011UNALLOCATED-
000110VDOT (by element)128-bit SIMD vectorFEAT_AA32BF16
0010UNALLOCATED-
0100UNALLOCATED-
010100VSDOT (by element)64-bit SIMD vectorFEAT_DotProd
010101VUDOT (by element)64-bit SIMD vectorFEAT_DotProd
010110VSDOT (by element)128-bit SIMD vectorFEAT_DotProd
010111VUDOT (by element)128-bit SIMD vectorFEAT_DotProd
011UNALLOCATED-
10UNALLOCATED-
100100VUSDOT (by element)64-bit SIMD vectorFEAT_AA32I8MM
100101VSUDOT (by element)64-bit SIMD vectorFEAT_AA32I8MM
100110VUSDOT (by element)128-bit SIMD vectorFEAT_AA32I8MM
100111VSUDOT (by element)128-bit SIMD vectorFEAT_AA32I8MM
1011UNALLOCATED-
11x1UNALLOCATED-

Advanced SIMD and System register load/store and 64-bit move

These instructions are under System register access, Advanced SIMD, floating-point, and Supervisor call.

313029282726252423222120191817161514131211109876543210
!= 1111110op01op1
Decode fields Instruction details
op0op1
00x0 0x Advanced SIMD and floating-point 64-bit move
00x0 11 System register 64-bit move
!= 00x0 0x Advanced SIMD and floating-point load/store
!= 00x0 11 System register load/store
10 UNALLOCATED

Advanced SIMD and floating-point 64-bit move

These instructions are under Advanced SIMD and System register load/store and 64-bit move.

313029282726252423222120191817161514131211109876543210
!= 111111000D0opRt2Rt10sizeopc2Mo3Vm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
Dopsizeopc2o3
0UNALLOCATED
10UNALLOCATED
10x001UNALLOCATED
101UNALLOCATED
1010001VMOV (between two general-purpose registers and two single-precision registers)from general-purpose registers
1011001VMOV (between two general-purpose registers and a doubleword floating-point register)from general-purpose registers
11xUNALLOCATED
1110001VMOV (between two general-purpose registers and two single-precision registers)to general-purpose registers
1111001VMOV (between two general-purpose registers and a doubleword floating-point register)to general-purpose registers

System register 64-bit move

These instructions are under Advanced SIMD and System register load/store and 64-bit move.

313029282726252423222120191817161514131211109876543210
!= 111111000D0LRt2Rt111cp15opc1CRm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
DL
0UNALLOCATED
10MCRR
11MRRC

Advanced SIMD and floating-point load/store

These instructions are under Advanced SIMD and System register load/store and 64-bit move.

313029282726252423222120191817161514131211109876543210
!= 1111110PUDWLRnVd10sizeimm8
cond

The following constraints also apply to this encoding: cond != 1111 && P:U:D:W != 00x0 && cond != 1111

Decode fields Instruction Details Feature
PUWLRnsizeimm8
001UNALLOCATED-
010xUNALLOCATED-
01010VSTM, VSTMDB, VSTMIAsingle-precision scalar-
01011xxxxxxx0VSTM, VSTMDB, VSTMIAdouble-precision scalar-
01011xxxxxxx1FSTMDBX, FSTMIAXIncrement After-
01110VLDM, VLDMDB, VLDMIAsingle-precision scalar-
01111xxxxxxx0VLDM, VLDMDB, VLDMIAdouble-precision scalar-
01111xxxxxxx1FLDM*X (FLDMDBX, FLDMIAX)Increment After-
10001VSTRhalf-precision scalarFEAT_FP16
10010VSTRsingle-precision scalar-
10011VSTRdouble-precision scalar-
101!= 111101VLDR (immediate)half-precision scalarFEAT_FP16
101!= 111110VLDR (immediate)single-precision scalar-
101!= 111111VLDR (immediate)double-precision scalar-
1010xUNALLOCATED-
101010VSTM, VSTMDB, VSTMIAsingle-precision scalar-
101011xxxxxxx0VSTM, VSTMDB, VSTMIAdouble-precision scalar-
101011xxxxxxx1FSTMDBX, FSTMIAXDecrement Before-
101110VLDM, VLDMDB, VLDMIAsingle-precision scalar-
101111xxxxxxx0VLDM, VLDMDB, VLDMIAdouble-precision scalar-
101111xxxxxxx1FLDM*X (FLDMDBX, FLDMIAX)Decrement Before-
101111101VLDR (literal)half-precision scalarFEAT_FP16
101111110VLDR (literal)single-precision scalar-
101111111VLDR (literal)double-precision scalar-
111UNALLOCATED-

System register load/store

These instructions are under Advanced SIMD and System register load/store and 64-bit move.

313029282726252423222120191817161514131211109876543210
!= 1111110PUDWLRnCRd111cp15imm8
cond

The following constraints also apply to this encoding: cond != 1111 && P:U:D:W != 00x0 && cond != 1111

Decode fields Instruction Details
P:U:WDLRnCRdcp15
!= 0000!= 01010UNALLOCATED
!= 00001111101010LDC (literal)
!= 0001UNALLOCATED
!= 000101010UNALLOCATED
0x10001010STCpost-indexed
0x101!= 111101010LDC (immediate)post-indexed
0100001010STCunindexed
01001!= 111101010LDC (immediate)unindexed
1x00001010STCoffset
1x001!= 111101010LDC (immediate)offset
1x10001010STCpre-indexed
1x101!= 111101010LDC (immediate)pre-indexed

Advanced SIMD and System register 32-bit move

These instructions are under System register access, Advanced SIMD, floating-point, and Supervisor call.

313029282726252423222120191817161514131211109876543210
!= 11111110op01op11
Decode fields Instruction details Architecture version
op0op1
000 000 UNALLOCATED-
000 001 VMOV (between general-purpose register and half-precision)FEAT_FP16
000 010 VMOV (between general-purpose register and single-precision)-
001 010 UNALLOCATED-
01x 010 UNALLOCATED-
10x 010 UNALLOCATED-
110 010 UNALLOCATED-
111 010 Floating-point move special register-
011 Advanced SIMD 8/16/32-bit element move/duplicate-
10x UNALLOCATED-
11x System register 32-bit move-

Floating-point move special register

These instructions are under Advanced SIMD and System register 32-bit move.

313029282726252423222120191817161514131211109876543210
!= 11111110111LregRt1010(0)(0)(0)1(0)(0)(0)(0)
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
L
0VMSR
1VMRS

Advanced SIMD 8/16/32-bit element move/duplicate

These instructions are under Advanced SIMD and System register 32-bit move.

313029282726252423222120191817161514131211109876543210
!= 11111110opc1LVnRt1011Nopc21(0)(0)(0)(0)
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
opc1Lopc2
0xx0VMOV (general-purpose register to scalar)
1VMOV (scalar to general-purpose register)
1xx00xVDUP (general-purpose register)
1xx01xUNALLOCATED

System register 32-bit move

These instructions are under Advanced SIMD and System register 32-bit move.

313029282726252423222120191817161514131211109876543210
!= 11111110opc1LCRnRt111cp15opc21CRm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details
L
0MCR
1MRC

Floating-point data-processing

These instructions are under System register access, Advanced SIMD, floating-point, and Supervisor call.

313029282726252423222120191817161514131211109876543210
!= 11111110op010op10
Decode fields Instruction details
op0op1
1x11 1 Floating-point data-processing (two registers)
1x11 0 Floating-point move immediate
!= 1x11 Floating-point data-processing (three registers)

Floating-point data-processing (two registers)

These instructions are under Floating-point data-processing.

313029282726252423222120191817161514131211109876543210
!= 111111101D11o1opc2Vd10sizeo31M0Vm
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details Feature
o1opc2sizeo3
00UNALLOCATED-
0000010UNALLOCATED-
0000011VABShalf-precision scalarFEAT_FP16
0000100VMOV (register)single-precision scalar-
0000101VABSsingle-precision scalar-
0000110VMOV (register)double-precision scalar-
0000111VABSdouble-precision scalar-
0001010VNEGhalf-precision scalarFEAT_FP16
0001011VSQRThalf-precision scalarFEAT_FP16
0001100VNEGsingle-precision scalar-
0001101VSQRTsingle-precision scalar-
0001110VNEGdouble-precision scalar-
0001111VSQRTdouble-precision scalar-
001001UNALLOCATED-
0010100VCVTBhalf-precision to single-precision-
0010101VCVTThalf-precision to single-precision-
0010110VCVTBhalf-precision to double-precision-
0010111VCVTThalf-precision to double-precision-
0011010VCVTB (BFloat16)FEAT_AA32BF16
0011011VCVTT (BFloat16)FEAT_AA32BF16
0011100VCVTBsingle-precision to half-precision-
0011101VCVTTsingle-precision to half-precision-
0011110VCVTBdouble-precision to half-precision-
0011111VCVTTdouble-precision to half-precision-
0100010VCMPFEAT_FP16
0100011VCMPEFEAT_FP16
0100100VCMP-
0100101VCMPE-
0100110VCMP-
0100111VCMPE-
0101010VCMPFEAT_FP16
0101011VCMPEFEAT_FP16
0101100VCMP-
0101101VCMPE-
0101110VCMP-
0101111VCMPE-
0110010VRINTRhalf-precision scalarFEAT_FP16
0110011VRINTZ (floating-point)half-precision scalarFEAT_FP16
0110100VRINTRsingle-precision scalar-
0110101VRINTZ (floating-point)single-precision scalar-
0110110VRINTRdouble-precision scalar-
0110111VRINTZ (floating-point)double-precision scalar-
0111010VRINTX (floating-point)half-precision scalarFEAT_FP16
0111011UNALLOCATED-
0111100VRINTX (floating-point)single-precision scalar-
0111101VCVT (between double-precision and single-precision)single-precision to double-precision-
0111110VRINTX (floating-point)double-precision scalar-
0111111VCVT (between double-precision and single-precision)double-precision to single-precision-
100001VCVT (integer to floating-point, floating-point)half-precision scalarFEAT_FP16
100010VCVT (integer to floating-point, floating-point)single-precision scalar-
100011VCVT (integer to floating-point, floating-point)double-precision scalar-
100101UNALLOCATED-
100110UNALLOCATED-
1001110UNALLOCATED-
1001111VJCVTFEAT_JSCVT
101x01VCVT (between floating-point and fixed-point, floating-point)FEAT_FP16
101x10VCVT (between floating-point and fixed-point, floating-point)-
101x11VCVT (between floating-point and fixed-point, floating-point)-
1100010VCVTRFEAT_FP16
1100011VCVT (floating-point to integer, floating-point)FEAT_FP16
1100100VCVTR-
1100101VCVT (floating-point to integer, floating-point)-
1100110VCVTR-
1100111VCVT (floating-point to integer, floating-point)-
1101010VCVTRFEAT_FP16
1101011VCVT (floating-point to integer, floating-point)FEAT_FP16
1101100VCVTR-
1101101VCVT (floating-point to integer, floating-point)-
1101110VCVTR-
1101111VCVT (floating-point to integer, floating-point)-
111x01VCVT (between floating-point and fixed-point, floating-point)FEAT_FP16
111x10VCVT (between floating-point and fixed-point, floating-point)-
111x11VCVT (between floating-point and fixed-point, floating-point)-

Floating-point move immediate

These instructions are under Floating-point data-processing.

313029282726252423222120191817161514131211109876543210
!= 111111101D11imm4HVd10size(0)0(0)0imm4L
cond

The following constraints also apply to this encoding: cond != 1111 && cond != 1111

Decode fields Instruction Details Feature
size
00UNALLOCATED-
01VMOV (immediate)half-precision scalarFEAT_FP16
10VMOV (immediate)single-precision scalar-
11VMOV (immediate)double-precision scalar-

Floating-point data-processing (three registers)

These instructions are under Floating-point data-processing.

313029282726252423222120191817161514131211109876543210
!= 11111110o0Do1VnVd10sizeNo2M0Vm
cond

The following constraints also apply to this encoding: cond != 1111 && o0:D:o1 != 1x11 && cond != 1111

Decode fields Instruction Details Feature
o0:o1sizeo2
!= 11100UNALLOCATED-
000010VMLA (floating-point)half-precision scalarFEAT_FP16
000011VMLS (floating-point)half-precision scalarFEAT_FP16
000100VMLA (floating-point)single-precision scalar-
000101VMLS (floating-point)single-precision scalar-
000110VMLA (floating-point)double-precision scalar-
000111VMLS (floating-point)double-precision scalar-
001010VNMLShalf-precision scalarFEAT_FP16
001011VNMLAhalf-precision scalarFEAT_FP16
001100VNMLSsingle-precision scalar-
001101VNMLAsingle-precision scalar-
001110VNMLSdouble-precision scalar-
001111VNMLAdouble-precision scalar-
010010VMUL (floating-point)half-precision scalarFEAT_FP16
010011VNMULhalf-precision scalarFEAT_FP16
010100VMUL (floating-point)single-precision scalar-
010101VNMULsingle-precision scalar-
010110VMUL (floating-point)double-precision scalar-
010111VNMULdouble-precision scalar-
011010VADD (floating-point)half-precision scalarFEAT_FP16
011011VSUB (floating-point)half-precision scalarFEAT_FP16
011100VADD (floating-point)single-precision scalar-
011101VSUB (floating-point)single-precision scalar-
011110VADD (floating-point)double-precision scalar-
011111VSUB (floating-point)double-precision scalar-
100010VDIVhalf-precision scalarFEAT_FP16
100100VDIVsingle-precision scalar-
100110VDIVdouble-precision scalar-
101010VFNMShalf-precision scalarFEAT_FP16
101011VFNMAhalf-precision scalarFEAT_FP16
101100VFNMSsingle-precision scalar-
101101VFNMAsingle-precision scalar-
101110VFNMSdouble-precision scalar-
101111VFNMAdouble-precision scalar-
110010VFMAhalf-precision scalarFEAT_FP16
110011VFMShalf-precision scalarFEAT_FP16
110100VFMAsingle-precision scalar-
110101VFMSsingle-precision scalar-
110110VFMAdouble-precision scalar-
110111VFMSdouble-precision scalar-

Unconditional instructions

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
11110op0op1
Decode fields Instruction details
op0op1
00x Miscellaneous
01x Advanced SIMD data-processing
1xx 1 Memory hints and barriers
100 0 Advanced SIMD element or structure load/store
101 0 UNALLOCATED
11x 0 UNALLOCATED

Miscellaneous

These instructions are under Unconditional instructions.

313029282726252423222120191817161514131211109876543210
1111000op0op1
Decode fields Instruction details Architecture version
op0op1
0xxxx UNALLOCATED-
10000 xx0x Change Process State-
10001 1000 UNALLOCATED-
10001 x100 UNALLOCATED-
10001 xx01 UNALLOCATED-
10001 0000 SETPANFEAT_PAN
1000x 0111 UNALLOCATED-
10010 0111 CONSTRAINED UNPREDICTABLE-
10011 0111 UNALLOCATED-
1001x xx0x UNALLOCATED-
100xx 0011 UNALLOCATED-
100xx 0x10 UNALLOCATED-
100xx 1x1x UNALLOCATED-
101xx UNALLOCATED-
11xxx UNALLOCATED-

The behavior of the CONSTRAINED UNPREDICTABLE encodings in this table is described in CONSTRAINED UNPREDICTABLE behavior for A32 and T32 instruction encodings


Change Process State

These instructions are under Miscellaneous.

313029282726252423222120191817161514131211109876543210
111100010000imodMop(0)(0)(0)(0)(0)(0)EAIF0mode
Decode fields Instruction Details
imodMopIFmode
1000xxxxSETEND
0010CPS, CPSID, CPSIEchange mode
100CPS, CPSID, CPSIEinterrupt enable and change mode
1001xxxxUNALLOCATED
101UNALLOCATED
11UNALLOCATED
110CPS, CPSID, CPSIEinterrupt disable and change mode

Advanced SIMD data-processing

These instructions are under Unconditional instructions.

313029282726252423222120191817161514131211109876543210
1111001op0op1
Decode fields Instruction details
op0op1
0 Advanced SIMD three registers of the same length
1 0 Advanced SIMD two registers, or three registers of different lengths
1 1 Advanced SIMD shifts and immediate generation

Advanced SIMD three registers of the same length

These instructions are under Advanced SIMD data-processing.

313029282726252423222120191817161514131211109876543210
1111001U0DsizeVnVdopcNQMo1Vm
Decode fields Instruction Details Feature
UsizeopcQo1
00x11001VFMA-
00x11010VADD (floating-point)-
00x11011VMLA (floating-point)-
00x11100VCEQ (register)A2-
00x11110VMAX (floating-point)-
00x11111VRECPS-
00000VHADD-
00000011VAND (register)-
00001VQADD-
00010VRHADD-
00011000SHA1C-
00100VHSUB-
00100011VBIC (register)-
00101VQSUB-
00110VCGT (register)A1-
00111VCGE (register)A1-
00111000SHA1P-
01x11001VFMS-
01x11010VSUB (floating-point)-
01x11011VMLS (floating-point)-
01x11100UNALLOCATED-
01x11110VMIN (floating-point)-
01x11111VRSQRTS-
01000VSHL (register)-
010000VADD (integer)-
01000011VORR (register)-
010001VTST-
01001VQSHL (register)-
010010VMLA (integer)-
01010VRSHL-
01011VQRSHL-
010110VQDMULH-
01011000SHA1M-
010111VPADD (integer)-
01100VMAX (integer)-
01100011VORN (register)-
01101VMIN (integer)-
01110VABD (integer)-
01111VABA-
01111000SHA1SU0-
10x11010VPADD (floating-point)-
10x11011VMUL (floating-point)-
10x11100VCGE (register)A2-
10x11101VACGE-
10x111100VPMAX (floating-point)-
10x11111VMAXNM-
10000011VEOR-
10011VMUL (integer and polynomial)-
10011000SHA256H-
101000VPMAX (integer)-
10100011VBSL-
101001VPMIN (integer)-
10101UNALLOCATED-
10111000SHA256H2-
11x11010VABD (floating-point)-
11x11100VCGT (register)A2-
11x11101VACGT-
11x111100VPMIN (floating-point)-
11x11111VMINNM-
110000VSUB (integer)-
11000011VBIT-
110001VCEQ (register)A1-
110010VMLS (integer)-
110110VQRDMULH-
11011000SHA256SU1-
110111VQRDMLAHFEAT_RDM
11100011VBIF-
111001VQRDMLSHFEAT_RDM
1111110UNALLOCATED-

Advanced SIMD two registers, or three registers of different lengths

These instructions are under Advanced SIMD data-processing.

313029282726252423222120191817161514131211109876543210
1111001op01op1op2op30
Decode fields Instruction details
op0op1op2op3
0 11 VEXT (byte elements)
1 11 0x Advanced SIMD two registers misc
1 11 10 VTBL, VTBX
1 11 11 Advanced SIMD duplicate (scalar)
!= 11 0 Advanced SIMD three registers of different lengths
!= 11 1 Advanced SIMD two registers and a scalar

Advanced SIMD two registers misc

These instructions are under Advanced SIMD two registers, or three registers of different lengths.

313029282726252423222120191817161514131211109876543210
111100111D11sizeopc1Vd0opc2QM0Vm
Decode fields Instruction Details Feature
sizeopc1opc2Q
000000VREV64-
000001VREV32-
000010VREV16-
000011UNALLOCATED-
00010xVPADDL-
0001100AESE-
0001101AESD-
0001110AESMC-
0001111AESIMC-
001000VCLS-
00100000VSWP-
001001VCLZ-
001010VCNT-
001011VMVN (register)-
001011001UNALLOCATED-
00110xVPADAL-
001110VQABS-
001111VQNEG-
01x000VCGT (immediate #0)-
01x001VCGE (immediate #0)-
01x010VCEQ (immediate #0)-
01x011VCLE (immediate #0)-
01x100VCLT (immediate #0)-
01x110VABS-
01x111VNEG-
0101011SHA1H-
011011001VCVT (from single-precision to BFloat16, Advanced SIMD)FEAT_AA32BF16
100001VTRN-
100010VUZP-
100011VZIP-
1001000VMOVN-
1001001VQMOVN, VQMOVUNVQMOVUN-
100101VQMOVN, VQMOVUNVQMOVN-
1001100VSHLL-
1001110SHA1SU1-
1001111SHA256SU0-
101000VRINTN (Advanced SIMD)-
101001VRINTX (Advanced SIMD)-
101010VRINTA (Advanced SIMD)-
101011VRINTZ (Advanced SIMD)-
101011001UNALLOCATED-
1011000VCVT (between half-precision and single-precision, Advanced SIMD)single-precision to half-precision-
101101VRINTM (Advanced SIMD)-
1011100VCVT (between half-precision and single-precision, Advanced SIMD)half-precision to single-precision-
1011101UNALLOCATED-
101111VRINTP (Advanced SIMD)-
11000xVCVTA (Advanced SIMD)-
11001xVCVTN (Advanced SIMD)-
11010xVCVTP (Advanced SIMD)-
11011xVCVTM (Advanced SIMD)-
1110x0VRECPE-
1110x1VRSQRTE-
111011001UNALLOCATED-
1111xxVCVT (between floating-point and integer, Advanced SIMD)-

Advanced SIMD duplicate (scalar)

These instructions are under Advanced SIMD two registers, or three registers of different lengths.

313029282726252423222120191817161514131211109876543210
111100111D11imm4Vd11opcQM0Vm
Decode fields Instruction Details
opc
000VDUP (scalar)
001UNALLOCATED
01xUNALLOCATED
1xxUNALLOCATED

Advanced SIMD three registers of different lengths

These instructions are under Advanced SIMD two registers, or three registers of different lengths.

313029282726252423222120191817161514131211109876543210
1111001U1D!= 11VnVdopcN0M0Vm
size

The following constraints also apply to this encoding: size != 11 && size != 11

Decode fields Instruction Details
Uopc
0000VADDL
0001VADDW
0010VSUBL
00100VADDHN
0011VSUBW
00110VSUBHN
01001VQDMLAL
0101VABAL
01011VQDMLSL
01101VQDMULL
0111VABDL (integer)
1000VMLAL (integer)
1010VMLSL (integer)
10100VRADDHN
10110VRSUBHN
11x0VMULL (integer and polynomial)
11001UNALLOCATED
11011UNALLOCATED
11101UNALLOCATED
1111UNALLOCATED

Advanced SIMD two registers and a scalar

These instructions are under Advanced SIMD two registers, or three registers of different lengths.

313029282726252423222120191817161514131211109876543210
1111001Q1D!= 11VnVdopcN1M0Vm
size

The following constraints also apply to this encoding: size != 11 && size != 11

Decode fields Instruction Details Feature
Qopc
000xVMLA (by scalar)-
00011VQDMLAL-
0010VMLAL (by scalar)-
00111VQDMLSL-
010xVMLS (by scalar)-
01011VQDMULL-
0110VMLSL (by scalar)-
100xVMUL (by scalar)-
10011UNALLOCATED-
1010VMULL (by scalar)-
10111UNALLOCATED-
1100VQDMULH-
1101VQRDMULH-
11011UNALLOCATED-
1110VQRDMLAHFEAT_RDM
1111VQRDMLSHFEAT_RDM

Advanced SIMD shifts and immediate generation

These instructions are under Advanced SIMD data-processing.

313029282726252423222120191817161514131211109876543210
11110011op01
Decode fields Instruction details
op0
000xxxxxxxxxxx0 Advanced SIMD one register and modified immediate
!= 000xxxxxxxxxxx0 Advanced SIMD two registers and shift amount

Advanced SIMD one register and modified immediate

These instructions are under Advanced SIMD shifts and immediate generation.

313029282726252423222120191817161514131211109876543210
1111001i1D000imm3Vdcmode0Qop1imm4
Decode fields Instruction Details
cmodeop
0xx00VMOV (immediate)A1
0xx01VMVN (immediate)A1
0xx10VORR (immediate)A1
0xx11VBIC (immediate)A1
10x00VMOV (immediate)A3
10x01VMVN (immediate)A2
10x10VORR (immediate)A2
10x11VBIC (immediate)A2
11xx0VMOV (immediate)A4
110x1VMVN (immediate)A3
11101VMOV (immediate)A5
11111UNALLOCATED

Advanced SIMD two registers and shift amount

These instructions are under Advanced SIMD shifts and immediate generation.

313029282726252423222120191817161514131211109876543210
1111001U1Dimm3Himm3LVdopcLQM1Vm

The following constraints also apply to this encoding: imm3H:imm3L:Vd:opc:L != 000xxxxxxxxxxx0

Decode fields Instruction Details
Uimm3H:Limm3LopcQ
!= 00000000VSHR
!= 00000001VSRA
!= 000000010100VMOVL
!= 00000010VRSHR
!= 00000011VRSRA
!= 00000111VQSHL, VQSHLU (immediate)VQSHL
!= 000010010VQSHRN, VQSHRUNVQSHRN
!= 000010011VQRSHRN, VQRSHRUNVQRSHRN
!= 000010100VSHLL
!= 000011xxVCVT (between floating-point and fixed-point, Advanced SIMD)
0!= 00000101VSHL (immediate)
0!= 000010000VSHRN
0!= 000010001VRSHRN
1!= 00000100VSRI
1!= 00000101VSLI
1!= 00000110VQSHL, VQSHLU (immediate)VQSHLU
1!= 000010000VQSHRN, VQSHRUNVQSHRUN
1!= 000010001VQRSHRN, VQRSHRUNVQRSHRUN

Memory hints and barriers

These instructions are under Unconditional instructions.

313029282726252423222120191817161514131211109876543210
111101op01op1
Decode fields Instruction details
op0op1
00xx1 CONSTRAINED UNPREDICTABLE
01001 CONSTRAINED UNPREDICTABLE
01011 Barriers
011x1 CONSTRAINED UNPREDICTABLE
0xxx0 Preload (immediate)
1xxx0 0 Preload (register)
1xxx1 0 CONSTRAINED UNPREDICTABLE
1xxxx 1 UNALLOCATED

The behavior of the CONSTRAINED UNPREDICTABLE encodings in this table is described in CONSTRAINED UNPREDICTABLE behavior for A32 and T32 instruction encodings


Barriers

These instructions are under Memory hints and barriers.

313029282726252423222120191817161514131211109876543210
111101010111(1)(1)(1)(1)(1)(1)(1)(1)(0)(0)(0)(0)opcodeoption
Decode fields Instruction Details Feature
opcodeoption
0000CONSTRAINED UNPREDICTABLE-
0001CLREX-
001xCONSTRAINED UNPREDICTABLE-
0100!= 0x00DSB-
01000000SSBB-
01000100PSSBB-
0101DMB-
0110ISB-
0111SBFEAT_SB
1xxxCONSTRAINED UNPREDICTABLE-

The behavior of the CONSTRAINED UNPREDICTABLE encodings in this table is described in CONSTRAINED UNPREDICTABLE behavior for A32 and T32 instruction encodings


Preload (immediate)

These instructions are under Memory hints and barriers.

313029282726252423222120191817161514131211109876543210
1111010DUR01Rn(1)(1)(1)(1)imm12
Decode fields Instruction Details
DRRn
00Reserved hint, behaves as NOP
01PLI (immediate, literal)
11111PLD (literal)
10!= 1111PLD, PLDW (immediate)preload write
11!= 1111PLD, PLDW (immediate)preload read

Preload (register)

These instructions are under Memory hints and barriers.

313029282726252423222120191817161514131211109876543210
1111011DUo201Rn(1)(1)(1)(1)imm5stype0Rm
Decode fields Instruction Details
Do2imm5:stype
00Reserved hint, behaves as NOP
01!= 0000011PLI (register)shift or rotate by value
010000011PLI (register)rotate right with extend
10!= 0000011PLD, PLDW (register)preload write, optional shift or rotate
100000011PLD, PLDW (register)preload write, rotate right with extend
11!= 0000011PLD, PLDW (register)preload read, optional shift or rotate
110000011PLD, PLDW (register)preload read, rotate right with extend

Advanced SIMD element or structure load/store

These instructions are under Unconditional instructions.

313029282726252423222120191817161514131211109876543210
11110100op00op1
Decode fields Instruction details
op0op1
0 Advanced SIMD load/store multiple structures
1 11 Advanced SIMD load single structure to all lanes
1 != 11 Advanced SIMD load/store single structure to one lane

Advanced SIMD load/store multiple structures

These instructions are under Advanced SIMD element or structure load/store.

313029282726252423222120191817161514131211109876543210
111101000DL0RnVditypesizealignRm
Decode fields Instruction Details
LitypeRm
0000x!= 11x1VST4 (multiple 4-element structures)
0000x1101VST4 (multiple 4-element structures)
0000x1111VST4 (multiple 4-element structures)
00010!= 11x1VST1 (multiple single elements)
000101101VST1 (multiple single elements)
000101111VST1 (multiple single elements)
00011!= 11x1VST2 (multiple 2-element structures)
000111101VST2 (multiple 2-element structures)
000111111VST2 (multiple 2-element structures)
0010x!= 11x1VST3 (multiple 3-element structures)
0010x1101VST3 (multiple 3-element structures)
0010x1111VST3 (multiple 3-element structures)
00110!= 11x1VST1 (multiple single elements)
001101101VST1 (multiple single elements)
001101111VST1 (multiple single elements)
00111!= 11x1VST1 (multiple single elements)
001111101VST1 (multiple single elements)
001111111VST1 (multiple single elements)
0100x!= 11x1VST2 (multiple 2-element structures)
0100x1101VST2 (multiple 2-element structures)
0100x1111VST2 (multiple 2-element structures)
01010!= 11x1VST1 (multiple single elements)
010101101VST1 (multiple single elements)
010101111VST1 (multiple single elements)
1000x!= 11x1VLD4 (multiple 4-element structures)
1000x1101VLD4 (multiple 4-element structures)
1000x1111VLD4 (multiple 4-element structures)
10010!= 11x1VLD1 (multiple single elements)
100101101VLD1 (multiple single elements)
100101111VLD1 (multiple single elements)
10011!= 11x1VLD2 (multiple 2-element structures)
100111101VLD2 (multiple 2-element structures)
100111111VLD2 (multiple 2-element structures)
1010x!= 11x1VLD3 (multiple 3-element structures)
1010x1101VLD3 (multiple 3-element structures)
1010x1111VLD3 (multiple 3-element structures)
1011UNALLOCATED
10110!= 11x1VLD1 (multiple single elements)
101101101VLD1 (multiple single elements)
101101111VLD1 (multiple single elements)
10111!= 11x1VLD1 (multiple single elements)
101111101VLD1 (multiple single elements)
101111111VLD1 (multiple single elements)
11xxUNALLOCATED
1100x!= 11x1VLD2 (multiple 2-element structures)
1100x1101VLD2 (multiple 2-element structures)
1100x1111VLD2 (multiple 2-element structures)
11010!= 11x1VLD1 (multiple single elements)
110101101VLD1 (multiple single elements)
110101111VLD1 (multiple single elements)

Advanced SIMD load single structure to all lanes

These instructions are under Advanced SIMD element or structure load/store.

313029282726252423222120191817161514131211109876543210
111101001DL0RnVd11NsizeTaRm
Decode fields Instruction Details
LNaRm
0UNALLOCATED
100!= 11x1VLD1 (single element to all lanes)
1001101VLD1 (single element to all lanes)
1001111VLD1 (single element to all lanes)
101!= 11x1VLD2 (single 2-element structure to all lanes)
1011101VLD2 (single 2-element structure to all lanes)
1011111VLD2 (single 2-element structure to all lanes)
1100!= 11x1VLD3 (single 3-element structure to all lanes)
11001101VLD3 (single 3-element structure to all lanes)
11001111VLD3 (single 3-element structure to all lanes)
1101UNALLOCATED
111!= 11x1VLD4 (single 4-element structure to all lanes)
1111101VLD4 (single 4-element structure to all lanes)
1111111VLD4 (single 4-element structure to all lanes)

Advanced SIMD load/store single structure to one lane

These instructions are under Advanced SIMD element or structure load/store.

313029282726252423222120191817161514131211109876543210
111101001DL0RnVd!= 11Nindex_alignRm
size

The following constraints also apply to this encoding: size != 11 && size != 11

Decode fields Instruction Details
LsizeNRm
00000!= 11x1VST1 (single element from one lane)
000001101VST1 (single element from one lane)
000001111VST1 (single element from one lane)
00001!= 11x1VST2 (single 2-element structure from one lane)
000011101VST2 (single 2-element structure from one lane)
000011111VST2 (single 2-element structure from one lane)
00010!= 11x1VST3 (single 3-element structure from one lane)
000101101VST3 (single 3-element structure from one lane)
000101111VST3 (single 3-element structure from one lane)
00011!= 11x1VST4 (single 4-element structure from one lane)
000111101VST4 (single 4-element structure from one lane)
000111111VST4 (single 4-element structure from one lane)
00100!= 11x1VST1 (single element from one lane)
001001101VST1 (single element from one lane)
001001111VST1 (single element from one lane)
00101!= 11x1VST2 (single 2-element structure from one lane)
001011101VST2 (single 2-element structure from one lane)
001011111VST2 (single 2-element structure from one lane)
00110!= 11x1VST3 (single 3-element structure from one lane)
001101101VST3 (single 3-element structure from one lane)
001101111VST3 (single 3-element structure from one lane)
00111!= 11x1VST4 (single 4-element structure from one lane)
001111101VST4 (single 4-element structure from one lane)
001111111VST4 (single 4-element structure from one lane)
01000!= 11x1VST1 (single element from one lane)
010001101VST1 (single element from one lane)
010001111VST1 (single element from one lane)
01001!= 11x1VST2 (single 2-element structure from one lane)
010011101VST2 (single 2-element structure from one lane)
010011111VST2 (single 2-element structure from one lane)
01010!= 11x1VST3 (single 3-element structure from one lane)
010101101VST3 (single 3-element structure from one lane)
010101111VST3 (single 3-element structure from one lane)
01011!= 11x1VST4 (single 4-element structure from one lane)
010111101VST4 (single 4-element structure from one lane)
010111111VST4 (single 4-element structure from one lane)
10000!= 11x1VLD1 (single element to one lane)
100001101VLD1 (single element to one lane)
100001111VLD1 (single element to one lane)
10001!= 11x1VLD2 (single 2-element structure to one lane)
100011101VLD2 (single 2-element structure to one lane)
100011111VLD2 (single 2-element structure to one lane)
10010!= 11x1VLD3 (single 3-element structure to one lane)
100101101VLD3 (single 3-element structure to one lane)
100101111VLD3 (single 3-element structure to one lane)
10011!= 11x1VLD4 (single 4-element structure to one lane)
100111101VLD4 (single 4-element structure to one lane)
100111111VLD4 (single 4-element structure to one lane)
10100!= 11x1VLD1 (single element to one lane)
101001101VLD1 (single element to one lane)
101001111VLD1 (single element to one lane)
10101!= 11x1VLD2 (single 2-element structure to one lane)
101011101VLD2 (single 2-element structure to one lane)
101011111VLD2 (single 2-element structure to one lane)
10110!= 11x1VLD3 (single 3-element structure to one lane)
101101101VLD3 (single 3-element structure to one lane)
101101111VLD3 (single 3-element structure to one lane)
10111!= 11x1VLD4 (single 4-element structure to one lane)
101111101VLD4 (single 4-element structure to one lane)
101111111VLD4 (single 4-element structure to one lane)
11000!= 11x1VLD1 (single element to one lane)
110001101VLD1 (single element to one lane)
110001111VLD1 (single element to one lane)
11001!= 11x1VLD2 (single 2-element structure to one lane)
110011101VLD2 (single 2-element structure to one lane)
110011111VLD2 (single 2-element structure to one lane)
11010!= 11x1VLD3 (single 3-element structure to one lane)
110101101VLD3 (single 3-element structure to one lane)
110101111VLD3 (single 3-element structure to one lane)
11011!= 11x1VLD4 (single 4-element structure to one lane)
110111101VLD4 (single 4-element structure to one lane)
110111111VLD4 (single 4-element structure to one lane)

Internal version only: isa v01_27v01_26, pseudocode v2022-03_relv2021-12_to_suppress_diffs_in_2022_03_RC1 ; Build timestamp: 2022-03-29T102022-03-08T10:4611

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