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Hypervisor Call causes a Hypervisor Call exception. For more information, see Hypervisor Call (HVC) exception. Software executing at EL1 can use this instruction to call the hypervisor to request a service.
The HVC instruction is undefined:
The HVC instruction is constrained unpredictable in Hyp mode when EL3 is implemented and using AArch32, and SCR.HCE is set to 0.
On executing an HVC instruction, the HSR, Hyp Syndrome Register reports the exception as a Hypervisor Call exception, using the EC value 0x12, and captures the value of the immediate argument, see Use of the HSR.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
!= 1111 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | imm12 | 0 | 1 | 1 | 1 | imm4 | |||||||||||||||||
cond |
if cond != '1110' then UNPREDICTABLE; imm16 = imm12:imm4;
If cond != '1110', then one of the following behaviors must occur:
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | imm4 | 1 | 0 | 0 | 0 | imm12 |
imm16 = imm4:imm12; if InITBlock() then UNPREDICTABLE;
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
<q> | See Standard assembler syntax fields. An HVC instruction must be unconditional. |
EncodingSpecificOperations();
if PSTATE.EL IN {if !HaveEL(EL2) || PSTATE.EL == EL0,|| ( EL3IsSecure} || !() && !EL2EnabledIsSecureEL2Enabled() then
()) then
UNDEFINED;
bit hvc_enable;
if HaveEL(EL3) then
if ELUsingAArch32(EL3) && SCR.HCE == '0' && PSTATE.EL == EL2 then
UNPREDICTABLE;
else
hvc_enable = SCR_GEN[].HCE;
else
hvc_enable = if ELUsingAArch32(EL2) then NOT(HCR.HCD) else NOT(HCR_EL2.HCD);
if hvc_enable == '0' then
UNDEFINED;
else
AArch32.CallHypervisor(imm16);
If ELUsingAArch32(EL3) && SCR.HCE == '0' && PSTATE.EL == EL2, then one of the following behaviors must occur:
Internal version only: isa v01_27v01_26, pseudocode v2022-03_relv2021-12_to_suppress_diffs_in_2022_03_RC1
; Build timestamp: 2022-03-29T102022-03-08T10:4611
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