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Data Synchronization Barrier is a memory barrier that ensures the completion of memory accesses, see Data Synchronization Barrier (DSB).
An AArch32 DSB instruction does not require the completion of any AArch64 TLB maintenance instructions, regardless of the nXS qualifier, appearing in program order before the AArch32 DSB.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | (1) | (1) | (1) | (1) | (1) | (1) | (1) | (1) | (0) | (0) | (0) | (0) | 0 | 1 | 0 | 0 | != 0x00 | |||
option |
// No additional decoding required
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | (1) | (1) | (1) | (1) | 1 | 0 | (0) | 0 | (1) | (1) | (1) | (1) | 0 | 1 | 0 | 0 | != 0x00 | |||
option |
// No additional decoding required
For more information about the constrained unpredictable behavior, see Architectural Constraints on UNPREDICTABLE behaviors.
<c> | For encoding A1: see Standard assembler syntax fields. Must be AL or omitted. |
For encoding T1: see Standard assembler syntax fields. |
<q> |
<option> | Specifies an optional limitation on the barrier operation. Values are:
For more information on whether an access is before or after a barrier instruction, see Data Synchronization Barrier (DSB). All other encodings of option are reserved, other than the values 0b0000 and 0b0100. All unsupported and reserved options must execute as a full system DSB operation, but software must not rely on this behavior. NoteThe value 0b0000 is used to encode SSBB and the value 0b0100 is used to encode PSSBB. The instruction supports the following alternative <option> values, but Arm recommends that software does not use these alternative values:
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if ConditionPassed() then
EncodingSpecificOperations();
boolean nXS;
if HaveFeatXS() && HaveFeatHCX() then
nXS = (PSTATE.EL IN {EL0, EL1} && !ELUsingAArch32(EL2) &&
IsHCRXEL2Enabled() && HCRX_EL2.FnXS == '1');
else
nXS = FALSE;
MBReqDomain domain;
MBReqTypes types;
case option of
when '0001' domain = MBReqDomain_OuterShareable; types = MBReqTypes_Reads;
when '0010' domain = MBReqDomain_OuterShareable; types = MBReqTypes_Writes;
when '0011' domain = MBReqDomain_OuterShareable; types = MBReqTypes_All;
when '0101' domain = MBReqDomain_Nonshareable; types = MBReqTypes_Reads;
when '0110' domain = MBReqDomain_Nonshareable; types = MBReqTypes_Writes;
when '0111' domain = MBReqDomain_Nonshareable; types = MBReqTypes_All;
when '1001' domain = MBReqDomain_InnerShareable; types = MBReqTypes_Reads;
when '1010' domain = MBReqDomain_InnerShareable; types = MBReqTypes_Writes;
when '1011' domain = MBReqDomain_InnerShareable; types = MBReqTypes_All;
when '1101' domain = MBReqDomain_FullSystem; types = MBReqTypes_Reads;
when '1110' domain = MBReqDomain_FullSystem; types = MBReqTypes_Writes;
otherwise
assert !(option IN {'0x00'});
domain = if option == '0000' then SEE "SSBB";
elsif option == '0100' then SEE "PSSBB";
else domain = MBReqDomain_FullSystem; types = MBReqTypes_All;
if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
if HCR.BSU == '11' then
domain = MBReqDomain_FullSystem;
if HCR.BSU == '10' && domain != MBReqDomain_FullSystem then
domain = MBReqDomain_OuterShareable;
if HCR.BSU == '01' && domain == MBReqDomain_Nonshareable then
domain = MBReqDomain_InnerShareable;
DataSynchronizationBarrier(domain, types, nXS);
Internal version only: isa v01_27v01_26, pseudocode v2022-03_relv2021-12_to_suppress_diffs_in_2022_03_RC1
; Build timestamp: 2022-03-29T102022-03-08T10:4611
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