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PMITCTRL, Performance Monitors Integration mode Control register

The PMITCTRL characteristics are:

Purpose

Enables the Performance Monitors to switch from default mode into integration mode, where test software can control directly the inputs and outputs of the PE, for integration testing or topology detection.

Configuration

Implementation of this register is OPTIONAL.

ThisIt register is present only when FEAT_PMUv3_EXT32 is implemented and an implementation implements PMITCTRL. Otherwise, direct accesses to PMITCTRL are RES0IMPLEMENTATION DEFINED.whether PMITCTRL is implemented in the Core power domain or in the Debug power domain.

Attributes

PMITCTRL is a 32-bit register.

This register is part of the PMU block.

Field descriptions

313029282726252423222120191817161514131211109876543210
RES0IME

Bits [31:1]

Reserved, RES0.

IME, bit [0]

Integration mode enable. When IME == 1, the device reverts to an integration mode to enable integration testing or topology detection. The integration mode behavior is IMPLEMENTATION DEFINED.

IMEMeaning
0b0

Normal operation.

0b1

Integration mode enabled.

The following resets apply:

Accessing PMITCTRL

PMITCTRL can be accessed through the external debug interface:

ComponentOffsetInstance
PMU0xF00PMITCTRL

This interface is accessible as follows:

Accessing PMITCTRL

Accesses to this register use the following encodings in the external debug interface:

BlockAccess at address 0xF00

PMITCTRL can be accessed through the PMU block as follows:

FrameOffset
PMU0xF00

3005/0907/2022 1517:5708; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96fb0421fa9a8865165f9b91af9b4a566111f866305

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