The PMINTENCLR_EL1 characteristics are:
Disables the generation of interrupt requests on overflows from the Cycle Count Register, PMU.PMCCNTR_EL0, and the event counters PMU.PMEVCNTR<n>_EL0. Reading the register shows which overflow interrupt requests are enabled.
External register PMINTENCLR_EL1 bits [31:0] are architecturally mapped to AArch64 System register PMINTENCLR_EL1[31:0].
External register PMINTENCLR_EL1 bits [63:32] are architecturally mapped to AArch64 System register PMINTENCLR_EL1[63:32] when FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented.
External register PMINTENCLR_EL1 bits [31:0] are architecturally mapped to AArch32 System register PMINTENCLR[31:0].
External register PMINTENCLR_EL1 bits [31:0] are architecturally mapped to AArch64 System register PMINTENSET_EL1[31:0].
External register PMINTENCLR_EL1 bits [63:32] are architecturally mapped to AArch64 System register PMINTENSET_EL1[63:32] when FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented.
External register PMINTENCLR_EL1 bits [31:0] are architecturally mapped to AArch32 System register PMINTENSET[31:0].
This register is present only when FEAT_PMUv3_EXT is implemented. Otherwise, direct accesses to PMINTENCLR_EL1 are RES0.
PMINTENCLR_EL1 is in the Core power domain.
PMINTENCLR_EL1 is a:
This register is part of the PMU block.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | F0 | ||||||||||||||||||||||||||||||
C | P30 | P29 | P28 | P27 | P26 | P25 | P24 | P23 | P22 | P21 | P20 | P19 | P18 | P17 | P16 | P15 | P14 | P13 | P12 | P11 | P10 | P9 | P8 | P7 | P6 | P5 | P4 | P3 | P2 | P1 | P0 |
Reserved, RES0.
Interrupt request on unsigned overflow of PMU.PMICNTR_EL0 disable. On writes, allows software to disable the interrupt request on unsigned overflow of PMU.PMICNTR_EL0. On reads, returns the interrupt request on unsigned overflow of PMU.PMICNTR_EL0 enable status.
F0 | Meaning |
---|---|
0b0 |
Interrupt request on unsigned overflow of PMU.PMICNTR_EL0 disabled. |
0b1 |
Interrupt request on unsigned overflow of PMU.PMICNTR_EL0 enabled. |
The reset behavior of this field is:
Accessing this field has the following behavior:
Reserved, RES0.
PMU.PMCCNTR_EL0 overflow interrupt request disable bit.
C | Meaning |
---|---|
0b0 |
When read, means the cycle counter overflow interrupt request is disabled. When written, has no effect. |
0b1 |
When read, means the cycle counter overflow interrupt request is enabled. When written, disables the cycle count overflow interrupt request. |
The reset behavior of this field is:
Event counter overflow interrupt request disable bit for PMU.PMEVCNTR<n>_EL0.
If PMU.PMCFGR.N is less than 31, bits [30:PMU.PMCFGR.N] are RAZ/WI.
P<n> | Meaning |
---|---|
0b0 |
When read, means that the PMU.PMEVCNTR<n>_EL0 event counter interrupt request is disabled. When written, has no effect. |
0b1 |
When read, means that the PMU.PMEVCNTR<n>_EL0 event counter interrupt request is enabled. When written, disables the PMU.PMEVCNTR<n>_EL0 interrupt request. |
The reset behavior of this field is:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
C | P30 | P29 | P28 | P27 | P26 | P25 | P24 | P23 | P22 | P21 | P20 | P19 | P18 | P17 | P16 | P15 | P14 | P13 | P12 | P11 | P10 | P9 | P8 | P7 | P6 | P5 | P4 | P3 | P2 | P1 | P0 |
PMU.PMCCNTR_EL0 overflow interrupt request disable bit.
C | Meaning |
---|---|
0b0 |
When read, means the cycle counter overflow interrupt request is disabled. When written, has no effect. |
0b1 |
When read, means the cycle counter overflow interrupt request is enabled. When written, disables the cycle count overflow interrupt request. |
The reset behavior of this field is:
Event counter overflow interrupt request disable bit for PMU.PMEVCNTR<n>_EL0.
If PMU.PMCFGR.N is less than 31, bits [30:PMU.PMCFGR.N] are RAZ/WI.
P<n> | Meaning |
---|---|
0b0 |
When read, means that the PMU.PMEVCNTR<n>_EL0 event counter interrupt request is disabled. When written, has no effect. |
0b1 |
When read, means that the PMU.PMEVCNTR<n>_EL0 event counter interrupt request is enabled. When written, disables the PMU.PMEVCNTR<n>_EL0 interrupt request. |
The reset behavior of this field is:
SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.
Accesses to this register use the following encodings in the external debug interface:
PMINTENCLR_EL1 can be accessed through the PMU block as follows:
Frame | Offset |
---|---|
PMU | 0xC60 |
PMINTENCLR_EL1 can be accessed through the PMU block as follows:
Frame | Offset | Range |
---|---|---|
PMU | 0xC60 | 31:0 |
PMINTENCLR_EL1 can be accessed through the PMU block as follows:
Frame | Offset | Range |
---|---|---|
PMU | 0xC64 | 63:32 |
30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f
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