The ID_AA64MMFR4_EL1 characteristics are:
Provides additional information about implemented memory model and memory management support in AArch64.
There are no configuration notes.
ID_AA64MMFR4_EL1 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | EIESB | RES0 |
Reserved, RES0.
Indicates whether the implicit Error synchronization event inserted on taking an exception is inserted before or after the exception is taken.
EIESB | Meaning |
---|---|
0b0000 |
The behavior is not described. |
0b0001 |
Implicit Error synchronization event is inserted before an exception is taken. |
0b1111 |
Implicit Error synchronization event is inserted after an exception is taken. |
All other values are reserved.
Implicit Error synchronization events are inserted on taking an exception to ELx when SCTLR_ELx.EISB is 0b1.
Inserting the event before the exception is taken means that if the Error synchronization event causes an SError exception to become pending, and SError exceptions are not masked and not disabled, then the SError exception is taken in place of the original exception.
Reserved, RES0.
Reserved, RES0.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0000 | 0b0111 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = ID_AA64MMFR4_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = ID_AA64MMFR4_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = ID_AA64MMFR4_EL1;
30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f
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