The TRBIDR_EL1 characteristics are:
Describes constraints on using the Trace Buffer Unit to an external debugger.
This register is present only when FEAT_TRBE is implemented. Otherwise, direct accesses to TRBIDR_EL1 are RES0.
TRBIDR_EL1 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | RAO | P | Align |
Reserved, RES0.
Reserved, RAO.
This field reads as an UNKNOWN value.
Defines the minimum alignment constraint for writes to TRBPTR_EL1 and TRBTRG_EL1.
Align | Meaning |
---|---|
0b0000 |
Byte. |
0b0001 |
Halfword. |
0b0010 |
Word. |
0b0011 |
Doubleword. |
0b0100 |
16 bytes. |
0b0101 |
32 bytes. |
0b0110 |
64 bytes. |
0b0111 |
128 bytes. |
0b1000 |
256 bytes. |
0b1001 |
512 bytes. |
0b1010 |
1KB. |
0b1011 |
2KB. |
All other values are reserved.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Component | Offset | Instance |
---|---|---|
TRBE | 0x030 | TRBIDR_EL1 |
Accesses to this interface are RO.
30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f
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