The ERRFHICR2 characteristics are:
Fault Handling Interrupt control and configuration register.
This register is present only when (the Fault Handling Interrupt is implemented or the implementation does not use the recommended layout for the ERRIRQCR<n> registers) and interrupt configuration registers are implemented. Otherwise, direct accesses to ERRFHICR2 are RES0.
ERRFHICR2 is implemented only as part of a memory-mapped group of error records.
ERRFHICR2 is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | IRQEN | NSMSI | SH | MemAttr |
Reserved, RES0.
Message signaled interrupt enable. Enables generation of message signaled interrupts.
IRQEN | Meaning |
---|---|
0b0 |
Disabled. |
0b1 |
Enabled. |
The reset behavior of this field is:
Reserved, RES0.
Message signaled interrupt enable.
Message signaled interrupts are always enabled.
Security attribute. Defines the physical address space for message signaled interrupts.
NSMSI | Meaning |
---|---|
0b0 |
Secure. |
0b1 |
Non-secure. |
The reset behavior of this field is:
Reserved, RES0.
Security attribute. Defines the physical address space for message signaled interrupts.
The Security attribute used for message signaled interrupts is Non-secure.
Reserved, RES0.
Security attribute. Defines the physical address space for message signaled interrupts.
The Security attribute for message signaled interrupts is IMPLEMENTATION DEFINED.
Shareability. Defines the Shareability domain for message signaled interrupts.
SH | Meaning |
---|---|
0b00 |
Not shared. |
0b10 |
Outer Shareable. |
0b11 |
Inner Shareable. |
All other values are reserved.
This field is ignored when ERRFHICR2.MemAttr specifies any of the following memory types:
All Device and Normal Inner Non-cacheable Outer Non-cacheable memory regions are always treated as Outer Shareable.
The reset behavior of this field is:
Reserved, RES0.
Shareability.
The Shareability domain for message signaled interrupts is IMPLEMENTATION DEFINED.
Memory type. Defines the memory type and attributes for message signaled interrupts.
MemAttr | Meaning |
---|---|
0b0000 |
Device-nGnRnE memory. |
0b0001 |
Device-nGnRE memory. |
0b0010 |
Device-nGRE memory. |
0b0011 |
Device-GRE memory. |
0b0101 |
Normal memory, Inner Non-cacheable, Outer Non-cacheable. |
0b0110 |
Normal memory, Inner Write-Through, Outer Non-cacheable. |
0b0111 |
Normal memory, Inner Write-Back, Outer Non-cacheable. |
0b1001 |
Normal memory, Inner Non-cacheable, Outer Write-Through. |
0b1010 |
Normal memory, Inner Write-Through, Outer Write-Through. |
0b1011 |
Normal memory, Inner Write-Back, Outer Write-Through. |
0b1101 |
Normal memory, Inner Non-cacheable, Outer Write-Back. |
0b1110 |
Normal memory, Inner Write-Through, Outer Write-Back. |
0b1111 |
Normal memory, Inner Write-Back, Outer Write-Back. |
All other values are reserved.
This is the same format as the VMSAv8-64 stage 2 memory region attributes.
The reset behavior of this field is:
Reserved, RES0.
Memory type.
The memory type used for message signaled interrupts is IMPLEMENTATION DEFINED.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED |
IMPLEMENTATION DEFINED.
Component | Offset | Instance |
---|---|---|
RAS | 0xE8C | ERRFHICR2 |
Accesses to this interface are RW.
30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f
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