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PMEVCNTR<n>_EL0, Performance Monitors Event Count Registers, n = 0 - 30

The PMEVCNTR<n>_EL0 characteristics are:

Purpose

Holds event counter <n>,, which counts events, where <n> is 0 to 30.

Configuration

External register PMEVCNTR<n>_EL0 bits [31:0] are architecturally mapped to AArch64 System register PMEVCNTR<n>_EL0[31:0].

External register PMEVCNTR<n>_EL0 bits [63:32] are architecturally mapped to AArch64 System register PMEVCNTR<n>_EL0[63:32] when FEAT_PMUv3p5 is implemented.

External register PMEVCNTR<n>_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMEVCNTR<n>[31:0].

This register is present only when FEAT_PMUv3_EXT is implemented. Otherwise, direct accesses to PMEVCNTR<n>_EL0 are RES0.

PMEVCNTR<n>_EL0 is in the Core power domain.

Attributes

PMEVCNTR<n>_EL0 is a:

This register is part of the PMU block.

Field descriptions

When FEAT_PMUv3p5 is implemented:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
Event counter n
Event counter n

Bits [63:0]

Event counter n. Value of event counter n, where n is the number of this register and is a number from 0 to 30.

If the highest implemented Exception level is using AArch32, the optional external interface to the performance monitors is implemented, and the PMCR.LP and HDCR.HLP bits are RAZ/WI, then locations in the external interface to the performance monitors that map to PMEVCNTR<n>_EL0[63:32] return UNKNOWN values on reads.

If the implementation does not support AArch64, bits [63:32] of the event counters are not required to be implemented.

The reset behavior of this field is:

Otherwise:

313029282726252423222120191817161514131211109876543210
Event counter n

Bits [31:0]

Event counter n. Value of event counter n, where n is the number of this register and is a number from 0 to 30.

The reset behavior of this field is:

Accessing PMEVCNTR<n>_EL0

External accesses to the performance monitors ignore the following controls:

This means that all counters are accessible regardless of the current Exception level or privilege of the access.

If FEAT_PMUv3p5 is not implemented, when IsCorePowered(), DoubleLockStatus(), OSLockStatus() or !AllowExternalPMUAccess(), 32-bit accesses to 0x004+8×n have a CONSTRAINED UNPREDICTABLE behavior.

Note

SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.

PMEVCNTR<n>_EL0 can be accessed through the external debug interface:

ComponentOffsetInstance
PMU0x000 + (8 * n)PMEVCNTR<n>_EL0

This interface is accessible as follows:

Accessing PMEVCNTR<n>_EL0

External accesses to the performance monitors ignore the following controls:

This means that all counters are accessible regardless of the current Exception level or privilege of the access.

If FEAT_PMUv3p5 is not implemented, when IsCorePowered(), DoubleLockStatus(), OSLockStatus() or !AllowExternalPMUAccess(), 32-bit accesses to 0x004+8×n have a CONSTRAINED UNPREDICTABLE behavior.

Note

SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.

Accesses to this register use the following encodings in the external debug interface:

BlockAccess at address 0x000 + (8 * n)

PMEVCNTR<n>_EL0 can be accessed through the PMU block as follows:

FrameOffset
PMU0x000 + (8 * n)

3005/0907/2022 1517:5708; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96fb0421fa9a8865165f9b91af9b4a566111f866305

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