PMICFILTR_EL0, Performance Monitors Instruction Counter Filter Register

The PMICFILTR_EL0 characteristics are:

Purpose

Configures the Instruction Counter.

Configuration

External register PMICFILTR_EL0 bits [63:0] are architecturally mapped to AArch64 System register PMICFILTR_EL0[63:0].

This register is present only when FEAT_PMUv3_ICNTR is implemented. Otherwise, direct accesses to PMICFILTR_EL0 are RES0.

PMICFILTR_EL0 is in the Core power domain.

Note

If FEAT_Debugv8p4 is implemented, the OPTIONAL Software Lock is not implemented.

Attributes

PMICFILTR_EL0 is a 64-bit register.

This register is part of the PMU block.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0SYNCRES0
PUNSKNSUNSHMRES0SHTRLKRLURLHRES0evtCount

Bits [63:59]

Reserved, RES0.

SYNC, bit [58]
When FEAT_SEBEP is implemented:

Synchronous mode. Controls whether a PMU exception generated by the counter is synchronous or asynchronous.

SYNCMeaning
0b0

Asynchronous PMU exception is enabled.

0b1

Synchronous PMU exception is enabled.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Bits [57:32]

Reserved, RES0.

P, bit [31]

EL1 filtering. Controls counting instructions in EL1.

PMeaning
0b0

This bit has no effect on filtering of instructions.

0b1

Instructions in EL1 are not counted.

If EL3 is implemented, then counting instructions in Non-secure EL1 is further controlled by PMICFILTR_EL0.NSK, and counting instructions in EL3 is further controlled by PMICFILTR_EL0.M.

If FEAT_RME is implemented, then counting instructions in Realm EL1 is further controlled by PMICFILTR_EL0.RLK.

The reset behavior of this field is:

U, bit [30]

EL0 filtering. Controls counting instructions in EL0.

UMeaning
0b0

This bit has no effect on filtering of instructions.

0b1

Instructions in EL0 are not counted.

If EL3 is implemented, then PMICFILTR_EL0.NSU further controls filtering instructions in Non-secure EL0.

If FEAT_RME is implemented, then counting instructions in Realm EL1 is further controlled by PMICFILTR_EL0.RLU.

The reset behavior of this field is:

NSK, bit [29]
When EL3 is implemented:

Non-secure EL1 filtering. Controls counting instructions in Non-secure EL1. If PMICFILTR_EL0.NSK is equal to PMICFILTR_EL0.P, then instructions in Non-secure EL1 are counted. Otherwise, instructions in Non-secure EL1 are not counted.

NSKMeaning
0b0

If PMICFILTR_EL0.P == 0, then this bit has no effect on filtering of instructions.

If PMICFILTR_EL0.P == 1, then instructions in Non-secure EL1 are not counted.

0b1

If PMICFILTR_EL0.P == 0, then instructions in Non-secure EL1 are not counted.

If PMICFILTR_EL0.P == 1, then this bit has no effect on filtering of instructions.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

NSU, bit [28]
When EL3 is implemented:

Non-secure EL0 filtering. Controls counting instructions in Non-secure EL0. If PMICFILTR_EL0.NSU is equal to PMICFILTR_EL0.U, then instructions in Non-secure EL0 are counted. Otherwise, instructions in Non-secure EL0 are not counted.

NSUMeaning
0b0

If PMICFILTR_EL0.U == 0, then this bit has no effect on filtering of instructions.

If PMICFILTR_EL0.U == 1, then instructions in Non-secure EL0 are not counted.

0b1

If PMICFILTR_EL0.U == 0, then instructions in Non-secure EL0 are not counted.

If PMICFILTR_EL0.U == 1, then this bit has no effect on filtering of instructions.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

NSH, bit [27]
When EL2 is implemented:

EL2 filtering. Controls counting instructions in EL2.

NSHMeaning
0b0

Instructions in EL2 are not counted.

0b1

This bit has no effect on filtering of instructions.

If EL3 is implemented and FEAT_SEL2 is implemented, then counting instructions in Secure EL2 is further controlled by PMICFILTR_EL0.SH.

If FEAT_RME is implemented, then counting instructions in Realm EL2 is further controlled by PMICFILTR_EL0.RLH.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

M, bit [26]
When EL3 is implemented:

EL3 filtering. Controls counting instructions in EL3. If PMICFILTR_EL0.M is equal to PMICFILTR_EL0.P, then instructions in EL3 are counted. Otherwise, instructions in EL3 are not counted.

MMeaning
0b0

If PMICFILTR_EL0.P == 0, then this bit has no effect on filtering of instructions.

If PMICFILTR_EL0.P == 1, then instructions in EL3 are not counted.

0b1

If PMICFILTR_EL0.P == 0, then instructions in EL3 are not counted.

If PMICFILTR_EL0.P == 1, then this bit has no effect on filtering of instructions.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Bit [25]

Reserved, RES0.

SH, bit [24]
When EL3 is implemented and FEAT_SEL2 is implemented:

Secure EL2 filtering. Controls counting instructions in Secure EL2. If PMICFILTR_EL0.SH is not equal to PMICFILTR_EL0.NSH, then instructions in Secure EL2 are counted. Otherwise, instructions in Secure EL2 are not counted.

SHMeaning
0b0

If PMICFILTR_EL0.NSH == 0, then instructions in Secure EL2 are not counted.

If PMICFILTR_EL0.NSH == 1, then this bit has no effect on filtering of instructions.

0b1

If PMICFILTR_EL0.NSH == 0, then this bit has no effect on filtering of instructions.

If PMICFILTR_EL0.NSH == 1, then instructions in Secure EL2 are not counted.

The reset behavior of this field is:

Accessing this field has the following behavior:


Otherwise:

Reserved, RES0.

T, bit [23]
When FEAT_TME is implemented:

Non-transactional state filtering. Controls counting instructions in Non-transactional state.

TMeaning
0b0

This bit has no effect on filtering of instructions.

0b1

Instructions in Non-transactional state are not counted.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

RLK, bit [22]
When FEAT_RME is implemented:

Realm EL1 filtering. Controls counting instructions in Realm EL1. If PMICFILTR_EL0.RLK is equal to PMICFILTR_EL0.P, then instructions in Realm EL1 are counted. Otherwise, instructions in Realm EL1 are not counted.

RLKMeaning
0b0

If PMICFILTR_EL0.P == 0, then this bit has no effect on filtering of instructions.

If PMICFILTR_EL0.P == 1, then instructions in Realm EL1 are not counted.

0b1

If PMICFILTR_EL0.P == 0, then instructions in Realm EL1 are not counted.

If PMICFILTR_EL0.P == 1, then this bit has no effect on filtering of instructions.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

RLU, bit [21]
When FEAT_RME is implemented:

Realm EL0 filtering. Controls counting instructions in Realm EL0. If PMICFILTR_EL0.RLU is equal to PMICFILTR_EL0.U, then instructions in Realm EL0 are counted. Otherwise, instructions in Realm EL0 are not counted.

RLUMeaning
0b0

If PMICFILTR_EL0.U == 0, then this bit has no effect on filtering of instructions.

If PMICFILTR_EL0.U == 1, then instructions in Realm EL0 are not counted.

0b1

If PMICFILTR_EL0.U == 0, then instructions in Realm EL0 are not counted.

If PMICFILTR_EL0.U == 1, then this bit has no effect on filtering of instructions.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

RLH, bit [20]
When FEAT_RME is implemented:

Realm EL2 filtering. Controls counting instructions in Realm EL2. If PMICFILTR_EL0.RLH is not equal to PMICFILTR_EL0.NSH, then instructions in Realm EL2 are counted. Otherwise, instructions in Realm EL2 are not counted.

RLHMeaning
0b0

If PMICFILTR_EL0.NSH == 0, then instructions in Realm EL2 are not counted.

If PMICFILTR_EL0.NSH == 1, then this bit has no effect on filtering of instructions.

0b1

If PMICFILTR_EL0.NSH == 0, then this bit has no effect on filtering of instructions.

If PMICFILTR_EL0.NSH == 1, then instructions in Realm EL2 are not counted.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Bits [19:16]

Reserved, RES0.

evtCount, bits [15:0]

Event to count.

Reads as 0x0008.

Access to this field is RO.

Accessing PMICFILTR_EL0

Accesses to this register use the following encodings in the external debug interface:

BlockAccess at address 0x480

PMICFILTR_EL0 can be accessed through the PMU block as follows:

FrameOffset
PMU0x480

30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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