MFAR_EL3, Physical Fault Address Register (EL3)

The MFAR_EL3 characteristics are:

Purpose

Records the faulting physical address for a Granule Protection Check, synchronous External Abort, or SError exception taken to EL3.

Configuration

This register is present only when FEAT_PFAR is implemented or FEAT_RME is implemented. Otherwise, direct accesses to MFAR_EL3 are UNDEFINED.

Attributes

MFAR_EL3 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
NSNSERES0FPA[55:52]FPA[51:48]FPA[47:12]
FPA[47:12]RES0

An exception return at EL3 makes MFAR_EL3 UNKNOWN.

NS, bit [63]

Together with the NSE field, reports the physical address space of the access that triggered the exception.

NSENSMeaning
0b00b0When Secure state is implemented, Secure. Otherwise reserved.
0b00b1Non-secure.
0b10b0Root.
0b10b1Realm.

The reset behavior of this field is:

NSE, bit [62]

Together with the NS field, reports the physical address space of the access that triggered the exception.

For a description of the values derived by evaluating NS and NSE together, see MFAR_EL3.NS.

The reset behavior of this field is:

Bits [61:56]

Reserved, RES0.

FPA[55:52], bits [55:52]
When FEAT_D128 is implemented:

When FEAT_D128 is implemented, extension to FPA[47:12].

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

FPA[51:48], bits [51:48]
When FEAT_LPA is implemented:

When FEAT_LPA is implemented, extension to FPA[47:12].

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

FPA[47:12], bits [47:12]

Bits [47:12] of the faulting physical address.

For implementations with fewer than 48 physical address bits, the corresponding upper bits in this field are RES0.

When recording an address for a synchronous External Abort or SError exception, the recorded address can be any address within the same naturally-aligned fault granule as the faulting physical address, where the size of the fault granule is IMPLEMENTATION DEFINED, but must be no larger than:

The reset behavior of this field is:

Bits [11:0]

Reserved, RES0.

Accessing MFAR_EL3

MFAR_EL3 is not valid and reads UNKNOWN if ESR_EL3.PFV is recorded as 0 and ESR_EL3.EC is recorded indicating an Abort or SError exception.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, MFAR_EL3

op0op1CRnCRmop2
0b110b1100b01100b00000b101

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then X[t, 64] = MFAR_EL3;

MSR MFAR_EL3, <Xt>

op0op1CRnCRmop2
0b110b1100b01100b00000b101

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then MFAR_EL3 = X[t, 64];


30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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