no old file | htmldiff from- | (new) |
The TRBDEVAFF characteristics are:
For additional information, see the CoreSight Architecture Specification.
Reads the same value as the MPIDR_EL1 register for the PE that this trace buffer has affinity with.
Depending on the IMPLEMENTATION DEFINED nature of the system, it might be possible that TRBDEVAFF is read before system firmware has configured the trace buffer and/or the PE or group of PEs that the trace buffer has affinity with. When this is the case, TRBDEVAFF reads as zero.
This register is present only when FEAT_TRBE_EXT is implemented. Otherwise, direct accesses to TRBDEVAFF are RES0.
TRBDEVAFF is in the Core power domain.
TRBDEVAFF is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MPIDR_EL1 | |||||||||||||||||||||||||||||||
MPIDR_EL1 |
Read-only copy of MPIDR_EL1, as seen from the highest implemented Exception level.
Component | Offset | Instance |
---|---|---|
TRBE | 0xFA8 | TRBDEVAFF |
This interface is accessible as follows:
30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
no old file | htmldiff from- | (new) |