The GICD_INMIR<n> characteristics are:
Holds whether the corresponding SPI has the non-maskable property.
This register is present only when FEAT_GICv3_NMI is implemented. Otherwise, direct accesses to GICD_INMIR<n> are RES0.
When GICR_TYPER.NMI is 0, this register is RES0.
The number of implemented GICD_INMIR<n> registers is (GICD_TYPER.ITLinesNumber+1). Registers are numbered from 0.
GICD_INMIR<n> is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NMI31 | NMI30 | NMI29 | NMI28 | NMI27 | NMI26 | NMI25 | NMI24 | NMI23 | NMI22 | NMI21 | NMI20 | NMI19 | NMI18 | NMI17 | NMI16 | NMI15 | NMI14 | NMI13 | NMI12 | NMI11 | NMI10 | NMI9 | NMI8 | NMI7 | NMI6 | NMI5 | NMI4 | NMI3 | NMI2 | NMI1 | NMI0 |
Non-maskable property.
NMI<x> | Meaning |
---|---|
0b0 |
Interrupt does not have the non-maskable property. |
0b1 |
Interrupt has the non-maskable property. |
This bit is RES0 when the corresponding interrupt is configured as Group 0.
The reset behavior of this field is:
For INTID m, when DIV and MOD are the integer division and modulo operations:
For SGIs and PPIs:
When affinity routing is not enabled for the Security state of an interrupt in GICD_IGROUPR<n>E, the corresponding bit is RES0.
Bits corresponding to unimplemented interrupts are RAZ/WI.
When GICD_CTLR.DS==0, bits corresponding to Group 0 and Secure Group 1 interrupts are RAZ/WI to Non-secure accesses.
Implementations must ensure that an interrupt that is pending at the time of the write uses either the old value or the new value and must ensure that the interrupt is neither lost nor handled more than one time. The effect of the change must be visible in finite time.
Component | Frame | Offset | Instance |
---|---|---|---|
GIC Distributor | Dist_base | 0x0F80 + (4 * n) | GICD_INMIR<n> |
Accesses to this interface are RW.
30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f
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