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The PMSSCR_EL1 characteristics are:
Holds status information about the captured counters and provides a mechanism for software to initiate a sample.
This register is present only when FEAT_PMUv3_SS is implemented. Otherwise, direct accesses to PMSSCR_EL1 are RES0.
PMSSCR_EL1 is a 64-bit register.
This register is part of the PMU block.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | NC | ||||||||||||||||||||||||||||||
RES0 | SS |
Reserved, RES0.
No Capture. Indicates whether the PMU counters have been captured.
NC | Meaning |
---|---|
0b0 | PMU counters captured. |
0b1 | PMU counters not captured. |
The reset behavior of this field is:
Reserved, RES0.
Snapshot Capture and Status.
SS | Meaning |
---|---|
0b0 | On a read: The Capture event has completed. On a write: Ignored. |
0b1 | On a read: The Capture event has not completed. On a write: Initiate a capture immediately. |
It is CONSTRAINED UNPREDICTABLE whether a Capture event has completed if this field is modified when the Capture event is ongoing.
If FEAT_Debugv8p4 is implemented, the OPTIONAL Software Lock is not implemented.
The reset behavior of this field is:
Accessing this field has the following behavior:
Accesses to this register use the following encodings in the external debug interface:
PMSSCR_EL1 can be accessed through the PMU block as follows:
Frame | Offset |
---|---|
PMU | 0xE30 |
30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f
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