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The PMCFGR characteristics are:
Contains PMU-specific configuration data.
This register is present only when FEAT_PMUv3_EXT is implemented. Otherwise, direct accesses to PMCFGR are RES0.
PMCFGR is in the Core power domain.
PMCFGR is a: 32-bit register.
This register is part of the PMU block.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
NCG | RES0 | SS | FZO | RES0 | UEN | WT | NA | EX | CCD | CC | SIZE | N |
This feature is not supported, so this field is RAZ.
Reads as 0b0000.
Access to this field is RO.
Reserved, RES0.
Counter Groups. Defines the number of counter groups implemented, minus one.
Reads as 0b0001.
Access to this field is RO.
Defines the number of counter groups implemented, minus one.
This field reads-as-zero.
Reads as 0b0000.
Access to this field is RO.
Reserved, RES0.
Snapshot supported.
SS | Meaning |
---|---|
0b0 | Snapshot mechanism not supported. The locations 0x600-0x7FC and 0xE30-0xE3C are IMPLEMENTATION DEFINED. |
0b1 | Snapshot mechanism supported. PMSVR<n> and PMSSSCR are implemented. |
FEAT_PMUv3_SS implements the functionality identified by the value 1.
If FEAT_PMUv3_SS is not implemented, a PMU might include an IMPLEMENTATION DEFINED snapshot mechanism, including one using the IMPLEMENTATION DEFINED registers 0x600-0x7FC and 0xE30-0xE3C.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Freeze-on-overflow supported. Defined values are:
FZO | Meaning |
---|---|
0b0 | Freeze-on-overflow mechanism is not supported. PMU.PMCR_EL0.FZO is |
0b1 | Freeze-on-overflow mechanism is supported. PMU.PMCR_EL0.FZO is RW. |
FEAT_PMUv3p7 implements the functionality added by the value 0b1.
From Armv8.7, if FEAT_PMUv3 is implemented, the only permitted value is 0b1.
Reserved, RES0.
User-mode Enable Register supported. PMUSERENR_EL0 is not visible in the external debug interface, so this bit is RAZ.
Reads as 0b0.
Access to this field is RO.
This feature is not supported, so this bit is RAZ.
Reads as 0b0.
Access to this field is RO.
This feature is not supported, so this bit is RAZ.
Reads as 0b0.
Access to this field is RO.
Export supported. Value is IMPLEMENTATION DEFINED.
EX | Meaning |
---|---|
0b0 |
|
0b1 |
|
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Cycle counter has prescale.
This is RES1 if AArch32 is supported, and RAZ otherwise.
CCD | Meaning |
---|---|
0b0 |
|
0b1 |
|
Dedicated cycle counter (counter 31) supported.
Reads as 0b1.
Access to this field is RO.
Size of counters, minus one. This field defines the size of the largest counter implemented by the Performance Monitors Unit.
From Armv8, the largest counter is 64-bits, so the value of this field is 0b111111.
This field is used by software to determine the spacing of the counters in the memory-map. From Armv8, the counters are a doubleword-aligned addresses.
Reads as 0b111111.
Access to this field is RO.
Number of counters, minusimplemented one.in addition to the cycle counter,PMCCNTR_EL0. The maximum number of event counters is 31.
N | Meaning |
---|---|
0x00 | Only PMU.PMCCNTR_EL0 implemented. |
0x01..0x20 |
|
All other values are reserved.
The count includes the optional Instruction Counter, PMU.PMICNTR_EL0.
The count includes the Cycle Counter, PMU.PMCCNTR_EL0. For example, if N == 0x00, there is a single counter, PMU.PMCCNTR_EL0, and PMEVCNTR0_EL0 is not implemented.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NCG | RES0 | SS | FZO | RES0 | UEN | WT | NA | EX | CCD | CC | SIZE | N |
This interface is accessible as follows:
Counter Groups. Defines the number of counter groups implemented, minus one.
Reads as 0b0001.
Access to this field is RO.
Defines the number of counter groups implemented, minus one.
This field reads-as-zero.
Reads as 0b0000.
Access to this field is RO.
Reserved, RES0.
Snapshot supported.
SS | Meaning |
---|---|
0b0 | Snapshot mechanism not supported. The locations 0x600-0x7FC and 0xE30-0xE3C are IMPLEMENTATION DEFINED. |
0b1 | Snapshot mechanism supported. PMSVR<n> and PMSSSCR are implemented. |
FEAT_PMUv3_SS implements the functionality identified by the value 1.
If FEAT_PMUv3_SS is not implemented, a PMU might include an IMPLEMENTATION DEFINED snapshot mechanism, including one using the IMPLEMENTATION DEFINED registers 0x600-0x7FC and 0xE30-0xE3C.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Freeze-on-overflow supported. Defined values are:
FZO | Meaning |
---|---|
0b0 | Freeze-on-overflow mechanism is not supported. PMU.PMCR_EL0.FZO is RES0. |
0b1 | Freeze-on-overflow mechanism is supported. PMU.PMCR_EL0.FZO is RW. |
FEAT_PMUv3p7 implements the functionality added by the value 0b1.
From Armv8.7, if FEAT_PMUv3 is implemented, the only permitted value is 0b1.
Reserved, RES0.
User-mode Enable Register supported. PMUSERENR_EL0 is not visible in the external debug interface, so this bit is RAZ.
Reads as 0b0.
Access to this field is RO.
This feature is not supported, so this bit is RAZ.
Reads as 0b0.
Access to this field is RO.
This feature is not supported, so this bit is RAZ.
Reads as 0b0.
Access to this field is RO.
Export supported. Value is IMPLEMENTATION DEFINED.
EX | Meaning |
---|---|
0b0 | PMU.PMCR_EL0.X is RES0. |
0b1 | PMU.PMCR_EL0.X is read/write. |
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Cycle counter has prescale.
This is RES1 if AArch32 is supported, and RAZ otherwise.
CCD | Meaning |
---|---|
0b0 | PMU.PMCR_EL0.D is RES0. |
0b1 | PMU.PMCR_EL0.D is read/write. |
Dedicated cycle counter (counter 31) supported.
Reads as 0b1.
Access to this field is RO.
Size of counters, minus one. This field defines the size of the largest counter implemented by the Performance Monitors Unit.
From Armv8, the largest counter is 64-bits, so the value of this field is 0b111111.
This field is used by software to determine the spacing of the counters in the memory-map. From Armv8, the counters are a doubleword-aligned addresses.
Reads as 0b111111.
Access to this field is RO.
Number of counters, minus one.
N | Meaning |
---|---|
0x00 | Only PMU.PMCCNTR_EL0 implemented. |
0x01..0x20 | Number of counters implemented, 1 to 33. |
All other values are reserved.
The count includes the optional Instruction Counter, PMU.PMICNTR_EL0.
The count includes the Cycle Counter, PMU.PMCCNTR_EL0. For example, if N == 0x00, there is a single counter, PMU.PMCCNTR_EL0, and PMEVCNTR0_EL0 is not implemented.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.
Accesses to this register use the following encodings in the external debug interface:
PMCFGR can be accessed through the PMU block as follows:
Frame | Offset |
---|---|
PMU | 0xE00 |
3005/0907/2022 1517:5708; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96fb0421fa9a8865165f9b91af9b4a566111f866305
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