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The PMIAR_EL1 characteristics are:
Captures the address of the instruction generating a PMU exception.
This register is present only when FEAT_SEBEP is implemented. Otherwise, direct accesses to PMIAR_EL1 are UNDEFINED.
PMIAR_EL1 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EL | RES0 | ADDRESS | |||||||||||||||||||||||||||||
ADDRESS |
Exception Level.
EL | Meaning |
---|---|
0b00 | EL0. |
0b01 | EL1. |
0b10 | EL2. |
0b11 | EL3. |
The reset behavior of this field is:
Reserved, RES0.
Instruction virtual address.
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1001 | 0b1110 | 0b111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then X[t, 64] = PMIAR_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = PMIAR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = PMIAR_EL1;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b1001 | 0b1110 | 0b111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then PMIAR_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then PMIAR_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then PMIAR_EL1 = X[t, 64];
30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f
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