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The PMPIDR1 characteristics are:
Provides information to identify a Performance Monitor component.
For more information, see 'About the Peripheral identification scheme'.
ThisImplementation registerof isthis presentregister only when FEAT_PMUv3_EXT is implemented and an implementation implements PMPIDR1. Otherwise, direct accesses to PMPIDR1 are RES0OPTIONAL.
If FEAT_DoPD is implemented, this register is in the Core power domain. If FEAT_DoPD is not implemented, this register is in the Debug power domain.
This register is required for CoreSight compliance.
PMPIDR1 is a 32-bit register.
This register is part of the PMU block.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | DES_0 | PART_1 |
Reserved, RES0.
Designer, least significant nibble of JEP106 ID code. For Arm Limited, this field is 0b1011.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Part number, most significant nibble.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
This interface is accessible as follows:
Accesses to this register use the following encodings in the external debug interface:
PMPIDR1 can be accessed through the PMU block as follows:
Frame | Offset |
---|---|
PMU | 0xFE4 |
3005/0907/2022 1517:5707; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96fb0421fa9a8865165f9b91af9b4a566111f866305
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