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SPMCFGR_EL1, System Performance Monitors Configuration Register

The SPMCFGR_EL1 characteristics are:

Purpose

Describes the System Performance Monitor.

Configuration

This register is present only when FEAT_SPMU is implemented. Otherwise, direct accesses to SPMCFGR_EL1 are UNDEFINED.

Attributes

SPMCFGR_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
NCGRES0HDBGTROSSFZOMSIRAORES0NAEXRAZSIZEN

Bits [63:32]

Reserved, RES0.

NCG, bits [31:28]

Counter Groups.

Defines the number of counter groups implemented, minus one.

If this field is zero, then one counter group is implemented and SPMCGCR<n>_EL1 read-as-zero.

Otherwise, for each counter group <m>, SPMCGCR<m DIV 8>_EL1.N<m MOD 8> defines the number of counters in the group.

Locating the first counter in each group depends on the number of implemented groups. Each counter group starts with counter:

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Bits [27:25]

Reserved, RES0.

HDBG, bit [24]

Halt-on-debug supported. For more information on this field, see 'CoreSight PMU Architecture'.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

TRO, bit [23]

Trace output supported. For more information on this field, see 'CoreSight PMU Architecture'.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

SS, bit [22]

Snapshot supported. For more information on this field, see 'CoreSight PMU Architecture'.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

FZO, bit [21]

Freeze-on-overflow supported. For more information on this field, see 'CoreSight PMU Architecture'.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

MSI, bit [20]

Message-signaled interrupts supported. For more information on this field, see 'CoreSight PMU Architecture'.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Bit [19]

Reserved, RAO.

Bit [18]

Reserved, RES0.

NA, bit [17]

No write access when running. For more information on this field, see 'CoreSight PMU Architecture'.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

EX, bit [16]

Export supported. For more information on this field, see 'CoreSight PMU Architecture'.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Bits [15:14]

Reserved, RAZ.

SIZE, bits [13:8]

Counter size. The size of the largest implemented counter.

SIZEMeaning
0b000111

8-bit counters.

0b001001

10-bit counters.

0b001011

12-bit counters.

0b001111

16-bit counters.

0b010011

20-bit counters.

0b010111

24-bit counters.

0b011111

32-bit counters.

0b100011

36-bit counters.

0b100111

40-bit counters.

0b101011

44-bit counters.

0b101111

48-bit counters.

0b110011

52-bit counters.

0b110111

56-bit counters.

0b111111

64-bit counters.

All other values are reserved.

Not all counters must be this size. For example, an implementation might include a mix of 32-bit and 64-bit counters.

N, bits [7:0]

Number of event counters.

Accessing SPMCFGR_EL1

To access SPMCFGR_EL1 for System PMU <s>, set SPMSELR_EL0.SYSPMUSEL to s.

SPMCFGR_EL1 reads-as-zero if the System PMU selected by SPMSELR_EL0.SYSPMUSEL is not implemented.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, SPMCFGR_EL1

op0op1CRnCRmop2
0b100b0000b10010b11010b111

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then X[t, 64] = SPMCFGR_EL1[UInt(SPMSELR_EL0.SYSPMUSEL)]; elsif PSTATE.EL == EL2 then X[t, 64] = SPMCFGR_EL1[UInt(SPMSELR_EL0.SYSPMUSEL)]; elsif PSTATE.EL == EL3 then X[t, 64] = SPMCFGR_EL1[UInt(SPMSELR_EL0.SYSPMUSEL)];


30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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