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ID_AA64MMFR4_EL1, AArch64 Memory Model Feature Register 4

The ID_AA64MMFR4_EL1 characteristics are:

Purpose

Provides additional information about implemented memory model and memory management support in AArch64.

Configuration

There are no configuration notes.

Attributes

ID_AA64MMFR4_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0EIESBRES0

Bits [63:8]

Reserved, RES0.

EIESB, bits [7:4]
When FEAT_IESB is implemented:

Indicates whether the implicit Error synchronization event inserted on taking an exception is inserted before or after the exception is taken.

EIESBMeaning
0b0000

The behavior is not described.

0b0001

Implicit Error synchronization event is inserted before an exception is taken.

0b1111

Implicit Error synchronization event is inserted after an exception is taken.

All other values are reserved.

Implicit Error synchronization events are inserted on taking an exception to ELx when SCTLR_ELx.EISB is 0b1.

Inserting the event before the exception is taken means that if the Error synchronization event causes an SError exception to become pending, and SError exceptions are not masked and not disabled, then the SError exception is taken in place of the original exception.


Otherwise:

Reserved, RES0.

Bits [3:0]

Reserved, RES0.

Accessing ID_AA64MMFR4_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, ID_AA64MMFR4_EL1

op0op1CRnCRmop2
0b110b0000b00000b01110b100

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = ID_AA64MMFR4_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = ID_AA64MMFR4_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = ID_AA64MMFR4_EL1;


30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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