PMUACR_EL1, Performance Monitors User Access Control Register

The PMUACR_EL1 characteristics are:

Purpose

Enables or disables EL0 access to specfic Performance Monitors.

Configuration

This register is present only when FEAT_PMUv3p9 is implemented. Otherwise, direct accesses to PMUACR_EL1 are UNDEFINED.

Attributes

PMUACR_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0F0
CP30P29P28P27P26P25P24P23P22P21P20P19P18P17P16P15P14P13P12P11P10P9P8P7P6P5P4P3P2P1P0

Bits [63:33]

Reserved, RES0.

F<m>, bit [m+32], for m = 0
When FEAT_PMUv3_ICNTR is implemented:

EL0 access to fixed-function counter <m> enable.

F<m>Meaning
0b0

EL0 access to fixed-function counter <m> disabled when PMUSERENR_EL0.{UEN,EN} == {1,0}.

0b1

EL0 access to fixed-function counter <m> enabled when PMUSERENR_EL0.{UEN,EN} == {1,0}.

This bit is ignored by the PE when any of the following are true:

The reset behavior of this field is:

Accessing this field has the following behavior:


Otherwise:

Reserved, RES0.

C, bit [31]

EL0 access to PMCCNTR_EL0 enable.

CMeaning
0b0

EL0 access to PMCCNTR_EL0 disabled when PMUSERENR_EL0.{UEN,EN} == {1,0}.

0b1

EL0 access to PMCCNTR_EL0 enabled when PMUSERENR_EL0.{UEN,EN} == {1,0}.

This field is ignored by the PE when any of the following are true:

The reset behavior of this field is:

P<m>, bit [m], for m = 30 to 0

EL0 access to PMEVCNTR<m>_EL0 enable.

P<m>Meaning
0b0

EL0 access to PMEVCNTR<m>_EL0 disabled when PMUSERENR_EL0.{UEN,EN} == {1,0}.

0b1

EL0 access to PMEVCNTR<m>_EL0 enabled when PMUSERENR_EL0.{UEN,EN} == {1,0}.

This bit is ignored by the PE when any of the following are true:

Accessing this bit has the following behavior:

The reset behavior of this field is:

Accessing PMUACR_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PMUACR_EL1

op0op1CRnCRmop2
0b110b0000b10010b11100b100

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then X[t, 64] = PMUACR_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = PMUACR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = PMUACR_EL1;

MSR PMUACR_EL1, <Xt>

op0op1CRnCRmop2
0b110b0000b10010b11100b100

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then PMUACR_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then PMUACR_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then PMUACR_EL1 = X[t, 64];


30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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