SPMCR_EL0, System Performance Monitor Control Register

The SPMCR_EL0 characteristics are:

Purpose

Main control register for the System Performance Monitors.

Configuration

This register is present only when FEAT_SPMU is implemented. Otherwise, direct accesses to SPMCR_EL0 are UNDEFINED.

Attributes

SPMCR_EL0 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0TROHDBGFZONARES0EXRES0PE

Bits [63:12]

Reserved, RES0.

TRO, bit [11]
When SPMCFGR_EL1.TRO == 1:

Trace enable. For more information on this field, see 'CoreSight PMU Architecture'.

The reset behavior of this field is:

Accessing this field has the following behavior:


Otherwise:

Reserved, RES0.

HDBG, bit [10]
When SPMCFGR_EL1.HDBG == 1:

Halt-on-debug. For more information on this field, see 'CoreSight PMU Architecture'.

The reset behavior of this field is:

Accessing this field has the following behavior:


Otherwise:

Reserved, RES0.

FZO, bit [9]
When SPMCFGR_EL1.FZO == 1:

Freeze-on-overflow. For more information on this field, see 'CoreSight PMU Architecture'.

Note that, if implemented by a System PMU, then freeze-on-overflow affects only the counters of that System PMU, not other System PMUs nor the PE PMU.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

NA, bit [8]
When SPMCFGR_EL1.NA == 1:

Not accessible. For more information on this field, see 'CoreSight PMU Architecture'.

The reset behavior of this field is:

Access to this field is RO.


Otherwise:

Reserved, RES0.

Bits [7:5]

Reserved, RES0.

EX, bit [4]
When SPMCFGR_EL1.EX == 1:

Export enable. For more information on this field, see 'CoreSight PMU Architecture'.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Bits [3:2]

Reserved, RES0.

P, bit [1]

Event counter reset.

PMeaning
0b0

Write is ignored.

0b1

Reset all event counters to zero. If the cycle counter is implemented, the cycle counter is not reset.

Note

Resetting the event counters does not affect any overflow flags.

Access to this field is WO/RAZ.

E, bit [0]

Count enable. This bit controls the System Performance Monitor.

EMeaning
0b0

Monitor is disabled.

0b1

Monitor is enabled.

Performance monitor overflow IRQs are only signaled when this bit is set to 1.

The reset behavior of this field is:

Accessing SPMCR_EL0

To access SPMCR_EL0 for System PMU <s>, set SPMSELR_EL0.SYSPMUSEL to s.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, SPMCR_EL0

op0op1CRnCRmop2
0b100b0110b10010b11000b000

if PSTATE.EL == EL0 then X[t, 64] = SPMCR_EL0[UInt(SPMSELR_EL0.SYSPMUSEL)]; elsif PSTATE.EL == EL1 then X[t, 64] = SPMCR_EL0[UInt(SPMSELR_EL0.SYSPMUSEL)]; elsif PSTATE.EL == EL2 then X[t, 64] = SPMCR_EL0[UInt(SPMSELR_EL0.SYSPMUSEL)]; elsif PSTATE.EL == EL3 then X[t, 64] = SPMCR_EL0[UInt(SPMSELR_EL0.SYSPMUSEL)];

MSR SPMCR_EL0, <Xt>

op0op1CRnCRmop2
0b100b0110b10010b11000b000

if PSTATE.EL == EL0 then SPMCR_EL0[UInt(SPMSELR_EL0.SYSPMUSEL)] = X[t, 64]; elsif PSTATE.EL == EL1 then SPMCR_EL0[UInt(SPMSELR_EL0.SYSPMUSEL)] = X[t, 64]; elsif PSTATE.EL == EL2 then SPMCR_EL0[UInt(SPMSELR_EL0.SYSPMUSEL)] = X[t, 64]; elsif PSTATE.EL == EL3 then SPMCR_EL0[UInt(SPMSELR_EL0.SYSPMUSEL)] = X[t, 64];


30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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