(old) htmldiff from-(new)

External register index by offset

Below are indexes for external registers in the following blocks:

In the AMU block:

OffsetNameDescriptionAccess
0x000 + (8 * n)AMEVCNTR0<n>[31:0]Activity Monitors Event Counter Registers 0RO
0x004 + (8 * n)AMEVCNTR0<n>[63:32]Activity Monitors Event Counter Registers 0RO
0x100 + (8 * n)AMEVCNTR1<n>[31:0]Activity Monitors Event Counter Registers 1RO
0x104 + (8 * n)AMEVCNTR1<n>[63:32]Activity Monitors Event Counter Registers 1RO
0x400 + (4 * n)AMEVTYPER0<n>Activity Monitors Event Type Registers 0RO
0x480 + (4 * n)AMEVTYPER1<n>Activity Monitors Event Type Registers 1RO
0xC00AMCNTENSET0Activity Monitors Count Enable Set Register 0RO
0xC04AMCNTENSET1Activity Monitors Count Enable Set Register 1RO
0xC20AMCNTENCLR0Activity Monitors Count Enable Clear Register 0RO
0xC24AMCNTENCLR1Activity Monitors Count Enable Clear Register 1RO
0xCE0AMCGCRActivity Monitors Counter Group Configuration RegisterRO
0xE00AMCFGRActivity Monitors Configuration RegisterRO
0xE04AMCRActivity Monitors Control RegisterRO
0xE08AMIIDRActivity Monitors Implementation Identification RegisterRO
0xFA8AMDEVAFF0Activity Monitors Device Affinity Register 0RO
0xFACAMDEVAFF1Activity Monitors Device Affinity Register 1RO
0xFBCAMDEVARCHActivity Monitors Device Architecture RegisterRO
0xFCCAMDEVTYPEActivity Monitors Device Type RegisterRO
0xFD0AMPIDR4Activity Monitors Peripheral Identification Register 4RO
0xFE0AMPIDR0Activity Monitors Peripheral Identification Register 0RO
0xFE4AMPIDR1Activity Monitors Peripheral Identification Register 1RO
0xFE8AMPIDR2Activity Monitors Peripheral Identification Register 2RO
0xFECAMPIDR3Activity Monitors Peripheral Identification Register 3RO
0xFF0AMCIDR0Activity Monitors Component Identification Register 0RO
0xFF4AMCIDR1Activity Monitors Component Identification Register 1RO
0xFF8AMCIDR2Activity Monitors Component Identification Register 2RO
0xFFCAMCIDR3Activity Monitors Component Identification Register 3RO

In the CTI block:

OffsetNameDescriptionAccess
0x000CTICONTROLCTI Control registerRW
0x010CTIINTACKCTI Output Trigger Acknowledge registerWO
0x014CTIAPPSETCTI Application Trigger Set registerRW
0x018CTIAPPCLEARCTI Application Trigger Clear registerWO
0x01CCTIAPPPULSECTI Application Pulse registerWO
0x020 + (4 * n)CTIINEN<n>CTI Input Trigger to Output Channel Enable registersRW
0x0A0 + (4 * n)CTIOUTEN<n>CTI Input Channel to Output Trigger Enable registersRW
0x130CTITRIGINSTATUSCTI Trigger In Status registerRO
0x134CTITRIGOUTSTATUSCTI Trigger Out Status registerRO
0x138CTICHINSTATUSCTI Channel In Status registerRO
0x13CCTICHOUTSTATUSCTI Channel Out Status registerRO
0x140CTIGATECTI Channel Gate Enable registerRW
0x144ASICCTLCTI External Multiplexer Control registerRO
0x150CTIDEVCTLCTI Device Control registerRW
0xF00CTIITCTRLCTI Integration mode Control registerRW
0xFA0CTICLAIMSETCTI CLAIM Tag Set registerRW
0xFA4CTICLAIMCLRCTI CLAIM Tag Clear registerRW
0xFA8CTIDEVAFF0CTI Device Affinity register 0RO
0xFACCTIDEVAFF1CTI Device Affinity register 1RO
0xFB0CTILARCTI Lock Access RegisterWO
0xFB4CTILSRCTI Lock Status RegisterRO
0xFB8CTIAUTHSTATUSCTI Authentication Status registerRO
0xFBCCTIDEVARCHCTI Device Architecture registerRO
0xFC0CTIDEVID2CTI Device ID register 2RO
0xFC4CTIDEVID1CTI Device ID register 1RO
0xFC8CTIDEVIDCTI Device ID register 0RO
0xFCCCTIDEVTYPECTI Device Type registerRO
0xFD0CTIPIDR4CTI Peripheral Identification Register 4RO
0xFE0CTIPIDR0CTI Peripheral Identification Register 0RO
0xFE4CTIPIDR1CTI Peripheral Identification Register 1RO
0xFE8CTIPIDR2CTI Peripheral Identification Register 2RO
0xFECCTIPIDR3CTI Peripheral Identification Register 3RO
0xFF0CTICIDR0CTI Component Identification Register 0RO
0xFF4CTICIDR1CTI Component Identification Register 1RO
0xFF8CTICIDR2CTI Component Identification Register 2RO
0xFFCCTICIDR3CTI Component Identification Register 3RO

In the Debug block:

OffsetNameDescriptionAccess
0x020EDESRExternal Debug Event Status RegisterRW
0x024EDECRExternal Debug Execution Control RegisterRW
0x028EDSCR2External Debug Status and Control Register 2RW
0x030EDWAR[31:0]External Debug Watchpoint Address RegisterRO
0x034EDWAR[63:32]External Debug Watchpoint Address RegisterRO
0x03CEDHSR[63:32]External Debug Halt Status RegisterRO
0x038EDHSR[31:0]External Debug HaltingHalt SyndromeStatus RegisterRO
0x080DBGDTRRX_EL0Debug Data Transfer Register, ReceiveRW
0x084EDITRExternal Debug Instruction Transfer RegisterWO
0x088EDSCRExternal Debug Status and Control RegisterRW
0x08CDBGDTRTX_EL0Debug Data Transfer Register, TransmitRW
0x090EDRCRExternal Debug Reserve Control RegisterWO
0x094EDACRExternal Debug Auxiliary Control RegisterRW
0x098EDECCRExternal Debug Exception Catch Control RegisterRW
0x0A0EDPCSR[31:0]External Debug Program Counter Sample RegisterRO
0x0A4EDCIDSRExternal Debug Context ID Sample RegisterRO
0x0A8EDVIDSRExternal Debug Virtual Context Sample RegisterRO
0x0ACEDPCSR[63:32]External Debug Program Counter Sample RegisterRO
0x300OSLAR_EL1OS Lock Access RegisterWO
0x310EDPRCRExternal Debug Power/Reset Control RegisterRW
0x314EDPRSRExternal Debug Processor Status RegisterRO
0x400 + (16 * n)DBGBVR<n>_EL1[63:0]Debug Breakpoint Value RegistersRW
0x408 + (16 * n)DBGBCR<n>_EL1Debug Breakpoint Control RegistersRW
0x800 + (16 * n)DBGWVR<n>_EL1[63:0]Debug Watchpoint Value RegistersRW
0x808 + (16 * n)DBGWCR<n>_EL1Debug Watchpoint Control RegistersRW
0xD00MIDR_EL1Main ID RegisterRO
0xD20EDPFR[31:0]External Debug Processor Feature RegisterRO
0xD24EDPFR[63:32]External Debug Processor Feature RegisterRO
0xD28EDDFR[31:0]External Debug Feature RegisterRO
0xD2CEDDFR[63:32]External Debug Feature RegisterRO
0xD48EDDFR1External Debug Feature Register 1RO
0xD60EDAA32PFRExternal Debug Auxiliary Processor Feature RegisterRO
0xF00EDITCTRLExternal Debug Integration mode Control registerRW
0xFA0DBGCLAIMSET_EL1Debug CLAIM Tag Set registerRW
0xFA4DBGCLAIMCLR_EL1Debug CLAIM Tag Clear registerRW
0xFA8EDDEVAFF0External Debug Device Affinity register 0RO
0xFACEDDEVAFF1External Debug Device Affinity register 1RO
0xFB0EDLARExternal Debug Lock Access RegisterWO
0xFB4EDLSRExternal Debug Lock Status RegisterRO
0xFB8DBGAUTHSTATUS_EL1Debug Authentication Status registerRO
0xFBCEDDEVARCHExternal Debug Device Architecture registerRO
0xFC0EDDEVID2External Debug Device ID register 2RO
0xFC4EDDEVID1External Debug Device ID register 1RO
0xFC8EDDEVIDExternal Debug Device ID register 0RO
0xFCCEDDEVTYPEExternal Debug Device Type registerRO
0xFD0EDPIDR4External Debug Peripheral Identification Register 4RO
0xFE0EDPIDR0External Debug Peripheral Identification Register 0RO
0xFE4EDPIDR1External Debug Peripheral Identification Register 1RO
0xFE8EDPIDR2External Debug Peripheral Identification Register 2RO
0xFECEDPIDR3External Debug Peripheral Identification Register 3RO
0xFF0EDCIDR0External Debug Component Identification Register 0RO
0xFF4EDCIDR1External Debug Component Identification Register 1RO
0xFF8EDCIDR2External Debug Component Identification Register 2RO
0xFFCEDCIDR3External Debug Component Identification Register 3RO

In the ETE block:

OffsetNameDescriptionAccess
0x004TRCPRGCTLRProgramming Control RegisterRW
0x00CTRCSTATRTrace Status RegisterRO
0x010TRCCONFIGRTrace Configuration RegisterRW
0x018TRCAUXCTLRAuxiliary Control RegisterRW
0x020TRCEVENTCTL0REvent Control 0 RegisterRW
0x024TRCEVENTCTL1REvent Control 1 RegisterRW
0x028TRCRSRResources Status RegisterRW
0x02CTRCSTALLCTLRStall Control RegisterRW
0x030TRCTSCTLRTimestamp Control RegisterRW
0x034TRCSYNCPRSynchronization Period RegisterRW
0x038TRCCCCTLRCycle Count Control RegisterRW
0x03CTRCBBCTLRBranch Broadcast Control RegisterRW
0x040TRCTRACEIDRTrace ID RegisterRW
0x044TRCQCTLRQ Element Control RegisterRW
0x048TRCITEEDCRInstrumentation Trace Extension External Debug Control RegisterRW
0x080TRCVICTLRViewInst Main Control RegisterRW
0x084TRCVIIECTLRViewInst Include/Exclude Control RegisterRW
0x088TRCVISSCTLRViewInst Start/Stop Control RegisterRW
0x08CTRCVIPCSSCTLRViewInst Start/Stop PE Comparator Control RegisterRW
0x100 + (4 * n)TRCSEQEVR<n>Sequencer State Transition Control Register <n>RW
0x118TRCSEQRSTEVRSequencer Reset Control RegisterRW
0x11CTRCSEQSTRSequencer State RegisterRW
0x120 + (4 * n)TRCEXTINSELR<n>External Input Select Register <n>RW
0x140 + (4 * n)TRCCNTRLDVR<n>Counter Reload Value Register <n>RW
0x150 + (4 * n)TRCCNTCTLR<n>Counter Control Register <n>RW
0x160 + (4 * n)TRCCNTVR<n>Counter Value Register <n>RW
0x180TRCIDR8ID Register 8RO
0x184TRCIDR9ID Register 9RO
0x188TRCIDR10ID Register 10RO
0x18CTRCIDR11ID Register 11RO
0x190TRCIDR12ID Register 12RO
0x194TRCIDR13ID Register 13RO
0x1C0TRCIMSPEC0IMP DEF Register 0RW
0x1C0 + (4 * n)TRCIMSPEC<n>IMP DEF Register <n>RW
0x1E0TRCIDR0ID Register 0RO
0x1E4TRCIDR1ID Register 1RO
0x1E8TRCIDR2ID Register 2RO
0x1ECTRCIDR3ID Register 3RO
0x1F0TRCIDR4ID Register 4RO
0x1F4TRCIDR5ID Register 5RO
0x1F8TRCIDR6ID Register 6RO
0x1FCTRCIDR7ID Register 7RO
0x200 + (4 * n)TRCRSCTLR<n>Resource Selection Control Register <n>RW
0x280 + (4 * n)TRCSSCCR<n>Single-shot Comparator Control Register <n>RW
0x2A0 + (4 * n)TRCSSCSR<n>Single-shot Comparator Control Status Register <n>RW
0x2C0 + (4 * n)TRCSSPCICR<n>Single-shot Processing Element Comparator Input Control Register <n>RW
0x304TRCOSLSRTrace OS Lock Status RegisterRO
0x310TRCPDCRPowerDown Control RegisterRW
0x314TRCPDSRPowerDown Status RegisterRO
0x400 + (8 * n)TRCACVR<n>Address Comparator Value Register <n>RW
0x480 + (8 * n)TRCACATR<n>Address Comparator Access Type Register <n>RW
0x600 + (8 * n)TRCCIDCVR<n>Context Identifier Comparator Value Registers <n>RW
0x640 + (8 * n)TRCVMIDCVR<n>Virtual Context Identifier Comparator Value Register <n>RW
0x680TRCCIDCCTLR0Context Identifier Comparator Control Register 0RW
0x684TRCCIDCCTLR1Context Identifier Comparator Control Register 1RW
0x688TRCVMIDCCTLR0Virtual Context Identifier Comparator Control Register 0RW
0x68CTRCVMIDCCTLR1Virtual Context Identifier Comparator Control Register 1RW
0xF00TRCITCTRLIntegration Mode Control RegisterRW
0xFA0TRCCLAIMSETClaim Tag Set RegisterRW
0xFA4TRCCLAIMCLRClaim Tag Clear RegisterRW
0xFA8TRCDEVAFFDevice Affinity RegisterRO
0xFB0TRCLARLock Access RegisterWO
0xFB4TRCLSRLock Status RegisterRO
0xFB8TRCAUTHSTATUSAuthentication Status RegisterRO
0xFBCTRCDEVARCHDevice Architecture RegisterRO
0xFC0TRCDEVID2Device Configuration Register 2RO
0xFC4TRCDEVID1Device Configuration Register 1RO
0xFC8TRCDEVIDDevice Configuration RegisterRO
0xFCCTRCDEVTYPEDevice Type RegisterRO
0xFD0TRCPIDR4Peripheral Identification Register 4RO
0xFD4TRCPIDR5Peripheral Identification Register 5RO
0xFD8TRCPIDR6Peripheral Identification Register 6RO
0xFDCTRCPIDR7Peripheral Identification Register 7RO
0xFE0TRCPIDR0Peripheral Identification Register 0RO
0xFE4TRCPIDR1Peripheral Identification Register 1RO
0xFE8TRCPIDR2Peripheral Identification Register 2RO
0xFECTRCPIDR3Peripheral Identification Register 3RO
0xFF0TRCCIDR0Component Identification Register 0RO
0xFF4TRCCIDR1Component Identification Register 1RO
0xFF8TRCCIDR2Component Identification Register 2RO
0xFFCTRCCIDR3Component Identification Register 3RO

In the GIC CPU interface block:

OffsetNameDescriptionAccess
0x0000GICC_CTLRCPU Interface Control RegisterRW
0x0004GICC_PMRCPU Interface Priority Mask RegisterRW
0x0008GICC_BPRCPU Interface Binary Point RegisterRW
0x000CGICC_IARCPU Interface Interrupt Acknowledge RegisterRO
0x0010GICC_EOIRCPU Interface End Of Interrupt RegisterWO
0x0014GICC_RPRCPU Interface Running Priority RegisterRO
0x0018GICC_HPPIRCPU Interface Highest Priority Pending Interrupt RegisterRO
0x001CGICC_ABPRCPU Interface Aliased Binary Point RegisterRW
0x0020GICC_AIARCPU Interface Aliased Interrupt Acknowledge RegisterRO
0x0024GICC_AEOIRCPU Interface Aliased End Of Interrupt RegisterWO
0x0028GICC_AHPPIRCPU Interface Aliased Highest Priority Pending Interrupt RegisterRO
0x002CGICC_STATUSRCPU Interface Status RegisterRW
0x002CGICC_STATUSRCPU Interface Status RegisterRW
0x00D0 + (4 * n)GICC_APR<n>CPU Interface Active Priorities RegistersRW
0x00E0 + (4 * n)GICC_NSAPR<n>CPU Interface Non-secure Active Priorities RegistersRW
0x00FCGICC_IIDRCPU Interface Identification RegisterRO
0x1000GICC_DIRCPU Interface Deactivate Interrupt RegisterWO

In the GIC Distributor block:

In the Dist_base block:

OffsetNameDescriptionAccess
0x0000GICD_CTLRDistributor Control RegisterRW
0x0004GICD_TYPERInterrupt Controller Type RegisterRO
0x0008GICD_IIDRDistributor Implementer Identification RegisterRO
0x000CGICD_TYPER2Interrupt Controller Type Register 2RO
0x0010GICD_STATUSRError Reporting Status RegisterRW
0x0010GICD_STATUSRError Reporting Status RegisterRW
0x0040GICD_SETSPI_NSRSet Non-secure SPI Pending RegisterWO
0x0048GICD_CLRSPI_NSRClear Non-secure SPI Pending RegisterWO
0x0050GICD_SETSPI_SRSet Secure SPI Pending RegisterWO
0x0058GICD_CLRSPI_SRClear Secure SPI Pending RegisterWO
0x0080 + (4 * n)GICD_IGROUPR<n>Interrupt Group RegistersRW
0x0100 + (4 * n)GICD_ISENABLER<n>Interrupt Set-Enable RegistersRW
0x0180 + (4 * n)GICD_ICENABLER<n>Interrupt Clear-Enable RegistersRW
0x0200 + (4 * n)GICD_ISPENDR<n>Interrupt Set-Pending RegistersRW
0x0280 + (4 * n)GICD_ICPENDR<n>Interrupt Clear-Pending RegistersRW
0x0300 + (4 * n)GICD_ISACTIVER<n>Interrupt Set-Active RegistersRW
0x0380 + (4 * n)GICD_ICACTIVER<n>Interrupt Clear-Active RegistersRW
0x0400 + (4 * n)GICD_IPRIORITYR<n>Interrupt Priority RegistersRW
0x0800 + (4 * n)GICD_ITARGETSR<n>Interrupt Processor Targets RegistersRW
0x0C00 + (4 * n)GICD_ICFGR<n>Interrupt Configuration RegistersRW
0x0D00 + (4 * n)GICD_IGRPMODR<n>Interrupt Group Modifier RegistersRW
0x0E00 + (4 * n)GICD_NSACR<n>Non-secure Access Control RegistersRW
0x0F00GICD_SGIRSoftware Generated Interrupt RegisterWO
0x0F10 + (4 * n)GICD_CPENDSGIR<n>SGI Clear-Pending RegistersRW
0x0F20 + (4 * n)GICD_SPENDSGIR<n>SGI Set-Pending RegistersRW
0x0F80 + (4 * n)GICD_INMIR<n>Non-maskable Interrupt Registers, x = 0 to 31RW
0x1000 + (4 * n)GICD_IGROUPR<n>EInterrupt Group Registers (extended SPI range)RW
0x1200 + (4 * n)GICD_ISENABLER<n>EInterrupt Set-Enable RegistersRW
0x1400 + (4 * n)GICD_ICENABLER<n>EInterrupt Clear-Enable RegistersRW
0x1600 + (4 * n)GICD_ISPENDR<n>EInterrupt Set-Pending Registers (extended SPI range)RW
0x1800 + (4 * n)GICD_ICPENDR<n>EInterrupt Clear-Pending Registers (extended SPI range)RW
0x1A00 + (4 * n)GICD_ISACTIVER<n>EInterrupt Set-Active Registers (extended SPI range)RW
0x1C00 + (4 * n)GICD_ICACTIVER<n>EInterrupt Clear-Active Registers (extended SPI range)RW
0x2000 + (4 * n)GICD_IPRIORITYR<n>EHolds the priority of the corresponding interrupt for each extended SPI supported by the GIC.RW
0x3000 + (4 * n)GICD_ICFGR<n>EInterrupt Configuration Registers (Extended SPI Range)RW
0x3400 + (4 * n)GICD_IGRPMODR<n>EInterrupt Group Modifier Registers (extended SPI range)RW
0x3600 + (4 * n)GICD_NSACR<n>ENon-secure Access Control RegistersRW
0x3B00 + (4 * n)GICD_INMIR<n>ENon-maskable Interrupt Registers for Extended SPIs, x = 0 to 31RW
0x6000 + (8 * n)GICD_IROUTER<n>Interrupt Routing RegistersRW
0x8000 + (8 * n)GICD_IROUTER<n>EInterrupt Routing Registers (Extended SPI Range)RW

In the MSI_base block:

OffsetNameDescriptionAccess
0x0004GICM_TYPERDistributor MSI Type RegisterRO
0x0040GICM_SETSPI_NSRSet Non-secure SPI Pending RegisterWO
0x0048GICM_CLRSPI_NSRClear Non-secure SPI Pending RegisterWO
0x0050GICM_SETSPI_SRSet Secure SPI Pending RegisterWO
0x0058GICM_CLRSPI_SRClear Secure SPI Pending RegisterWO
0x0FCCGICM_IIDRDistributor Implementer Identification RegisterRO

In the GIC ITS control block:

OffsetNameDescriptionAccess
0x0000GITS_CTLRITS Control RegisterRW
0x0004GITS_IIDRITS Identification RegisterRO
0x0008GITS_TYPERITS Type RegisterRO
0x0010GITS_MPAMIDRReport maximum PARTID and PMG RegisterRO
0x0014GITS_PARTIDRSet PARTID and PMG RegisterRW
0x0018GITS_MPIDRReport ITS's affinity.RO
0x0040GITS_STATUSRITS Error Reporting Status RegisterRW
0x0048GITS_UMSIRITS Unmapped MSI registerRO
0x0080GITS_CBASERITS Command Queue DescriptorRW
0x0088GITS_CWRITERITS Write RegisterRW
0x0090GITS_CREADRITS Read RegisterRO
0x0100 + (8 * n)GITS_BASER<n>ITS Translation Table DescriptorsRW
0x20020GITS_SGIRITS SGI RegisterWO

In the GIC ITS translation block:

OffsetNameDescriptionAccess
0x0040GITS_TRANSLATERITS Translation RegisterWO

In the GIC Redistributor block:

In the RD_base block:

OffsetNameDescriptionAccess
0x0000GICR_CTLRRedistributor Control RegisterRW
0x0004GICR_IIDRRedistributor Implementer Identification RegisterRO
0x0008GICR_TYPERRedistributor Type RegisterRO
0x0010GICR_STATUSRError Reporting Status RegisterRW
0x0010GICR_STATUSRError Reporting Status RegisterRW
0x0014GICR_WAKERRedistributor Wake RegisterRW
0x0018GICR_MPAMIDRReport maximum PARTID and PMG RegisterRO
0x001CGICR_PARTIDRSet PARTID and PMG RegisterRW
0x0040GICR_SETLPIRSet LPI Pending RegisterWO
0x0048GICR_CLRLPIRClear LPI Pending RegisterWO
0x0070GICR_PROPBASERRedistributor Properties Base Address RegisterRW
0x0078GICR_PENDBASERRedistributor LPI Pending Table Base Address RegisterRW
0x00A0GICR_INVLPIRRedistributor Invalidate LPI RegisterWO
0x00B0GICR_INVALLRRedistributor Invalidate All RegisterWO
0x00C0GICR_SYNCRRedistributor Synchronize RegisterRO

In the SGI_base block:

OffsetNameDescriptionAccess
0x0080GICR_IGROUPR0Interrupt Group Register 0RW
0x0080 + (4 * n)GICR_IGROUPR<n>EInterrupt Group RegistersRW
0x0100GICR_ISENABLER0Interrupt Set-Enable Register 0RW
0x0100 + (4 * n)GICR_ISENABLER<n>EInterrupt Set-Enable RegistersRW
0x0180GICR_ICENABLER0Interrupt Clear-Enable Register 0RW
0x0180 + (4 * n)GICR_ICENABLER<n>EInterrupt Clear-Enable RegistersRW
0x0200GICR_ISPENDR0Interrupt Set-Pending Register 0RW
0x0200 + (4 * n)GICR_ISPENDR<n>EInterrupt Set-Pending RegistersRW
0x0280GICR_ICPENDR0Interrupt Clear-Pending Register 0RW
0x0280 + (4 * n)GICR_ICPENDR<n>EInterrupt Clear-Pending RegistersRW
0x0300GICR_ISACTIVER0Interrupt Set-Active Register 0RW
0x0300 + (4 * n)GICR_ISACTIVER<n>EInterrupt Set-Active RegistersRW
0x0380GICR_ICACTIVER0Interrupt Clear-Active Register 0RW
0x0380 + (4 * n)GICR_ICACTIVER<n>EInterrupt Clear-Active RegistersRW
0x0400 + (4 * n)GICR_IPRIORITYR<n>Interrupt Priority RegistersRW
0x0400 + (4 * n)GICR_IPRIORITYR<n>EInterrupt Priority Registers (extended PPI range)RW
0x0400 + (4 * n)GICR_IPRIORITYR<n>Interrupt Priority RegistersRW
0x0C00GICR_ICFGR0Interrupt Configuration Register 0RW
0x0C00 + (4 * n)GICR_ICFGR<n>EInterrupt configuration registersRW
0x0C04GICR_ICFGR1Interrupt Configuration Register 1RW
0x0D00GICR_IGRPMODR0Interrupt Group Modifier Register 0RW
0x0D00 + (4 * n)GICR_IGRPMODR<n>EInterrupt Group Modifier RegistersRW
0x0E00GICR_NSACRNon-secure Access Control RegisterRW
0x0F80GICR_INMIR0Non-maskable Interrupt Register for PPIs.RW
0x0F80 + (4 * n)GICR_INMIR<n>ENon-maskable Interrupt Registers for Extended PPIs, x = 1 to 2.RW

In the VLPI_base block:

OffsetNameDescriptionAccess
0x0070GICR_VPROPBASERVirtual Redistributor Properties Base Address RegisterRW
0x0078GICR_VPENDBASERVirtual Redistributor LPI Pending Table Base Address RegisterRW
0x0080GICR_VSGIRRedistributor virtual SGI pending state request registerWO
0x0088GICR_VSGIPENDRRedistributor virtual SGI pending state registerRO

In the GIC Virtual CPU interface block:

OffsetNameDescriptionAccess
0x0000GICV_CTLRVirtual Machine Control RegisterRW
0x0004GICV_PMRVirtual Machine Priority Mask RegisterRW
0x0008GICV_BPRVirtual Machine Binary Point RegisterRW
0x000CGICV_IARVirtual Machine Interrupt Acknowledge RegisterRO
0x0010GICV_EOIRVirtual Machine End Of Interrupt RegisterWO
0x0014GICV_RPRVirtual Machine Running Priority RegisterRO
0x0018GICV_HPPIRVirtual Machine Highest Priority Pending Interrupt RegisterRO
0x001CGICV_ABPRVirtual Machine Aliased Binary Point RegisterRW
0x0020GICV_AIARVirtual Machine Aliased Interrupt Acknowledge RegisterRO
0x0024GICV_AEOIRVirtual Machine Aliased End Of Interrupt RegisterWO
0x0028GICV_AHPPIRVirtual Machine Aliased Highest Priority Pending Interrupt RegisterRO
0x002CGICV_STATUSRVirtual Machine Error Reporting Status RegisterRW
0x00D0 + (4 * n)GICV_APR<n>Virtual Machine Active Priorities RegistersRW
0x00FCGICV_IIDRVirtual Machine CPU Interface Identification RegisterRO
0x1000GICV_DIRVirtual Machine Deactivate Interrupt RegisterWO

In the GIC Virtual interface control block:

OffsetNameDescriptionAccess
0x0000GICH_HCRHypervisor Control RegisterRW
0x0004GICH_VTRVirtual Type RegisterRO
0x0008GICH_VMCRVirtual Machine Control RegisterRW
0x0010GICH_MISRMaintenance Interrupt Status RegisterRO
0x0020GICH_EISREnd Interrupt Status RegisterRO
0x0030GICH_ELRSREmpty List Register Status RegisterRO
0x00F0 + (4 * n)GICH_APR<n>Active Priorities RegistersRW
0x0100 + (4 * n)GICH_LR<n>List RegistersRW

In the MPAM block:

In the MPAMF_BASE_ns block:

OffsetNameDescriptionAccess
0x0000MPAMF_IDRMPAM Features Identification RegisterRO
0x0018MPAMF_IIDRMPAM Implementation Identification RegisterRO
0x0020MPAMF_AIDRMPAM Architecture Identification RegisterRO
0x0028MPAMF_IMPL_IDRMPAM Implementation-Specific Partitioning Feature Identification RegisterRO
0x0030MPAMF_CPOR_IDRMPAM Features Cache Portion Partitioning ID registerRO
0x0038MPAMF_CCAP_IDRMPAM Features Cache Capacity Partitioning ID registerRO
0x0040MPAMF_MBW_IDRMPAM Memory Bandwidth Partitioning Identification RegisterRO
0x0048MPAMF_PRI_IDRMPAM Priority Partitioning Identification RegisterRO
0x0050MPAMF_PARTID_NRW_IDRMPAM PARTID Narrowing ID registerRO
0x0080MPAMF_MSMON_IDRMPAM Resource Monitoring Identification RegisterRO
0x0088MPAMF_CSUMON_IDRMPAM Features Cache Storage Usage Monitoring ID registerRO
0x0090MPAMF_MBWUMON_IDRMPAM Features Memory Bandwidth Usage Monitoring ID registerRO
0x00DCMPAMF_ERR_MSI_MPAMMPAM Error MSI Write MPAM Information RegisterRW
0x00E0MPAMF_ERR_MSI_ADDR_LMPAM Error MSI Low-part Address RegisterRW
0x00E4MPAMF_ERR_MSI_ADDR_HMPAM Error MSI High-part Address RegisterRW
0x00E8MPAMF_ERR_MSI_DATAMPAM Error MSI Data RegisterRW
0x00ECMPAMF_ERR_MSI_ATTRMPAM Error MSI Write Attributes RegisterRW
0x00F0MPAMF_ECRMPAM Error Control RegisterRW
0x00F8MPAMF_ESRMPAM Error Status RegisterRW
0x0100MPAMCFG_PART_SELMPAM Partition Configuration Selection RegisterRW
0x0108MPAMCFG_CMAXMPAM Cache Maximum Capacity Partition Configuration RegisterRW
0x0110MPAMCFG_CMINMPAM Cache Minimum Capacity Partition Configuration RegisterRW
0x0118MPAMCFG_CASSOCMPAM Cache Maximum Associativity Partition Configuration RegisterRW
0x0200MPAMCFG_MBW_MINMPAM Memory Bandwidth Minimum Partition Configuration RegisterRW
0x0208MPAMCFG_MBW_MAXMPAM Memory Bandwidth Maximum Partition Configuration RegisterRW
0x0220MPAMCFG_MBW_WINWDMPAM Memory Bandwidth Partitioning Window Width Configuration RegisterRW
0x0300MPAMCFG_ENMPAM Partition Configuration Enable RegisterWO/RAZ
0x0310MPAMCFG_DISMPAM Partition Configuration Disable RegisterWO/RAZ
0x0320MPAMCFG_EN_FLAGSMPAM Partition Configuration Enable Flags RegisterRW
0x0400MPAMCFG_PRIMPAM Priority Partition Configuration RegisterRW
0x0500MPAMCFG_MBW_PROPMPAM Memory Bandwidth Proportional Stride Partition Configuration RegisterRW
0x0600MPAMCFG_INTPARTIDMPAM Internal PARTID Narrowing Configuration RegisterRW
0x0800MSMON_CFG_MON_SELMPAM Monitor Instance Selection RegisterRW
0x0808MSMON_CAPT_EVNTMPAM Capture Event Generation RegisterWO/RAZ
0x0810MSMON_CFG_CSU_FLTMPAM Memory System Monitor Configure Cache Storage Usage Monitor Filter RegisterRW
0x0818MSMON_CFG_CSU_CTLMPAM Memory System Monitor Configure Cache Storage Usage Monitor Control RegisterRW
0x0820MSMON_CFG_MBWU_FLTMPAM Memory System Monitor Configure Memory Bandwidth Usage Monitor Filter RegisterRW
0x0828MSMON_CFG_MBWU_CTLMPAM Memory System Monitor Configure Memory Bandwidth Usage Monitor Control RegisterRW
0x0840MSMON_CSUMPAM Cache Storage Usage Monitor RegisterRW
0x0848MSMON_CSU_CAPTUREMPAM Cache Storage Usage Monitor Capture RegisterRW
0x0858MSMON_CSU_OFSRMPAM CSU Monitor Overflow Status RegisterRO
0x0860MSMON_MBWUMPAM Memory Bandwidth Usage Monitor RegisterRW
0x0868MSMON_MBWU_CAPTUREMPAM Memory Bandwidth Usage Monitor Capture RegisterRW
0x0880MSMON_MBWU_LMPAM Long Memory Bandwidth Usage Monitor RegisterRW
0x0890MSMON_MBWU_L_CAPTUREMPAM Long Memory Bandwidth Usage Monitor Capture RegisterRW
0x0898MSMON_MBWU_OFSRMPAM MBWU Monitor Overflow Status RegisterRO
0x08DCMSMON_OFLOW_MSI_MPAMMPAM Monitor Overflow MSI Write MPAM Information RegisterRW
0x08E0MSMON_OFLOW_MSI_ADDR_LMPAM Monitor Overflow MSI Low-part Address RegisterRW
0x08E4MSMON_OFLOW_MSI_ADDR_HMPAM Monitor Overflow MSI Write High-part Address RegisterRW
0x08E8MSMON_OFLOW_MSI_DATAMPAM Monitor Overflow MSI Write Data RegisterRW
0x08ECMSMON_OFLOW_MSI_ATTRMPAM Monitor Overflow MSI Write Attributes RegisterRW
0x08F0MSMON_OFLOW_SRMPAM Monitor Overflow Status RegisterRO
0x1000 + (4 * n)MPAMCFG_CPBM<n>MPAM Cache Portion Bitmap Partition Configuration RegisterRW
0x2000 + (4 * n)MPAMCFG_MBW_PBM<n>MPAM Bandwidth Portion Bitmap Partition Configuration RegisterRW

In the MPAMF_BASE_rl block:

OffsetNameDescriptionAccess
0x0000MPAMF_IDRMPAM Features Identification RegisterRO
0x0018MPAMF_IIDRMPAM Implementation Identification RegisterRO
0x0020MPAMF_AIDRMPAM Architecture Identification RegisterRO
0x0028MPAMF_IMPL_IDRMPAM Implementation-Specific Partitioning Feature Identification RegisterRO
0x0030MPAMF_CPOR_IDRMPAM Features Cache Portion Partitioning ID registerRO
0x0038MPAMF_CCAP_IDRMPAM Features Cache Capacity Partitioning ID registerRO
0x0040MPAMF_MBW_IDRMPAM Memory Bandwidth Partitioning Identification RegisterRO
0x0048MPAMF_PRI_IDRMPAM Priority Partitioning Identification RegisterRO
0x0050MPAMF_PARTID_NRW_IDRMPAM PARTID Narrowing ID registerRO
0x0080MPAMF_MSMON_IDRMPAM Resource Monitoring Identification RegisterRO
0x0088MPAMF_CSUMON_IDRMPAM Features Cache Storage Usage Monitoring ID registerRO
0x0090MPAMF_MBWUMON_IDRMPAM Features Memory Bandwidth Usage Monitoring ID registerRO
0x00DCMPAMF_ERR_MSI_MPAMMPAM Error MSI Write MPAM Information RegisterRW
0x00E0MPAMF_ERR_MSI_ADDR_LMPAM Error MSI Low-part Address RegisterRW
0x00E4MPAMF_ERR_MSI_ADDR_HMPAM Error MSI High-part Address RegisterRW
0x00E8MPAMF_ERR_MSI_DATAMPAM Error MSI Data RegisterRW
0x00ECMPAMF_ERR_MSI_ATTRMPAM Error MSI Write Attributes RegisterRW
0x00F0MPAMF_ECRMPAM Error Control RegisterRW
0x00F8MPAMF_ESRMPAM Error Status RegisterRW
0x0100MPAMCFG_PART_SELMPAM Partition Configuration Selection RegisterRW
0x0108MPAMCFG_CMAXMPAM Cache Maximum Capacity Partition Configuration RegisterRW
0x0110MPAMCFG_CMINMPAM Cache Minimum Capacity Partition Configuration RegisterRW
0x0118MPAMCFG_CASSOCMPAM Cache Maximum Associativity Partition Configuration RegisterRW
0x0200MPAMCFG_MBW_MINMPAM Memory Bandwidth Minimum Partition Configuration RegisterRW
0x0208MPAMCFG_MBW_MAXMPAM Memory Bandwidth Maximum Partition Configuration RegisterRW
0x0220MPAMCFG_MBW_WINWDMPAM Memory Bandwidth Partitioning Window Width Configuration RegisterRW
0x0300MPAMCFG_ENMPAM Partition Configuration Enable RegisterWO/RAZ
0x0310MPAMCFG_DISMPAM Partition Configuration Disable RegisterWO/RAZ
0x0320MPAMCFG_EN_FLAGSMPAM Partition Configuration Enable Flags RegisterRW
0x0400MPAMCFG_PRIMPAM Priority Partition Configuration RegisterRW
0x0500MPAMCFG_MBW_PROPMPAM Memory Bandwidth Proportional Stride Partition Configuration RegisterRW
0x0600MPAMCFG_INTPARTIDMPAM Internal PARTID Narrowing Configuration RegisterRW
0x0800MSMON_CFG_MON_SELMPAM Monitor Instance Selection RegisterRW
0x0808MSMON_CAPT_EVNTMPAM Capture Event Generation RegisterWO/RAZ
0x0810MSMON_CFG_CSU_FLTMPAM Memory System Monitor Configure Cache Storage Usage Monitor Filter RegisterRW
0x0818MSMON_CFG_CSU_CTLMPAM Memory System Monitor Configure Cache Storage Usage Monitor Control RegisterRW
0x0820MSMON_CFG_MBWU_FLTMPAM Memory System Monitor Configure Memory Bandwidth Usage Monitor Filter RegisterRW
0x0828MSMON_CFG_MBWU_CTLMPAM Memory System Monitor Configure Memory Bandwidth Usage Monitor Control RegisterRW
0x0840MSMON_CSUMPAM Cache Storage Usage Monitor RegisterRW
0x0848MSMON_CSU_CAPTUREMPAM Cache Storage Usage Monitor Capture RegisterRW
0x0858MSMON_CSU_OFSRMPAM CSU Monitor Overflow Status RegisterRO
0x0860MSMON_MBWUMPAM Memory Bandwidth Usage Monitor RegisterRW
0x0868MSMON_MBWU_CAPTUREMPAM Memory Bandwidth Usage Monitor Capture RegisterRW
0x0880MSMON_MBWU_LMPAM Long Memory Bandwidth Usage Monitor RegisterRW
0x0890MSMON_MBWU_L_CAPTUREMPAM Long Memory Bandwidth Usage Monitor Capture RegisterRW
0x0898MSMON_MBWU_OFSRMPAM MBWU Monitor Overflow Status RegisterRO
0x08DCMSMON_OFLOW_MSI_MPAMMPAM Monitor Overflow MSI Write MPAM Information RegisterRW
0x08E0MSMON_OFLOW_MSI_ADDR_LMPAM Monitor Overflow MSI Low-part Address RegisterRW
0x08E4MSMON_OFLOW_MSI_ADDR_HMPAM Monitor Overflow MSI Write High-part Address RegisterRW
0x08E8MSMON_OFLOW_MSI_DATAMPAM Monitor Overflow MSI Write Data RegisterRW
0x08ECMSMON_OFLOW_MSI_ATTRMPAM Monitor Overflow MSI Write Attributes RegisterRW
0x08F0MSMON_OFLOW_SRMPAM Monitor Overflow Status RegisterRO
0x1000 + (4 * n)MPAMCFG_CPBM<n>MPAM Cache Portion Bitmap Partition Configuration RegisterRW
0x2000 + (4 * n)MPAMCFG_MBW_PBM<n>MPAM Bandwidth Portion Bitmap Partition Configuration RegisterRW

In the MPAMF_BASE_rt block:

OffsetNameDescriptionAccess
0x0000MPAMF_IDRMPAM Features Identification RegisterRO
0x0018MPAMF_IIDRMPAM Implementation Identification RegisterRO
0x0020MPAMF_AIDRMPAM Architecture Identification RegisterRO
0x0028MPAMF_IMPL_IDRMPAM Implementation-Specific Partitioning Feature Identification RegisterRO
0x0030MPAMF_CPOR_IDRMPAM Features Cache Portion Partitioning ID registerRO
0x0038MPAMF_CCAP_IDRMPAM Features Cache Capacity Partitioning ID registerRO
0x0040MPAMF_MBW_IDRMPAM Memory Bandwidth Partitioning Identification RegisterRO
0x0048MPAMF_PRI_IDRMPAM Priority Partitioning Identification RegisterRO
0x0050MPAMF_PARTID_NRW_IDRMPAM PARTID Narrowing ID registerRO
0x0080MPAMF_MSMON_IDRMPAM Resource Monitoring Identification RegisterRO
0x0088MPAMF_CSUMON_IDRMPAM Features Cache Storage Usage Monitoring ID registerRO
0x0090MPAMF_MBWUMON_IDRMPAM Features Memory Bandwidth Usage Monitoring ID registerRO
0x00DCMPAMF_ERR_MSI_MPAMMPAM Error MSI Write MPAM Information RegisterRW
0x00E0MPAMF_ERR_MSI_ADDR_LMPAM Error MSI Low-part Address RegisterRW
0x00E4MPAMF_ERR_MSI_ADDR_HMPAM Error MSI High-part Address RegisterRW
0x00E8MPAMF_ERR_MSI_DATAMPAM Error MSI Data RegisterRW
0x00ECMPAMF_ERR_MSI_ATTRMPAM Error MSI Write Attributes RegisterRW
0x00F0MPAMF_ECRMPAM Error Control RegisterRW
0x00F8MPAMF_ESRMPAM Error Status RegisterRW
0x0100MPAMCFG_PART_SELMPAM Partition Configuration Selection RegisterRW
0x0108MPAMCFG_CMAXMPAM Cache Maximum Capacity Partition Configuration RegisterRW
0x0110MPAMCFG_CMINMPAM Cache Minimum Capacity Partition Configuration RegisterRW
0x0118MPAMCFG_CASSOCMPAM Cache Maximum Associativity Partition Configuration RegisterRW
0x0200MPAMCFG_MBW_MINMPAM Memory Bandwidth Minimum Partition Configuration RegisterRW
0x0208MPAMCFG_MBW_MAXMPAM Memory Bandwidth Maximum Partition Configuration RegisterRW
0x0220MPAMCFG_MBW_WINWDMPAM Memory Bandwidth Partitioning Window Width Configuration RegisterRW
0x0300MPAMCFG_ENMPAM Partition Configuration Enable RegisterWO/RAZ
0x0310MPAMCFG_DISMPAM Partition Configuration Disable RegisterWO/RAZ
0x0320MPAMCFG_EN_FLAGSMPAM Partition Configuration Enable Flags RegisterRW
0x0400MPAMCFG_PRIMPAM Priority Partition Configuration RegisterRW
0x0500MPAMCFG_MBW_PROPMPAM Memory Bandwidth Proportional Stride Partition Configuration RegisterRW
0x0600MPAMCFG_INTPARTIDMPAM Internal PARTID Narrowing Configuration RegisterRW
0x0800MSMON_CFG_MON_SELMPAM Monitor Instance Selection RegisterRW
0x0808MSMON_CAPT_EVNTMPAM Capture Event Generation RegisterWO/RAZ
0x0810MSMON_CFG_CSU_FLTMPAM Memory System Monitor Configure Cache Storage Usage Monitor Filter RegisterRW
0x0818MSMON_CFG_CSU_CTLMPAM Memory System Monitor Configure Cache Storage Usage Monitor Control RegisterRW
0x0820MSMON_CFG_MBWU_FLTMPAM Memory System Monitor Configure Memory Bandwidth Usage Monitor Filter RegisterRW
0x0828MSMON_CFG_MBWU_CTLMPAM Memory System Monitor Configure Memory Bandwidth Usage Monitor Control RegisterRW
0x0840MSMON_CSUMPAM Cache Storage Usage Monitor RegisterRW
0x0848MSMON_CSU_CAPTUREMPAM Cache Storage Usage Monitor Capture RegisterRW
0x0858MSMON_CSU_OFSRMPAM CSU Monitor Overflow Status RegisterRO
0x0860MSMON_MBWUMPAM Memory Bandwidth Usage Monitor RegisterRW
0x0868MSMON_MBWU_CAPTUREMPAM Memory Bandwidth Usage Monitor Capture RegisterRW
0x0880MSMON_MBWU_LMPAM Long Memory Bandwidth Usage Monitor RegisterRW
0x0890MSMON_MBWU_L_CAPTUREMPAM Long Memory Bandwidth Usage Monitor Capture RegisterRW
0x0898MSMON_MBWU_OFSRMPAM MBWU Monitor Overflow Status RegisterRO
0x08DCMSMON_OFLOW_MSI_MPAMMPAM Monitor Overflow MSI Write MPAM Information RegisterRW
0x08E0MSMON_OFLOW_MSI_ADDR_LMPAM Monitor Overflow MSI Low-part Address RegisterRW
0x08E4MSMON_OFLOW_MSI_ADDR_HMPAM Monitor Overflow MSI Write High-part Address RegisterRW
0x08E8MSMON_OFLOW_MSI_DATAMPAM Monitor Overflow MSI Write Data RegisterRW
0x08ECMSMON_OFLOW_MSI_ATTRMPAM Monitor Overflow MSI Write Attributes RegisterRW
0x08F0MSMON_OFLOW_SRMPAM Monitor Overflow Status RegisterRO
0x1000 + (4 * n)MPAMCFG_CPBM<n>MPAM Cache Portion Bitmap Partition Configuration RegisterRW
0x2000 + (4 * n)MPAMCFG_MBW_PBM<n>MPAM Bandwidth Portion Bitmap Partition Configuration RegisterRW

In the MPAMF_BASE_s block:

OffsetNameDescriptionAccess
0x0000MPAMF_IDRMPAM Features Identification RegisterRO
0x0008MPAMF_SIDRMPAM Features Secure Identification RegisterRO
0x0018MPAMF_IIDRMPAM Implementation Identification RegisterRO
0x0020MPAMF_AIDRMPAM Architecture Identification RegisterRO
0x0028MPAMF_IMPL_IDRMPAM Implementation-Specific Partitioning Feature Identification RegisterRO
0x0030MPAMF_CPOR_IDRMPAM Features Cache Portion Partitioning ID registerRO
0x0038MPAMF_CCAP_IDRMPAM Features Cache Capacity Partitioning ID registerRO
0x0040MPAMF_MBW_IDRMPAM Memory Bandwidth Partitioning Identification RegisterRO
0x0048MPAMF_PRI_IDRMPAM Priority Partitioning Identification RegisterRO
0x0050MPAMF_PARTID_NRW_IDRMPAM PARTID Narrowing ID registerRO
0x0080MPAMF_MSMON_IDRMPAM Resource Monitoring Identification RegisterRO
0x0088MPAMF_CSUMON_IDRMPAM Features Cache Storage Usage Monitoring ID registerRO
0x0090MPAMF_MBWUMON_IDRMPAM Features Memory Bandwidth Usage Monitoring ID registerRO
0x00DCMPAMF_ERR_MSI_MPAMMPAM Error MSI Write MPAM Information RegisterRW
0x00E0MPAMF_ERR_MSI_ADDR_LMPAM Error MSI Low-part Address RegisterRW
0x00E4MPAMF_ERR_MSI_ADDR_HMPAM Error MSI High-part Address RegisterRW
0x00E8MPAMF_ERR_MSI_DATAMPAM Error MSI Data RegisterRW
0x00ECMPAMF_ERR_MSI_ATTRMPAM Error MSI Write Attributes RegisterRW
0x00F0MPAMF_ECRMPAM Error Control RegisterRW
0x00F8MPAMF_ESRMPAM Error Status RegisterRW
0x0100MPAMCFG_PART_SELMPAM Partition Configuration Selection RegisterRW
0x0108MPAMCFG_CMAXMPAM Cache Maximum Capacity Partition Configuration RegisterRW
0x0110MPAMCFG_CMINMPAM Cache Minimum Capacity Partition Configuration RegisterRW
0x0118MPAMCFG_CASSOCMPAM Cache Maximum Associativity Partition Configuration RegisterRW
0x0200MPAMCFG_MBW_MINMPAM Memory Bandwidth Minimum Partition Configuration RegisterRW
0x0208MPAMCFG_MBW_MAXMPAM Memory Bandwidth Maximum Partition Configuration RegisterRW
0x0220MPAMCFG_MBW_WINWDMPAM Memory Bandwidth Partitioning Window Width Configuration RegisterRW
0x0300MPAMCFG_ENMPAM Partition Configuration Enable RegisterWO/RAZ
0x0310MPAMCFG_DISMPAM Partition Configuration Disable RegisterWO/RAZ
0x0320MPAMCFG_EN_FLAGSMPAM Partition Configuration Enable Flags RegisterRW
0x0400MPAMCFG_PRIMPAM Priority Partition Configuration RegisterRW
0x0500MPAMCFG_MBW_PROPMPAM Memory Bandwidth Proportional Stride Partition Configuration RegisterRW
0x0600MPAMCFG_INTPARTIDMPAM Internal PARTID Narrowing Configuration RegisterRW
0x0800MSMON_CFG_MON_SELMPAM Monitor Instance Selection RegisterRW
0x0808MSMON_CAPT_EVNTMPAM Capture Event Generation RegisterWO/RAZ
0x0810MSMON_CFG_CSU_FLTMPAM Memory System Monitor Configure Cache Storage Usage Monitor Filter RegisterRW
0x0818MSMON_CFG_CSU_CTLMPAM Memory System Monitor Configure Cache Storage Usage Monitor Control RegisterRW
0x0820MSMON_CFG_MBWU_FLTMPAM Memory System Monitor Configure Memory Bandwidth Usage Monitor Filter RegisterRW
0x0828MSMON_CFG_MBWU_CTLMPAM Memory System Monitor Configure Memory Bandwidth Usage Monitor Control RegisterRW
0x0840MSMON_CSUMPAM Cache Storage Usage Monitor RegisterRW
0x0848MSMON_CSU_CAPTUREMPAM Cache Storage Usage Monitor Capture RegisterRW
0x0858MSMON_CSU_OFSRMPAM CSU Monitor Overflow Status RegisterRO
0x0860MSMON_MBWUMPAM Memory Bandwidth Usage Monitor RegisterRW
0x0868MSMON_MBWU_CAPTUREMPAM Memory Bandwidth Usage Monitor Capture RegisterRW
0x0880MSMON_MBWU_LMPAM Long Memory Bandwidth Usage Monitor RegisterRW
0x0890MSMON_MBWU_L_CAPTUREMPAM Long Memory Bandwidth Usage Monitor Capture RegisterRW
0x0898MSMON_MBWU_OFSRMPAM MBWU Monitor Overflow Status RegisterRO
0x08DCMSMON_OFLOW_MSI_MPAMMPAM Monitor Overflow MSI Write MPAM Information RegisterRW
0x08E0MSMON_OFLOW_MSI_ADDR_LMPAM Monitor Overflow MSI Low-part Address RegisterRW
0x08E4MSMON_OFLOW_MSI_ADDR_HMPAM Monitor Overflow MSI Write High-part Address RegisterRW
0x08E8MSMON_OFLOW_MSI_DATAMPAM Monitor Overflow MSI Write Data RegisterRW
0x08ECMSMON_OFLOW_MSI_ATTRMPAM Monitor Overflow MSI Write Attributes RegisterRW
0x08F0MSMON_OFLOW_SRMPAM Monitor Overflow Status RegisterRO
0x1000 + (4 * n)MPAMCFG_CPBM<n>MPAM Cache Portion Bitmap Partition Configuration RegisterRW
0x2000 + (4 * n)MPAMCFG_MBW_PBM<n>MPAM Bandwidth Portion Bitmap Partition Configuration RegisterRW

In the PMU block:

OffsetNameDescriptionAccessAccessor ConditionRegister Condition
0x000 + (8 * n) for n in 30:0PMEVCNTR<n>_EL0Performance Monitors Event Count RegistersRW-When FEAT_PMUv3_EXT is implemented
0x0F8PMCCNTR_EL0PMCCNTR_EL0[31:0]Performance Monitors Cycle CounterRW-When FEAT_PMUv3_EXT is implemented
0x1000x0FCPMICNTR_EL0PMCCNTR_EL0[63:32]Performance Monitors InstructionCycle Counter RegisterRWWhen FEAT_PMUv3_ICNTR is implemented-When FEAT_PMUv3_ICNTR is implemented
0x200PMPCSRPMPCSR[31:0]Program Counter Sample RegisterRO-When FEAT_PMUv3_EXT is implemented and FEAT_PCSRv8p2 is implemented
0x2080x204PMCID1SRPMPCSR[63:32]CONTEXTIDR_EL1Program Counter Sample RegisterROWhen FEAT_PMUv3_EXT32 is implemented-When FEAT_PMUv3_EXT32 is implemented and FEAT_PCSRv8p2 is implemented
0x208PMVCIDSRPMCID1SRCONTEXTIDR_EL1 and VMID Sample RegisterROWhen FEAT_PMUv3_EXT64 is implemented-When FEAT_PMUv3_EXT64 is implemented and FEAT_PCSRv8p2 is implemented
0x20CPMVIDSRVMID Sample RegisterROWhen FEAT_PMUv3_EXT32 is implemented-When FEAT_PMUv3_EXT32 is implemented, FEAT_PCSRv8p2 is implemented and EL2 is implemented
0x220PMPCSRPMPCSR[31:0]Program Counter Sample RegisterRO-When FEAT_PMUv3_EXT is implemented and FEAT_PCSRv8p2 is implemented
0x2280x224PMCID1SRPMPCSR[63:32]CONTEXTIDR_EL1Program Counter Sample RegisterROWhen FEAT_PMUv3_EXT32 is implemented-When FEAT_PMUv3_EXT32 is implemented and FEAT_PCSRv8p2 is implemented
0x228PMCCIDSRPMCID1SRCONTEXTIDR_ELxCONTEXTIDR_EL1 Sample RegisterROWhen FEAT_PMUv3_EXT64 is implemented-When FEAT_PMUv3_EXT is implemented
0x22CPMCID2SRCONTEXTIDR_EL2 Sample RegisterROWhen FEAT_PMUv3_EXT32 is implemented-When FEAT_PMUv3_EXT32 is implemented
0x2300x400 + (4 * n)PMPCSCTLPMEVTYPER<n>_EL0[31:0]PCPerformance Sample-basedMonitors ProfilingEvent ControlType RegisterRegistersRWWhen FEAT_PCSRv8p9FEAT_PMUv3_TH is implemented or FEAT_PMUv3p8 is implementedWhen FEAT_PCSRv8p9 is implemented
0x400 + (4 * n) for n in 30:00x47CPMEVTYPER<n>_EL0[31:0]PMCCFILTR_EL0Performance Monitors EventCycle TypeCounter RegistersFilter RegisterRWWhen FEAT_PMUv3_EXT32 is implemented-When FEAT_PMUv3_EXT is implemented
0x4000xA00 + (84 * n) for n in 30:0PMEVTYPER<n>_EL0[63:0]PMEVTYPER<n>_EL0[63:32]Performance Monitors Event Type RegistersRWWhen FEAT_PMUv3_EXT64FEAT_PMUv3_TH is implemented or FEAT_PMUv3p8 is implementedWhen FEAT_PMUv3_EXT is implemented
0x47C0xC00PMCCFILTR_EL0PMCNTENSET_EL0Performance Monitors CycleCount CounterEnable FilterSet RegisterregisterRWWhen FEAT_PMUv3_EXT32 is implemented-When FEAT_PMUv3_EXT is implemented
0x4800xC20PMICFILTR_EL0PMCNTENCLR_EL0Performance Monitors InstructionCount CounterEnable FilterClear RegisterregisterRWWhen FEAT_PMUv3_ICNTR is implemented-When FEAT_PMUv3_ICNTR is implemented
0x4F80xC40PMCCFILTR_EL0PMINTENSET_EL1Performance Monitors CycleInterrupt CounterEnable FilterSet RegisterregisterRWWhen FEAT_PMUv3_EXT64 is implemented-When FEAT_PMUv3_EXT is implemented
0x600 + (8 * n) for n in 30:00xC60PMEVCNTSVR<n>_EL1PMINTENCLR_EL1Performance Monitors EventInterrupt CountEnable SavedClear Value Register <n>registerRORWWhen FEAT_PMUv3_SS is implemented-When FEAT_PMUv3_SS is implemented
0x6F80xC80PMCCNTSVR_EL1PMOVSCLR_EL0Performance Monitors CycleOverflow CountFlag SavedStatus ValueClear RegisterregisterRORWWhen FEAT_PMUv3_SS is implemented-When FEAT_PMUv3_SS is implemented
0x7000xCA0PMICNTSVR_EL1PMSWINC_EL0Performance Monitors InstructionSoftware CountIncrement Saved Value RegisterregisterROWOWhen FEAT_PMUv3_SS is implemented and FEAT_PMUv3_ICNTR is implemented-When FEAT_PMUv3_ICNTR is implemented and FEAT_PMUv3_SS is implemented
0xA00 + (4 * n) for n in 30:00xCC0PMEVTYPER<n>_EL0[63:32]PMOVSSET_EL0Performance Monitors EventOverflow TypeFlag RegistersStatus Set registerRWWhen FEAT_PMUv3_EXT32 is implemented-When FEAT_PMUv3_EXT is implemented
0xC000xE00PMCNTENSET_EL0PMCFGRPerformance Monitors CountConfiguration Enable Set registerRegisterRWROWhen FEAT_PMUv3_EXT32 is implemented-When FEAT_PMUv3_EXT is implemented
0xC040xE04PMCNTENSET_EL0[63:32]PMCR_EL0Performance Monitors CountControl Enable Set registerRegisterRWWhen FEAT_PMUv3_EXT32 is implemented and (FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented)-When FEAT_PMUv3_EXT is implemented
0xC100xE20PMCNTENPMCEID0Performance Monitors CountCommon EnableEvent Identification register 0RWROWhen FEAT_PMUv3_EXT64 is implemented-When FEAT_PMUv3_EXT64 is implemented
0xC200xE24PMCNTENCLR_EL0PMCEID1Performance Monitors CountCommon EnableEvent ClearIdentification register 1RWROWhen FEAT_PMUv3_EXT32 is implemented-When FEAT_PMUv3_EXT is implemented
0xC240xE28PMCNTENCLR_EL0[63:32]PMCEID2Performance Monitors CountCommon EnableEvent ClearIdentification register 2RWROWhen FEAT_PMUv3_EXT32 is implemented and (FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented)-When FEAT_PMUv3_EXT is implemented
0xC400xE2CPMINTENSET_EL1PMCEID3Performance Monitors InterruptCommon EnableEvent SetIdentification register 3RWROWhen FEAT_PMUv3_EXT32 is implemented-When FEAT_PMUv3_EXT is implemented
0xC440xE40PMINTENSET_EL1[63:32]PMMIRPerformance Monitors InterruptMachine EnableIdentification Set registerRegisterRWROWhen FEAT_PMUv3_EXT32 is implemented and (FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented)-When FEAT_PMUv3_EXT is implemented
0xC500xF00PMINTENPMITCTRLPerformance Monitors InterruptIntegration Enablemode Control registerRWWhen FEAT_PMUv3_EXT64 is implemented-When FEAT_PMUv3_EXT64 is implemented
0xC600xFA8PMINTENCLR_EL1PMDEVAFF0Performance Monitors InterruptDevice EnableAffinity Clearregister register0RWROWhen FEAT_PMUv3_EXT32 is implemented-When FEAT_PMUv3_EXT is implemented
0xC640xFACPMINTENCLR_EL1[63:32]PMDEVAFF1Performance Monitors InterruptDevice EnableAffinity Clearregister register1RWROWhen FEAT_PMUv3_EXT32 is implemented and (FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented)-When FEAT_PMUv3_EXT is implemented
0xC800xFB0PMOVSCLR_EL0PMLARPerformance Monitors OverflowLock FlagAccess Status Clear registerRegisterRWWOWhen FEAT_PMUv3_EXT32 is implemented-When FEAT_PMUv3_EXT is implemented
0xC840xFB4PMOVSCLR_EL0[63:32]PMLSRPerformance Monitors OverflowLock Flag Status Clear registerRegisterRWROWhen FEAT_PMUv3_EXT32 is implemented and (FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented)-When FEAT_PMUv3_EXT is implemented
0xC900xFB8PMOVSPMAUTHSTATUSPerformance Monitors Overflow FlagAuthentication Status registerRWROWhen FEAT_PMUv3_EXT64 is implemented-When FEAT_PMUv3_EXT64 is implemented
0xCA00xFBCPMSWINC_EL0PMDEVARCHPerformance Monitors SoftwareDevice IncrementArchitecture registerWOROWhen FEAT_PMUv3_EXT32 is implemented-When FEAT_PMUv3_EXT32 is implemented and an implementation implements PMSWINC_EL0
0xCC00xFC8PMOVSSET_EL0PMDEVIDPerformance Monitors OverflowDevice Flag Status SetID registerRWROWhen FEAT_PMUv3_EXT32 is implemented-When FEAT_PMUv3_EXT is implemented
0xCC40xFCCPMOVSSET_EL0[63:32]PMDEVTYPEPerformance Monitors OverflowDevice Flag Status SetType registerRWROWhen FEAT_PMUv3_EXT32 is implemented and (FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented)-When FEAT_PMUv3_EXT is implemented
0xCE00xFD0PMCGCR0PMPIDR4CounterPerformance GroupMonitors ConfigurationPeripheral Identification Register 04ROWhen FEAT_PMUv3_ICNTR is implemented-When FEAT_PMUv3_ICNTR is implemented
0xE000xFE0PMCFGRPMPIDR0Performance Monitors ConfigurationPeripheral Identification Register 0RO-When FEAT_PMUv3_EXT is implemented
0xE040xFE4PMCR_EL0PMPIDR1Performance Monitors ControlPeripheral Identification Register 1RWROWhen FEAT_PMUv3_EXT32 is implemented-When FEAT_PMUv3_EXT is implemented
0xE080xFE8PMIIDRPMPIDR2Performance Monitors ImplementationPeripheral Identification Register 2ROWhen FEAT_PMUv3_EXT64 is implemented-When (FEAT_PMUv3_EXT32 is implemented and an implementation implements PMIIDR) or FEAT_PMUv3_EXT64 is implemented
0xE100xFECPMCR_EL0PMPIDR3Performance Monitors ControlPeripheral Identification Register 3RWROWhen FEAT_PMUv3_EXT64 is implemented-When FEAT_PMUv3_EXT is implemented
0xE200xFF0PMCEID0PMCIDR0Performance Monitors CommonComponent Event Identification registerRegister 0ROWhen FEAT_PMUv3_EXT32 is implemented-When FEAT_PMUv3_EXT32 is implemented
0xE240xFF4PMCEID1PMCIDR1Performance Monitors CommonComponent Event Identification registerRegister 1ROWhen FEAT_PMUv3_EXT32 is implemented-When FEAT_PMUv3_EXT32 is implemented
0xE280xFF8PMCEID2PMCIDR2Performance Monitors CommonComponent Event Identification registerRegister 2ROWhen FEAT_PMUv3_EXT32 is implemented-When FEAT_PMUv3_EXT32 is implemented and FEAT_PMUv3p1 is implemented
0xE2C0xFFCPMCEID3PMCIDR3Performance Monitors CommonComponent Event Identification registerRegister 3ROWhen FEAT_PMUv3_EXT32 is implemented-When FEAT_PMUv3_EXT32 is implemented and FEAT_PMUv3p1 is implemented
0xE30PMSSCR_EL1Performance Monitors Snapshot Status and Capture RegisterRWWhen FEAT_PMUv3_SS is implementedWhen FEAT_PMUv3_SS is implemented
0xE40PMMIRPerformance Monitors Machine Identification RegisterRO-When FEAT_PMUv3_EXT is implemented and FEAT_PMUv3p4 is implemented
0xF00PMITCTRLPerformance Monitors Integration mode Control registerRWWhen FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT32 is implemented and an implementation implements PMITCTRL
0xFA8PMDEVAFFPerformance Monitors Device Affinity registerROWhen FEAT_PMUv3_EXT64 is implementedWhen FEAT_PMUv3_EXT64 is implemented
0xFA8PMDEVAFF0Performance Monitors Device Affinity register 0ROWhen FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT32 is implemented
0xFACPMDEVAFF1Performance Monitors Device Affinity register 1ROWhen FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT32 is implemented
0xFB0PMLARPerformance Monitors Lock Access RegisterWOWhen FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT32 is implemented
0xFB4PMLSRPerformance Monitors Lock Status RegisterROWhen FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT32 is implemented
0xFB8PMAUTHSTATUSPerformance Monitors Authentication Status registerRO-When FEAT_PMUv3_EXT is implemented
0xFBCPMDEVARCHPerformance Monitors Device Architecture registerRO-When FEAT_PMUv3_EXT is implemented
0xFC8PMDEVIDPerformance Monitors Device ID registerROWhen FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT32 is implemented
0xFCCPMDEVTYPEPerformance Monitors Device Type registerRO-When an implementation implements PMDEVTYPE
0xFD0PMPIDR4Performance Monitors Peripheral Identification Register 4RO-When FEAT_PMUv3_EXT is implemented and an implementation implements PMPIDR4
0xFE0PMPIDR0Performance Monitors Peripheral Identification Register 0RO-When FEAT_PMUv3_EXT is implemented and an implementation implements PMPIDR0
0xFE4PMPIDR1Performance Monitors Peripheral Identification Register 1RO-When FEAT_PMUv3_EXT is implemented and an implementation implements PMPIDR1
0xFE8PMPIDR2Performance Monitors Peripheral Identification Register 2RO-When FEAT_PMUv3_EXT is implemented and an implementation implements PMPIDR2
0xFECPMPIDR3Performance Monitors Peripheral Identification Register 3RO-When FEAT_PMUv3_EXT is implemented and an implementation implements PMPIDR3
0xFF0PMCIDR0Performance Monitors Component Identification Register 0RO-When FEAT_PMUv3_EXT is implemented and an implementation implements PMCIDR0
0xFF4PMCIDR1Performance Monitors Component Identification Register 1RO-When FEAT_PMUv3_EXT is implemented and an implementation implements PMCIDR1
0xFF8PMCIDR2Performance Monitors Component Identification Register 2RO-When FEAT_PMUv3_EXT is implemented and an implementation implements PMCIDR2
0xFFCPMCIDR3Performance Monitors Component Identification Register 3RO-When FEAT_PMUv3_EXT is implemented and an implementation implements PMCIDR3

In the RAS block:

OffsetNameDescriptionAccess
0x000 + (64 * n)ERR<n>FRError Record <n> Feature RegisterRO
0x008 + (64 * n)ERR<n>CTLRError Record <n> Control RegisterRW
0x010 + (64 * n)ERR<n>STATUSError Record <n> Primary Status RegisterRW
0x018 + (64 * n)ERR<n>ADDRError Record <n> Address RegisterRW
0x020 + (64 * n)ERR<n>MISC0Error Record <n> Miscellaneous Register 0RW
0x028 + (64 * n)ERR<n>MISC1Error Record <n> Miscellaneous Register 1RW
0x030 + (64 * n)ERR<n>MISC2Error Record <n> Miscellaneous Register 2RW
0x038 + (64 * n)ERR<n>MISC3Error Record <n> Miscellaneous Register 3RW
0x800 + (64 * n)ERR<n>PFGFError Record <n> Pseudo-fault Generation Feature RegisterRO
0x800 + (8 * n)ERRIMPDEF<n>IMPLEMENTATION DEFINED Register <n>RW
0x808 + (64 * n)ERR<n>PFGCTLError Record <n> Pseudo-fault Generation Control RegisterRW
0x810 + (64 * n)ERR<n>PFGCDNError Record <n> Pseudo-fault Generation Countdown RegisterRW
0xE00ERRGSRError Group Status RegisterRO
0xE10ERRIIDRImplementation Identification RegisterRO
0xE80ERRFHICR0Fault Handling Interrupt Configuration Register 0RW
0xE80 + (8 * n)ERRIRQCR<n>Generic Error Interrupt Configuration Register <n>RW
0xE88ERRFHICR1Fault Handling Interrupt Configuration Register 1RW
0xE8CERRFHICR2Fault Handling Interrupt Configuration Register 2RW
0xE90ERRERICR0Error Recovery Interrupt Configuration Register 0RW
0xE98ERRERICR1Error Recovery Interrupt Configuration Register 1RW
0xE9CERRERICR2Error Recovery Interrupt Configuration Register 2RW
0xEA0ERRCRICR0Critical Error Interrupt Configuration Register 0RW
0xEA8ERRCRICR1Critical Error Interrupt Configuration Register 1RW
0xEACERRCRICR2Critical Error Interrupt Configuration Register 2RW
0xEF8ERRIRQSRError Interrupt Status RegisterRW
0xFA8ERRDEVAFFDevice Affinity RegisterRO
0xFBCERRDEVARCHDevice Architecture RegisterRO
0xFC8ERRDEVIDDevice Configuration RegisterRO
0xFD0ERRPIDR4Peripheral Identification Register 4RO
0xFE0ERRPIDR0Peripheral Identification Register 0RO
0xFE4ERRPIDR1Peripheral Identification Register 1RO
0xFE8ERRPIDR2Peripheral Identification Register 2RO
0xFECERRPIDR3Peripheral Identification Register 3RO
0xFF0ERRCIDR0Component Identification Register 0RO
0xFF4ERRCIDR1Component Identification Register 1RO
0xFF8ERRCIDR2Component Identification Register 2RO
0xFFCERRCIDR3Component Identification Register 3RO

In the TRBE block:

OffsetNameDescriptionAccess
0x000TRBBASER_EL1Trace Buffer Base Address RegisterRW
0x008TRBPTR_EL1Trace Buffer Write Pointer RegisterRW
0x010TRBLIMITR_EL1Trace Buffer Limit Address RegisterRW
0x018TRBSR_EL1Trace Buffer Status/syndrome RegisterRW
0x020TRBTRG_EL1Trace Buffer Trigger Counter RegisterRW
0x028TRBMAR_EL1Trace Buffer Memory Attribute RegisterRW
0x030TRBIDR_EL1Trace Buffer ID RegisterRO
0x038TRBCRTrace Buffer Control RegisterRW
0x040TRBMPAMTrace Buffer MPAM Configuration RegisterRW
0xF00TRBITCTRLIntegration Mode Control RegisterRW
0xFA8TRBDEVAFFDevice Affinity RegisterRO
0xFB0TRBLARLock Access RegisterWO
0xFB4TRBLSRLock Status RegisterRO
0xFB8TRBAUTHSTATUSAuthentication Status RegisterRO
0xFBCTRBDEVARCHTrace Buffer Device Architecture RegisterRO
0xFC0TRBDEVID2Device Configuration Register 2RO
0xFC4TRBDEVID1Device Configuration Register 1RO
0xFC8TRBDEVIDDevice Configuration RegisterRO
0xFCCTRBDEVTYPEDevice Type RegisterRO
0xFD0TRBPIDR4Peripheral Identification Register 4RO
0xFD4TRBPIDR5Peripheral Identification Register 5RO
0xFD8TRBPIDR6Peripheral Identification Register 6RO
0xFDCTRBPIDR7Peripheral Identification Register 7RO
0xFE0TRBPIDR0Peripheral Identification Register 0RO
0xFE4TRBPIDR1Peripheral Identification Register 1RO
0xFE8TRBPIDR2Peripheral Identification Register 2RO
0xFECTRBPIDR3Peripheral Identification Register 3RO
0xFF0TRBCIDR0Component Identification Register 0RO
0xFF4TRBCIDR1Component Identification Register 1RO
0xFF8TRBCIDR2Component Identification Register 2RO
0xFFCTRBCIDR3Component Identification Register 3RO

In the Timer block:

In the CNTBaseN block:

OffsetNameDescriptionAccess
0x000CNTPCT[31:0]Counter-timer Physical CountRO
0x004CNTPCT[63:32]Counter-timer Physical CountRO
0x008CNTVCT[31:0]Counter-timer Virtual CountRO
0x00CCNTVCT[63:32]Counter-timer Virtual CountRO
0x010CNTFRQCounter-timer FrequencyRO
0x014CNTEL0ACRCounter-timer EL0 Access Control RegisterRW
0x018CNTVOFF[31:0]Counter-timer Virtual OffsetRO
0x01CCNTVOFF[63:32]Counter-timer Virtual OffsetRO
0x020CNTP_CVAL[31:0]Counter-timer Physical Timer CompareValueRW
0x024CNTP_CVAL[63:32]Counter-timer Physical Timer CompareValueRW
0x028CNTP_TVALCounter-timer Physical Timer TimerValueRW
0x02CCNTP_CTLCounter-timer Physical Timer ControlRW
0x030CNTV_CVAL[31:0]Counter-timer Virtual Timer CompareValueRW
0x034CNTV_CVAL[63:32]Counter-timer Virtual Timer CompareValueRW
0x038CNTV_TVALCounter-timer Virtual Timer TimerValueRW
0x03CCNTV_CTLCounter-timer Virtual Timer ControlRW
0xFD0 + (4 * n)CounterID<n>Counter ID registersRO

In the CNTCTLBase block:

OffsetNameDescriptionAccess
0x000CNTFRQCounter-timer FrequencyRO
0x004CNTNSARCounter-timer Non-secure Access RegisterRW
0x008CNTTIDRCounter-timer Timer ID RegisterRO
0x040 + (4 * n)CNTACR<n>Counter-timer Access Control RegistersRW
0x080 + (8 * n)CNTVOFF<n>[31:0]Counter-timer Virtual OffsetsRW
0x084 + (8 * n)CNTVOFF<n>[63:32]Counter-timer Virtual OffsetsRW
0xFD0 + (4 * n)CounterID<n>Counter ID registersRO

In the CNTControlBase block:

OffsetNameDescriptionAccess
0x000CNTCRCounter Control RegisterRW
0x004CNTSRCounter Status RegisterRO
0x008CNTCV[63:0]Counter Count Value registerRW
0x020CNTFID0Counter Frequency IDImplementationDefined:RO,RW
0x020 + (4 * n)CNTFID<n>Counter Frequency IDs, n > 0ImplementationDefined:RO,RW
0x10CNTSCRCounter Scale RegisterRW
0x1CCNTIDCounter Identification RegisterRO
0xFD0 + (4 * n)CounterID<n>Counter ID registersRO

In the CNTEL0BaseN block:

OffsetNameDescriptionAccess
0x000CNTPCT[31:0]Counter-timer Physical CountRO
0x004CNTPCT[63:32]Counter-timer Physical CountRO
0x008CNTVCT[31:0]Counter-timer Virtual CountRO
0x00CCNTVCT[63:32]Counter-timer Virtual CountRO
0x010CNTFRQCounter-timer FrequencyRO
0x020CNTP_CVAL[31:0]Counter-timer Physical Timer CompareValueRW
0x024CNTP_CVAL[63:32]Counter-timer Physical Timer CompareValueRW
0x028CNTP_TVALCounter-timer Physical Timer TimerValueRW
0x02CCNTP_CTLCounter-timer Physical Timer ControlRW
0x030CNTV_CVAL[31:0]Counter-timer Virtual Timer CompareValueRW
0x034CNTV_CVAL[63:32]Counter-timer Virtual Timer CompareValueRW
0x038CNTV_TVALCounter-timer Virtual Timer TimerValueRW
0x03CCNTV_CTLCounter-timer Virtual Timer ControlRW
0xFD0 + (4 * n)CounterID<n>Counter ID registersRO

In the CNTReadBase block:

OffsetNameDescriptionAccess
0x000CNTCV[63:0]Counter Count Value registerRO
0xFD0 + (4 * n)CounterID<n>Counter ID registersRO

3005/0907/2022 1517:5809; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96fb0421fa9a8865165f9b91af9b4a566111f866305

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