The PMVIDSR characteristics are:
Contains the sampled VMID value that is captured on reading PMPCSR[31:0].
PMVIDSR is in the Core power domain.
This register is present only when FEAT_PCSRv8p2 is implemented and EL2 is implemented. Otherwise, direct accesses to PMVIDSR are RES0.
Before Armv8.2, the PC Sample-based Profiling Extension can be implemented in the external debug register space, as indicated by the value of EDDEVID.PCSample.
PMVIDSR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | VMID[15:8] | VMID |
Reserved, RES0.
Extension to VMID[7:0]. For more information, see VMID[7:0].
The reset behavior of this field is:
Reserved, RES0.
VMID sample. The VMID associated with the most recent PMPCSR sample. When the most recent PMPCSR sample was generated:
Because the value written to PMVIDSR is an indirect read of the VMID value, it is CONSTRAINED UNPREDICTABLE whether PMVIDSR is set to the original or new value if PMPCSR samples:
The reset behavior of this field is:
IMPLEMENTATION DEFINED extensions to external debug might make the value of this register UNKNOWN, see 'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN'.
Component | Offset | Instance |
---|---|---|
PMU | 0x20C | PMVIDSR |
This interface is accessible as follows:
05/07/2022 17:07; b0421fa9a8865165f9b91af9b4a566111f866305
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.