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PMICNTSVR_EL1, Performance Monitors Instruction Count Saved Value Register

The PMICNTSVR_EL1 characteristics are:

Purpose

Captures the PMU Instruction counter, PMICNTR_EL0.

Configuration

AArch64 System register PMICNTSVR_EL1 bits [63:0] are architecturally mapped to External register PMU.PMICNTSVR_EL1[63:0].

This register is present only when FEAT_PMUv3_ICNTR is implemented and FEAT_PMUv3_SS is implemented. Otherwise, direct accesses to PMICNTSVR_EL1 are UNDEFINED.

Attributes

PMICNTSVR_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
ICNT
ICNT

ICNT, bits [63:0]

Sampled Instruction Count. The value of PMICNTR_EL0 at the last Capture event.

The reset behavior of this field is:

Accessing PMICNTSVR_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PMICNTSVR_EL1

op0op1CRnCRmop2
0b100b0000b11100b11000b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then X[t, 64] = PMICNTSVR_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = PMICNTSVR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = PMICNTSVR_EL1;


30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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