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PMSSCR_EL1, Performance Monitors Snapshot Status and Capture Register

The PMSSCR_EL1 characteristics are:

Purpose

Holds status information about the captured counters and provides a mechanism for software to initiate a sample.

Configuration

AArch64 System register PMSSCR_EL1 bits [63:0] are architecturally mapped to External register PMU.PMSSCR_EL1[63:0].

This register is present only when FEAT_PMUv3_SS is implemented. Otherwise, direct accesses to PMSSCR_EL1 are UNDEFINED.

Attributes

PMSSCR_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0NC
RES0SS

Bits [63:33]

Reserved, RES0.

NC, bit [32]

No Capture. Indicates whether the PMU counters have been captured.

NCMeaning
0b0

PMU counters captured.

0b1

PMU counters not captured.

The reset behavior of this field is:

Bits [31:1]

Reserved, RES0.

SS, bit [0]

Snapshot Capture and Status.

SSMeaning
0b0

On a read: The Capture event has completed.

On a write: Ignored.

0b1

On a read: The Capture event has not completed.

On a write: Initiate a capture immediately.

It is CONSTRAINED UNPREDICTABLE whether a Capture event has completed if this field is modified when the Capture event is ongoing.

The reset behavior of this field is:

Accessing PMSSCR_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PMSSCR_EL1

op0op1CRnCRmop2
0b110b0000b10010b11010b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then X[t, 64] = PMSSCR_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = PMSSCR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = PMSSCR_EL1;

MSR PMSSCR_EL1, <Xt>

op0op1CRnCRmop2
0b110b0000b10010b11010b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then PMSSCR_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then PMSSCR_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then PMSSCR_EL1 = X[t, 64];


30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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