HFGWTR2_EL2, Hypervisor Fine-Grained Write Trap Register 2

The HFGWTR2_EL2 characteristics are:

Purpose

Provides controls for traps of MSR and MCR writes of System registers.

Configuration

This register is present only when FEAT_FGT2 is implemented. Otherwise, direct accesses to HFGWTR2_EL2 are UNDEFINED.

Attributes

HFGWTR2_EL2 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0nRCWSMASK_EL1RES0nPFAR_EL1

Bits [63:3]

Reserved, RES0.

nRCWSMASK_EL1, bit [2]
When FEAT_THE is implemented:

Trap MSR or MSRR writes of RCWSMASK_EL1 at EL1 using AArch64 to EL2.

nRCWSMASK_EL1Meaning
0b0

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MSR or MSRR writes of RCWSMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18 for 64-bit access and 0x14 for 128-bit access, unless the write generates a higher priority exception.

0b1

MSR or MSRR writes of RCWSMASK_EL1 are not trapped by this mechanism.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Bit [1]

Reserved, RES0.

nPFAR_EL1, bit [0]
When FEAT_PFAR is implemented:

Trap MSR writes of PFAR_EL1 at EL1 using AArch64 to EL2.

nPFAR_EL1Meaning
0b0

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MSR writes of PFAR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

0b1

MSR writes of PFAR_EL1 are not trapped by this mechanism.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Accessing HFGWTR2_EL2

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, HFGWTR2_EL2

op0op1CRnCRmop2
0b110b1000b00110b00010b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then X[t, 64] = NVMem[0x2C8]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then X[t, 64] = HFGWTR2_EL2; elsif PSTATE.EL == EL3 then X[t, 64] = HFGWTR2_EL2;

MSR HFGWTR2_EL2, <Xt>

op0op1CRnCRmop2
0b110b1000b00110b00010b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then NVMem[0x2C8] = X[t, 64]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then HFGWTR2_EL2 = X[t, 64]; elsif PSTATE.EL == EL3 then HFGWTR2_EL2 = X[t, 64];


30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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