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PMOVSSET_EL0, Performance Monitors Overflow Flag Status Set register

The PMOVSSET_EL0 characteristics are:

Purpose

Sets the state of the overflow bit for the Cycle Count Register, PMU.PMCCNTR_EL0, and each of the implemented event counters PMU.PMEVCNTR<n>_EL0.PMCCNTR_EL0, and each of the implemented event counters PMEVCNTR<n>_EL0.

Configuration

External register PMOVSSET_EL0 bits [31:0] are architecturally mapped to AArch64 System register PMOVSSET_EL0[31:0].

External register PMOVSSET_EL0 bits [63:32] are architecturally mapped to AArch64 System register PMOVSSET_EL0[63:32] when FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented.

External register PMOVSSET_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMOVSSET[31:0].

External register PMOVSSET_EL0 bits [31:0] are architecturally mapped to AArch64 System register PMOVSCLR_EL0[31:0].

External register PMOVSSET_EL0 bits [63:32] are architecturally mapped to AArch64 System register PMOVSCLR_EL0[63:32] when FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented.

External register PMOVSSET_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMOVSR[31:0].

This register is present only when FEAT_PMUv3_EXT is implemented. Otherwise, direct accesses to PMOVSSET_EL0 are RES0.

PMOVSSET_EL0 is in the Core power domain.

Attributes

PMOVSSET_EL0 is a: 32-bit register.

This register is part of the PMU block.

Field descriptions

When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented:

6331623061296028592758265725562455235422532152205119501849174816471546144513441243114210419408397386375364353342331320
313029282726252423222120191817161514131211109876543210
RES0F0
CP30P29P28P27P26P25P24P23P22P21P20P19P18P17P16P15P14P13P12P11P10P9P8P7P6P5P4P3P2P1P0

Bits [63:33]

Reserved, RES0.

F0, bit [32]
When FEAT_PMUv3_ICNTR is implemented:

Unsigned overflow flag for PMU.PMICNTR_EL0 set. On writes, allows software to set the unsigned overflow flag for PMU.PMICNTR_EL0 to 1. On reads, returns the unsigned overflow flag for PMU.PMICNTR_EL0.

F0Meaning
0b0

PMU.PMICNTR_EL0 has not overflowed.

0b1

PMU.PMICNTR_EL0 has overflowed.

The reset behavior of this field is:

Accessing this field has the following behavior:


Otherwise:

Reserved, RES0.

C, bit [31]

Cycle counter overflow set bit.

CMeaning
0b0

When read, means the cycle counter has not overflowed since this bit was last cleared. When written, has no effect.

0b1

When read, means the cycle counter has overflowed since this bit was last cleared. When written, sets the cycle counter overflow bit to 1.

PMCR_EL0.LC controls whether an overflow is detected from unsigned overflow of PMCCNTR_EL0[31:0] or unsigned overflow of PMCCNTR_EL0PMU.PMCR_EL0.LC controls whether an overflow is detected from unsigned overflow of PMU.PMCCNTR_EL0[31:0] or unsigned overflow of PMU.PMCCNTR_EL0[63:0].

The reset behavior of this field is:

P<n>, bit [n], for n = 30 to 0

Event counter overflow set bit for PMU.PMEVCNTR<n>_EL0.PMEVCNTR<n>_EL0.

If PMU.PMCFGR.N is less than 31, bits [30:PMU.PMCFGR.N] are RAZ/WI.PMCFGR.N is less than 31, bits [30:PMCFGR.N] are RAZ/WI.

P<n>Meaning
0b0

When read, means that PMU.PMEVCNTR<n>_EL0 has not overflowed since this bit was last cleared. When written, has no effect.PMEVCNTR<n>_EL0 has not overflowed since this bit was last cleared. When written, has no effect.

0b1

When read, means that PMU.PMEVCNTR<n>_EL0 has overflowed since this bit was last cleared. When written, sets the PMU.PMEVCNTR<n>_EL0 overflow bit to 1.PMEVCNTR<n>_EL0 has overflowed since this bit was last cleared. When written, sets the PMEVCNTR<n>_EL0 overflow bit to 1.

If FEAT_PMUv3p5 is implemented, MDCR_EL2.HLP and PMU.PMCR_EL0.LP control whether an overflow is detected from unsigned overflow of PMU.PMEVCNTR<n>_EL0[31:0] or unsigned overflow of PMU.PMEVCNTR<n>_EL0[63:0].PMCR_EL0.LP control whether an overflow is detected from unsigned overflow of PMEVCNTR<n>_EL0[31:0] or unsigned overflow of PMEVCNTR<n>_EL0[63:0].

The reset behavior of this field is:

Accessing PMOVSSET_EL0

Note

SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.

PMOVSSET_EL0 can be accessed through the external debug interface:

Otherwise:

313029282726252423222120191817161514131211109876543210
CP30P29P28P27P26P25P24P23P22P21P20P19P18P17P16P15P14P13P12P11P10P9P8P7P6P5P4P3P2P1P0
ComponentOffsetInstance
PMU0xCC0PMOVSSET_EL0

This interface is accessible as follows:

C, bit [31]

Cycle counter overflow set bit.

CMeaning
0b0

When read, means the cycle counter has not overflowed since this bit was last cleared. When written, has no effect.

0b1

When read, means the cycle counter has overflowed since this bit was last cleared. When written, sets the cycle counter overflow bit to 1.

PMU.PMCR_EL0.LC controls whether an overflow is detected from unsigned overflow of PMU.PMCCNTR_EL0[31:0] or unsigned overflow of PMU.PMCCNTR_EL0[63:0].

The reset behavior of this field is:

P<n>, bit [n], for n = 30 to 0

Event counter overflow set bit for PMU.PMEVCNTR<n>_EL0.

If PMU.PMCFGR.N is less than 31, bits [30:PMU.PMCFGR.N] are RAZ/WI.

P<n>Meaning
0b0

When read, means that PMU.PMEVCNTR<n>_EL0 has not overflowed since this bit was last cleared. When written, has no effect.

0b1

When read, means that PMU.PMEVCNTR<n>_EL0 has overflowed since this bit was last cleared. When written, sets the PMU.PMEVCNTR<n>_EL0 overflow bit to 1.

If FEAT_PMUv3p5 is implemented, MDCR_EL2.HLP and PMU.PMCR_EL0.LP control whether an overflow is detected from unsigned overflow of PMU.PMEVCNTR<n>_EL0[31:0] or unsigned overflow of PMU.PMEVCNTR<n>_EL0[63:0].

The reset behavior of this field is:

Accessing PMOVSSET_EL0

Note

SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.

Accesses to this register use the following encodings in the external debug interface:

When FEAT_PMUv3_EXT64 is implemented
BlockAccess at address 0xCC0

PMOVSSET_EL0 can be accessed through the PMU block as follows:

FrameOffset
PMU0xCC0

When FEAT_PMUv3_EXT32 is implemented
BlockAccess at address 0xCC0

PMOVSSET_EL0 can be accessed through the PMU block as follows:

FrameOffsetRange
PMU0xCC031:0

When (FEAT_PMUv3_EXT32 is implemented and FEAT_PMUv3p9 is implemented) or FEAT_PMUv3_ICNTR is implemented
BlockAccess at address 0xCC4

PMOVSSET_EL0 can be accessed through the PMU block as follows:

FrameOffsetRange
PMU0xCC463:32

3005/0907/2022 1517:5708; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96fb0421fa9a8865165f9b91af9b4a566111f866305

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