The MPAMF_SIDR characteristics are:
The MPAMF_SIDR is a 32-bit read-only register that indicates the maximum Secure PARTID and Secure PMG on this MSC.
The power domain of MPAMF_SIDR is IMPLEMENTATION DEFINED.
This register is present only when FEAT_MPAM is implemented. Otherwise, direct accesses to MPAMF_SIDR are RES0.
The power and reset domain of each MSC component is specific to that component.
MPAMF_SIDR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | S_PMG_MAX | S_PARTID_MAX |
Reserved, RES0.
Maximum value of Secure PMG supported by this component.
Maximum value of Secure PARTID supported by this component.
This register is only within the Secure MPAM feature page memory frame.
MPAMF_SIDR is read-only.
MPAMF_SIDR must only be readable from the Secure MPAM feature page. If the system or the MSC does not support the Secure address map, this register must not be accessible.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_s | 0x0008 | MPAMF_SIDR_s |
Accesses to this interface are RO.
30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f
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