S3_<op1>_<Cn>_<Cm>_<op2>, IMPLEMENTATION DEFINED registers

The S3_<op1>_<Cn>_<Cm>_<op2> characteristics are:

Purpose

This area of the instruction set space is reserved for IMPLEMENTATION DEFINED registers.

Configuration

There are no configuration notes.

Attributes

S3_<op1>_<Cn>_<Cm>_<op2> is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
IMPLEMENTATION DEFINED
IMPLEMENTATION DEFINED

IMPLEMENTATION DEFINED, bits [63:0]

IMPLEMENTATION DEFINED.

Accessing S3_<op1>_<Cn>_<Cm>_<op2>

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, S3_<op1>_C<Cn>_C<Cm>_<op2>

op0op1CRnCRmop2
0b11op1[2:0]0b1x11Cm[3:0]op2[2:0]

if PSTATE.EL == EL0 then if !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && SCTLR_EL1.TIDCP == '1' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && SCTLR_EL2.TIDCP == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.ImpDefSysRegRead(op0, op1, CRn, CRm, op2, t); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TIDCP == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.ImpDefSysRegRead(op0, op1, CRn, CRm, op2, t); elsif PSTATE.EL == EL2 then AArch64.ImpDefSysRegRead(op0, op1, CRn, CRm, op2, t); elsif PSTATE.EL == EL3 then AArch64.ImpDefSysRegRead(op0, op1, CRn, CRm, op2, t);

MSR S3_<op1>_C<Cn>_C<Cm>_<op2>, <Xt>

op0op1CRnCRmop2
0b11op1[2:0]0b1x11Cm[3:0]op2[2:0]

if PSTATE.EL == EL0 then if !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && SCTLR_EL1.TIDCP == '1' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && SCTLR_EL2.TIDCP == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.ImpDefSysRegWrite(op0, op1, CRn, CRm, op2, t); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TIDCP == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.ImpDefSysRegWrite(op0, op1, CRn, CRm, op2, t); elsif PSTATE.EL == EL2 then AArch64.ImpDefSysRegWrite(op0, op1, CRn, CRm, op2, t); elsif PSTATE.EL == EL3 then AArch64.ImpDefSysRegWrite(op0, op1, CRn, CRm, op2, t);


05/07/2022 17:08; b0421fa9a8865165f9b91af9b4a566111f866305

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