PMCFGR, Performance Monitors Configuration Register

The PMCFGR characteristics are:

Purpose

Contains PMU-specific configuration data.

Configuration

This register is present only when FEAT_PMUv3_EXT is implemented. Otherwise, direct accesses to PMCFGR are RES0.

PMCFGR is in the Core power domain.

Attributes

PMCFGR is a:

This register is part of the PMU block.

Field descriptions

When FEAT_PMUv3_EXT64 is implemented:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
NCGRES0SSFZORES0UENWTNAEXCCDCCSIZEN

Bits [63:32]

Reserved, RES0.

NCG, bits [31:28]
When FEAT_PMUv3p9 is implemented:

Counter Groups. Defines the number of counter groups implemented, minus one.

Reads as 0b0001.

Access to this field is RO.


Otherwise:

Defines the number of counter groups implemented, minus one.

This field reads-as-zero.

Reads as 0b0000.

Access to this field is RO.

Bits [27:23]

Reserved, RES0.

SS, bit [22]

Snapshot supported.

SSMeaning
0b0

Snapshot mechanism not supported. The locations 0x600-0x7FC and 0xE30-0xE3C are IMPLEMENTATION DEFINED.

0b1

Snapshot mechanism supported. PMSVR<n> and PMSSSCR are implemented.

FEAT_PMUv3_SS implements the functionality identified by the value 1.

If FEAT_PMUv3_SS is not implemented, a PMU might include an IMPLEMENTATION DEFINED snapshot mechanism, including one using the IMPLEMENTATION DEFINED registers 0x600-0x7FC and 0xE30-0xE3C.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

FZO, bit [21]

Freeze-on-overflow supported. Defined values are:

FZOMeaning
0b0

Freeze-on-overflow mechanism is not supported. PMU.PMCR_EL0.FZO is RES0.

0b1

Freeze-on-overflow mechanism is supported. PMU.PMCR_EL0.FZO is RW.

FEAT_PMUv3p7 implements the functionality added by the value 0b1.

From Armv8.7, if FEAT_PMUv3 is implemented, the only permitted value is 0b1.

Bit [20]

Reserved, RES0.

UEN, bit [19]

User-mode Enable Register supported. PMUSERENR_EL0 is not visible in the external debug interface, so this bit is RAZ.

Reads as 0b0.

Access to this field is RO.

WT, bit [18]

This feature is not supported, so this bit is RAZ.

Reads as 0b0.

Access to this field is RO.

NA, bit [17]

This feature is not supported, so this bit is RAZ.

Reads as 0b0.

Access to this field is RO.

EX, bit [16]

Export supported. Value is IMPLEMENTATION DEFINED.

EXMeaning
0b0

PMU.PMCR_EL0.X is RES0.

0b1

PMU.PMCR_EL0.X is read/write.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

CCD, bit [15]

Cycle counter has prescale.

This is RES1 if AArch32 is supported, and RAZ otherwise.

CCDMeaning
0b0

PMU.PMCR_EL0.D is RES0.

0b1

PMU.PMCR_EL0.D is read/write.

CC, bit [14]

Dedicated cycle counter (counter 31) supported.

Reads as 0b1.

Access to this field is RO.

SIZE, bits [13:8]

Size of counters, minus one. This field defines the size of the largest counter implemented by the Performance Monitors Unit.

From Armv8, the largest counter is 64-bits, so the value of this field is 0b111111.

This field is used by software to determine the spacing of the counters in the memory-map. From Armv8, the counters are a doubleword-aligned addresses.

Reads as 0b111111.

Access to this field is RO.

N, bits [7:0]

Number of counters, minus one.

NMeaning
0x00

Only PMU.PMCCNTR_EL0 implemented.

0x01..0x20

Number of counters implemented, 1 to 33.

All other values are reserved.

The count includes the optional Instruction Counter, PMU.PMICNTR_EL0.

The count includes the Cycle Counter, PMU.PMCCNTR_EL0. For example, if N == 0x00, there is a single counter, PMU.PMCCNTR_EL0, and PMEVCNTR0_EL0 is not implemented.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Otherwise:

313029282726252423222120191817161514131211109876543210
NCGRES0SSFZORES0UENWTNAEXCCDCCSIZEN

NCG, bits [31:28]
When FEAT_PMUv3p9 is implemented:

Counter Groups. Defines the number of counter groups implemented, minus one.

Reads as 0b0001.

Access to this field is RO.


Otherwise:

Defines the number of counter groups implemented, minus one.

This field reads-as-zero.

Reads as 0b0000.

Access to this field is RO.

Bits [27:23]

Reserved, RES0.

SS, bit [22]

Snapshot supported.

SSMeaning
0b0

Snapshot mechanism not supported. The locations 0x600-0x7FC and 0xE30-0xE3C are IMPLEMENTATION DEFINED.

0b1

Snapshot mechanism supported. PMSVR<n> and PMSSSCR are implemented.

FEAT_PMUv3_SS implements the functionality identified by the value 1.

If FEAT_PMUv3_SS is not implemented, a PMU might include an IMPLEMENTATION DEFINED snapshot mechanism, including one using the IMPLEMENTATION DEFINED registers 0x600-0x7FC and 0xE30-0xE3C.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

FZO, bit [21]

Freeze-on-overflow supported. Defined values are:

FZOMeaning
0b0

Freeze-on-overflow mechanism is not supported. PMU.PMCR_EL0.FZO is RES0.

0b1

Freeze-on-overflow mechanism is supported. PMU.PMCR_EL0.FZO is RW.

FEAT_PMUv3p7 implements the functionality added by the value 0b1.

From Armv8.7, if FEAT_PMUv3 is implemented, the only permitted value is 0b1.

Bit [20]

Reserved, RES0.

UEN, bit [19]

User-mode Enable Register supported. PMUSERENR_EL0 is not visible in the external debug interface, so this bit is RAZ.

Reads as 0b0.

Access to this field is RO.

WT, bit [18]

This feature is not supported, so this bit is RAZ.

Reads as 0b0.

Access to this field is RO.

NA, bit [17]

This feature is not supported, so this bit is RAZ.

Reads as 0b0.

Access to this field is RO.

EX, bit [16]

Export supported. Value is IMPLEMENTATION DEFINED.

EXMeaning
0b0

PMU.PMCR_EL0.X is RES0.

0b1

PMU.PMCR_EL0.X is read/write.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

CCD, bit [15]

Cycle counter has prescale.

This is RES1 if AArch32 is supported, and RAZ otherwise.

CCDMeaning
0b0

PMU.PMCR_EL0.D is RES0.

0b1

PMU.PMCR_EL0.D is read/write.

CC, bit [14]

Dedicated cycle counter (counter 31) supported.

Reads as 0b1.

Access to this field is RO.

SIZE, bits [13:8]

Size of counters, minus one. This field defines the size of the largest counter implemented by the Performance Monitors Unit.

From Armv8, the largest counter is 64-bits, so the value of this field is 0b111111.

This field is used by software to determine the spacing of the counters in the memory-map. From Armv8, the counters are a doubleword-aligned addresses.

Reads as 0b111111.

Access to this field is RO.

N, bits [7:0]

Number of counters, minus one.

NMeaning
0x00

Only PMU.PMCCNTR_EL0 implemented.

0x01..0x20

Number of counters implemented, 1 to 33.

All other values are reserved.

The count includes the optional Instruction Counter, PMU.PMICNTR_EL0.

The count includes the Cycle Counter, PMU.PMCCNTR_EL0. For example, if N == 0x00, there is a single counter, PMU.PMCCNTR_EL0, and PMEVCNTR0_EL0 is not implemented.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Accessing PMCFGR

Note

AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.

Accesses to this register use the following encodings in the external debug interface:

BlockAccess at address 0xE00

PMCFGR can be accessed through the PMU block as follows:

FrameOffset
PMU0xE00

30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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