no old filehtmldiff from-(new)

PMCCNTSVR_EL1, Performance Monitors Cycle Count Saved Value Register

The PMCCNTSVR_EL1 characteristics are:

Purpose

Captures the PMU Cycle counter, PMCCNTR_EL0.

Configuration

AArch64 System register PMCCNTSVR_EL1 bits [63:0] are architecturally mapped to External register PMU.PMCCNTSVR_EL1[63:0].

This register is present only when FEAT_PMUv3_SS is implemented. Otherwise, direct accesses to PMCCNTSVR_EL1 are UNDEFINED.

Attributes

PMCCNTSVR_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
CCNT
CCNT

CCNT, bits [63:0]

Sampled Cycle Count. The value of PMCCNTR_EL0 at the last Capture event.

The reset behavior of this field is:

Accessing PMCCNTSVR_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PMCCNTSVR_EL1

op0op1CRnCRmop2
0b100b0000b11100b10110b111

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then X[t, 64] = PMCCNTSVR_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = PMCCNTSVR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = PMCCNTSVR_EL1;


30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

no old filehtmldiff from-(new)