System Register XML
for A-Profile Architecture
(2022-09)
3 Oct 2022
Introduction
This is the 2022-09 release
of the System Register XML for A-profile Architecture:
-
The AArch64 and AArch32 views of the System registers, including Debug, PMU, AMU, MPAM, Generic Timer, and GIC.
-
The AArch64 and AArch32 system control operations.
-
The memory-mapped Debug, CTI, PMU, AMU, MPAM, GIC, and Generic Timer registers.
The Proprietary Notice
gives details of the terms and conditions under which this package
is provided.
The Feature list lists the feature names used in A-profile architecture.
If you have comments on the content of this package, please send
them by e-mail to
support-aarchv8@arm.com.
Give:
- The title, "System Register XML for A-profile Architecture, describing:".
- The version, "2022-09".
- A concise explanation of your comments.
Please see the Documentation for
more information on the general structure of these descriptions.
Contents
Product Status
This release covers multiple versions of the architecture. The content relating to different versions is given different quality ratings.
The information relating to the 2022 Extensions of the A-profile Architecture, and features FEAT_MEC and FEAT_PMUv3_EXT64 is at Alpha quality. Alpha quality means that most major features of the specification are described in this release, but some features and details might be missing.
The information relating to SME2 and previously released features, including FEAT_PMUv3_EXT32, is at Beta quality. Beta quality means that all major features of the specification are described, but some details might be missing.
Release notes
Change history
- This release introduces SME2 and the 2022 Extensions of the A-profile Architecture, as well as features FEAT_MEC and FEAT_PMUv3_EXT64. The Guarded Control Stack (GCS) and some 2022 Extension features are not yet available.
Note: An implementation of FEAT_PMUv3 can include an OPTIONAL external debug interface, FEAT_PMUv3_EXT. Previously this feature was called the external interface to the Performance Monitors registers.
FEAT_PMUv3_EXT is implemented in one of two variants:
- The 32-bit external view, FEAT_PMUv3_EXT32.
- Since Armv8.8, the 64-bit external view, FEAT_PMUv3_EXT64. In the I.a ArmARM this feature is called the 64-bit external PMU programmers' model extension.
These feature names will be used in future.
- The architecture is relaxed to allow a PE to implement FEAT_RME without Secure state.
- TRBSR_EL1.EC and PMBSR_EL1.EC are corrected to indicate that TRBSR_EL1.MSS and PMBSR_EL1.MSS are RES0 for this exception class 0b011110.
- ZCR_ELx.LEN description is updated to specify that a power-of-two vector length must be selected for both Non-Streaming SVE mode and Streaming SVE mode.
- FEAT_SME dependency for ID_AA64ISAR1_EL1.BF16 and ID_AA64ZFR0_EL1.BF16 value 0b0010 is removed.
- Software usage information added to ID_AA64ZFR0_EL1 configuration, and the following field descriptions: F64MM, F32MM, SM4, SHA3, BitPerm, AES.
- The T field descriptions in PMEVTYPERn_EL0 and PMCCFILTR_EL0 registers are clarified.
- The block size defined by DCZID_EL0.BS is corrected to indicate that the minimum value is 16 bytes when FEAT_MTE2 is implemented.
- The registers added by the optional 64-bit PMU external interface are present.
- ID_AA64ISAR2_EL1.RPRES is updated to indicate FEAT_RPRES is optional.
- Updated PMMIR BUS_SLOTS to include behavior when the information is not available.
- FEAT_MTE corrected to FEAT_MTE2 in DSPSR_EL0.TCO, SPSR_ELx.TCO, TCO.
- Clarification of the differences in TTL level hint between Leaf-level entries and non-Leaf-level entries.
- Information about access to GICx_INMIRnE external registers when GICD_CTLR.DS is 0 is corrected.
- Clarified GICx_INMIRn and GICx_INMIRnE external register field descriptions for Group 0 interrupts.
- Updated EL1 HCRX_EL2 traps to include the test "IsHCRXEL2Enabled()" function.
- Added feature names FEAT_TRC_SR and FEAT_TRC_EXT to refer to implementations with System register or external register access to trace and performance monitors.
- Clarified that HDFGWTR_EL2 and HDFGRTR_EL2 fields PMCCNTR_EL0 and PMEVCNTRn_EL0, do not trap when the registers are indirectly accessed via PMCR_EL0.
- ID_AA64ISAR0_EL1.AES effect of FEAT_PMULL is clarified.
- Corrected accessibility pseudocode for TLBI VAE2* and TLBI VAE3* System instructions to show VMID_NONE is passed instead of VMID[].
- Added Spec_FPACC field to ID_AA64MMFR3.
- CCSIDR_EL1.LineSize is corrected to reflect the effects of FEAT_MTE2 when FEAT_CCIDX is not implemented.
- The value descriptions of GICR_TYPER.CommonLPIAff are corrected to take into account the vPE Configuration table when GICv4.1 is implemented.
- Corrected SPI routing mode is set to [1:N] in GICD_IROUTER<n>{E} when [1:N] not supported.
- Note about synchronization is added to RGSR_EL1 configuration.
- Reset values of HCRX_EL2.{MSCEn, CMOW} are clarified.
- Tightened restrictions on effects of speculation to all registers in ID_AA64PFR0_EL1, ID_PFR2_EL1, and ID_PFR2.
- SCTLR_EL1.{M, C} field descriptions are clarified to include behavior in all Security states.
- Updated CNTPS registers to indicate that they are only present if EL3 is implemented.
- Note added to field definitions for LoUU and LoUIS in CLIDR and CLIDR_EL1.
- References to FEAT_MTE instead of FEAT_MTE2 corrected in TCO fields in SPSR registers, and the TCO register.
- RGSR_EL1 is updated to support wider RGSR_EL1.SEED field.
- Corrected the VSTTBR_EL2.BADDR and VTTBR_EL2.BADDR field descriptions to hold the stage 2 translation table address instead of the stage 1 translation table address.
Many simple clarifications and corrections are also present, but are too small to be listed here. Some minor formatting changes are supressed and not highlighted in the diff output.
Known issues
All issues identified in the below list will be fixed in a future release.
- This release does not include the Guarded Control Stack (GCS) Extension.
- The external DBGBCR<n>_EL1 and DBGWVR<n>_EL1 register fields do not include the extension of the VA field to bit 56.
- TLBI accessibility will be updated to cope correctly with reserved Security states.
- The address in FAR_ELx when FEAT_MOPS is implemented is relaxed to be within an address range determined by the current translation granule size, not the smallest implemented translation granule size.
- FAR_ELx and HPFAR_EL2 behavior when there are multiple aborts will be clarified.
- The SCTLR_EL1.EPAN and SCTLR_EL2.EPAN behavior when speculative data accesses would generate a Permission fault if it was not speculative is relaxed to apply only when PSTATE.PAN=1.
- HCRX_EL2 behavior when EL2 is not implemented or SCR_EL3.HXEn is 0, and the interaction of the value of HCRX_EL2.MSCEn will be clarified.
- Information about ordering of direct and indirect reads and writes of RGSR_EL1 will be relaxed to apply whether GCR_EL1.RRND is 1 or 0.
- Non-secure accesses to ERRIRQCR2.NSMSI changed from RES1 to WI.
- The EDSCR fields which can be indirectly read by MDSCR_EL1 and DBGDSCRext will be clarified.
- PMCCNTR accessibility will be updated to confirm no change to bits[63:32] when accessed as a 32-bit register.
- Corresponding SET and CLR registers will be mapped to each other.
- Clarification of field descriptions and values in PMUSERENR_EL0 and PMUSERENR.
- Accessibility conditions added to ERRIRQCR<n> registers, and condition on ERRIRQCR2.NSMSI field simplified.
- The accessibility pseudocode for DBGDSCRint does not currently show that access is CONSTRAINED UNPREDICTABLE in Debug state.
- ERRPFGF.MV and ERRPFGCTL.MV clarified to remove ambiguity.
- The read values of *DEVAFF registers before error records have been configured will be clarified.
- The recommended operations when clearing valid fields in ERR<n>STATUS will be clarified.
- The accessibility pseudocode for DBGDTRTXint will be updated to consider DBGDSCRext.UDCCdis.
Potential upcoming changes
Arm is constantly exploring ways to make the architecture presentation precise and clear. Towards this, the following changes are expected in future releases:
-
Accessibility of unimplemented registers in arrays will be improved.
-
Accessibility for memory mapped accesses will be improved by use of register block schema elements.
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Accessibility when there is a width mismatch between the accessor and the register will be improved.
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Configurability details will be captured more formally to define features, acceptable feature choices, and mapping of features to ID registers.
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Implementation of improved field access properties, which have become available due to the new schema, for example W1C, W1S.
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Banking in MRS will be captured, for example, A32 S/NS register banking.
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The behavior of resets in AArch32 registers when not reset into an exception level using AArch32 will be clarified.
Documentation
General
A description within the XML contains the following sections:
- Purpose
-
A short description of the purpose of the register in the
Arm Architecture.
- Configuration
-
How the register is architecturally mapped onto another System
register or a memory-mapped register. If the configuration of
the PE affects the implementation of the register, then
information about this is also included here.
- Attributes
-
The size of the register.
- Field descriptions
-
The register diagram and a description of the behavior of each field within the register.
Memory-mapped registers
A memory-mapped register description also contains the following
sections:
- Accessing ...
-
The address or offset of the register in the memory map, and
the accessibility.
System registers
A System register description also contains an "Accessing
..." section, that includes:
-
The assembler syntax for the instructions used to access the
register, and how the instruction is encoded.
-
Pseudocode that describes the execution of all instructions
used to access the register, including information about
traps and enables that apply upon that access.
-
For some System registers, additional text is provided which
gives extra information regarding the access to the
register.
-
The accessibility pseudocode for a register assumes that
that register is implemented and that all features which
affects its accesses are implemented. In most cases, the
behavior upon access to a register is determined in part or
in whole by the Exception level at which it is accessed.