The AMDEVARCH characteristics are:
Identifies the programmers' model architecture of the AMU component.
The power domain of AMDEVARCH is IMPLEMENTATION DEFINED.
Implementation of this register is OPTIONAL.
This register is present only when FEAT_AMUv1 is implemented.
AMDEVARCH is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ARCHITECT | PRESENT | REVISION | ARCHID |
Defines the architecture of the component. For AMU, this is Arm Limited.
Bits [31:28] are the JEP106 continuation code, 0x4.
Bits [27:21] are the JEP106 ID code, 0x3B.
Reads as 0b01000111011.
Access to this field is RO.
Indicates that the DEVARCH is present.
Reads as 0b1.
Access to this field is RO.
Defines the architecture revision. For architectures defined by Arm this is the minor revision.
REVISION | Meaning |
---|---|
0b0000 |
Architecture revision is AMUv1. |
All other values are reserved.
Access to this field is RO.
Defines this part to be an AMU component. For architectures defined by Arm this is further subdivided.
For AMU:
This corresponds to AMU architecture version AMUv1.
Reads as 0x0A66.
Access to this field is RO.
Component | Offset | Instance |
---|---|---|
AMU | 0xFBC | AMDEVARCH |
Accesses to this interface are RO.
30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f
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