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TTBR0_EL2, Translation Table Base Register 0 (EL2)

The TTBR0_EL2 characteristics are:

Purpose

When HCR_EL2.E2H is 0, holds the base address of the translation table for the initial lookup for stage 1 of an address translation in the EL2 translation regime, and other information for this translation regime.

When HCR_EL2.E2H is 1, holds the base address of the translation table for the initial lookup for stage 1 of the translation of an address from the lower VA range in the EL2&0 translation regime, and other information for this translation regime.

Configuration

AArch64 System register TTBR0_EL2 bits [47:1] are architecturally mapped to AArch32 System register HTTBR[47:1].

If EL2 is not implemented, this register is RES0 from EL3.

This register has no effect if EL2 is not enabled in the current Security state.

TTBR0_EL2 is a 128-bit register that can also be accessed as a 64-bit value. If it is accessed as a 64-bit register, accesses read and write bits [63:0] and do not modify bits [127:64].

Attributes

TTBR0_EL2 is a: 64-bit register.

Field descriptions

When FEAT_D128 is implemented, TCR2_EL2.D128 == 1 and HCR_EL2.E2H == 1:

12712612512412312212112011911811711611511411311211111010910810710610510410310210110099989796
RES0
9594939291908988878685848382818079787776757473727170696867666564
RES0BADDR[55:5][50:43]RES0
6362616059585756555453525150494847464544434241403938373635343332
ASIDBADDR[55:5][42:0]
313029282726252423222120191817161514131211109876543210
BADDR[55:5][42:0]RES0SKLCnP
6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
ASIDBADDR[47:1]
BADDR[47:1]CnP

Bits [127:88]

Reserved, RES0.

BADDR[55:5], bits [87:80, 47:5]

Translation table base address:

Address bit x is the minimum address bit required to align the translation table to the size of the table. x is calculated based on LOG2(StartTableSize), as described in VMSAv9-128. The smallest permitted value of x is 5.

The BADDR[55:5] field is split as follows:

The reset behavior of this field is:

Bits [79:64]

Reserved, RES0.

ASID, bits [63:48]
When FEAT_VHE is implemented:

When HCR_EL2.E2H is 1, it holds an ASID for the translation table base address. The TCR_EL2.A1 field selects either TTBR0_EL2.ASID or TTBR1_EL2.ASID.

If the implementation has only 8 bits of ASID, then the upper 8 bits of this field are RES0.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Bits [4:3]

Reserved, RES0.

SKL, bits [2:1]

Skip Level associated with translation table walks using TTBR0_EL2.

This determines the number of levels to be skipped from the regular start level of the Stage 1 EL2&0 translation table walks using TTBR0_EL2.

SKLMeaning
0b00

Skip 0 level from the regular start level.

0b01

Skip 1 level from the regular start level.

0b10

Skip 2 levels from the regular start level.

0b11

Skip 3 levels from the regular start level.

The reset behavior of this field is:

CnP, bit [0]
When FEAT_TTCNP is implemented:

Common not Private. This bit indicates whether each entry that is pointed to by TTBR0_EL2 is a member of a common set that can be used by every PE in the Inner Shareable domain for which the value of TTBR0_EL2.CnP is 1.

CnPMeaning
0b0

The translation table entries pointed to by TTBR0_EL2 for the current translation regime, and ASID if applicable, are permitted to differ from corresponding entries for TTBR0_EL2 for other PEs in the Inner Shareable domain. This is not affected by:

  • The value of TTBR0_EL2.CnP on those other PEs.

  • When the current translation regime is the EL2&0 regime, the value of the current ASID.

0b1

The translation table entries pointed to by TTBR0_EL2 are the same as the translation table entries for every other PE in the Inner Shareable domain for which the value of TTBR0_EL2.CnP is 1 and all of the following apply:

  • The translation table entries are pointed to by TTBR0_EL2.

  • The translation tables relate to the same translation regime.

  • If that translation regime is the EL2&0 regime, the ASID is the same as the current ASID.

This bit is permitted to be cached in a TLB.

Note

If the value of the TTBR0_EL2.CnP bit is 1 on multiple PEs in the same Inner Shareable domain and those TTBR0_EL2s do not point to the same translation table entries when the other conditions specified for the case when the value of CnP is 1 apply, then the results of translations are CONSTRAINED UNPREDICTABLE, see 'CONSTRAINED UNPREDICTABLE behaviors due to caching of control or data values'.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

When FEAT_D128 is not implemented or TCR2_EL2.D128 == 0:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
ASIDBADDR[47:1]
BADDR[47:1]CnP

ASID, bits [63:48]
When FEAT_VHE is implemented:

When HCR_EL2.E2H is 0, this field is RES0.

When HCR_EL2.E2H is 1, it holds an ASID for the translation table base address. The TCR_EL2.A1 field selects either TTBR0_EL2.ASID or TTBR1_EL2.ASID.

If the implementation has only 8 bits of ASID, then the upper 8 bits of this field are RES0.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

BADDR[47:1], bits [47:1]

Translation table base address:

Address bit x is the minimum address bit required to align the translation table to the size of the table. The smallest permitted value of x is 6. The AArch64 Virtual Memory System Architecture chapter describes how x is calculated based on the value of TCR_EL2.T0SZ, the translation stage, and the translation granule size.

Note

A translation table is required to be aligned to the size of the table. If a table contains fewer than eight entries, it must be aligned on a 64 byte address boundary.

If the value of TCR_EL2.{I}PS is not 0b110, then:

If FEAT_LPA is implemented and the value of TCR_EL2.{I}PS is 0b110, then:

Note

The OA size specified by TCR_EL2.{I}PS is determined as follows:

TCR_EL2.{I}PS==0b110 is permitted when:

When the value of ID_AA64MMFR0_EL1.PARange indicates that the implementation does not support a 52 bit PA size, if a translation table lookup uses this register when the Effective value of TCR_EL2.{I}PS is 0b110 and the value of register bits[5:2] is nonzero, an Address size fault is generated.

When the value of ID_AA64MMFR0_EL1.PARange indicates that the implementation supports a 56 bit PA size, bits A[55:52] of the stage 1 translation table base address are zero.

If any register bit[47:1] that is defined as RES0 has the value 1 when a translation table walk is done using TTBR0_EL2, then the translation table base address might be misaligned, with effects that are CONSTRAINED UNPREDICTABLE, and must be one of the following:

The reset behavior of this field is:

CnP, bit [0]
When FEAT_TTCNP is implemented:

Common not Private. This bit indicates whether each entry that is pointed to by TTBR0_EL2 is a member of a common set that can be used by every PE in the Inner Shareable domain for which the value of TTBR0_EL2.CnP is 1.

CnPMeaning
0b0

The translation table entries pointed to by TTBR0_EL2 for the current translation regime, and ASID if applicable, are permitted to differ from corresponding entries for TTBR0_EL2 for other PEs in the Inner Shareable domain. This is not affected by:

  • The value of TTBR0_EL2.CnP on those other PEs.

  • When the current translation regime is the EL2&0 regime, the value of the current ASID.

0b1

The translation table entries pointed to by TTBR0_EL2 are the same as the translation table entries for every other PE in the Inner Shareable domain for which the value of TTBR0_EL2.CnP is 1 and all of the following apply:

  • The translation table entries are pointed to by TTBR0_EL2.

  • The translation tables relate to the same translation regime.

  • If that translation regime is the EL2&0 regime, the ASID is the same as the current ASID.

This bit is permitted to be cached in a TLB.

Note

If the value of the TTBR0_EL2.CnP bit is 1 on multiple PEs in the same Inner Shareable domain and those TTBR0_EL2s do not point to the same translation table entries when the other conditions specified for the case when the value of CnP is 1 apply, then the results of translations are CONSTRAINED UNPREDICTABLE, see 'CONSTRAINED UNPREDICTABLE behaviors due to caching of control or data values'.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Accessing TTBR0_EL2

When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic TTBR0_EL2 or TTBR0_EL1 are not guaranteed to be ordered with respect to accesses using the other mnemonic.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, TTBR0_EL2

op0op1CRnCRmop2
0b110b1000b00100b00000b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then X[t, 64] = TTBR0_EL2<63:0>;; elsif PSTATE.EL == EL3 then X[t, 64] = TTBR0_EL2<63:0>;;

MSR TTBR0_EL2, <Xt>

op0op1CRnCRmop2
0b110b1000b00100b00000b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then TTBR0_EL2<63:0> = X[t, 64]; elsif PSTATE.EL == EL3 then TTBR0_EL2<63:0> = X[t, 64];

MRS <Xt>, TTBR0_EL1

op0op1CRnCRmop2
0b110b0000b00100b00000b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TRVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.TTBR0_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then X[t, 64] = NVMem[0x200]; else X[t, 64] = TTBR0_EL1<63:0>;; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then X[t, 64] = TTBR0_EL2<63:0>;; else X[t, 64] = TTBR0_EL1<63:0>;; elsif PSTATE.EL == EL3 then X[t, 64] = TTBR0_EL1<63:0>;;

MSR TTBR0_EL1, <Xt>

op0op1CRnCRmop2
0b110b0000b00100b00000b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGWTR_EL2.TTBR0_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then NVMem[0x200] = X[t, 64]; else TTBR0_EL1<63:0> = X[t, 64]; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then TTBR0_EL2<63:0> = X[t, 64]; else TTBR0_EL1<63:0> = X[t, 64]; elsif PSTATE.EL == EL3 then TTBR0_EL1<63:0> = X[t, 64];

When FEAT_D128 is implemented
MRRS <Xt+1>, <Xt>, TTBR0_EL2

op0op1CRnCRmop2
0b110b1000b00100b00000b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x14); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.D128En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.D128En == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); else (X[t + 1, 64], X[t, 64]) = (TTBR0_EL2<127:64>, TTBR0_EL2<63:0>); elsif PSTATE.EL == EL3 then (X[t + 1, 64], X[t, 64]) = (TTBR0_EL2<127:64>, TTBR0_EL2<63:0>);

When FEAT_D128 is implemented
MSRR TTBR0_EL2, <Xt+1>, <Xt>

op0op1CRnCRmop2
0b110b1000b00100b00000b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x14); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.D128En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.D128En == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); else (TTBR0_EL2<127:64>, TTBR0_EL2<63:0>) = (X[t + 1, 64], X[t, 64]); elsif PSTATE.EL == EL3 then (TTBR0_EL2<127:64>, TTBR0_EL2<63:0>) = (X[t + 1, 64], X[t, 64]);

When FEAT_D128 is implemented
MRRS <Xt+1>, <Xt>, TTBR0_EL1

op0op1CRnCRmop2
0b110b0000b00100b00000b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.D128En == '0' then UNDEFINED; elsif EL2Enabled() && HCR_EL2.TRVM == '1' then AArch64.SystemAccessTrap(EL2, 0x14); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.TTBR0_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x14); elsif HaveEL(EL3) && SCR_EL3.D128En == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then (X[t + 1, 64], X[t, 64]) = (NVMem[0x208], NVMem[0x200]); else (X[t + 1, 64], X[t, 64]) = (TTBR0_EL1<127:64>, TTBR0_EL1<63:0>); elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.D128En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.D128En == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); elsif HCR_EL2.E2H == '1' then (X[t + 1, 64], X[t, 64]) = (TTBR0_EL2<127:64>, TTBR0_EL2<63:0>); else (X[t + 1, 64], X[t, 64]) = (TTBR0_EL1<127:64>, TTBR0_EL1<63:0>); elsif PSTATE.EL == EL3 then (X[t + 1, 64], X[t, 64]) = (TTBR0_EL1<127:64>, TTBR0_EL1<63:0>);

When FEAT_D128 is implemented
MSRR TTBR0_EL1, <Xt+1>, <Xt>

op0op1CRnCRmop2
0b110b0000b00100b00000b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.D128En == '0' then UNDEFINED; elsif EL2Enabled() && HCR_EL2.TVM == '1' then AArch64.SystemAccessTrap(EL2, 0x14); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGWTR_EL2.TTBR0_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x14); elsif HaveEL(EL3) && SCR_EL3.D128En == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then (NVMem[0x208], NVMem[0x200]) = (X[t + 1, 64], X[t, 64]); else (TTBR0_EL1<127:64>, TTBR0_EL1<63:0>) = (X[t + 1, 64], X[t, 64]); elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.D128En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.D128En == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); elsif HCR_EL2.E2H == '1' then (TTBR0_EL2<127:64>, TTBR0_EL2<63:0>) = (X[t + 1, 64], X[t, 64]); else (TTBR0_EL1<127:64>, TTBR0_EL1<63:0>) = (X[t + 1, 64], X[t, 64]); elsif PSTATE.EL == EL3 then (TTBR0_EL1<127:64>, TTBR0_EL1<63:0>) = (X[t + 1, 64], X[t, 64]);


3005/0907/2022 1517:5808; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96fb0421fa9a8865165f9b91af9b4a566111f866305

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