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MDCR_EL3, Monitor Debug Configuration Register (EL3)

The MDCR_EL3 characteristics are:

Purpose

Provides EL3 configuration options for self-hosted debug and the Performance Monitors Extension.

Configuration

This register is present only when EL3 is implemented. Otherwise, direct accesses to MDCR_EL3 are UNDEFINED.

Attributes

MDCR_EL3 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0ETBADE3BRECEnITEE3BREWEPMSSADEnPMSNEnPMSSMPMXEBWEMCCDEnPMS3SBRBEPMEERES0E3BRECE3BREWEnPMSNMPMXMCCDSBRBE
RES0PMSSEMTPMEMTPMETDCCTDCCNSTBENSTBENSTBNSTBSCCDSCCDETADETADEPMADEPMADEDADEDADTTRFTTRFSTESTESPMESPMESDDSDDSPD32SPD32NSPBNSPBNSPBENSPBETDOSATDOSATDATDARES0RES0TPMEnPM2RES0TPMEDADERES0ETADEEDADEEPMADEETADERES0EPMADERLTERES0RLTE

Bits [63:5039]

Reserved, RES0.

ETBAD, bits [49:48]
When FEAT_TRBE_EXT is implemented:

External Trace Buffer Access Disable. Controls access to the Trace Buffer registers from an external debugger.

ETBADMeaningApplies when
0b00

Non-secure accesses from an external debugger to Trace Buffer registers are prohibited.

If FEAT_RME is implemented, Secure and Realm accesses from an external debugger to Trace Buffer registers are prohibited and Root accesses to Trace Buffer registers are allowed.

If FEAT_RME is not implemented, Secure accesses to Trace Buffer registers are allowed.

0b01

Secure and Non-secure accesses from an external debugger to Trace Buffer registers are prohibited. Root and Realm accesses to Trace Buffer registers are allowed.

When FEAT_RME is implemented
0b10

Realm and Non-secure accesses from an external debugger to Trace Buffer registers are prohibited. Root and Secure accesses to Trace Buffer registers are allowed.

When FEAT_RME is implemented
0b11

All accesses from an external debugger to Trace Buffer registers are allowed.

If EL3 is not implemented, then the Effective value of this field is 0b11.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

EnITE, bit [47]
When FEAT_ITE is implemented:

Enable access to Instrumentation trace registers. When disabled, accesses to Instrumentation trace registers generate a trap to EL3.

EnITEMeaning
0b0

The following instructions at EL2 and EL1 are trapped to EL3, unless the instruction generates a higher priority exception:

AArch64: MRS and MSR accesses to TRCITECR_EL1, TRCITECR_EL2, and TRCITECR_EL12, reported with EC syndrome value 0x18.

0b1

Accesses of Instrumentation trace registers are not trapped by this mechanism.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

EPMSSAD, bits [46:45]
When FEAT_PMUv3_SS is implemented:

External PMU Snapshot Access Disable. Controls access to the PMU Snapshot registers from an external debugger.

EPMSSADMeaningApplies when
0b00

Non-secure accesses from an external debugger to PMU Snapshot registers are prohibited.

If FEAT_RME is implemented, Secure and Realm accesses from an external debugger to PMU Snapshot registers are prohibited and Root accesses to PMU Snapshot registers are allowed.

If FEAT_RME is not implemented, Secure accesses to PMU Snapshot registers are allowed.

0b01

Secure and Non-secure accesses from an external debugger to PMU Snapshot registers are prohibited. Root and Realm accesses to PMU Snapshot registers are allowed.

When FEAT_RME is implemented
0b10

Realm and Non-secure accesses from an external debugger to PMU Snapshot registers are prohibited. Root and Secure accesses to PMU Snapshot registers are allowed.

When FEAT_RME is implemented
0b11

All accesses from an external debugger to PMU Snapshot registers are allowed.

If EL3 is not implemented, then the Effective value of this field is 0b11.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

EnPMSS, bit [44]
When FEAT_PMUv3_SS is implemented:

Enable access to PMU Snapshot registers. When disabled, accesses to PMU Snapshot registers generate a trap to EL3.

EnPMSSMeaning
0b0

Accesses of the specified PMU Snapshot registers at EL2 and EL1 are trapped to EL3, unless the instruction generates a higher priority exception.

0b1

Accesses of the specified PMU Snapshot registers are not trapped by this mechanism.

In AArch64 state, the instructions affected by this control are:

Unless the instruction generates a higher priority exception, trapped instructions generate an exception to EL3.

Trapped instructions are reported using EC value 0x18.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

EBWE, bit [43]
When FEAT_Debugv8p9 is implemented:

Extended Breakpoint and Watchpoint Enable. Enables use of additional breakpoints or watchpoints, and enables a trap to EL3 on accesses to debug registers.

EBWEMeaning
0b0

The Effective value of MDSCR_EL1.EBWE is 0.

MRS and MSR accesses to MDSELR_EL1 at EL2 and EL1 are trapped to EL3, reported with EC syndrome value 0x18.

0b1

The Effective value of MDSCR_EL1.EBWE is not affected by this bit.

Accesses to MDSELR_EL1 are not trapped by this mechanism.

It is IMPLEMENTATION DEFINED whether this field is implemented or is RES0 when 16 or fewer breakpoints are implemented, 16 or fewer watchpoints are implemented, and MDSELR_EL1 is implemented as RAZ/WI.

If EL3 is not implemented, then the Effective value of this field is 1.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

EnPMS3, bit [42]
When FEAT_SPEv1p4 is implemented or FEAT_SPE_FDS is implemented:

Enable access to additional SPE registers. When disabled, accesses to additional SPE registers generate a trap to EL3.

EnPMS3Meaning
0b0

The following instructions at EL2 and EL1 are trapped to EL3, unless the instruction generates a higher priority exception:

AArch64: MRS and MSR accesses to PMSDSFR_EL1, reported with EC syndrome value 0x18.

0b1

Accesses of additional SPE registers are not trapped by this mechanism.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

PMEE, bits [41:40]
When FEAT_EBEP is implemented:

Performance Monitors Exception Enable. Controls the generation of PMUIRQ signal and PMU exception at all Exception levels.

PMEEMeaning
0b00

PMUIRQ signal is enabled, and PMU exception is disabled.

0b01

PMUIRQ signal and PMU exception are both controlled by MDCR_EL2.PMEE.

0b10

PMUIRQ signal is disabled, and PMU exception is disabled.

0b11

PMUIRQ signal is disabled, and PMU exception is enabled.

If EL3 is not implemented, then the Effective value of this field is 0b01.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Bit [39]

Reserved, RES0.

E3BREC, bit [38]
When FEAT_BRBEv1p1 is implemented:

Branch Record Buffer EL3 Cold Reset Enable. With MDCR_EL3.E3BREW, controls branch recording at EL3.

E3BRECMeaning
0b0

When MDCR_EL3.E3BREW == 0: Branch recording at EL3 is disabled.

When MDCR_EL3.E3BREW == 1: Branch recording at EL3 is enabled.

0b1

When MDCR_EL3.E3BREW == 0: Branch recording at EL3 is enabled.

When MDCR_EL3.E3BREW == 1: Branch recording at EL3 is disabled.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

E3BREW, bit [37]
When FEAT_BRBEv1p1 is implemented:

Branch Record Buffer EL3 Warm Reset Enable. With MDCR_EL3.E3BREC, controls branch recording at EL3.

For a description of the values derived by evaluating MDCR_EL3.E3BREC and MDCR_EL3.E3BREW together, see MDCR_EL3.E3BREC.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

EnPMSN, bit [36]
When FEAT_SPEv1p2 is implemented:

Trap accesses to PMSNEVFR_EL1. Controls access to Statistical Profiling PMSNEVFR_EL1 System register from EL2 and EL1.

EnPMSNMeaning
0b0

Accesses to PMSNEVFR_EL1 at EL2 and EL1 generate a Trap exception to EL3.

0b1

Do not trap PMSNEVFR_EL1 to EL3.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

MPMX, bit [35]
When FEAT_PMUv3p7 is implemented:

Monitor Performance Monitors Extended control. WithIn conjunction with MDCR_EL3.SPME, controls PMUwhen operationevent counters are enabled at EL3.EL3 and in other Secure Exception levels.

MPMXMeaning
0b0

CountersEvent arecounting not affected by this mechanism.andPMCCNTR_EL0 are not affected by this mechanism.

0b1

SomeEvent counting by some or all event counters areis prohibited from counting at EL3. IfPMCR_EL0.DP is 1, PMCCNTR_EL0 is disabled at EL3. Otherwise, PMCCNTR_EL0 is not affected by this mechanism.

If PMCR_EL0.DP is 1, PMCCNTR_EL0 is disabled at EL3. Otherwise, PMCCNTR_EL0 is not affected by this mechanism.

TheIf countersEL2 affectedis byimplemented, thisMDCR_EL3.SPME field== are:1, andMDCR_EL2.HPMN is less than PMCR_EL0.N then all the following are true:

If EL2 is not implemented, MDCR_EL3.SPME == 0, or MDCR_EL2.HPMN is equal to PMCR_EL0.N then this field affects the operation of all event counters at EL3, and if PMCR_EL0.DP is 1, the operation of PMCCNTR_EL0 at EL3.

OtherThe eventoperation countersof arethis notfield affectedapplies byeven thiswhen field.EL2 Whenis disabled in the current Security state. PMCR_EL0.DP is 0, PMCCNTR_EL0 is not affected by this field.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

MCCD, bit [34]
When FEAT_PMUv3p7 is implemented:

Monitor Cycle Counter Disable. Prohibits the Cycle Counter, PMCCNTR_EL0, from counting at EL3.

MCCDMeaning
0b0

Cycle counting by PMCCNTR_EL0 is not affected by this mechanism.

0b1

Cycle counting by PMCCNTR_EL0 is prohibited at EL3.

This field does not affect the CPU_CYCLES event or any other event that counts cycles.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

SBRBE, bits [33:32]
When FEAT_BRBE is implemented:

Secure Branch Record Buffer Enable. Controls branch recording by the BRBE, and access to BRBE registers and instructions at EL2 and EL1.

SBRBEMeaning
0b00

Direct accesses to BRBE registers and instructions, except when in EL3, generate a Trap exception to EL3. EL0, EL1, and EL2 are prohibited regions.

0b01

Direct accesses to BRBE registers and instructions in Secure state, except when in EL3, generate a Trap exception to EL3. EL0, EL1, and EL2 in Secure state are prohibited regions. This control does not cause any direct accesses to BRBE registers when not in Secure state to be trapped, and does not cause any Exception levels when not in Secure state to be a prohibited region.

0b10

Direct accesses to BRBE registers and instructions, except when in EL3, generate a Trap exception to EL3. This control does not cause any Exception levels to be prohibited regions.

0b11

This control does not cause any direct accesses to BRBE registers or instruction to be trapped, and does not cause any Exception levels to be a prohibited region.

The Branch Record Buffer registers trapped by this control are: BRBCR_EL1, BRBCR_EL2, BRBCR_EL12, BRBFCR_EL1, BRBIDR0_EL1, BRBINF<n>_EL1, BRBINFINJ_EL1, BRBSRC<n>_EL1, BRBSRCINJ_EL1, BRBTGT<n>_EL1, BRBTGTINJ_EL1, and BRBTS_EL1.

The Branch Record Buffer instructions trapped by this control are:

Note

If FEAT_BRBEv1p1 is not implemented, EL3 is a prohibited region.

If EL3 is not implemented then the Effective value of this field is 0b11.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

BitBits [31:29]

Reserved, RES0.

PMSSE, bits [30:29]
When FEAT_PMUv3_SS is implemented:

Performance Monitors Snapshot Enable. Controls the generation of Capture events.

PMSSEMeaning
0b00

Capture events are disabled.

0b01

Capture events are enabled and prohibited.

0b11

Capture events are enabled and allowed.

All other values are reserved.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

MTPME, bit [28]
When FEAT_MTPMU is implemented:

Multi-threaded PMU Enable. Enables use of the PMEVTYPER<n>_EL0.MT bits.

MTPMEMeaning
0b0

FEAT_MTPMU is disabled. The Effective value of PMEVTYPER<n>_EL0.MT is zero.

0b1

PMEVTYPER<n>_EL0.MT bits not affected by this field.

If FEAT_MTPMU is disabled for any other PE in the system that has the same level 1 Affinity as the PE, it is IMPLEMENTATION DEFINED whether the PE behaves as if this field is 0.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

TDCC, bit [27]
When FEAT_FGT is implemented:

Trap DCC. Traps use of the Debug Comms Channel at EL2, EL1, and EL0 to EL3.

TDCCMeaning
0b0

This control does not cause any register accesses to be trapped.

0b1

Accesses to the DCC registers at EL2, EL1, and EL0 generate a Trap exception to EL3, unless the access also generates a higher priority exception.

Traps on the DCC data transfer registers are ignored when the PE is in Debug state.

The DCC registers trapped by this control are:

AArch64: OSDTRRX_EL1, OSDTRTX_EL1, MDCCSR_EL0, MDCCINT_EL1, and, when the PE is in Non-debug state, DBGDTR_EL0, DBGDTRRX_EL0, and DBGDTRTX_EL0.

AArch32: DBGDTRRXext, DBGDTRTXext, DBGDSCRint, DBGDCCINT, and, when the PE is in Non-debug state, DBGDTRRXint and DBGDTRTXint.

The traps are reported with EC syndrome value:

When the PE is in Debug state, MDCR_EL3.TDCC does not trap any accesses to:

AArch64: DBGDTR_EL0, DBGDTRRX_EL0, and DBGDTRTX_EL0.

AArch32: DBGDTRRXint and DBGDTRTXint.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

NSTBE, bit [26]
When FEAT_TRBE is implemented and FEAT_RME is implemented:

Non-secure Trace Buffer Extended. Together with MDCR_EL3.NSTB, controls the owning translation regime and accesses to Trace Buffer control registers from EL2 and EL1.

For a description of the values derived by evaluating NSTB and NSTBE together, see MDCR_EL3.NSTB.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

NSTB, bits [25:24]
When FEAT_TRBE is implemented and FEAT_RME is implemented:

Non-secure Trace Buffer. Together with MDCR_EL3.NSTBE, controls the owning translation regime and accesses to Trace Buffer control registers from EL2 and EL1.

NSTBENSTBMeaning
0b00b00Secure state owns the Trace Buffer. When TraceBufferEnabled()==TRUE, tracing is prohibited in Realm and Non-secure states. Accesses to Trace Buffer control registers at EL2 and EL1 generate Trap exceptions to EL3. When Secure state is not implemented, this encoding is reserved.
0b00b01Secure state owns the Trace Buffer. When TraceBufferEnabled()==TRUE, tracing is prohibited in Realm and Non-secure states. Accesses to Trace Buffer control registers at Realm and Non-secure EL2, and Realm and Non-secure EL1, generate Trap exceptions to EL3. When Secure state is not implemented, this encoding is reserved.
0b00b10Non-secure state owns the Trace Buffer. When TraceBufferEnabled()==TRUE, tracing is prohibited in Secure and Realm states. Accesses to Trace Buffer control registers at EL2 and EL1 generate Trap exceptions to EL3.
0b00b11Non-secure state owns the Trace Buffer. When TraceBufferEnabled()==TRUE, tracing is prohibited in Secure and Realm states. Accesses to Trace Buffer control registers at Secure and Realm EL2, and Secure and Realm EL1, generate Trap exceptions to EL3.
0b10b0xReserved
0b10b10Realm state owns the Trace Buffer. When TraceBufferEnabled()==TRUE, tracing is prohibited in Secure and Non-secure states. Accesses to Trace Buffer control registers at EL2 and EL1 generate Trap exceptions to EL3.
0b10b11Realm state owns the Trace Buffer. When TraceBufferEnabled()==TRUE, tracing is prohibited in Secure and Non-secure states. Accesses to Trace Buffer control registers at Secure and Non-secure EL2, and Secure and Non-secure EL1, generate Trap exceptions to EL3.
NSTBMeaning
0b00

When MDCR_EL3.NSTBE == 0b0:

Trace Buffer owning Security state is Secure state. If TraceBufferEnabled() == TRUE, tracing is prohibited in Non-secure and Realm state. Accesses to Trace Buffer control registers at EL2 and EL1 generate Trap exceptions to EL3.

When MDCR_EL3.NSTBE == 0b1: Reserved.

0b01

When MDCR_EL3.NSTBE == 0b0:

Trace Buffer owning Security state is Secure state. If TraceBufferEnabled() == TRUE, tracing is prohibited in Non-secure and Realm state. Accesses to Trace Buffer control registers at EL2 and EL1 in Non-secure and Realm state generate Trap exceptions to EL3.

When MDCR_EL3.NSTBE == 0b1: Reserved.

0b10

When MDCR_EL3.NSTBE == 0b0:

Trace Buffer owning Security state is Non-secure state. If TraceBufferEnabled() == TRUE, tracing is prohibited in Secure and Realm state. Accesses to Trace Buffer control registers at EL2 and EL1 generate Trap exceptions to EL3.

When MDCR_EL3.NSTBE == 0b1:

Trace Buffer owning Security state is Realm state. If TraceBufferEnabled() == TRUE, tracing is prohibited in Non-secure and Secure state. Accesses to Trace Buffer control registers at EL2 and EL1 generate Trap exceptions to EL3.

0b11

When MDCR_EL3.NSTBE == 0b0:

Trace Buffer owning Security state is Non-secure state. If TraceBufferEnabled() == TRUE, tracing is prohibited in Secure and Realm state. Accesses to Trace Buffer control registers at EL2 and EL1 in Secure and Realm state generate Trap exceptions to EL3.

When MDCR_EL3.NSTBE == 0b1:

Trace Buffer owning Security state is Realm state. If TraceBufferEnabled() == TRUE, tracing is prohibited in Non-secure and Secure state. Accesses to Trace Buffer control registers at EL2 and EL1 in Non-secure and Secure state generate Trap exceptions to EL3.

The Trace Buffer control registers trapped by this control are: TRBBASER_EL1, TRBLIMITR_EL1, TRBMAR_EL1, TRBPTR_EL1, TRBSR_EL1, and TRBTRG_EL1.

The reset behavior of this field is:


When FEAT_TRBE is implemented and FEAT_RME is not implemented:

Non-secure Trace Buffer. Controls the owning translation regime and accesses to Trace Buffer control registers from EL2 and EL1.

NSTBMeaning
0b00

Trace Buffer owning Security state is Secure state. If TraceBufferEnabled() == TRUE, tracing is prohibited in Non-secure state. Accesses to Trace Buffer control registers at EL2 and EL1 generate Trap exceptions to EL3.

0b01

Trace Buffer owning Security state is Secure state. If TraceBufferEnabled() == TRUE, tracing is prohibited in Non-secure state. Accesses to Trace Buffer control registers at EL2 and EL1 in Non-secure state generate Trap exceptions to EL3.

0b10

Trace Buffer owning Security state is Non-secure state. If TraceBufferEnabled() == TRUE, tracing is prohibited in Secure state. Accesses to Trace Buffer control registers at EL2 and EL1 generate Trap exceptions to EL3.

0b11

Trace Buffer owning Security state is Non-secure state. If TraceBufferEnabled() == TRUE, tracing is prohibited in Secure state. Accesses to Trace Buffer control registers at EL2 and EL1 in Secure state generate Trap exceptions to EL3.

The Trace Buffer control registers trapped by this control are: TRBBASER_EL1, TRBLIMITR_EL1, TRBMAR_EL1, TRBPTR_EL1, TRBSR_EL1, and TRBTRG_EL1.

If EL3 is not implemented and the Effective value of SCR_EL3.NS is 1, then the Effective value of this field is 0b11.

If EL3 is not implemented and the Effective value of SCR_EL3.NS is 0, then the Effective value of this field is 0b01.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

SCCD, bit [23]
When FEAT_PMUv3p5 is implemented:

Secure Cycle Counter Disable. Prohibits PMCCNTR_EL0 from counting in Secure state.

SCCDMeaning
0b0

Cycle counting by PMCCNTR_EL0 is not affected by this mechanism.

0b1

Cycle counting by PMCCNTR_EL0 is prohibited in Secure state.

This field does not affect the CPU_CYCLES event or any other event that counts cycles.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

ETAD, bit [22]
When FEAT_RME is implemented, external debugger access to the trace unit registers is implemented and FEAT_TRBE is implemented:

External Trace Access Disable. Together with MDCR_EL3.ETADE, controls access to trace unit registers by an external debugger.

ETADEETADMeaning
0b00b0Access to trace unit registers by an external debugger is permitted.
0b00b1Root and Secure access to trace unit registers by an external debugger is permitted. Realm and Non-secure access to trace unit registers by an external debugger is not permitted.
0b10b0Root and Realm access to trace unit registers by an external debugger is permitted. Secure and Non-secure access to trace unit registers by an external debugger is not permitted.
0b10b1Root access to trace unit registers by an external debugger is permitted. Secure, Non-secure, and Realm access to trace unit registers by an external debugger is not permitted.

The reset behavior of this field is:


When external debugger access to the trace unit registers is implemented and FEAT_TRBE is implemented:

External Trace Access Disable. Controls Non-secure access to trace unit registers by an external debugger.

ETADMeaning
0b0

Non-secure accesses from an external debugger to trace unit are allowed.

0b1

Non-secure accesses from an external debugger to some trace unit registers are prohibited. See individual registers for the effect of this field.

If EL3 is not implemented and the Effective value of SCR_EL3.NS is 0, then the Effective value of this field is 1.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

EPMAD, bit [21]
When FEAT_RME is implemented, FEAT_PMUv3 is implemented and the Performance Monitors Extension supports external debug interface accesses:

External Performance Monitors Access Disable. Together with MDCR_EL3.EPMADE, controls access to Performance Monitor registers by an external debugger.

EPMADEEPMADMeaning
0b00b0Access to Performance Monitor registers by an external debugger is permitted.
0b00b1Root and Secure access to Performance Monitor registers by an external debugger is permitted. Realm and Non-secure access to Performance Monitor registers by an external debugger is not permitted.
0b10b0Root and Realm access to Performance Monitor registers by an external debugger is permitted. Secure and Non-secure access to Performance Monitor registers by an external debugger is not permitted.
0b10b1Root access to Performance Monitor registers by an external debugger is permitted. Secure, Non-secure, and Realm access to Performance Monitor registers by an external debugger is not permitted.

The reset behavior of this field is:


When FEAT_Debugv8p4 is implemented, FEAT_PMUv3 is implemented and the Performance Monitors Extension supports external debug interface accesses:

External Performance Monitors Non-secure Access Disable. Controls Non-secure access to Performance Monitor registers by an external debugger.

EPMADMeaning
0b0

Non-secure access to Performance Monitor registers from external debugger is permitted.

0b1

Non-secure access to Performance Monitor registers from external debugger is not permitted.

If EL3 is not implemented and the Effective value of SCR_EL3.NS is 0b0, then the Effective value of this bit is 0b1.

The reset behavior of this field is:


When FEAT_PMUv3 is implemented and the Performance Monitors Extension supports external debug interface accesses:

External Performance Monitors Access Disable. Controls access to Performance Monitor registers by an external debugger.

EPMADMeaning
0b0

Access to Performance Monitor registers from external debugger is permitted.

0b1

Access to Performance Monitor registers from external debugger is not permitted, unless overridden by the IMPLEMENTATION DEFINED authentication interface.

If EL3 is not implemented and the Effective value of SCR_EL3.NS is 0b0, then the Effective value of this bit is 0b1.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

EDAD, bit [20]
When FEAT_RME is implemented:

External Debug Access Disable. Together with MDCR_EL3.EDADE, controls access to breakpoint registers, watchpoint registers, and OSLAR_EL1 by an external debugger.

EDADEEDADMeaning
0b00b0Access to Debug registers by an external debugger is permitted.
0b00b1Root and Secure access to Debug registers by an external debugger is permitted. Realm and Non-secure access to Debug registers by an external debugger is not permitted.
0b10b0Root and Realm access to Debug registers by an external debugger is permitted. Secure and Non-secure access to Debug registers by an external debugger is not permitted.
0b10b1Root access to Debug registers by an external debugger is permitted. Secure, Non-secure, and Realm access to Debug registers by an external debugger is not permitted.

The reset behavior of this field is:


When FEAT_Debugv8p4 is implemented:

External Debug Non-secure Access Disable. Controls Non-secure access to breakpoint, watchpoint, and OSLAR_EL1 registers by an external debugger.

EDADMeaning
0b0

Non-secure access to debug registers from external debugger is permitted.

0b1

Non-secure access to breakpoint and watchpoint registers, and OSLAR_EL1 from external debugger is not permitted.

If EL3 is not implemented and the Effective value of SCR_EL3.NS is 0b0, then the Effective value of this field is 0b1.

The reset behavior of this field is:


When FEAT_Debugv8p2 is implemented:

External Debug Access Disable. Controls access to breakpoint, watchpoint, and OSLAR_EL1 registers by an external debugger.

EDADMeaning
0b0

Access to debug registers, and to OSLAR_EL1 from external debugger is permitted.

0b1

Access to breakpoint and watchpoint registers, and to OSLAR_EL1 from external debugger is not permitted, unless overridden by the IMPLEMENTATION DEFINED authentication interface.

If EL3 is not implemented and the Effective value of SCR_EL3.NS is 0b0, then the Effective value of this field is 0b1.

The reset behavior of this field is:


Otherwise:

External Debug Access disable. Controls access to breakpoint, watchpoint, and optionally OSLAR_EL1 registers by an external debugger.

EDADMeaning
0b0

Access to debug registers from external debugger is permitted.

0b1

Access to breakpoint and watchpoint registers from an external debugger is not permitted, unless overridden by the IMPLEMENTATION DEFINED authentication interface.

It is IMPLEMENTATION DEFINED whether access to the OSLAR_EL1 register from an external debugger is permitted or not permitted.

If EL3 is not implemented and the Effective value of SCR_EL3.NS is 0b0, then the Effective value of this field is 0b1.

The reset behavior of this field is:

TTRF, bit [19]
When FEAT_TRF is implemented:

Trap Trace Filter controls. Traps use of the Trace Filter control registers at EL2 and EL1 to EL3.

The Trace Filter registers trapped by this control are:

TTRFMeaning
0b0

Accesses to Trace Filter registers at EL2 and EL1 are not affected by this bit.

0b1

Accesses to Trace Filter registers at EL2 and EL1 generate a Trap exception to EL3, unless the access generates a higher priority exception.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

STE, bit [18]
When FEAT_TRF is implemented and Secure state is implemented:

Secure Trace enable. Enables tracing in Secure state.

STEMeaning
0b0

Trace prohibited in Secure state unless overridden by the IMPLEMENTATION DEFINED authentication interface.

0b1

Trace in Secure state is not affected by this bit.

This bit also controls the level of authentication required by an external debugger to enable external tracing. See 'Register controls to enable self-hosted trace'.

If EL3 is not implemented and the Effective value of SCR_EL3.NS is 0b0, the Effective value of this bit is 0b1.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

SPME, bit [17]
When FEAT_PMUv3 is implemented and FEAT_PMUv3p7 is implemented:

Secure Performance Monitors Enable. Controls PMUevent operationcounting in Secure state and at EL3 when MDCR_EL3.MPMX is 0.EL3.

SPMEMeaning
0b0

When MDCR_EL3.MPMX == 0: CountersEvent arecounting is prohibited from counting in Secure state and at EL3.state. If PMCR_EL0.DP is 1, PMCCNTR_EL0 is disabled in Secure state and at EL3.state. Otherwise, PMCCNTR_EL0 is not affected by this mechanism.

0b1

When MDCR_EL3.MPMX == 0: CountersEvent arecounting not affected by this mechanism.andPMCCNTR_EL0 are not affected by this mechanism.

When MDCR_EL3.MPMX is 0, this field affects the operation of all event counters affectedin bySecure thisstate, fieldand are:ifPMCR_EL0.DP is 1, the operation of PMCCNTR_EL0 in Secure state.

When MDCR_EL3.MPMX is 1, this field affects the operation of event counters at EL3 only, and if PMCR_EL0.DP is 1, the operation of PMCCNTR_EL0 at EL3 only. See MDCR_EL3.MPMX for more information.

When PMCR_EL0.DP is 0, PMCCNTR_EL0 is not affected by this field.

When MDCR_EL3.MPMX is 1, this field controls which event counters are affected by MDCR_EL3.MPMX at EL3. See MDCR_EL3.MPMX for more information.

If EL3 is not implemented and the Effective value of SCR_EL3.NS is 0, then the Effective value of this field is 1.

The reset behavior of this field is:


When FEAT_PMUv3 is implemented and FEAT_Debugv8p2 is implemented:

Secure Performance Monitors Enable. Controls PMUevent operationcounting in Secure state.

SPMEMeaning
0b0

WhenEvent MDCR_EL3.MPMXcounting ==is 0: Counters are prohibited from counting in Secure state and at EL3.state. If PMCR_EL0.DP is 1, PMCCNTR_EL0 is disabled in Secure state and at EL3.state. Otherwise, PMCCNTR_EL0 is not affected by this mechanism.

0b1

WhenEvent MDCR_EL3.MPMXcounting == 0: Counters are not affected by this mechanism.andPMCCNTR_EL0 are not affected by this mechanism.

This field affects the operation of all event counters in Secure state, and if PMCR_EL0.DP is 1, the operation of PMCCNTR_EL0 in Secure state. When PMCR_EL0.DP is 0, PMCCNTR_EL0 is not affected by this field.

If EL3 is not implemented and the Effective value of SCR_EL3.NS is 0, then the Effective value of this field is 1.

The reset behavior of this field is:


When FEAT_PMUv3 is implemented:

Secure Performance Monitors Enable. Controls PMUevent operationcounting in Secure state.

SPMEMeaning
0b0

If ExternalSecureNoninvasiveDebugEnabled() is FALSE, event counting is prohibited in Secure state, and if PMCR_EL0.DP is 1, PMCCNTR_EL0 is disabled in Secure state.

0b1

Event counting and PMCCNTR_EL0 are not affected by this mechanism.

If ExternalSecureNoninvasiveDebugEnabled() is TRUE, the event counters and PMCCNTR_EL0 are not affected by this field.

Otherwise, this field affects the operation of all event counters in Secure state, and if PMCR_EL0.DP is 1, the operation of PMCCNTR_EL0 in Secure state. When PMCR_EL0.DP is 0, PMCCNTR_EL0 is not affected by this field.

If EL3 is not implemented and the Effective value of SCR_EL3.NS is 0, then the Effective value of this field is 1.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

SDD, bit [16]
When Secure state is implemented:

AArch64 Secure Self-hosted invasive debug disable. Disables Software debug exceptions in Secure state, other than Breakpoint Instruction exceptions.

SDDMeaning
0b0

Debug exceptions in Secure state are not affected by this bit.

0b1

Debug exceptions, other than Breakpoint Instruction exceptions, are disabled from all Exception levels in Secure state.

The SDD bit is ignored unless both of the following are true:

If Secure EL2 is implemented and enabled, and Secure EL1 is using AArch32, then:

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

SPD32, bits [15:14]
When EL1 is capable of using AArch32:

AArch32 Secure self-hosted privileged debug. Enables or disables debug exceptions from Secure EL1 using AArch32, other than Breakpoint Instruction exceptions.

SPD32Meaning
0b00

Legacy mode. Debug exceptions from Secure EL1 are enabled by the IMPLEMENTATION DEFINED authentication interface.

0b10

Secure privileged debug disabled. Debug exceptions from Secure EL1 are disabled.

0b11

Secure privileged debug enabled. Debug exceptions from Secure EL1 are enabled.

Other values are reserved, and have the CONSTRAINED UNPREDICTABLE behavior that they must have the same behavior as 0b00. Software must not rely on this property as the behavior of reserved values might change in a future revision of the architecture.

This field has no effect on Breakpoint Instruction exceptions. These are always enabled.

This field is ignored unless both of the following are true:

If Secure EL1 is using AArch32, then:

If EL3 is not implemented and the Effective value of SCR_EL3.NS is 0b0, then the Effective value of this field is 0b11.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

NSPB, bits [13:12]
When FEAT_SPE is implemented and FEAT_RME is implemented:

Non-secure Profiling Buffer. Together with MDCR_EL3.NSPBE, controls the owning translation regime and accesses to Statistical Profiling and Profiling Buffer control registers from EL2 and EL1.registers.

NSPBENSPBMeaning
0b00b00The Profiling Buffer uses Secure virtual addresses. Statistical Profiling is disabled in Realm and Non-secure states. Accesses to Statistical Profiling and Profiling Buffer control registers at EL2 and EL1 generate Trap exceptions to EL3. When Secure state is not implemented, this encoding is reserved.
0b00b01The Profiling Buffer uses Secure virtual addresses. Statistical Profiling is disabled in Realm and Non-secure states. Accesses to Statistical Profiling and Profiling Buffer control registers at Realm and Non-secure EL2, and Realm and Non-secure EL1, generate Trap exceptions to EL3. When Secure state is not implemented, this encoding is reserved.
0b00b10The Profiling Buffer uses Non-secure virtual addresses. Statistical Profiling is disabled in Secure and Realm states. Accesses to Statistical Profiling and Profiling Buffer control registers at EL2 and EL1 generate Trap exceptions to EL3.
0b00b11The Profiling Buffer uses Non-secure virtual addresses. Statistical Profiling is disabled in Secure and Realm states. Accesses to Statistical Profiling and Profiling Buffer control registers at Secure and Realm EL2, and Secure and Realm EL1, generate Trap exceptions to EL3.
0b10b0xReserved
0b10b10The Profiling Buffer uses Realm virtual addresses. Statistical Profiling is disabled in Secure and Non-secure states. Accesses to Statistical Profiling and Profiling Buffer control registers at EL2 and EL1 generate Trap exceptions to EL3.
0b10b11The Profiling Buffer uses Realm virtual addresses. Statistical Profiling is disabled in Secure and Non-secure states. Accesses to Statistical Profiling and Profiling Buffer control registers at Secure and Non-secure EL2, and Secure and Non-secure EL1, generate Trap exceptions to EL3.
NSPBMeaning
0b00

When MDCR_EL3.NSPBE == 0b0:

Profiling Buffer uses Secure Virtual Addresses. Statistical Profiling enabled in Secure state and disabled in Non-secure and Realm state. Accesses to Statistical Profiling and Profiling Buffer control registers at EL2 and EL1 in all Security states generate Trap exceptions to EL3.

When MDCR_EL3.NSPBE == 0b1: Reserved.

0b01

When MDCR_EL3.NSPBE == 0b0:

Profiling Buffer uses Secure Virtual Addresses. Statistical Profiling enabled in Secure state and disabled in Non-secure and Realm state. Accesses to Statistical Profiling and Profiling Buffer control registers at EL2 and EL1 in Non-secure and Realm states generate Trap exceptions to EL3.

When MDCR_EL3.NSPBE == 0b1: Reserved.

0b10

When MDCR_EL3.NSPBE == 0b0:

Profiling Buffer uses Non-secure Virtual Addresses. Statistical Profiling enabled in Non-secure state and disabled in Secure and Realm state. Accesses to Statistical Profiling and Profiling Buffer control registers at EL2 and EL1 in all Security states generate Trap exceptions to EL3.

When MDCR_EL3.NSPBE == 0b1:

Profiling Buffer uses Realm Virtual Addresses. Statistical Profiling enabled in Realm state and disabled in Non-secure and Secure state. Accesses to Statistical Profiling and Profiling Buffer control registers at EL2 and EL1 in all Security states generate Trap exceptions to EL3.

0b11

When MDCR_EL3.NSPBE == 0b0:

Profiling Buffer uses Non-secure Virtual Addresses. Statistical Profiling enabled in Non-secure state and disabled in Secure and Realm state. Accesses to Statistical Profiling and Profiling Buffer control registers at EL2 and EL1 in Secure and Realm states generate Trap exceptions to EL3.

When MDCR_EL3.NSPBE == 0b1:

Profiling Buffer uses Realm Virtual Addresses. Statistical Profiling enabled in Realm state and disabled in Non-secure and Secure state. Accesses to Statistical Profiling and Profiling Buffer control registers at EL2 and EL1 in Non-secure and Secure states generate Trap exceptions to EL3.

The Statistical Profiling and Profiling Buffer control registers trapped by this control are:

The reset behavior of this field is:


When FEAT_SPE is implemented and FEAT_RME is not implemented:

Non-secure Profiling Buffer. Controls the owning translation regime and accesses to Statistical Profiling and Profiling Buffer control registers.

NSPBMeaning
0b00

Profiling Buffer uses Secure Virtual Addresses. Statistical Profiling enabled in Secure state and disabled in Non-secure state. Accesses to Statistical Profiling and Profiling Buffer control registers at EL2 and EL1 in Non-secure and Secure states generate Trap exceptions to EL3.

0b01

Profiling Buffer uses Secure Virtual Addresses. Statistical Profiling enabled in Secure state and disabled in Non-secure state. Accesses to Statistical Profiling and Profiling Buffer control registers at EL2 and EL1 in Non-secure state generate Trap exceptions to EL3.

0b10

Profiling Buffer uses Non-secure Virtual Addresses. Statistical Profiling enabled in Non-secure state and disabled in Secure state. Accesses to Statistical Profiling and Profiling Buffer control registers at EL2 and EL1 in Non-secure and Secure states generate Trap exceptions to EL3.

0b11

Profiling Buffer uses Non-secure Virtual Addresses. Statistical Profiling enabled in Non-secure state and disabled in Secure state. Accesses to Statistical Profiling and Profiling Buffer control registers at EL2 and EL1 in Secure state generate Trap exceptions to EL3.

The Statistical Profiling and Profiling Buffer control registers trapped by this control are:

If EL3 is not implemented and the Effective value of SCR_EL3.NS is 1, then the Effective value of this field is 0b11.

If EL3 is not implemented and the Effective value of SCR_EL3.NS is 0, then the Effective value of this field is 0b01.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

NSPBE, bit [11]
When FEAT_SPE is implemented and FEAT_RME is implemented:

Non-secure Profiling Buffer Extended. Together with MDCR_EL3.NSPB, controls the owning translation regime and accesses to Statistical Profiling and Profiling Buffer control registers from EL2 and EL1.registers.

For a description of the values derived by evaluating NSPB and NSPBE together, see MDCR_EL3.NSPB.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

TDOSA, bit [10]
When FEAT_DoubleLock is implemented:

Trap debug OS-related register access. Traps EL2 and EL1 System register accesses to the powerdown debug registers to EL3.

Accesses to the registers are trapped as follows:

TDOSAMeaning
0b0

This control does not cause any instructions to be trapped.

0b1

EL2 and EL1 System register accesses to the powerdown debug registers are trapped to EL3, unless it is trapped by HDCR.TDOSA or MDCR_EL2.TDOSA.

Note

The powerdown debug registers are not accessible at EL0.

The reset behavior of this field is:


Otherwise:

Trap debug OS-related register access. Traps EL2 and EL1 System register accesses to the powerdown debug registers to EL3.

The following registers are affected by this trap:

TDOSAMeaning
0b0

This control does not cause any instructions to be trapped.

0b1

EL2 and EL1 System register accesses to the powerdown debug registers are trapped to EL3, unless it is trapped by HDCR.TDOSA or MDCR_EL2.TDOSA.

Note

The powerdown debug registers are not accessible at EL0.

The reset behavior of this field is:

TDA, bit [9]

Trap Debug Access. Traps EL2, EL1, and EL0 System register accesses to those debug System registers that cannot be trapped using the MDCR_EL3.TDOSA field.

Accesses to the debug registers are trapped as follows:

TDAMeaning
0b0

AccessesThis ofcontrol thedoes specifiednot debugcause Systemany registersinstructions areto notbe trapped by this mechanism.trapped.

0b1

AccessesEL0, ofEL1, and EL2 accesses to the specified debug Systemregisters, other than the registers atthat EL2,can EL1,be andtrapped EL0by MDCR_EL3.TDOSA, are trapped to EL3, unlessfrom theany instructionSecurity generatesstate aand higherboth priorityExecution exception.states, unless it is trapped byDBGDSCRext.UDCCdis, MDSCR_EL1.TDCC, HDCR.TDA or MDCR_EL2.TDA.

AArch64 accesses to DBGDTR_EL0, DBGDTRRX_EL0, and DBGDTRTX_EL0, and AArch32 accesses using MCR or MRC to DBGDTRRXint and DBGDTRTXint are not trapped when the PE is in Debug state.

If 16 or fewer breakpoints and 16 or fewer watchpoints are implemented, and MDSELR_EL1 is implemented as RAZ/WI, then it is IMPLEMENTATION DEFINED whether AArch64 accesses to MDSELR_EL1 are trapped to EL3 when MDCR_EL3.TDA is 1.

The reset behavior of this field is:

BitBits [8:7]

Reserved, RES0.

EnPM2, bit [7]
When FEAT_PMUv3p9 is implemented, or FEAT_SPMU is implemented or FEAT_SEBEP is implemented:

Enable access to additional PMU registers. When disabled, accesses to additional PMU registers generate a trap to EL3.

EnPM2Meaning
0b0

Accesses of the specified additional PMU registers at EL2 and EL1 are trapped to EL3, unless the instruction generates a higher priority exception.

0b1

Accesses of the specified additional PMU registers are not trapped by this mechanism.

In AArch64 state, the instructions affected by this control are:

Unless the instruction generates a higher priority exception, trapped instructions generate an exception to EL3.

Trapped instructions are reported using EC value 0x18.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

TPM, bit [6]
When FEAT_PMUv3 is implemented:

Trap Performance Monitor register accesses. Accesses to all Performance Monitor registers from EL0, EL1, and EL2 to EL3, from any Security state and both Execution states are trapped as follows:

TPMMeaning
0b0

This control does not cause any instructions to be trapped.

0b1

EL2, EL1, and EL0 System register accesses to all Performance Monitor registers are trapped to EL3, unless it is trapped by HDCR.TPM or MDCR_EL2.TPM.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Bit [5]

Reserved, RES0.

EDADE, bit [4]
When FEAT_RME is implemented:

External Debug Access Disable Extended. Together with MDCR_EL3.EDAD, controls access to breakpoint registers, watchpoint registers, and OSLAR_EL1 by an external debugger.

For a description of the values derived by evaluating EDAD and EDADE together, see MDCR_EL3.EDAD.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

ETADE, bit [3]
When FEAT_RME is implemented, external debugger access to the trace unit registers is implemented and FEAT_TRBE is implemented:

External Trace Access Disable Extended. Together with MDCR_EL3.ETAD, controls access to trace unit registers by an external debugger.

For a description of the values derived by evaluating ETAD and ETADE together, see MDCR_EL3.ETAD.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

EPMADE, bit [2]
When FEAT_RME is implemented, FEAT_PMUv3 is implemented and the Performance Monitors Extension supports external debug interface accesses:

External Performance Monitors Access Disable Extended. Together with MDCR_EL3.EPMAD, controls access to Performance Monitor registers by an external debugger.

For a description of the values derived by evaluating EPMAD and EPMADE together, see MDCR_EL3.EPMAD.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Bit [1]

Reserved, RES0.

RLTE, bit [0]
When FEAT_RME is implemented and FEAT_TRF is implemented:

Realm Trace enable. Enables tracing in Realm state.

RLTEMeaning
0b0

Trace prohibited in Realm state, unless overridden by the IMPLEMENTATION DEFINED authentication interface.

0b1

Trace in Realm state is not affected by this bit.

This bit also controls the level of authentication that is required by an external debugger to enable external tracing.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Accessing MDCR_EL3

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, MDCR_EL3

op0op1CRnCRmop2
0b110b1100b00010b00110b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then X[t, 64] = MDCR_EL3;

MSR MDCR_EL3, <Xt>

op0op1CRnCRmop2
0b110b1100b00010b00110b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then MDCR_EL3 = X[t, 64];


3005/0907/2022 1517:5808; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96fb0421fa9a8865165f9b91af9b4a566111f866305

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