ISR_EL1, Interrupt Status Register

The ISR_EL1 characteristics are:

Purpose

Shows the pending status of the IRQ, FIQ, or SError interrupt.

When executing at EL2, EL3 or Secure EL1 when SCR_EL3.EEL2 == 0b0, this shows the pending status of the physical IRQ, FIQ, or SError interrupts.

When executing at either Non-secure EL1 or at Secure EL1 when SCR_EL3.EEL2 == 0b1:

Configuration

AArch64 System register ISR_EL1 bits [31:0] are architecturally mapped to AArch32 System register ISR[31:0].

Attributes

ISR_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0ISFSAIFRES0

Bits [63:11]

Reserved, RES0.

IS, bit [10]
When FEAT_NMI is implemented:

IRQ with Superpriority pending bit. Indicates whether an IRQ interrupt with Superpriority is pending.

ISMeaning
0b0

No pending IRQ with Superpriority.

0b1

An IRQ interrupt with Superpriority is pending.


Otherwise:

Reserved, RES0.

FS, bit [9]
When FEAT_NMI is implemented:

FIQ with Superpriority pending bit. Indicates whether an FIQ interrupt with Superpriority is pending.

FSMeaning
0b0

No pending FIQ with Superpriority.

0b1

An FIQ interrupt with Superpriority is pending.


Otherwise:

Reserved, RES0.

A, bit [8]

SError interrupt pending bit. Indicates whether an SError interrupt is pending.

AMeaning
0b0

No pending SError.

0b1

An SError interrupt is pending.

If the SError interrupt is edge-triggered, this field is cleared to zero when the physical SError interrupt is taken.

I, bit [7]

IRQ pending bit. Indicates whether an IRQ interrupt is pending.

IMeaning
0b0

No pending IRQ.

0b1

An IRQ interrupt is pending.

Note

This bit indicates the presence of a pending IRQ interrupt regardless of whether the interrupt has Superpriority.

F, bit [6]

FIQ pending bit. Indicates whether an FIQ interrupt is pending.

FMeaning
0b0

No pending FIQ.

0b1

An FIQ interrupt is pending.

Note

This bit indicates the presence of a pending FIQ interrupt regardless of whether the interrupt has Superpriority.

Bits [5:0]

Reserved, RES0.

Accessing ISR_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, ISR_EL1

op0op1CRnCRmop2
0b110b0000b11000b00010b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.ISR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = ISR_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = ISR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = ISR_EL1;


05/07/2022 17:08; b0421fa9a8865165f9b91af9b4a566111f866305

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