The PMEVTYPER<n> characteristics are:
Configures event counter n, where n is 0 to 30.
AArch32 System register PMEVTYPER<n> bits [31:0] are architecturally mapped to AArch64 System register PMEVTYPER<n>_EL0[31:0].
AArch32 System register PMEVTYPER<n> bits [31:0] are architecturally mapped to External register PMU.PMEVTYPER<n>_EL0[31:0].
This register is present only when AArch32 is supported and FEAT_PMUv3 is implemented. Otherwise, direct accesses to PMEVTYPER<n> are UNDEFINED.
PMEVTYPER<n> is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
P | U | NSK | NSU | NSH | RES0 | MT | RES0 | RLU | RES0 | evtCount[15:10] | evtCount[9:0] |
Privileged filtering bit. Controls counting in EL1.
If EL3 is implemented, then counting in Non-secure EL1 is further controlled by the PMEVTYPER<n>.NSK bit.
P | Meaning |
---|---|
0b0 |
Count events in EL1. |
0b1 |
Do not count events in EL1. |
The reset behavior of this field is:
User filtering bit. Controls counting in EL0.
If EL3 is implemented, then counting in Non-secure EL0 is further controlled by the PMEVTYPER<n>.NSU bit.
If FEAT_RME is implemented, then counting in Realm EL0 is further controlled by the PMEVTYPER<n>.RLU bit.
U | Meaning |
---|---|
0b0 |
Count events in EL0. |
0b1 |
Do not count events in EL0. |
The reset behavior of this field is:
Non-secure EL1 (kernel) modes filtering bit. Controls counting in Non-secure EL1.
If the value of this bit is equal to the value of PMEVTYPER<n>.P, events in Non-secure EL1 are counted.
Otherwise, events in Non-secure EL1 are not counted.
The reset behavior of this field is:
Reserved, RES0.
Non-secure EL0 (Unprivileged) filtering. Controls counting in Non-secure EL0.
If the value of this bit is equal to the value of PMEVTYPER<n>.U, events in Non-secure EL0 are counted.
Otherwise, events in Non-secure EL0 are not counted.
The reset behavior of this field is:
Reserved, RES0.
EL2 (Hyp mode) filtering bit. Controls counting in EL2.
NSH | Meaning |
---|---|
0b0 |
Do not count events in EL2. |
0b1 |
Count events in EL2. |
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Multithreading.
MT | Meaning |
---|---|
0b0 |
Count events only on controlling PE. |
0b1 |
Count events from any PE with the same affinity at level 1 and above as this PE. |
From Armv8.6, the IMPLEMENTATION DEFINED multi-threaded PMU extension is not permitted, meaning if FEAT_MTPMU is not implemented, this bit is RES0. See ID_DFR1.MTPMU.
This bit is ignored by the PE and treated as zero when FEAT_MTPMU is implemented and Disabled.
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Realm EL0 (unprivileged) filtering bit. Controls counting in Realm EL0.
If the value of this bit is equal to the value of the PMEVTYPER<n>.U bit, events in Realm EL0 are counted.
Otherwise, events in Realm EL0 are not counted.
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Extension to evtCount[9:0]. For more information, see evtCount[9:0].
The reset behavior of this field is:
Reserved, RES0.
Event to count.
The event number of the event that is counted by event counter PMEVCNTR<n>.
The ranges of event numbers allocated to each type of event are shown in 'Allocation of the PMU event number space'.
If FEAT_PMUv3p8 is implemented and PMEVTYPER<n>.evtCount is programmed to an event that is reserved or not supported by the PE, no events are counted and the value returned by a direct or external read of the PMEVTYPER<n>.evtCount field is the value written to the field.
Arm recommends this behavior for all implementations of FEAT_PMUv3.
Otherwise, if PMEVTYPER<n>.evtCount is programmed to an event that is reserved or not supported by the PE, the behavior depends on the value written:
UNPREDICTABLE means the event must not expose privileged information.
The reset behavior of this field is:
PMEVTYPER<n> can also be accessed by using PMXEVTYPER with PMSELR.SEL set to n.
If FEAT_FGT is implemented and <n> is greater than or equal to the number of accessible event counters, then the behavior of permitted reads and writes of PMEVTYPER<n> is as follows:
If FEAT_FGT is not implemented and <n> is greater than or equal to the number of accessible event counters, then reads and writes of PMEVTYPER<n> are CONSTRAINED UNPREDICTABLE, and the following behaviors are permitted:
In EL0, an access is permitted if it is enabled by PMUSERENR.EN or PMUSERENR_EL0.EN.
If EL2 is implemented and enabled in the current Security state, at EL0 and EL1:
Otherwise, the number of accessible event counters is the number of implemented event counters. For more information, see HDCR.HPMN and MDCR_EL2.HPMN.
Accesses to this register use the following encodings in the System register encoding space:
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b1110 | 0b11:m[4:3] | m[2:0] |
integer m = UInt(CRm<1:0>:opc2<2:0>); if m >= NUM_PMU_COUNTERS then if IsFeatureImplemented(FEAT_FGT) then UNDEFINED; else ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); elsif PSTATE.EL == EL0 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then UNDEFINED; elsif !ELUsingAArch32(EL1) && PMUSERENR_EL0.EN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); else AArch64.AArch32SystemAccessTrap(EL1, 0x03); elsif ELUsingAArch32(EL1) && PMUSERENR.EN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then AArch32.TakeHypTrapException(0x00); else UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL1) && HCR_EL2.<E2H,TGE> != '11' && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMEVTYPERn_EL0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TPM == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && m >= AArch32.GetNumEventCountersAccessible() then if !IsFeatureImplemented(FEAT_FGT) then ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); elsif ELUsingAArch32(EL1) then AArch32.TakeHypTrapException(0x03); else AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); else R[t] = PMEVTYPER[m]; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TPM == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && m >= AArch32.GetNumEventCountersAccessible() then if !IsFeatureImplemented(FEAT_FGT) then ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); elsif ELUsingAArch32(EL2) then AArch32.TakeHypTrapException(0x03); else AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); else R[t] = PMEVTYPER[m]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); else R[t] = PMEVTYPER[m]; elsif PSTATE.EL == EL3 then R[t] = PMEVTYPER[m];
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b1110 | 0b11:m[4:3] | m[2:0] |
integer m = UInt(CRm<1:0>:opc2<2:0>); if m >= NUM_PMU_COUNTERS then if IsFeatureImplemented(FEAT_FGT) then UNDEFINED; else ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); elsif PSTATE.EL == EL0 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then UNDEFINED; elsif !ELUsingAArch32(EL1) && PMUSERENR_EL0.EN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); else AArch64.AArch32SystemAccessTrap(EL1, 0x03); elsif ELUsingAArch32(EL1) && PMUSERENR.EN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then AArch32.TakeHypTrapException(0x00); else UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL1) && HCR_EL2.<E2H,TGE> != '11' && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.PMEVTYPERn_EL0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TPM == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && m >= AArch32.GetNumEventCountersAccessible() then if !IsFeatureImplemented(FEAT_FGT) then ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); elsif ELUsingAArch32(EL1) then AArch32.TakeHypTrapException(0x03); else AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); else PMEVTYPER[m] = R[t]; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TPM == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && m >= AArch32.GetNumEventCountersAccessible() then if !IsFeatureImplemented(FEAT_FGT) then ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); elsif ELUsingAArch32(EL2) then AArch32.TakeHypTrapException(0x03); else AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); else PMEVTYPER[m] = R[t]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); else PMEVTYPER[m] = R[t]; elsif PSTATE.EL == EL3 then PMEVTYPER[m] = R[t];
30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f
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