TRCITEEDCR, Instrumentation Trace Extension External Debug Control Register

The TRCITEEDCR characteristics are:

Purpose

Controls instrumentation trace filtering.

Configuration

This register is present only when FEAT_ETE is implemented, FEAT_TRC_SR is implemented and TRCIDR0.ITE == 1. Otherwise, direct accesses to TRCITEEDCR are UNDEFINED.

Attributes

TRCITEEDCR is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0RLSNSE3E2E1E0

Bits [63:7]

Reserved, RES0.

RL, bit [6]
When FEAT_RME is implemented:

Instrumentation Trace in Realm state.

RLMeaning
0b0

Instrumentation trace prohibited in Realm state.

0b1

Instrumentation trace permitted in Realm state.

Used in conjunction with TRCCONFIGR.ITO and TRCITEEDCR.E<m> to control whether Instrumentation trace is permitted or prohibited in Realm state.

This field is ignored when SelfHostedTraceEnabled() returns TRUE.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

S, bit [5]
When Secure state is implemented:

Instrumentation Trace in Secure state.

SMeaning
0b0

Instrumentation trace prohibited in Secure state.

0b1

Instrumentation trace permitted in Secure state.

Used in conjunction with TRCCONFIGR.ITO and TRCITEEDCR.E<m> to control whether Instrumentation trace is permitted or prohibited in Secure state.

This field is ignored when SelfHostedTraceEnabled() returns TRUE.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

NS, bit [4]
When Any of Non-secure EL2, EL1, or EL0 are implemented:

Instrumentation Trace in Non-secure state.

NSMeaning
0b0

Instrumentation trace prohibited in Non-secure state.

0b1

Instrumentation trace permitted in Non-secure state.

Used in conjunction with TRCCONFIGR.ITO and TRCITEEDCR.E<m> to control whether Instrumentation trace is permitted or prohibited in Non-secure state.

This field is ignored when SelfHostedTraceEnabled() returns TRUE.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

E3, bit [3]
When EL3 is implemented:

Instrumentation Trace Enable at EL3.

E3Meaning
0b0

Instrumentation trace prohibited at EL3.

0b1

Instrumentation trace permitted at EL3.

This field is ignored when SelfHostedTraceEnabled() returns TRUE.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

E<m>, bit [m], for m = 2 to 0

Instrumentation Trace Enable at EL<m>.

E<m>Meaning
0b0

Instrumentation trace prohibited at EL<m>.

0b1

Instrumentation trace permitted at EL<m>.

Used in conjunction with TRCCONFIGR.ITO, TRCITEEDCR.NS, TRCITEEDCR.S, and TRCITEEDCR.RL to control whether Instrumentation trace is permitted or prohibited at EL<m> in the specified security states.

This field is ignored when SelfHostedTraceEnabled() returns TRUE.

E<2> is RES0 if EL2 is not implemented in any security states.

The reset behavior of this field is:

Accessing TRCITEEDCR

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, TRCITEEDCR

op0op1CRnCRmop2
0b100b0010b00000b00100b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TTA == '1' then UNDEFINED; elsif CPACR_EL1.TTA == '1' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.TRC == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = TRCITEEDCR; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TTA == '1' then UNDEFINED; elsif CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = TRCITEEDCR; elsif PSTATE.EL == EL3 then if CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = TRCITEEDCR;

MSR TRCITEEDCR, <Xt>

op0op1CRnCRmop2
0b100b0010b00000b00100b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TTA == '1' then UNDEFINED; elsif CPACR_EL1.TTA == '1' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.TRC == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else TRCITEEDCR = X[t, 64]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TTA == '1' then UNDEFINED; elsif CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else TRCITEEDCR = X[t, 64]; elsif PSTATE.EL == EL3 then if CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else TRCITEEDCR = X[t, 64];


30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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