PMCFGR, Performance Monitors Configuration Register

The PMCFGR characteristics are:

Purpose

Contains PMU-specific configuration data.

Configuration

PMCFGR is in the Core power domain.

Attributes

PMCFGR is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
NCGRES0FZORES0UENWTNAEXCCDCCSIZEN

NCG, bits [31:28]

This feature is not supported, so this field is RAZ.

Reads as 0b0000.

Access to this field is RO.

Bits [27:22]

Reserved, RES0.

FZO, bit [21]

Freeze-on-overflow supported. Defined values are:

FZOMeaning
0b0

Freeze-on-overflow mechanism is not supported. PMCR_EL0.FZO is RES0.

0b1

Freeze-on-overflow mechanism is supported. PMCR_EL0.FZO is RW.

FEAT_PMUv3p7 implements the functionality added by the value 0b1.

From Armv8.7, if FEAT_PMUv3 is implemented, the only permitted value is 0b1.

Bit [20]

Reserved, RES0.

UEN, bit [19]

User-mode Enable Register supported. PMUSERENR_EL0 is not visible in the external debug interface, so this bit is RAZ.

Reads as 0b0.

Access to this field is RO.

WT, bit [18]

This feature is not supported, so this bit is RAZ.

Reads as 0b0.

Access to this field is RO.

NA, bit [17]

This feature is not supported, so this bit is RAZ.

Reads as 0b0.

Access to this field is RO.

EX, bit [16]

Export supported. Value is IMPLEMENTATION DEFINED.

EXMeaning
0b0

PMCR_EL0.X is RES0.

0b1

PMCR_EL0.X is read/write.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

CCD, bit [15]

Cycle counter has prescale.

This is RES1 if AArch32 is supported, and RAZ otherwise.

CCDMeaning
0b0

PMCR_EL0.D is RES0.

0b1

PMCR_EL0.D is read/write.

CC, bit [14]

Dedicated cycle counter (counter 31) supported.

Reads as 0b1.

Access to this field is RO.

SIZE, bits [13:8]

Size of counters, minus one. This field defines the size of the largest counter implemented by the Performance Monitors Unit.

From Armv8, the largest counter is 64-bits, so the value of this field is 0b111111.

This field is used by software to determine the spacing of the counters in the memory-map. From Armv8, the counters are a doubleword-aligned addresses.

Reads as 0b111111.

Access to this field is RO.

N, bits [7:0]

Number of counters implemented in addition to the cycle counter, PMCCNTR_EL0. The maximum number of event counters is 31.

NMeaning
0x00

Only PMCCNTR_EL0 implemented.

0x01..0x1F

PMCCNTR_EL0 plus this number of event counters are implemented.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Accessing PMCFGR

Note

AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.

PMCFGR can be accessed through the external debug interface:

ComponentOffsetInstance
PMU0xE00PMCFGR

This interface is accessible as follows:


05/07/2022 17:08; b0421fa9a8865165f9b91af9b4a566111f866305

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