The GICR_INMIR<n>E characteristics are:
Controls whether the corresponding Extended PPI has the non-maskable property.
This register is present only when FEAT_GICv3p1 is implemented and FEAT_GICv3_NMI is implemented. Otherwise, direct accesses to GICR_INMIR<n>E are RES0.
When GICR_TYPER.PPInum is 0b0000 or GICD_TYPER.NMI is 0, these registers are RES0.
A copy of this register is provided for each Redistributor.
GICR_INMIR<n>E is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
nmi31 | nmi30 | nmi29 | nmi28 | nmi27 | nmi26 | nmi25 | nmi24 | nmi23 | nmi22 | nmi21 | nmi20 | nmi19 | nmi18 | nmi17 | nmi16 | nmi15 | nmi14 | nmi13 | nmi12 | nmi11 | nmi10 | nmi9 | nmi8 | nmi7 | nmi6 | nmi5 | nmi4 | nmi3 | nmi2 | nmi1 | nmi0 |
Non-maskable property.
nmi<x> | Meaning |
---|---|
0b0 |
Interrupt does not have the non-maskable property. |
0b1 |
Interrupt has the non-maskable property. |
This bit is RES0 when the corresponding interrupt is configured as Group 0.
The reset behavior of this field is:
If affinity routing is disabled for the Security state of an interrupt, the bit is RES0.
Bits corresponding to unimplemented interrupts are RAZ/WI.
When GICD_CTLR.DS==0, bits corresponding to Group 0 and Secure Group 1 interrupts are RAZ/WI to Non-secure accesses.
Implementations must ensure that an interrupt that is pending at the time of the write uses either the old value or the new value and must ensure that the interrupt is neither lost nor handled more than one time. The effect of the change must be visible in finite time.
Component | Frame | Offset | Instance |
---|---|---|---|
GIC Redistributor | SGI_base | 0x0F80 + (4 * n) | GICR_INMIR<n>E |
Accesses to this interface are RW.
30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f
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