The SPMCFGR_EL1 characteristics are:
Describes the System Performance Monitor.
This register is present only when FEAT_SPMU is implemented. Otherwise, direct accesses to SPMCFGR_EL1 are UNDEFINED.
SPMCFGR_EL1 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
NCG | RES0 | HDBG | TRO | SS | FZO | MSI | RAO | RES0 | NA | EX | RAZ | SIZE | N |
Reserved, RES0.
Counter Groups.
Defines the number of counter groups implemented, minus one.
If this field is zero, then one counter group is implemented and SPMCGCR<n>_EL1 read-as-zero.
Otherwise, for each counter group <m>, SPMCGCR<m DIV 8>_EL1.N<m MOD 8> defines the number of counters in the group.
Locating the first counter in each group depends on the number of implemented groups. Each counter group starts with counter:
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Reserved, RES0.
Halt-on-debug supported. For more information on this field, see 'CoreSight PMU Architecture'.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Trace output supported. For more information on this field, see 'CoreSight PMU Architecture'.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Snapshot supported. For more information on this field, see 'CoreSight PMU Architecture'.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Freeze-on-overflow supported. For more information on this field, see 'CoreSight PMU Architecture'.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Message-signaled interrupts supported. For more information on this field, see 'CoreSight PMU Architecture'.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Reserved, RAO.
Reserved, RES0.
No write access when running. For more information on this field, see 'CoreSight PMU Architecture'.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Export supported. For more information on this field, see 'CoreSight PMU Architecture'.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Reserved, RAZ.
Counter size. The size of the largest implemented counter.
SIZE | Meaning |
---|---|
0b000111 |
8-bit counters. |
0b001001 |
10-bit counters. |
0b001011 |
12-bit counters. |
0b001111 |
16-bit counters. |
0b010011 |
20-bit counters. |
0b010111 |
24-bit counters. |
0b011111 |
32-bit counters. |
0b100011 |
36-bit counters. |
0b100111 |
40-bit counters. |
0b101011 |
44-bit counters. |
0b101111 |
48-bit counters. |
0b110011 |
52-bit counters. |
0b110111 |
56-bit counters. |
0b111111 |
64-bit counters. |
All other values are reserved.
Not all counters must be this size. For example, an implementation might include a mix of 32-bit and 64-bit counters.
Number of event counters.
To access SPMCFGR_EL1 for System PMU <s>, set SPMSELR_EL0.SYSPMUSEL to s.
SPMCFGR_EL1 reads-as-zero if the System PMU selected by SPMSELR_EL0.SYSPMUSEL is not implemented.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b000 | 0b1001 | 0b1101 | 0b111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then X[t, 64] = SPMCFGR_EL1[UInt(SPMSELR_EL0.SYSPMUSEL)]; elsif PSTATE.EL == EL2 then X[t, 64] = SPMCFGR_EL1[UInt(SPMSELR_EL0.SYSPMUSEL)]; elsif PSTATE.EL == EL3 then X[t, 64] = SPMCFGR_EL1[UInt(SPMSELR_EL0.SYSPMUSEL)];
30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.