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PMPIDR3, Performance Monitors Peripheral Identification Register 3

The PMPIDR3 characteristics are:

Purpose

Provides information to identify a Performance Monitor component.

For more information, see 'About the Peripheral identification scheme'.

Configuration

ThisImplementation registerof isthis presentregister only when FEAT_PMUv3_EXT is implemented and an implementation implements PMPIDR3. Otherwise, direct accesses to PMPIDR3 are RES0OPTIONAL.

If FEAT_DoPD is implemented, this register is in the Core power domain. If FEAT_DoPD is not implemented, this register is in the Debug power domain.

This register is required for CoreSight compliance.

Attributes

PMPIDR3 is a 32-bit register.

This register is part of the PMU block.

Field descriptions

313029282726252423222120191817161514131211109876543210
RES0REVANDCMOD

Bits [31:8]

Reserved, RES0.

REVAND, bits [7:4]

Part minor revision. Parts using PMU.PMPIDR2.REVISION as an extension to the Part number must use this field as a major revision number.PMPIDR2.REVISION as an extension to the Part number must use this field as a major revision number.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

CMOD, bits [3:0]

Customer modified. Indicates someone other than the Designer has modified the component.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Accessing PMPIDR3

PMPIDR3 can be accessed through the external debug interface:

ComponentOffsetInstance
PMU0xFECPMPIDR3

This interface is accessible as follows:

Accessing PMPIDR3

Accesses to this register use the following encodings in the external debug interface:

BlockAccess at address 0xFEC

PMPIDR3 can be accessed through the PMU block as follows:

FrameOffset
PMU0xFEC

3005/0907/2022 1517:5708; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96fb0421fa9a8865165f9b91af9b4a566111f866305

Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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