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The PMCCFILTR_EL0 characteristics are:
Determines the modes in which the Cycle Counter, PMU.PMCCNTR_EL0, increments.PMCCNTR_EL0, increments.
External register PMCCFILTR_EL0 bits [31:0] are architecturally mapped to AArch64 System register PMCCFILTR_EL0[31:0].
External register PMCCFILTR_EL0 bits [63:32] are architecturally mapped to AArch64 System register PMCCFILTR_EL0[63:32] when FEAT_PMUv3_EXT64 is implemented.
External register PMCCFILTR_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMCCFILTR[31:0].
This register is present only when FEAT_PMUv3_EXT is implemented. Otherwise, direct accesses to PMCCFILTR_EL0 are RES0.
PMCCFILTR_EL0 is in the Core power domain.
On a Warm or Cold reset, RW fields in this register reset to:
Architecturally UNKNOWN values if the reset is to an Exception level that is using AArch64.
0 if the reset is to an Exception level that is using AArch32.
The register is not affected by an External debug reset.
PMCCFILTR_EL0 is a: 32-bit register.
This register is part of the PMU block.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
P | U | NSK | NSU | NSH | M | RES0 | SH | T | RLK | RLU | RLH | RES0 |
Reserved, RES0.
Privileged filtering bit. Controls counting in EL1.
If EL3 is implemented, then counting in Non-secure EL1 is further controlled by the PMCCFILTR_EL0.NSK bit.
If FEAT_RME is implemented, then counting in Realm EL1 is further controlled by the PMCCFILTR_EL0.RLK bit.
P | Meaning |
---|---|
0b0 | Count cycles in EL1. |
0b1 | Do not count cycles in EL1. |
User filtering bit. Controls counting in EL0.
If EL3 is implemented, then counting in Non-secure EL0 is further controlled by the PMCCFILTR_EL0.NSU bit.
If FEAT_RME is implemented, then counting in Realm EL0 is further controlled by the PMCCFILTR_EL0.RLU bit.
U | Meaning |
---|---|
0b0 | Count cycles in EL0. |
0b1 | Do not count cycles in EL0. |
Non-secure EL1 (kernel) modes filtering bit. Controls counting in Non-secure EL1.
If the value of this bit is equal to the value of the PMCCFILTR_EL0.P bit, cycles in Non-secure EL1 are counted.
Otherwise, cycles in Non-secure EL1 are not counted.
Reserved, RES0.
Non-secure EL0 (Unprivileged) filtering bit. Controls counting in Non-secure EL0.
If the value of this bit is equal to the value of the PMCCFILTR_EL0.U bit, cycles in Non-secure EL0 are counted.
Otherwise, cycles in Non-secure EL0 are not counted.
Reserved, RES0.
EL2 (Hypervisor) filtering bit. Controls counting in EL2.
If FEAT_SEL2 and EL3 are implemented, counting in Secure EL2 is further controlled by the PMCCFILTR_EL0.SH bit.
If FEAT_RME is implemented, then counting in Realm EL2 is further controlled by the PMCCFILTR_EL0.RLH bit.
NSH | Meaning |
---|---|
0b0 | Do not count cycles in EL2. |
0b1 | Count cycles in EL2. |
Reserved, RES0.
Secure EL3 filtering bit.
If the value of this bit is equal to the value of the PMCCFILTR_EL0.P bit, cycles in Secure EL3 are counted.
Otherwise, cycles in Secure EL3 are not counted.
Most applications can ignore this field and set its value to 0.
This field is not visible in the AArch32 PMCCFILTR System register.
Reserved, RES0.
Reserved, RES0.
Secure EL2 filtering.
If the value of this bit is not equal to the value of the PMCCFILTR_EL0.NSH bit, cycles in Secure EL2 are counted.
Otherwise, cycles in Secure EL2 are not counted.
This field is not visible in the AArch32 PMCCFILTR System register.
Reserved, RES0.
Transactional state filtering bit. Controls counting of Attributable events in Non-transactional state.
T | Meaning |
---|---|
0b0 | This bit has no effect on the filtering of events. |
0b1 | Do not count Attributable events in Non-transactional state. |
For each Unattributable event, it is IMPLEMENTATION DEFINED whether the filtering applies.
The reset behavior of this field is:
Reserved, RES0.
Realm EL1 (kernel) filtering bit. Controls counting in Realm EL1.
If the value of this bit is equal to the value of the PMCCFILTR_EL0.P bit, cycles in Realm EL1 are counted.
Otherwise, cycles in Realm EL1 are not counted.
The reset behavior of this field is:
Reserved, RES0.
Realm EL0 (unprivileged) filtering bit. Controls counting in Realm EL0.
If the value of this bit is equal to the value of the PMCCFILTR_EL0.U bit, cycles in Realm EL0 are counted.
Otherwise, cycles in Realm EL0 are not counted.
The reset behavior of this field is:
Reserved, RES0.
Realm EL2 filtering bit. Controls counting in Realm EL2.
If the value of this bit is not equal to the value of the PMCCFILTR_EL0.NSH bit, cycles in Realm EL2 are counted.
Otherwise, cycles in Realm EL2 are not counted.
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
P | U | NSK | NSU | NSH | M | RES0 | SH | T | RLK | RLU | RLH | RES0 |
This interface is accessible as follows:
Privileged filtering bit. Controls counting in EL1.
If EL3 is implemented, then counting in Non-secure EL1 is further controlled by the PMCCFILTR_EL0.NSK bit.
If FEAT_RME is implemented, then counting in Realm EL1 is further controlled by the PMCCFILTR_EL0.RLK bit.
P | Meaning |
---|---|
0b0 | Count cycles in EL1. |
0b1 | Do not count cycles in EL1. |
User filtering bit. Controls counting in EL0.
If EL3 is implemented, then counting in Non-secure EL0 is further controlled by the PMCCFILTR_EL0.NSU bit.
If FEAT_RME is implemented, then counting in Realm EL0 is further controlled by the PMCCFILTR_EL0.RLU bit.
U | Meaning |
---|---|
0b0 | Count cycles in EL0. |
0b1 | Do not count cycles in EL0. |
Non-secure EL1 (kernel) modes filtering bit. Controls counting in Non-secure EL1.
If the value of this bit is equal to the value of the PMCCFILTR_EL0.P bit, cycles in Non-secure EL1 are counted.
Otherwise, cycles in Non-secure EL1 are not counted.
Reserved, RES0.
Non-secure EL0 (Unprivileged) filtering bit. Controls counting in Non-secure EL0.
If the value of this bit is equal to the value of the PMCCFILTR_EL0.U bit, cycles in Non-secure EL0 are counted.
Otherwise, cycles in Non-secure EL0 are not counted.
Reserved, RES0.
EL2 (Hypervisor) filtering bit. Controls counting in EL2.
If FEAT_SEL2 and EL3 are implemented, counting in Secure EL2 is further controlled by the PMCCFILTR_EL0.SH bit.
If FEAT_RME is implemented, then counting in Realm EL2 is further controlled by the PMCCFILTR_EL0.RLH bit.
NSH | Meaning |
---|---|
0b0 | Do not count cycles in EL2. |
0b1 | Count cycles in EL2. |
Reserved, RES0.
Secure EL3 filtering bit.
If the value of this bit is equal to the value of the PMCCFILTR_EL0.P bit, cycles in Secure EL3 are counted.
Otherwise, cycles in Secure EL3 are not counted.
Most applications can ignore this field and set its value to 0.
This field is not visible in the AArch32 PMCCFILTR System register.
Reserved, RES0.
Reserved, RES0.
Secure EL2 filtering.
If the value of this bit is not equal to the value of the PMCCFILTR_EL0.NSH bit, cycles in Secure EL2 are counted.
Otherwise, cycles in Secure EL2 are not counted.
This field is not visible in the AArch32 PMCCFILTR System register.
Reserved, RES0.
Transactional state filtering bit. Controls counting of Attributable events in Non-transactional state.
T | Meaning |
---|---|
0b0 | This bit has no effect on the filtering of events. |
0b1 | Do not count Attributable events in Non-transactional state. |
For each Unattributable event, it is IMPLEMENTATION DEFINED whether the filtering applies.
The reset behavior of this field is:
Reserved, RES0.
Realm EL1 (kernel) filtering bit. Controls counting in Realm EL1.
If the value of this bit is equal to the value of the PMCCFILTR_EL0.P bit, cycles in Realm EL1 are counted.
Otherwise, cycles in Realm EL1 are not counted.
The reset behavior of this field is:
Reserved, RES0.
Realm EL0 (unprivileged) filtering bit. Controls counting in Realm EL0.
If the value of this bit is equal to the value of the PMCCFILTR_EL0.U bit, cycles in Realm EL0 are counted.
Otherwise, cycles in Realm EL0 are not counted.
The reset behavior of this field is:
Reserved, RES0.
Realm EL2 filtering bit. Controls counting in Realm EL2.
If the value of this bit is not equal to the value of the PMCCFILTR_EL0.NSH bit, cycles in Realm EL2 are counted.
Otherwise, cycles in Realm EL2 are not counted.
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.
Accesses to this register use the following encodings in the external debug interface:
PMCCFILTR_EL0 can be accessed through the PMU block as follows:
Frame | Offset |
---|---|
PMU | 0x47C |
PMCCFILTR_EL0 can be accessed through the PMU block as follows:
Frame | Offset |
---|---|
PMU | 0x4F8 |
3005/0907/2022 1517:5707; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96fb0421fa9a8865165f9b91af9b4a566111f866305
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