The ID_AA64PFR1_EL1 characteristics are:
Reserved for future expansion of information about implemented PE features in AArch64 state.
For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'.
There are no configuration notes.
ID_AA64PFR1_EL1 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | NMI | CSV2_frac | |||||||||||||||||||||||||||||
RNDR_trap | SME | RES0 | MPAM_frac | RAS_frac | MTE | SSBS | BT |
Reserved, RES0.
Non-maskable Interrupt. Indicates support for Non-maskable interrupts. Defined values are:
NMI | Meaning |
---|---|
0b0000 |
SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT with its associated instructions are not supported. |
0b0001 |
SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT with its associated instructions are supported. |
All other values are reserved.
FEAT_NMI implements the functionality identified by the value 0b0001.
From Armv8.8, the only permitted value is 0b0001.
CSV2 fractional field. Defined values are:
CSV2_frac | Meaning |
---|---|
0b0000 | Either ID_AA64PFR0_EL1.CSV2 is not 0b0001, or the implementation does not disclose whether FEAT_CSV2_1p1 is implemented. FEAT_CSV2_1p2 is not implemented. |
0b0001 |
FEAT_CSV2_1p1 is implemented, but FEAT_CSV2_1p2 is not implemented. |
0b0010 |
FEAT_CSV2_1p2 is implemented. |
All other values are reserved.
FEAT_CSV2_1p1 implements the functionality identified by the value 0b0001.
FEAT_CSV2_1p2 implements the functionality identified by the value 0b0010.
From Armv8.0, the permitted values are 0b0000, 0b0001, and 0b0010.
The values 0b0001 and 0b0010 are permitted only when ID_AA64PFR0_EL1.CSV2 is 0b0001.
Random Number trap to EL3 field. Defined values are:
RNDR_trap | Meaning |
---|---|
0b0000 | |
0b0001 | Trapping of RNDR and RNDRRS to EL3 is supported. SCR_EL3.TRNDR is present. |
All other values are reserved.
FEAT_RNG_TRAP implements the functionality identified by the value 0b0001.
Scalable Matrix Extension. Defined values are:
SME | Meaning |
---|---|
0b0000 |
SME architectural state and programmers' model are not implemented. |
0b0001 |
SME architectural state and programmers' model are implemented. |
All other values are reserved.
FEAT_SME implements the functionality identified by the value 0b0001.
From Armv9.2, the permitted values are 0b0000 and 0b0001.
If implemented, refer to ID_AA64SMFR0_EL1 and ID_AA64ZFR0_EL1 for information about which SME and SVE instructions are available.
Reserved, RES0.
Indicates the minor version number of support for the MPAM Extension.
Defined values are:
MPAM_frac | Meaning |
---|---|
0b0000 |
The minor version number of the MPAM extension is 0. |
0b0001 |
The minor version number of the MPAM extension is 1. |
All other values are reserved.
When combined with the major version number from ID_AA64PFR0_EL1.MPAM, The combined "major.minor" version is:
MPAM Extension version | MPAM | MPAM_frac |
---|---|---|
Not implemented. | 0b0000 | 0b0000 |
v0.1 is implemented. | 0b0000 | 0b0001 |
v1.0 is implemented. | 0b0001 | 0b0000 |
v1.1 is implemented. | 0b0001 | 0b0001 |
For more information, see 'The Memory Partitioning and Monitoring (MPAM) Extension'.
RAS Extension fractional field. Defined values are:
RAS_frac | Meaning |
---|---|
0b0000 |
If ID_AA64PFR0_EL1.RAS == 0b0001, RAS Extension implemented. |
0b0001 | If ID_AA64PFR0_EL1.RAS == 0b0001, as 0b0000 and adds support for:
Error records accessed through System registers conform to RAS System Architecture v1.1, which includes simplifications to ERR<n>STATUS, and support for the optional RAS Timestamp and RAS Common Fault Injection Model Extensions. |
All other values are reserved.
FEAT_RASv1p1 implements the functionality identified by the value 0b0001.
This field is valid only if ID_AA64PFR0_EL1.RAS == 0b0001.
Support for the Memory Tagging Extension. Defined values are:
MTE | Meaning |
---|---|
0b0000 |
Memory Tagging Extension is not implemented. |
0b0001 |
Instruction-only Memory Tagging Extension is implemented. |
0b0010 |
Full Memory Tagging Extension is implemented. |
0b0011 |
Memory Tagging Extension is implemented with support for asymmetric Tag Check Fault handling. |
All other values are reserved.
FEAT_MTE implements the functionality identified by the value 0b0001.
FEAT_MTE2 implements the functionality identified by the value 0b0010.
FEAT_MTE3 implements the functionality identified by the value 0b0011.
In Armv8.5, the permitted values are 0b0000, 0b0001, 0b0010, and 0b0011.
From Armv8.7, the value 0b0010 is not permitted.
Speculative Store Bypassing controls in AArch64 state. Defined values are:
SSBS | Meaning |
---|---|
0b0000 |
AArch64 provides no mechanism to control the use of Speculative Store Bypassing. |
0b0001 |
AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe. |
0b0010 |
As 0b0001, and adds the MSR and MRS instructions to directly read and write the PSTATE.SSBS field. |
All other values are reserved.
FEAT_SSBS implements the functionality identified by the value 0b0001.
FEAT_SSBS2 implements the functionality identified by the value 0b0010.
Branch Target Identification mechanism support in AArch64 state. Defined values are:
BT | Meaning |
---|---|
0b0000 |
The Branch Target Identification mechanism is not implemented. |
0b0001 |
The Branch Target Identification mechanism is implemented. |
All other values are reserved.
FEAT_BTI implements the functionality identified by the value 0b0001.
From Armv8.5, the only permitted value is 0b0001.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b000 | 0b0000 | 0b0100 | 0b001 |
if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = ID_AA64PFR1_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = ID_AA64PFR1_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = ID_AA64PFR1_EL1;
05/07/2022 17:07; b0421fa9a8865165f9b91af9b4a566111f866305
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