RCWSMASK_EL1, Software Read Check Write Instruction Mask (EL1)

The RCWSMASK_EL1 characteristics are:

Purpose

Contains the software mask used by RCWS instructions.

Configuration

This register is present only when FEAT_THE is implemented. Otherwise, direct accesses to RCWSMASK_EL1 are UNDEFINED.

RCWSMASK_EL1 is a 128-bit register that can also be accessed as a 64-bit value. If it is accessed as a 64-bit register, accesses read and write bits [63:0] and do not modify bits [127:64].

Attributes

RCWSMASK_EL1 is a:

Field descriptions

When FEAT_D128 is implemented:

12712612512412312212112011911811711611511411311211111010910810710610510410310210110099989796
Software_Mask[38]RES0Software_Mask[37:34]RES0Software_Mask[33:30]RES0Software_Mask[29]RES0Software_Mask[28:26]MaskRES0Software_Mask[25:16]
9594939291908988878685848382818079787776757473727170696867666564
Software_Mask[25:16]RES0
6362616059585756555453525150494847464544434241403938373635343332
RES0
313029282726252423222120191817161514131211109876543210
RES0Software_Mask[15:0]RES0

Software_Mask, bits [127, 124:121, 118:115, 113, 111:109, 100:91, 16:1]

Software Mask used to decide which bit-fields are writable to the 128-bit Descriptor by RCWS Instruction.

The Software_Mask field is split as follows:

The reset behavior of this field is:

Bits [126:125]

Reserved, RES0.

Bits [120:119]

Reserved, RES0.

Bit [114]

Reserved, RES0.

Bit [112]

Reserved, RES0.

Mask, bit [108]
When FEAT_THE is implemented and FEAT_MEC is implemented:

Mask used to decide which bit-fields are writable to the 128-Bit Descriptor by RCWS Instructions, aligning with the 128-bit AMEC format.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Bits [107:101]

Reserved, RES0.

Bits [90:17]

Reserved, RES0.

Bit [0]

Reserved, RES0.

Otherwise:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
Software_Mask[30:17]RES0
RES0Software_Mask[16:0]RES0

Software_Mask, bits [63:50, 17:1]

Software Mask used to decide which bit-fields are writable to the 64-bit Descriptor by RCWS Instruction.

The Software_Mask field is split as follows:

The reset behavior of this field is:

Bits [49:18]

Reserved, RES0.

Bit [0]

Reserved, RES0.

Accessing RCWSMASK_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, RCWSMASK_EL1

op0op1CRnCRmop2
0b110b0000b11010b00000b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.RCWMASKEn == '0' then UNDEFINED; elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn2 == '1') && HFGRTR2_EL2.nRCWSMASK_EL1 == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.RCWMASKEn == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = RCWSMASK_EL1<63:0>; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.RCWMASKEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.RCWMASKEn == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = RCWSMASK_EL1<63:0>; elsif PSTATE.EL == EL3 then X[t, 64] = RCWSMASK_EL1<63:0>;

MSR RCWSMASK_EL1, <Xt>

op0op1CRnCRmop2
0b110b0000b11010b00000b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.RCWMASKEn == '0' then UNDEFINED; elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn2 == '1') && HFGWTR2_EL2.nRCWSMASK_EL1 == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.RCWMASKEn == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else RCWSMASK_EL1<63:0> = X[t, 64]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.RCWMASKEn == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.RCWMASKEn == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else RCWSMASK_EL1<63:0> = X[t, 64]; elsif PSTATE.EL == EL3 then RCWSMASK_EL1<63:0> = X[t, 64];

When FEAT_D128 is implemented
MRRS <Xt+1>, <Xt>, RCWSMASK_EL1

op0op1CRnCRmop2
0b110b0000b11010b00000b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.RCWMASKEn == '0' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.D128En == '0' then UNDEFINED; elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn2 == '1') && HFGRTR2_EL2.nRCWSMASK_EL1 == '0' then AArch64.SystemAccessTrap(EL2, 0x14); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.D128En == '0') then AArch64.SystemAccessTrap(EL2, 0x14); elsif HaveEL(EL3) && SCR_EL3.RCWMASKEn == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); elsif HaveEL(EL3) && SCR_EL3.D128En == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); else (X[t + 1, 64], X[t, 64]) = (RCWSMASK_EL1<127:64>, RCWSMASK_EL1<63:0>); elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.RCWMASKEn == '0' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.D128En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.RCWMASKEn == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); elsif HaveEL(EL3) && SCR_EL3.D128En == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); else (X[t + 1, 64], X[t, 64]) = (RCWSMASK_EL1<127:64>, RCWSMASK_EL1<63:0>); elsif PSTATE.EL == EL3 then (X[t + 1, 64], X[t, 64]) = (RCWSMASK_EL1<127:64>, RCWSMASK_EL1<63:0>);

When FEAT_D128 is implemented
MSRR RCWSMASK_EL1, <Xt+1>, <Xt>

op0op1CRnCRmop2
0b110b0000b11010b00000b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.RCWMASKEn == '0' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.D128En == '0' then UNDEFINED; elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn2 == '1') && HFGWTR2_EL2.nRCWSMASK_EL1 == '0' then AArch64.SystemAccessTrap(EL2, 0x14); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.D128En == '0') then AArch64.SystemAccessTrap(EL2, 0x14); elsif HaveEL(EL3) && SCR_EL3.RCWMASKEn == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); elsif HaveEL(EL3) && SCR_EL3.D128En == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); else (RCWSMASK_EL1<127:64>, RCWSMASK_EL1<63:0>) = (X[t + 1, 64], X[t, 64]); elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.RCWMASKEn == '0' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.D128En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.RCWMASKEn == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); elsif HaveEL(EL3) && SCR_EL3.D128En == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); else (RCWSMASK_EL1<127:64>, RCWSMASK_EL1<63:0>) = (X[t + 1, 64], X[t, 64]); elsif PSTATE.EL == EL3 then (RCWSMASK_EL1<127:64>, RCWSMASK_EL1<63:0>) = (X[t + 1, 64], X[t, 64]);


30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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