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The SPMDEVARCH_EL1 characteristics are:
Provides discovery information for the component.
This register is present only when FEAT_SPMU is implemented. Otherwise, direct accesses to SPMDEVARCH_EL1 are UNDEFINED.
SPMDEVARCH_EL1 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
ARCHITECT | PRESENT | REVISION | ARCHVER | ARCHPART |
Reserved, RES0.
Architect. Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
DEVARCH present. Defines that SPMDEVARCH_EL1 register is present.
PRESENT | Meaning |
---|---|
0b0 | Device Architecture information not present. |
0b1 | Device Architecture information present. |
This bit reads as 1.
Revision. Defines the architecture revision of the component.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Architecture Version. Defines the architecture version of the component.
SPMDEVARCH_EL1.ARCHVER and SPMDEVARCH_EL1.ARCHPART are also defined as a single field, SPMDEVARCH_EL1.ARCHID, so that SPMDEVARCH_EL1.ARCHVER is SPMDEVARCH_EL1.ARCHID[15:12].
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Architecture Part. Defines the architecture of the component.
SPMDEVARCH_EL1.ARCHVER and SPMDEVARCH_EL1.ARCHPART are also defined as a single field, SPMDEVARCH_EL1.ARCHID, so that SPMDEVARCH_EL1.ARCHPART is SPMDEVARCH_EL1.ARCHID[11:0].
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
To access SPMDEVARCH_EL1 for System PMU <s>, set SPMSELR_EL0.SYSPMUSEL to s.
SPMDEVARCH_EL1 reads-as-zero if the System PMU selected by SPMSELR_EL0.SYSPMUSEL is not implemented.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b000 | 0b1001 | 0b1101 | 0b101 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then X[t, 64] = SPMDEVARCH_EL1[UInt(SPMSELR_EL0.SYSPMUSEL)]; elsif PSTATE.EL == EL2 then X[t, 64] = SPMDEVARCH_EL1[UInt(SPMSELR_EL0.SYSPMUSEL)]; elsif PSTATE.EL == EL3 then X[t, 64] = SPMDEVARCH_EL1[UInt(SPMSELR_EL0.SYSPMUSEL)];
30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f
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