The TLBI PAALL characteristics are:
Invalidates cached copies of GPT entries from TLBs. Details:
The invalidation applies to TLB entries containing GPT information that relates to a physical address.
The invalidation applies to all TLB entries containing GPT information.
The invalidation affects only the TLBs for the PE executing the operation.
The full set of TLB maintenance instructions that invalidate cached GPT entries is: TLBI PAALL, TLBI PAALLOS, TLBI RPALOS, and TLBI RPAOS.
These instructions have the same ordering, observability, and completion behavior as all other TLBI instructions.
This instruction is present only when FEAT_RME is implemented. Otherwise, direct accesses to TLBI PAALL are UNDEFINED.
TLBI PAALL is a 64-bit System instruction.
This instruction has no applicable fields.
The value in the register specified by <Xt> is ignored.
Accesses to this instruction use the following encodings in the System instruction encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b01 | 0b110 | 0b1000 | 0b0111 | 0b100 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then AArch64.TLBI_PAALL(Shareability_NSH);
05/07/2022 17:08; b0421fa9a8865165f9b91af9b4a566111f866305
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