TRCIDR0, ID Register 0

The TRCIDR0 characteristics are:

Purpose

Returns the tracing capabilities of the trace unit.

Configuration

External register TRCIDR0 bits [31:0] are architecturally mapped to AArch64 System register TRCIDR0[31:0].

This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCIDR0 are RES0.

Attributes

TRCIDR0 is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
RES0COMMTRANSCOMMOPTTSSIZETSMARKITERES0TRCEXDATAQSUPPQFILTCONDTYPENUMEVENTRETSTACKRES0TRCCCITRCCONDTRCBBTRCDATAINSTP0RES1

Bit [31]

Reserved, RES0.

COMMTRANS, bit [30]

Transaction Start element behavior.

COMMTRANSMeaning
0b0

Transaction Start elements are P0 elements.

0b1

Transaction Start elements are not P0 elements.

COMMOPT, bit [29]

Indicates the contents and encodings of Cycle count packets.

COMMOPTMeaning
0b0

Commit mode 0.

0b1

Commit mode 1.

The Commit mode defines the contents and encodings of Cycle Count packets, in particular how Commit elements are indicated by these packets. See the descriptions of these packets for more details.

Accessing this field has the following behavior:

TSSIZE, bits [28:24]

Indicates that the trace unit implements Global timestamping and the size of the timestamp value.

TSSIZEMeaning
0b00000

Global timestamping not implemented.

0b01000

Global timestamping implemented with a 64-bit timestamp value.

All other values are reserved.

This field reads as 0b01000.

TSMARK, bit [23]
When FEAT_ETEv1p1 is implemented:

Indicates whether Timestamp Marker elements are generated.

TSMARKMeaning
0b0

Timestamp Marker elements are not generated.

0b1

Timestamp Marker elements are generated.


Otherwise:

Reserved, RES0.

ITE, bit [22]
When FEAT_ETEv1p3 is implemented:

Indicates whether Instrumentation Trace is implemented.

ITEMeaning
0b0

Instrumentation Trace not implemented.

0b1

Instrumentation Trace implemented.

This field has the value 1 if FEAT_ITE is implemented.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.


Otherwise:

Reserved, RES0.

Bits [21:18]

Reserved, RES0.

TRCEXDATA, bit [17]
When TRCIDR0.TRCDATA != 0b00:

Indicates if the trace unit implements tracing of data transfers for exceptions and exception returns. Data tracing is not implemented in ETE and this field is reserved for other trace architectures. Allocated in other trace architectures.

TRCEXDATAMeaning
0b0

Tracing of data transfers for exceptions and exception returns not implemented.

0b1

Tracing of data transfers for exceptions and exception returns implemented.


Otherwise:

Reserved, RES0.

QSUPP, bits [16:15]

Indicates that the trace unit implements Q element support.

QSUPPMeaning
0b00

Q element support is not implemented.

0b01

Q element support is implemented, and only supports Q elements with instruction counts.

0b10

Q element support is implemented, and only supports Q elements without instruction counts.

0b11

Q element support is implemented, and supports:

  • Q elements with instruction counts.
  • Q elements without instruction counts.

QFILT, bit [14]

Indicates if the trace unit implements Q element filtering.

QFILTMeaning
0b0

Q element filtering is not implemented.

0b1

Q element filtering is implemented.

If TRCIDR0.QSUPP == 0b00 then this field is 0.

CONDTYPE, bits [13:12]
When TRCIDR0.TRCCOND == 1:

Indicates how conditional instructions are traced. Conditional instruction tracing is not implemented in ETE and this field is reserved for other trace architectures. Allocated in other trace architectures.

CONDTYPEMeaning
0b00

Conditional instructions are traced with an indication of whether they pass or fail their condition code check.

0b01

Conditional instructions are traced with an indication of the APSR condition flags.

All other values are reserved.


Otherwise:

Reserved, RES0.

NUMEVENT, bits [11:10]
When TRCIDR4.NUMRSPAIR == 0b0000:

Indicates the number of ETEEvents implemented.

NUMEVENTMeaning
0b00

The trace unit supports 0 ETEEvents.

All other values are reserved.


When TRCIDR4.NUMRSPAIR != 0b0000:

Indicates the number of ETEEvents implemented.

NUMEVENTMeaning
0b00

The trace unit supports 1 ETEEvent.

0b01

The trace unit supports 2 ETEEvents.

0b10

The trace unit supports 3 ETEEvents.

0b11

The trace unit supports 4 ETEEvents.


Otherwise:

Reserved, RES0.

RETSTACK, bit [9]

Indicates if the trace unit supports the return stack.

RETSTACKMeaning
0b0

Return stack not implemented.

0b1

Return stack implemented.

Bit [8]

Reserved, RES0.

TRCCCI, bit [7]

Indicates if the trace unit implements cycle counting.

TRCCCIMeaning
0b0

Cycle counting not implemented.

0b1

Cycle counting implemented.

This field reads as 1.

TRCCOND, bit [6]

Indicates if the trace unit implements conditional instruction tracing. Conditional instruction tracing is not implemented in ETE and this field is reserved for other trace architectures.

TRCCONDMeaning
0b0

Conditional instruction tracing not implemented.

0b1

Conditional instruction tracing implemented.

This field reads as 0.

TRCBB, bit [5]

Indicates if the trace unit implements branch broadcasting.

TRCBBMeaning
0b0

Branch broadcasting not implemented.

0b1

Branch broadcasting implemented.

This field reads as 1.

TRCDATA, bits [4:3]

Indicates if the trace unit implements data tracing. Data tracing is not implemented in ETE and this field is reserved for other trace architectures.

TRCDATAMeaning
0b00

Data tracing not implemented.

0b11

Data tracing implemented.

All other values are reserved.

This field reads as 0b00.

INSTP0, bits [2:1]

Indicates if load and store instructions are P0 instructions. Load and store instructions as P0 instructions is not implemented in ETE and this field is reserved for other trace architectures.

INSTP0Meaning
0b00

Load and store instructions are not P0 instructions.

0b11

Load and store instructions are P0 instructions.

All other values are reserved.

This field reads as 0b00.

Bit [0]

Reserved, RES1.

Accessing TRCIDR0

TRCIDR0 can be accessed through the external debug interface:

ComponentOffsetInstance
ETE0x1E0TRCIDR0

This interface is accessible as follows:


30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.