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The EDHSR characteristics are:
HoldsProvides syndromeDebug informationHalt forStatus a debug event.information.
This register is present only when (FEAT_SME is implemented and an implementation implements EDHSR) or FEAT_Debugv8p9 is implemented. Otherwise, direct accesses to EDHSR are RES0.
EDHSR is in the Core power domain.
This register is present only when FEAT_SME is implemented. Otherwise, direct accesses to EDHSR are RES0.
This register is only valid when the PE is in Debug state and EDSCR.STATUS is 0b101011, indicating a Watchpoint debug event. Otherwise, it has an UNKNOWN value.
The field EDDEVID1.HSR indicates support for this register.
EDHSR is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | WPT | WPTV | WPF | FnP | RES0 | VNCR | RES0 | FnV | RES0 | CM | RES0 | WnR | RES0 |
Reserved, RES0.
All other values are reserved.
Watchpoint number. When EDHSR.WPTV is 1number, holds0 theto index15 of a watchpoint that triggered the Watchpoint debug event.inclusive.
The reset behavior of this field is:
Watchpoint number valid.Valid.
WPTV | Meaning | Applies when |
---|---|---|
0b0 | EDHSR.WPT | When FEAT_SME is implemented and FEAT_Debugv8p9 is not implemented |
0b1 | EDHSR.WPT |
When an entry to Debug state is triggered by a watchpoint match:
The reset behavior of this field is:
Watchpoint match might be False.false-positive.
WPF | Meaning | Applies when |
---|---|---|
0b0 | The watchpoint matched the original access or set of contiguous accesses. | |
0b1 | The watchpoint matched an access or set of contiguous accesses where the lowest accessed address was rounded down to the nearest multiple of 16 bytes and the highest accessed address was rounded up to the nearest multiple of 16 bytes minus 1, but the watchpoint might not have matched the original address of the access or set of contiguous accesses. | When (FEAT_SVE is implemented and FEAT_Debugv8p9 is implemented) or FEAT_SME is implemented |
The reset behavior of this field is:
This field only has meaning if the EDWAR is valid; that is, when the FnV field is 0. If the FnV field is 1, the FnP field is 0.
EDWAR FAR not Precise.
FnP | Meaning | Applies when |
---|---|---|
0b0 | If the | |
0b1 | If | When (FEAT_SVE is implemented and FEAT_Debugv8p9 is implemented) or FEAT_SME is implemented |
The reset behavior of this field is:
Reserved, RES0.
VNCR_EL2 access. Indicates that the Watchpoint debug event came from use of VNCR_EL2 register by EL1 code.
VNCR | Meaning |
---|---|
0b0 | The Watchpoint debug event was not generated by the use of VNCR_EL2 by EL1 code. |
0b1 | The Watchpoint debug event was generated by the use of VNCR_EL2 by EL1 code. |
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
EDWAR FAR not Valid.
FnV | Meaning | Applies when |
---|---|---|
0b0 | EDWAR | |
0b1 | EDWAR | When (FEAT_SVE is implemented and FEAT_Debugv8p9 is implemented) or FEAT_SME is implemented |
The reset behavior of this field is:
Reserved, RES0.
Cache maintenance. Indicates whether the Watchpoint debug event came from a cache maintenance instruction.
CM | Meaning |
---|---|
0b0 | The Watchpoint debug event was not generated by the execution of one of the System instructions identified in the description of value 1. |
0b1 | The Watchpoint debug event was generated by the execution of a cache maintenance instruction. The DC ZVA, DC GVA, and DC GZVA instructions are not cache maintenance instructions, and therefore do not cause this bit to be set to 1. |
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Write not Read. Indicates whether the Watchpoint debug event was caused by an instruction writing to a memory location, or by an instruction reading from a memory location.
WnR | Meaning |
---|---|
0b0 | Watchpoint debug event caused by an instruction reading from a memory location. |
0b1 | Watchpoint debug event caused by an instruction writing to a memory location. |
For Watchpoint debug events on cache maintenance instructions, this bit is set to 1.
For Watchpoint debug events from an atomic instruction, this bit is set to 0 if a read of the location would have generated the Watchpoint debug event, otherwise it is set to 1.
If multiple watchpoints match on the same access, it is UNPREDICTABLE which watchpoint generates the Watchpoint debug event.
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Component | Offset | Instance |
---|---|---|
Debug | 0x038 | EDHSR |
This interface is accessible as follows:
This interface is accessible as follows:
3005/0907/2022 1517:5708; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96fb0421fa9a8865165f9b91af9b4a566111f866305
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