MDSELR_EL1, Breakpoint and Watchpoint Selection Register

The MDSELR_EL1 characteristics are:

Purpose

Selects the current breakpoints or watchpoints accessed by System register instructions.

Configuration

This register is present only when FEAT_Debugv8p9 is implemented. Otherwise, direct accesses to MDSELR_EL1 are UNDEFINED.

Attributes

MDSELR_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0BANKRES0

Bits [63:6]

Reserved, RES0.

BANK, bits [5:4]
When more than 16 breakpoints are implemented or more than 16 watchpoints are implemented:

Breakpoint and watchpoint bank select.

BANKMeaningApplies when
0b00

Select 0 to 15.

0b01

Select 16 to 31.

0b10

Select 32 to 47.

When at least 32 breakpoints or at least 32 watchpoints are implemented
0b11

Select 48 to 63.

When at least 48 breakpoints or at least 48 watchpoints are implemented

Each of the following register names accesses a register for breakpoint or watchpoint <n>, where n = UInt(MDSELR_EL1.BANK:m[3:0]):

This field is ignored by the PE and treated as zeros when the Effective value of MDSCR_EL1.EBWE is 0.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Bits [3:0]

Reserved, RES0.

Accessing MDSELR_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, MDSELR_EL1

op0op1CRnCRmop2
0b100b0000b00000b01000b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TDA == '1' then UNDEFINED; elsif EL2Enabled() && MDCR_EL2.<TDE,TDA> != '00' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TDA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = MDSELR_EL1; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TDA == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TDA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = MDSELR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = MDSELR_EL1;

MSR MDSELR_EL1, <Xt>

op0op1CRnCRmop2
0b100b0000b00000b01000b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TDA == '1' then UNDEFINED; elsif EL2Enabled() && MDCR_EL2.<TDE,TDA> != '00' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TDA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else MDSELR_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TDA == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TDA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else MDSELR_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then MDSELR_EL1 = X[t, 64];


30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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