The HDFGWTR2_EL2 characteristics are:
Provides controls for traps of MSR and MCR writes of debug, trace, PMU, and Statistical Profiling System registers.
This register is present only when FEAT_FGT2 is implemented. Otherwise, direct accesses to HDFGWTR2_EL2 are UNDEFINED.
HDFGWTR2_EL2 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | nPMZR_EL0 | nTRCITECR_EL1 | nPMSDSFR_EL1 | RES0 | nSPMSCR_EL1 | nSPMACCESSR_EL1 | nSPMCR_EL0 | nSPMOVS | nSPMINTEN | nSPMCNTEN | nSPMSELR_EL0 | nSPMEVTYPERn_EL0 | nSPMEVCNTRn_EL0 | nPMSSCR_EL1 | RES0 | nMDSELR_EL1 | nPMUACR_EL1 | nPMICFILTR_EL0 | nPMICNTR_EL0 | nPMIAR_EL1 | nPMECR_EL1 |
Reserved, RES0.
Trap MSR writes of PMZR_EL0 at EL1 and EL0 using AArch64 to EL2.
nPMZR_EL0 | Meaning |
---|---|
0b0 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MSR writes of PMZR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
0b1 |
MSR writes of PMZR_EL0 are not trapped by this mechanism. |
The reset behavior of this field is:
Reserved, RES0.
Trap MSR writes of TRCITECR_EL1 at EL1 using AArch64 to EL2.
nTRCITECR_EL1 | Meaning |
---|---|
0b0 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MSR writes of TRCITECR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
0b1 |
MSR writes of TRCITECR_EL1 are not trapped by this mechanism. |
The reset behavior of this field is:
Reserved, RES0.
Trap MSR writes of PMSDSFR_EL1 at EL1 using AArch64 to EL2.
nPMSDSFR_EL1 | Meaning |
---|---|
0b0 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MSR writes of PMSDSFR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
0b1 |
MSR writes of PMSDSFR_EL1 are not trapped by this mechanism. |
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Trap MSR writes of SPMSCR_EL1 at EL1 using AArch64 to EL2.
nSPMSCR_EL1 | Meaning |
---|---|
0b0 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MSR writes of SPMSCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
0b1 |
MSR writes of SPMSCR_EL1 are not trapped by this mechanism. |
The reset behavior of this field is:
Reserved, RES0.
Trap MSR writes of SPMACCESSR_EL1 at EL1 using AArch64 to EL2.
nSPMACCESSR_EL1 | Meaning |
---|---|
0b0 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MSR writes of SPMACCESSR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
0b1 |
MSR writes of SPMACCESSR_EL1 are not trapped by this mechanism. |
The reset behavior of this field is:
Reserved, RES0.
Trap MSR writes of SPMCR_EL0 at EL1 and EL0 using AArch64 to EL2.
nSPMCR_EL0 | Meaning |
---|---|
0b0 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MSR writes of SPMCR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
0b1 |
MSR writes of SPMCR_EL0 are not trapped by this mechanism. |
The reset behavior of this field is:
Reserved, RES0.
Trap MSR writes of multiple System registers. Enables a trap on MSR writes at EL1 and EL0 using AArch64 of any of the following AArch64 System registers to EL2:
nSPMOVS | Meaning |
---|---|
0b0 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MSR writes at EL1 and EL0 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
0b1 |
MSR writes of the System registers listed above are not trapped by this mechanism. |
The reset behavior of this field is:
Reserved, RES0.
Trap MSR writes of multiple System registers. Enables a trap on MSR writes at EL1 using AArch64 of any of the following AArch64 System registers to EL2:
nSPMINTEN | Meaning |
---|---|
0b0 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MSR writes at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
0b1 |
MSR writes of the System registers listed above are not trapped by this mechanism. |
The reset behavior of this field is:
Reserved, RES0.
Trap MSR writes of multiple System registers. Enables a trap on MSR writes at EL1 and EL0 using AArch64 of any of the following AArch64 System registers to EL2:
nSPMCNTEN | Meaning |
---|---|
0b0 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MSR writes at EL1 and EL0 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
0b1 |
MSR writes of the System registers listed above are not trapped by this mechanism. |
The reset behavior of this field is:
Reserved, RES0.
Trap MSR writes of SPMSELR_EL0 at EL1 and EL0 using AArch64 to EL2.
nSPMSELR_EL0 | Meaning |
---|---|
0b0 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MSR writes of SPMSELR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
0b1 |
MSR writes of SPMSELR_EL0 are not trapped by this mechanism. |
The reset behavior of this field is:
Reserved, RES0.
Trap MSR writes of multiple System registers. Enables a trap on MSR writes at EL1 and EL0 using AArch64 of any of the following AArch64 System registers to EL2:
nSPMEVTYPERn_EL0 | Meaning |
---|---|
0b0 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MSR writes at EL1 and EL0 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
0b1 |
MSR writes of the System registers listed above are not trapped by this mechanism. |
Regardless of the value of this bit, if event counter n is not implemented, a write of SPMEVTYPER<n>_EL0, SPMEVFILTR<n>_EL0, or SPMEVFILT2R<n>_EL0 is UNDEFINED.
The reset behavior of this field is:
Reserved, RES0.
Trap MSR writes of multiple System registers. Enables a trap on MSR writes at EL1 and EL0 using AArch64 of any of the following AArch64 System registers to EL2: SPMEVCNTR<n>_EL0.
nSPMEVCNTRn_EL0 | Meaning |
---|---|
0b0 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MSR writes at EL1 and EL0 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
0b1 |
MSR writes of the System registers listed above are not trapped by this mechanism. |
Regardless of the value of this bit, if event counter n is not implemented, a write of SPMEVCNTR<n>_EL0 is UNDEFINED.
The reset behavior of this field is:
Reserved, RES0.
Trap MSR writes of PMSSCR_EL1 at EL1 using AArch64 to EL2.
nPMSSCR_EL1 | Meaning |
---|---|
0b0 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MSR writes of PMSSCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
0b1 |
MSR writes of PMSSCR_EL1 are not trapped by this mechanism. |
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Trap MSR writes of MDSELR_EL1 at EL1 using AArch64 to EL2.
nMDSELR_EL1 | Meaning |
---|---|
0b0 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MSR writes of MDSELR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
0b1 |
MSR writes of MDSELR_EL1 are not trapped by this mechanism. |
It is IMPLEMENTATION DEFINED whether this field is implemented or is RES0 when 16 or fewer breakpoints are implemented, 16 or fewer watchpoints are implemented, and MDSELR_EL1 is implemented as RAZ/WI.
The reset behavior of this field is:
Reserved, RES0.
Trap MSR writes of PMUACR_EL1 at EL1 using AArch64 to EL2.
nPMUACR_EL1 | Meaning |
---|---|
0b0 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MSR writes of PMUACR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
0b1 |
MSR writes of PMUACR_EL1 are not trapped by this mechanism. |
The reset behavior of this field is:
Reserved, RES0.
Trap MSR writes of PMICFILTR_EL0 at EL1 and EL0 using AArch64 to EL2.
nPMICFILTR_EL0 | Meaning |
---|---|
0b0 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MSR writes of PMICFILTR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
0b1 |
MSR writes of PMICFILTR_EL0 are not trapped by this mechanism. |
The reset behavior of this field is:
Reserved, RES0.
Trap MSR writes of PMICNTR_EL0 at EL1 and EL0 using AArch64 to EL2.
nPMICNTR_EL0 | Meaning |
---|---|
0b0 |
If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MSR writes of PMICNTR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
0b1 |
MSR writes of PMICNTR_EL0 are not trapped by this mechanism. |
The reset behavior of this field is:
Reserved, RES0.
Trap MSR writes of PMIAR_EL1 at EL1 using AArch64 to EL2.
nPMIAR_EL1 | Meaning |
---|---|
0b0 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MSR writes of PMIAR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
0b1 |
MSR writes of PMIAR_EL1 are not trapped by this mechanism. |
The reset behavior of this field is:
Reserved, RES0.
Trap MSR writes of PMECR_EL1 at EL1 using AArch64 to EL2.
nPMECR_EL1 | Meaning |
---|---|
0b0 |
If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MSR writes of PMECR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. |
0b1 |
MSR writes of PMECR_EL1 are not trapped by this mechanism. |
The reset behavior of this field is:
Reserved, RES0.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0011 | 0b0001 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then X[t, 64] = NVMem[0x1B0]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then X[t, 64] = HDFGWTR2_EL2; elsif PSTATE.EL == EL3 then X[t, 64] = HDFGWTR2_EL2;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b100 | 0b0011 | 0b0001 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then NVMem[0x1B0] = X[t, 64]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then HDFGWTR2_EL2 = X[t, 64]; elsif PSTATE.EL == EL3 then HDFGWTR2_EL2 = X[t, 64];
30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f
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