CounterID<n>, Counter ID registers, n = 0 - 11

The CounterID<n> characteristics are:

Purpose

IMPLEMENTATION DEFINED identification registers 0 to 11 for the memory-mapped Generic Timer.

Configuration

The power domain of CounterID<n> is IMPLEMENTATION DEFINED.

For more information, see 'Power and reset domains for the system level implementation of the Generic Timer'.

These registers are implemented independently in each of the implemented Generic Timer memory-mapped frames.

If the implementation of the Counter ID registers requires an architecture version, the value for this version of the Arm Generic Timer is version 0.

The Counter ID registers can be implemented as a set of CoreSight ID registers, comprising Peripheral ID Registers and Component ID Registers. An implementation of these registers for the Generic Timer must use a Component class value of 0xF.

Attributes

CounterID<n> is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
IMPLEMENTATION DEFINED

IMPLEMENTATION DEFINED, bits [31:0]

IMPLEMENTATION DEFINED.

Accessing CounterID<n>

These registers must be implemented, as RO registers, in every implemented Generic Timer memory-mapped frame.

For the CNTCTLBase frame, in a system that recognizes two Security states these registers are accessible by both Secure and Non-secure accesses.

For the CNTControlBase frame, in a system that supports Secure and Non-secure memory maps the frame is implemented only in the Secure memory map, meaning these registers are implemented only in the Secure memory map.

For the CNTBaseN frames, 'CNTCTLBase status and control fields for the CNTBaseN and CNTEL0BaseN frames' describes the status fields that identify whether a frame is implemented, and for an implemented frame:

CounterID<n> can be accessed through the memory-mapped interfaces:

ComponentFrameOffsetInstance
TimerCNTControlBase0xFD0 + (4 * n)CounterID<n>

Accesses to this interface are RO.

ComponentFrameOffsetInstance
TimerCNTReadBase0xFD0 + (4 * n)CounterID<n>

Accesses to this interface are RO.

ComponentFrameOffsetInstance
TimerCNTBaseN0xFD0 + (4 * n)CounterID<n>

Accesses to this interface are RO.

ComponentFrameOffsetInstance
TimerCNTEL0BaseN0xFD0 + (4 * n)CounterID<n>

Accesses to this interface are RO.

ComponentFrameOffsetInstance
TimerCNTCTLBase0xFD0 + (4 * n)CounterID<n>

Accesses to this interface are RO.


30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.