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The TRBPTR_EL1 characteristics are:
Defines the current write pointer for the trace buffer.
External register TRBPTR_EL1 bits [63:0] are architecturally mapped to AArch64 System register TRBPTR_EL1[63:0].
This register is present only when FEAT_TRBE_EXT is implemented. Otherwise, direct accesses to TRBPTR_EL1 are RES0.
TRBPTR_EL1 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PTR | |||||||||||||||||||||||||||||||
PTR |
Trace Buffer current write pointer address.
Defines the virtual address of the next entry to be written to the trace buffer.
The architecture places restrictions on the values that software can write to the pointer.
As a result of the restrictions an implementation might treat some of PTR[M:0] as RES0, where M is defined by TRBIDR_EL1.Align.
The reset behavior of this field is:
The PE might ignore a write to TRBPTR_EL1 if any of the following apply:
Component | Offset | Instance |
---|---|---|
TRBE | 0x008 | TRBPTR_EL1 |
Accesses to this interface are RW.
30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f
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