PMECR_EL1, Performance Monitors Exception Control Register

The PMECR_EL1 characteristics are:

Purpose

Controls the behavior on overflow of the performance monitors.

Configuration

This register is present only when FEAT_PMUv3 is implemented and FEAT_EBEP is implemented. Otherwise, direct accesses to PMECR_EL1 are UNDEFINED.

Attributes

PMECR_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0KPMEPMEE

Bits [63:3]

Reserved, RES0.

KPME, bit [2]

Local (Kernel) PMU Exception Enable. Enables PMU exceptions taken to the current Exception level.

KPMEMeaning
0b0

PMU exceptions taken to the current Exception level are disabled.

0b1

PMU exceptions taken to the current Exception level are not affected by this field.

The reset behavior of this field is:

PMEE, bits [1:0]

Performance Monitors Exception Enable. Controls the generation of PMUIRQ signal and PMU exception at EL0 and EL1.

PMEEMeaning
0b00

PMUIRQ signal is enabled, and PMU exception is disabled.

0b10

PMUIRQ signal is disabled, and PMU exception is disabled.

0b11

PMUIRQ signal is disabled, and PMU exception is enabled.

All other values are reserved.

This field is ignored by the PE when any of the following are true:

The reset behavior of this field is:

Accessing PMECR_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PMECR_EL1

op0op1CRnCRmop2
0b110b0000b10010b11100b101

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then X[t, 64] = PMECR_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = PMECR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = PMECR_EL1;

MSR PMECR_EL1, <Xt>

op0op1CRnCRmop2
0b110b0000b10010b11100b101

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then PMECR_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then PMECR_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then PMECR_EL1 = X[t, 64];


30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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