The PMPIDR0 characteristics are:
Provides information to identify a Performance Monitor component.
For more information, see 'About the Peripheral identification scheme'.
This register is present only when FEAT_PMUv3_EXT is implemented and an implementation implements PMPIDR0. Otherwise, direct accesses to PMPIDR0 are RES0.
If FEAT_DoPD is implemented, this register is in the Core power domain. If FEAT_DoPD is not implemented, this register is in the Debug power domain.
This register is required for CoreSight compliance.
PMPIDR0 is a 32-bit register.
This register is part of the PMU block.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | PART_0 |
Reserved, RES0.
Part number, least significant byte.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Accesses to this register use the following encodings in the external debug interface:
PMPIDR0 can be accessed through the PMU block as follows:
Frame | Offset |
---|---|
PMU | 0xFE0 |
30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f
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