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PMICNTR_EL0, Performance Monitors Instruction Counter Register

The PMICNTR_EL0 characteristics are:

Purpose

If event counting is not prohibited and the instruction counter is enabled, the counter increments for each architecturally-executed instruction, according to the configuration specified by PMICFILTR_EL0.

Configuration

AArch64 System register PMICNTR_EL0 bits [63:0] are architecturally mapped to External register PMU.PMICNTR_EL0[63:0].

This register is present only when FEAT_PMUv3_ICNTR is implemented. Otherwise, direct accesses to PMICNTR_EL0 are UNDEFINED.

Attributes

PMICNTR_EL0 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
ICNT
ICNT

ICNT, bits [63:0]

Instruction Counter.

The reset behavior of this field is:

Accessing PMICNTR_EL0

PMICNTR_EL0 reads-as-zero and ignores writes if all of the following are true:

PMICNTR_EL0 ignores writes if all of the following are true:

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PMICNTR_EL0

op0op1CRnCRmop2
0b110b0110b10010b01000b000

if PSTATE.EL == EL0 then X[t, 64] = PMICNTR_EL0; elsif PSTATE.EL == EL1 then X[t, 64] = PMICNTR_EL0; elsif PSTATE.EL == EL2 then X[t, 64] = PMICNTR_EL0; elsif PSTATE.EL == EL3 then X[t, 64] = PMICNTR_EL0;

MSR PMICNTR_EL0, <Xt>

op0op1CRnCRmop2
0b110b0110b10010b01000b000

if PSTATE.EL == EL0 then if PMUSERENR_EL0.EN == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else PMICNTR_EL0 = X[t, 64]; elsif PSTATE.EL == EL1 then PMICNTR_EL0 = X[t, 64]; elsif PSTATE.EL == EL2 then PMICNTR_EL0 = X[t, 64]; elsif PSTATE.EL == EL3 then PMICNTR_EL0 = X[t, 64];


30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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