The TRCIDR0 characteristics are:
Returns the tracing capabilities of the trace unit.
AArch64 System register TRCIDR0 bits [31:0] are architecturally mapped to External register TRCIDR0[31:0].
This register is present only when FEAT_ETE is implemented and FEAT_TRC_SR is implemented. Otherwise, direct accesses to TRCIDR0 are UNDEFINED.
TRCIDR0 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | COMMTRANS | COMMOPT | TSSIZE | TSMARK | ITE | RES0 | TRCEXDATA | QSUPP | QFILT | CONDTYPE | NUMEVENT | RETSTACK | RES0 | TRCCCI | TRCCOND | TRCBB | TRCDATA | INSTP0 | RES1 |
Reserved, RES0.
Transaction Start element behavior.
COMMTRANS | Meaning |
---|---|
0b0 |
Transaction Start elements are P0 elements. |
0b1 |
Transaction Start elements are not P0 elements. |
Indicates the contents and encodings of Cycle count packets.
COMMOPT | Meaning |
---|---|
0b0 |
Commit mode 0. |
0b1 |
Commit mode 1. |
The Commit mode defines the contents and encodings of Cycle Count packets, in particular how Commit elements are indicated by these packets. See the descriptions of these packets for more details.
Accessing this field has the following behavior:
Indicates that the trace unit implements Global timestamping and the size of the timestamp value.
TSSIZE | Meaning |
---|---|
0b00000 |
Global timestamping not implemented. |
0b01000 |
Global timestamping implemented with a 64-bit timestamp value. |
All other values are reserved.
This field reads as 0b01000.
Indicates whether Timestamp Marker elements are generated.
TSMARK | Meaning |
---|---|
0b0 |
Timestamp Marker elements are not generated. |
0b1 |
Timestamp Marker elements are generated. |
Reserved, RES0.
Indicates whether Instrumentation Trace is implemented.
ITE | Meaning |
---|---|
0b0 |
Instrumentation Trace not implemented. |
0b1 |
Instrumentation Trace implemented. |
This field has the value 1 if FEAT_ITE is implemented.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Reserved, RES0.
Reserved, RES0.
Indicates if the trace unit implements tracing of data transfers for exceptions and exception returns. Data tracing is not implemented in ETE and this field is reserved for other trace architectures. Allocated in other trace architectures.
TRCEXDATA | Meaning |
---|---|
0b0 |
Tracing of data transfers for exceptions and exception returns not implemented. |
0b1 |
Tracing of data transfers for exceptions and exception returns implemented. |
Reserved, RES0.
Indicates that the trace unit implements Q element support.
QSUPP | Meaning |
---|---|
0b00 |
Q element support is not implemented. |
0b01 |
Q element support is implemented, and only supports Q elements with instruction counts. |
0b10 |
Q element support is implemented, and only supports Q elements without instruction counts. |
0b11 | Q element support is implemented, and supports:
|
Indicates if the trace unit implements Q element filtering.
QFILT | Meaning |
---|---|
0b0 |
Q element filtering is not implemented. |
0b1 |
Q element filtering is implemented. |
If TRCIDR0.QSUPP == 0b00 then this field is 0.
Indicates how conditional instructions are traced. Conditional instruction tracing is not implemented in ETE and this field is reserved for other trace architectures. Allocated in other trace architectures.
CONDTYPE | Meaning |
---|---|
0b00 |
Conditional instructions are traced with an indication of whether they pass or fail their condition code check. |
0b01 |
Conditional instructions are traced with an indication of the APSR condition flags. |
All other values are reserved.
Reserved, RES0.
Indicates the number of ETEEvents implemented.
NUMEVENT | Meaning |
---|---|
0b00 |
The trace unit supports 0 ETEEvents. |
All other values are reserved.
Indicates the number of ETEEvents implemented.
NUMEVENT | Meaning |
---|---|
0b00 |
The trace unit supports 1 ETEEvent. |
0b01 |
The trace unit supports 2 ETEEvents. |
0b10 |
The trace unit supports 3 ETEEvents. |
0b11 |
The trace unit supports 4 ETEEvents. |
Reserved, RES0.
Indicates if the trace unit supports the return stack.
RETSTACK | Meaning |
---|---|
0b0 |
Return stack not implemented. |
0b1 |
Return stack implemented. |
Reserved, RES0.
Indicates if the trace unit implements cycle counting.
TRCCCI | Meaning |
---|---|
0b0 |
Cycle counting not implemented. |
0b1 |
Cycle counting implemented. |
This field reads as 1.
Indicates if the trace unit implements conditional instruction tracing. Conditional instruction tracing is not implemented in ETE and this field is reserved for other trace architectures.
TRCCOND | Meaning |
---|---|
0b0 |
Conditional instruction tracing not implemented. |
0b1 |
Conditional instruction tracing implemented. |
This field reads as 0.
Indicates if the trace unit implements branch broadcasting.
TRCBB | Meaning |
---|---|
0b0 |
Branch broadcasting not implemented. |
0b1 |
Branch broadcasting implemented. |
This field reads as 1.
Indicates if the trace unit implements data tracing. Data tracing is not implemented in ETE and this field is reserved for other trace architectures.
TRCDATA | Meaning |
---|---|
0b00 |
Data tracing not implemented. |
0b11 |
Data tracing implemented. |
All other values are reserved.
This field reads as 0b00.
Indicates if load and store instructions are P0 instructions. Load and store instructions as P0 instructions is not implemented in ETE and this field is reserved for other trace architectures.
INSTP0 | Meaning |
---|---|
0b00 |
Load and store instructions are not P0 instructions. |
0b11 |
Load and store instructions are P0 instructions. |
All other values are reserved.
This field reads as 0b00.
Reserved, RES1.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b001 | 0b0000 | 0b1000 | 0b111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TTA == '1' then UNDEFINED; elsif CPACR_EL1.TTA == '1' then AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.TRCID == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = TRCIDR0; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && CPTR_EL3.TTA == '1' then UNDEFINED; elsif CPTR_EL2.TTA == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TTA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = TRCIDR0; elsif PSTATE.EL == EL3 then if CPTR_EL3.TTA == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = TRCIDR0;
30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f
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