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The SPMSCR_EL1 characteristics are:
Controls observability of Secure events by the System Performance Monitor, and optionally controls Secure attributes for message signaled interrupts and Non-secure access to the performance monitor registers.
This register is present only when FEAT_SPMU is implemented. Otherwise, direct accesses to SPMSCR_EL1 are UNDEFINED.
SPMSCR_EL1 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
IMPL | RES0 | NAO | RES0 | SO |
IMPLEMENTATION DEFINED observation controls. Additional IMPLEMENTATION DEFINED bits to control certain types of filter or events.
Indicates SPMSCR_EL1 is present.
The reset behavior of this field is:
Access to this field is RO.
Reserved, RES0.
Non-attributable Observation. Controls whether events or monitorable characteristics not attributable with any source can be monitored.
NAO | Meaning |
---|---|
0b0 | Events not attributable with any event source are not counted, unless overridden by SPMSCR_EL1.SO. |
0b1 | Counting non-attributable events is not prevented by this bit. |
When both SPMROOTCR_EL3 and SPMSCR_EL1 are implemented, non-attributable events are counted only if both SPMROOTCR_EL3.NAO is 1 and SPMSCR_EL1.{NAO, SO} is nonzero.
SPMSCR_EL1.NAO has the opposite reset polarity to SPMROOTCR_EL3.NAO.
This bit is optional if Root and Realm states are not implemented. When this bit is not implemented, the PMU behaves as if SPMSCR_EL1.NAO is 0, and whether events or monitorable characteristics not attributable with any source can be monitored is controlled by SPMSCR_EL1.SO.
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Secure Observation. Controls whether events or monitorable characteristics attributable to a Secure event source can be monitored.
SO | Meaning |
---|---|
0b0 | Events attributable to a Secure event source are not counted. |
0b1 | Events attributable to a Secure event source are counted. |
Also controls whether events or monitorable characteristics not attributable with any source can be monitored. See SPMSCR_EL1.NAO.
The reset behavior of this field is:
To access SPMSCR_EL1 for System PMU <s>, set SPMSELR_EL0.SYSPMUSEL to s.
SPMSCR_EL1 is UNDEFINED if accessed in Non-secure or Realm state.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b111 | 0b1001 | 0b1110 | 0b111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then X[t, 64] = SPMSCR_EL1[UInt(SPMSELR_EL0.SYSPMUSEL)]; elsif PSTATE.EL == EL2 then X[t, 64] = SPMSCR_EL1[UInt(SPMSELR_EL0.SYSPMUSEL)]; elsif PSTATE.EL == EL3 then X[t, 64] = SPMSCR_EL1[UInt(SPMSELR_EL0.SYSPMUSEL)];
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b111 | 0b1001 | 0b1110 | 0b111 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then SPMSCR_EL1[UInt(SPMSELR_EL0.SYSPMUSEL)] = X[t, 64]; elsif PSTATE.EL == EL2 then SPMSCR_EL1[UInt(SPMSELR_EL0.SYSPMUSEL)] = X[t, 64]; elsif PSTATE.EL == EL3 then SPMSCR_EL1[UInt(SPMSELR_EL0.SYSPMUSEL)] = X[t, 64];
30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f
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