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The PMEVTYPER<n>_EL0 characteristics are:
Configures event counter n, where n is 0 to 30.
AArch64 System register PMEVTYPER<n>_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMEVTYPER<n>[31:0].
AArch64 System register PMEVTYPER<n>_EL0 bits [63:0] are architecturally mapped to External register PMU.PMEVTYPER<n>_EL0[63:0]PMEVTYPER<n>_EL0[63:0].
This register is present only when FEAT_PMUv3 is implemented. Otherwise, direct accesses to PMEVTYPER<n>_EL0 are UNDEFINED.
PMEVTYPER<n>_EL0 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TC | TE | RES0 | SYNC | RES0 | TH | ||||||||||||||||||||||||||
P | U | NSK | NSU | NSH | M | MT | SH | T | RLK | RLU | RLH | RES0 | evtCount[15:10] | evtCount[9:0] |
Threshold Control. Defines the threshold function. In the description of this field, the value V is the value the event specified by PMEVTYPER<n>_EL0 would increment the counter by on a processor cycle if the threshold function is disabled. Comparisons treat V and PMEVTYPER<n>_EL0.TH as unsigned integer values.
Defines the threshold function. In the description of this field:
Comparisons treat VB and TH as unsigned integer values.
TC | Meaning |
---|---|
0b000 | Not-equal. The counter increments by V |
0b001 | Not-equal, count. The counter increments by 1 on each processor cycle when V |
0b010 | Equals. The counter increments by V |
0b011 | Equals, count. The counter increments by 1 on each processor cycle when V |
0b100 | Greater-than-or-equal. The counter increments by V |
0b101 | Greater-than-or-equal, count. The counter increments by 1 on each processor cycle when V |
0b110 | Less-than. The counter increments by V |
0b111 | Less-than, count. The counter increments by 1 on each processor cycle when V |
The reset behavior of this field is:
Threshold Control.
Defines the threshold function. In the description of this field:
Comparisons treat VB and TH as unsigned integer values.
TC | Meaning |
---|---|
0b001 | Equal to not-equal. The counter increments by 1 on each processor cycle when VB is not equal to TH and VB was equal to TH on the previous processor cycle. |
0b010 | Equal to/from not-equal. The counter increments by 1 on each processor cycle when either:
|
0b011 | Not-equal to equal. The counter increments by 1 on each processor cycle when VB is equal to TH and VB was not equal to TH on the previous processor cycle. |
0b101 | Less-than to greater-than-or-equal. The counter increments by 1 on each processor cycle when VB is greater than or equal to TH and VB was less than TH on the previous processor cycle. |
0b110 | Less-than to/from greater-than-or-equal. The counter increments by 1 on each processor cycle when either:
|
0b111 | Greater-than-or-equal to less-than. The counter increments by 1 on each processor cycle when VB is less than TH and VB was greater than or equal to TH on the previous processor cycle. |
All other values are reserved.
The reset behavior of this field is:
Reserved, RES0.
Threshold Control.
Defines the threshold function. In the description of this field:
Comparisons treat VB and TH as unsigned integer values.
Threshold Edge. Enables the edge condition. When PMEVTYPER<n>_EL0.TE is 1, the event counter increments on cycles when the result of the threshold condition changes. See PMEVTYPER<n>_EL0.TC for more information.
TE | Meaning |
---|---|
0b0 | Threshold edge condition disabled. |
0b1 | Threshold edge condition enabled. |
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Synchronous Mode. Controls whether a PMU exception generated by the counter is synchronous or asynchronous.
SYNC | Meaning |
---|---|
0b0 | Asynchronous PMU exception is enabled. |
0b1 | Synchronous PMU exception is enabled. |
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Threshold value. Provides the unsigned value for the threshold function defined by PMEVTYPER<n>_EL0.TC.
If PMEVTYPER<n>_EL0.TC is 0b000 and PMEVTYPER<n>_EL0.TH is zero, then the threshold function is disabled.
If PMMIR_EL1.THWIDTH is less than 12, then bits PMEVTYPER<n>_EL0.TH[11:PMMIR_EL1.THWIDTH] are RES0. This accounts for the behavior when writing a value greater-than-or-equal-to 2(PMMIR_EL1.THWIDTH).
The reset behavior of this field is:
Reserved, RES0.
Privileged filtering bit. Controls counting in EL1.
If EL3 is implemented, then counting in Non-secure EL1 is further controlled by the PMEVTYPER<n>_EL0.NSK bit.
If FEAT_RME is implemented, then counting in Realm EL1 is further controlled by the PMEVTYPER<n>_EL0.RLK bit.
P | Meaning |
---|---|
0b0 | Count events in EL1. |
0b1 | Do not count events in EL1. |
The reset behavior of this field is:
User filtering bit. Controls counting in EL0.
If EL3 is implemented, then counting in Non-secure EL0 is further controlled by the PMEVTYPER<n>_EL0.NSU bit.
If FEAT_RME is implemented, then counting in Realm EL0 is further controlled by the PMEVTYPER<n>_EL0.RLU bit.
U | Meaning |
---|---|
0b0 | Count events in EL0. |
0b1 | Do not count events in EL0. |
The reset behavior of this field is:
Non-secure EL1 (kernel) modes filtering bit. Controls counting in Non-secure EL1.
If the value of this bit is equal to the value of the PMEVTYPER<n>_EL0.P bit, events in Non-secure EL1 are counted.
Otherwise, events in Non-secure EL1 are not counted.
The reset behavior of this field is:
Reserved, RES0.
Non-secure EL0 (Unprivileged) filtering bit. Controls counting in Non-secure EL0.
If the value of this bit is equal to the value of the PMEVTYPER<n>_EL0.U bit, events in Non-secure EL0 are counted.
Otherwise, events in Non-secure EL0 are not counted.
The reset behavior of this field is:
Reserved, RES0.
EL2 (Hypervisor) filtering bit. Controls counting in EL2.
If Secure EL2 is implemented, and EL3 is implemented, counting in Secure EL2 is further controlled by the PMEVTYPER<n>_EL0.SH bit.
If FEAT_RME is implemented, then counting in Realm EL2 is further controlled by the PMEVTYPER<n>_EL0.RLH bit.
NSH | Meaning |
---|---|
0b0 | Do not count events in EL2. |
0b1 | Count events in EL2. |
The reset behavior of this field is:
Reserved, RES0.
EL3 filtering bit.
If the value of this bit is equal to the value of the PMEVTYPER<n>_EL0.P bit, events in EL3 are counted.
Otherwise, events in EL3 are not counted.
The reset behavior of this field is:
Reserved, RES0.
Multithreading.
MT | Meaning |
---|---|
0b0 | Count events only on controlling PE. |
0b1 | Count events from any PE with the same affinity at level 1 and above as this PE. |
From Armv8.6, the IMPLEMENTATION DEFINED multi-threaded PMU extension is not permitted, meaning if FEAT_MTPMU is not implemented, this field is RES0. See ID_AA64DFR0_EL1.MTPMU.
This field is ignored by the PE and treated as zero when FEAT_MTPMU is implemented and Disabled.
The reset behavior of this field is:
Reserved, RES0.
Secure EL2 filtering.
If the value of this bit is not equal to the value of the PMEVTYPER<n>_EL0.NSH bit, events in Secure EL2 are counted.
Otherwise, events in Secure EL2 are not counted.
The reset behavior of this field is:
Reserved, RES0.
Transactional state filtering bit. Controls counting of Attributable events in Non-transactionalTransactional state.
T | Meaning |
---|---|
0b0 | This bit has no effect on the filtering of events. |
0b1 | Do not count Attributable events in Non-transactional |
For each Unattributable event, it is IMPLEMENTATION DEFINED whether the filtering applies.
The reset behavior of this field is:
Reserved, RES0.
Realm EL1 (kernel) filtering bit. Controls counting in Realm EL1.
If the value of this bit is equal to the value of the PMEVTYPER<n>_EL0.P bit, events in Realm EL1 are counted.
Otherwise, events in Realm EL1 are not counted.
The reset behavior of this field is:
Reserved, RES0.
Realm EL0 (unprivileged) filtering bit. Controls counting in Realm EL0.
If the value of this bit is equal to the value of the PMEVTYPER<n>_EL0.U bit, events in Realm EL0 are counted.
Otherwise, events in Realm EL0 are not counted.
The reset behavior of this field is:
Reserved, RES0.
Realm EL2 filtering bit. Controls counting in Realm EL2.
If the value of this bit is not equal to the value of the PMEVTYPER<n>_EL0.NSH bit, events in Realm EL2 are counted.
Otherwise, events in Realm EL2 are not counted.
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Extension to evtCount[9:0]. For more information, see evtCount[9:0].
The reset behavior of this field is:
Reserved, RES0.
Event to count.
The event number of the event that is counted by event counter PMEVCNTR<n>_EL0.
The ranges of event numbers allocated to each type of event are shown in 'Allocation of the PMU event number space'.
If FEAT_PMUv3p8 is implemented and PMEVTYPER<n>_EL0.evtCount is programmed to an event that is reserved or not supported by the PE, no events are counted and the value returned by a direct or external read of the PMEVTYPER<n>_EL0.evtCount field is the value written to the field.
Arm recommends this behavior for all implementations of FEAT_PMUv3.
Otherwise, if PMEVTYPER<n>_EL0.evtCount is programmed to an event that is reserved or not supported by the PE, the behavior depends on the value written:
UNPREDICTABLE means the event must not expose privileged information.
The reset behavior of this field is:
PMEVTYPER<n>_EL0 can also be accessed by using PMXEVTYPER_EL0 with PMSELR_EL0.SEL set to n.
If FEAT_FGT is implemented and <n> is greater than or equal to the number of accessible event counters, then the behavior of permitted reads and writes of PMEVTYPER<n>_EL0 is as follows:
If FEAT_FGT is not implemented and <n> is greater than or equal to the number of accessible event counters, then reads and writes of PMEVTYPER<n>_EL0 are CONSTRAINED UNPREDICTABLE, and the following behaviors are permitted:
In EL0, an access is permitted if it is enabled by PMUSERENR_EL0.EN.
If EL2 is implemented and enabled in the current Security state, in EL1 and EL0, MDCR_EL2.HPMN identifies the number of accessible event counters. Otherwise, the number of accessible event counters is the number of implemented event counters. For more information, see MDCR_EL2.HPMN.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b011 | 0b1110 | 0b11:m[4:3] | m[2:0] |
integer m = UInt(CRm<1:0>:op2<2:0>); if m >= NUM_PMU_COUNTERS then if IsFeatureImplemented(FEAT_FGT) then UNDEFINED; else ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); elsif PSTATE.EL == EL0 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then UNDEFINED; elsif PMUSERENR_EL0.EN == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMEVTYPERn_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && m >= AArch64.GetNumEventCountersAccessible() then if !IsFeatureImplemented(FEAT_FGT) then ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); else AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMEVTYPER_EL0[m]; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMEVTYPERn_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && m >= AArch64.GetNumEventCountersAccessible() then if !IsFeatureImplemented(FEAT_FGT) then ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); else AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMEVTYPER_EL0[m]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMEVTYPER_EL0[m]; elsif PSTATE.EL == EL3 then X[t, 64] = PMEVTYPER_EL0[m];
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b011 | 0b1110 | 0b11:m[4:3] | m[2:0] |
integer m = UInt(CRm<1:0>:op2<2:0>); if m >= NUM_PMU_COUNTERS then if IsFeatureImplemented(FEAT_FGT) then UNDEFINED; else ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); elsif PSTATE.EL == EL0 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then UNDEFINED; elsif PMUSERENR_EL0.EN == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.PMEVTYPERn_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && m >= AArch64.GetNumEventCountersAccessible() then if !IsFeatureImplemented(FEAT_FGT) then ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); else AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMEVTYPER_EL0[m] = X[t, 64]; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.PMEVTYPERn_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && m >= AArch64.GetNumEventCountersAccessible() then if !IsFeatureImplemented(FEAT_FGT) then ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); else AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMEVTYPER_EL0[m] = X[t, 64]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMEVTYPER_EL0[m] = X[t, 64]; elsif PSTATE.EL == EL3 then PMEVTYPER_EL0[m] = X[t, 64];
3005/0907/2022 1517:5808; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96fb0421fa9a8865165f9b91af9b4a566111f866305
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