PMIAR_EL1, Performance Monitors Instruction Address Register

The PMIAR_EL1 characteristics are:

Purpose

Captures the address of the instruction generating a PMU exception.

Configuration

This register is present only when FEAT_SEBEP is implemented. Otherwise, direct accesses to PMIAR_EL1 are UNDEFINED.

Attributes

PMIAR_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
ELRES0ADDRESS
ADDRESS

EL, bits [63:62]

Exception Level.

ELMeaning
0b00

EL0.

0b01

EL1.

0b10

EL2.

0b11

EL3.

The reset behavior of this field is:

Bits [61:56]

Reserved, RES0.

ADDRESS, bits [55:0]

Instruction virtual address.

The reset behavior of this field is:

Accessing PMIAR_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PMIAR_EL1

op0op1CRnCRmop2
0b110b0000b10010b11100b111

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then X[t, 64] = PMIAR_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = PMIAR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = PMIAR_EL1;

MSR PMIAR_EL1, <Xt>

op0op1CRnCRmop2
0b110b0000b10010b11100b111

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then PMIAR_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then PMIAR_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then PMIAR_EL1 = X[t, 64];


30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.