PMCGCR0, Counter Group Configuration Register 0

The PMCGCR0 characteristics are:

Purpose

Encodes the number of PMU.PMEVCNTR<n>_EL0 counters implemented.

Configuration

This register is present only when FEAT_PMUv3_ICNTR is implemented. Otherwise, direct accesses to PMCGCR0 are RES0.

PMCGCR0 is in the Core power domain.

Attributes

PMCGCR0 is a 32-bit register.

This register is part of the PMU block.

Field descriptions

313029282726252423222120191817161514131211109876543210
RES0CG1NCCG0NC

Bits [31:16]

Reserved, RES0.

CG1NC, bits [15:8]

Number of counters in group 1, which comprises the instruction counter PMICNTR_EL0.

Reads as 0x01.

Access to this field is RO.

CG0NC, bits [7:0]

Number of counters in group 0, which comprises the event counters PMEVCNTR<n>_EL0 and the cycle counter PMCCNTR_EL0.

This field reads as PMCFGR.N.

Accessing PMCGCR0

Accesses to this register use the following encodings in the external debug interface:

BlockAccess at address 0xCE0

PMCGCR0 can be accessed through the PMU block as follows:

FrameOffset
PMU0xCE0

30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.