PMEVTYPER<n>_EL0, Performance Monitors Event Type Registers, n = 0 - 30

The PMEVTYPER<n>_EL0 characteristics are:

Purpose

Configures event counter <n>, where <n> is 0 to 30.

Configuration

External register PMEVTYPER<n>_EL0 bits [63:0] are architecturally mapped to AArch64 System register PMEVTYPER<n>_EL0[63:0].

External register PMEVTYPER<n>_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMEVTYPER<n>[31:0].

This register is present only when FEAT_PMUv3_EXT is implemented. Otherwise, direct accesses to PMEVTYPER<n>_EL0 are RES0.

PMEVTYPER<n>_EL0 is in the Core power domain.

If event counter n is not implemented:

Attributes

PMEVTYPER<n>_EL0 is a 64-bit register.

This register is part of the PMU block.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
TCTERES0SYNCRES0TH
PUNSKNSUNSHMMTSHTRLKRLURLHRES0evtCount[15:10]evtCount[9:0]

TC, bits [63:61]
When FEAT_PMUv3_EDGE is implemented and PMU.PMEVTYPER<n>_EL0.TE == 1:

Threshold Control.

Defines the threshold function. In the description of this field:

Comparisons treat VB and TH as unsigned integer values.

TCMeaning
0b001

Equal to not-equal. The counter increments by 1 on each processor cycle when VB is not equal to TH and VB was equal to TH on the previous processor cycle.

0b010

Equal to/from not-equal. The counter increments by 1 on each processor cycle when either:

  • VB is not equal to TH and VB was equal to TH on the previous processor cycle.
  • VB is equal to TH and VB was not equal to TH on the previous processor cycle.
0b011

Not-equal to equal. The counter increments by 1 on each processor cycle when VB is equal to TH and VB was not equal to TH on the previous processor cycle.

0b101

Less-than to greater-than-or-equal. The counter increments by 1 on each processor cycle when VB is greater than or equal to TH and VB was less than TH on the previous processor cycle.

0b110

Less-than to/from greater-than-or-equal. The counter increments by 1 on each processor cycle when either:

  • VB is greater than or equal to TH and VB was less than TH on the previous processor cycle.
  • VB is less than TH and VB was greater than or equal to TH on the previous processor cycle.
0b111

Greater-than-or-equal to less-than. The counter increments by 1 on each processor cycle when VB is less than TH and VB was greater than or equal to TH on the previous processor cycle.

All other values are reserved.

The reset behavior of this field is:


When ((FEAT_PMUv3_EDGE is implemented and PMU.PMEVTYPER<n>_EL0.TE == 0) or FEAT_PMUv3_EDGE is not implemented) and FEAT_PMUv3_TH is implemented:

Threshold Control.

Defines the threshold function. In the description of this field:

Comparisons treat VB and TH as unsigned integer values.

TCMeaning
0b000

Not-equal. The counter increments by VB on each processor cycle when VB is not equal to TH. If TH is zero, the threshold function is disabled.

0b001

Not-equal, count. The counter increments by 1 on each processor cycle when VB is not equal to TH.

0b010

Equals. The counter increments by VB on each processor cycle when VB is equal to TH.

0b011

Equals, count. The counter increments by 1 on each processor cycle when VB is equal to TH.

0b100

Greater-than-or-equal. The counter increments by VB on each processor cycle when VB is greater than or equal to TH.

0b101

Greater-than-or-equal, count. The counter increments by 1 on each processor cycle when VB is greater than or equal to TH.

0b110

Less-than. The counter increments by VB on each processor cycle when VB is less than TH.

0b111

Less-than, count. The counter increments by 1 on each processor cycle when VB is less than TH.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Threshold Control.

Defines the threshold function. In the description of this field:

Comparisons treat VB and TH as unsigned integer values.

TE, bit [60]
When FEAT_PMUv3_EDGE is implemented:

Threshold Edge. Enables the edge condition. When PMEVTYPER<n>.TE is 1, the event counter increments on cycles when the result of the threshold condition changes. See PMEVTYPER<n>.TC for more information.

TEMeaning
0b0

Threshold edge condition disabled.

0b1

Threshold edge condition enabled.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Bit [59]

Reserved, RES0.

SYNC, bit [58]
When FEAT_SEBEP is implemented:

Synchronous Mode. Controls whether a PMU exception generated by the counter is synchronous or asynchronous.

SYNCMeaning
0b0

Asynchronous PMU exception is enabled.

0b1

Synchronous PMU exception is enabled.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Bits [57:44]

Reserved, RES0.

TH, bits [43:32]
When FEAT_PMUv3_TH is implemented:

Threshold value. Provides the unsigned value for the threshold function defined by PMEVTYPER<n>_EL0.TC.

If PMEVTYPER<n>_EL0.TC is 0b000 and PMEVTYPER<n>_EL0.TH is zero, then the threshold function is disabled.

If PMMIR_EL1.THWIDTH is less than 12, then bits PMEVTYPER<n>_EL0.TH[11:PMMIR_EL1.THWIDTH] are RES0. This accounts for the behavior when writing a value greater-than-or-equal-to 2(PMMIR_EL1.THWIDTH).

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

P, bit [31]

Privileged filtering bit. Controls counting in EL1.

If EL3 is implemented, then counting in Non-secure EL1 is further controlled by the PMEVTYPER<n>_EL0.NSK bit.

If FEAT_RME is implemented, then counting in Realm EL1 is further controlled by the PMEVTYPER<n>_EL0.RLK bit.

PMeaning
0b0

Count events in EL1.

0b1

Do not count events in EL1.

The reset behavior of this field is:

U, bit [30]

User filtering bit. Controls counting in EL0.

If EL3 is implemented, then counting in Non-secure EL0 is further controlled by the PMEVTYPER<n>_EL0.NSU bit.

If FEAT_RME is implemented, then counting in Realm EL0 is further controlled by the PMEVTYPER<n>_EL0.RLU bit.

UMeaning
0b0

Count events in EL0.

0b1

Do not count events in EL0.

The reset behavior of this field is:

NSK, bit [29]
When EL3 is implemented:

Non-secure EL1 (kernel) modes filtering bit. Controls counting in Non-secure EL1.

If the value of this bit is equal to the value of the PMEVTYPER<n>_EL0.P bit, events in Non-secure EL1 are counted.

Otherwise, events in Non-secure EL1 are not counted.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

NSU, bit [28]
When EL3 is implemented:

Non-secure EL0 (Unprivileged) filtering bit. Controls counting in Non-secure EL0.

If the value of this bit is equal to the value of the PMEVTYPER<n>_EL0.U bit, events in Non-secure EL0 are counted.

Otherwise, events in Non-secure EL0 are not counted.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

NSH, bit [27]
When EL2 is implemented:

EL2 (Hypervisor) filtering bit. Controls counting in EL2.

If FEAT_SEL2 and EL3 are implemented, counting in Secure EL2 is further controlled by the PMEVTYPER<n>_EL0.SH bit.

If FEAT_RME is implemented, then counting in Realm EL2 is further controlled by the PMEVTYPER<n>_EL0.RLH bit.

NSHMeaning
0b0

Do not count events in EL2.

0b1

Count events in EL2.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

M, bit [26]
When EL3 is implemented:

EL3 filtering bit.

If the value of this bit is equal to the value of the PMEVTYPER<n>_EL0.P bit, events in EL3 are counted.

Otherwise, events in EL3 are not counted.

Most applications can ignore this field and set its value to 0b0.

Note

This field is not visible in the AArch32 PMEVTYPER<n> System register.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

MT, bit [25]
When (FEAT_MTPMU is implemented and enabled) or an IMPLEMENTATION DEFINED multi-threaded PMU Extension is implemented:

Multithreading.

MTMeaning
0b0

Count events only on controlling PE.

0b1

Count events from any PE with the same affinity at level 1 and above as this PE.

Note

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

SH, bit [24]
When FEAT_SEL2 is implemented and EL3 is implemented:

Secure EL2 filtering.

If the value of this bit is not equal to the value of the PMEVTYPER<n>_EL0.NSH bit, events in Secure EL2 are counted.

Otherwise, events in Secure EL2 are not counted.

Note

This field is not visible in the AArch32 PMEVTYPER<n> System register.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

T, bit [23]
When FEAT_TME is implemented:

Transactional state filtering bit. Controls counting of Attributable events in Non-transactional state.

TMeaning
0b0

This bit has no effect on the filtering of events.

0b1

Do not count Attributable events in Non-transactional state.

For each Unattributable event, it is IMPLEMENTATION DEFINED whether the filtering applies.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

RLK, bit [22]
When FEAT_RME is implemented:

Realm EL1 (kernel) filtering bit. Controls counting in Realm EL1.

If the value of this bit is equal to the value of the PMEVTYPER<n>_EL0.P bit, events in Realm EL1 are counted.

Otherwise, events in Realm EL1 are not counted.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

RLU, bit [21]
When FEAT_RME is implemented:

Realm EL0 (unprivileged) filtering bit. Controls counting in Realm EL0.

If the value of this bit is equal to the value of the PMEVTYPER<n>_EL0.U bit, events in Realm EL0 are counted.

Otherwise, events in Realm EL0 are not counted.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

RLH, bit [20]
When FEAT_RME is implemented:

Realm EL2 filtering bit. Controls counting in Realm EL2.

If the value of this bit is not equal to the value of the PMEVTYPER<n>_EL0.NSH bit, events in Realm EL2 are counted.

Otherwise, events in Realm EL2 are not counted.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Bits [19:16]

Reserved, RES0.

evtCount[15:10], bits [15:10]
When FEAT_PMUv3p1 is implemented:

Extension to evtCount[9:0]. For more information, see evtCount[9:0].

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

evtCount[9:0], bits [9:0]

Event to count. The event number of the event that is counted by event counter PMU.PMEVCNTR<n>_EL0.

Software must program this field with an event that is supported by the PE being programmed.

The ranges of event numbers allocated to each type of event are shown in 'Allocation of the PMU event number space'.

If FEAT_PMUv3p8 is implemented and PMEVTYPER<n>_EL0.evtCount is programmed to an event that is reserved or not supported by the PE, no events are counted and the value returned by a direct or external read of the PMEVTYPER<n>_EL0.evtCount field is the value written to the field.

Note

Arm recommends this behavior for all implementations of FEAT_PMUv3.

Otherwise, if PMEVTYPER<n>_EL0.evtCount is programmed to an event that is reserved or not supported by the PE, the behavior depends on the value written:

Note

UNPREDICTABLE means the event must not expose privileged information.

The reset behavior of this field is:

Accessing PMEVTYPER<n>_EL0

If FEAT_PMUv3_TH is implemented, and at least one of FEAT_PMUv3_TH or FEAT_PMUv3p8 is implemented, bits [63:32] of this interface are accessible at offset 0xA00 + (4*n). Otherwise accesses at this offset are IMPLEMENTATION DEFINED.

Note

SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.

Accesses to this register use the following encodings in the external debug interface:

When FEAT_PMUv3_EXT32 is implemented
BlockAccess at address 0x400 + (4 * n)

PMEVTYPER<n>_EL0 can be accessed through the PMU block as follows:

FrameOffsetRange
PMU0x400 + (4 * n)31:0

When FEAT_PMUv3_EXT64 is implemented
BlockAccess at address 0x400 + (8 * n)

PMEVTYPER<n>_EL0 can be accessed through the PMU block as follows:

FrameOffsetRange
PMU0x400 + (8 * n)63:0

When FEAT_PMUv3_EXT32 is implemented
BlockAccess at address 0xA00 + (4 * n)

PMEVTYPER<n>_EL0 can be accessed through the PMU block as follows:

FrameOffsetRange
PMU0xA00 + (4 * n)63:32

30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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