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SPMCGCR<n>_EL1, Counter Group Configuration Register <n>, n = 0 - 1

The SPMCGCR<n>_EL1 characteristics are:

Purpose

Describes the performance monitor.

Configuration

This register is present only when FEAT_SPMU is implemented. Otherwise, direct accesses to SPMCGCR<n>_EL1 are UNDEFINED.

Attributes

SPMCGCR<n>_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
N7N6N5N4
N3N2N1N0

N<m>, bits [8m+7:8m], for m = 7 to 0

Number of counters in group n×8+m.

The maximum size of each counter group depends on the number of implemented groups and the largest implemented counter size. For more information, see SPMCFGR_EL1.NCG.

The reset behavior of this field is:

Accessing SPMCGCR<n>_EL1

To access SPMCGCR<n>_EL1 for System PMU <s>, set SPMSELR_EL0.SYSPMUSEL to s.

SPMCGCR<n>_EL1 reads-as-zero if any of the following are true:

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, SPMCGCR<n>_EL1 ; Where n = 0-1

op0op1CRnCRmop2
0b100b0000b10010b11010b00:n[0]

integer n = UInt(op2<0>); if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then X[t, 64] = SPMCGCR_EL1[UInt(SPMSELR_EL0.SYSPMUSEL)]; elsif PSTATE.EL == EL2 then X[t, 64] = SPMCGCR_EL1[UInt(SPMSELR_EL0.SYSPMUSEL)]; elsif PSTATE.EL == EL3 then X[t, 64] = SPMCGCR_EL1[UInt(SPMSELR_EL0.SYSPMUSEL)];


30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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