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SPMOVSSET_EL0, System Performance Monitors Overflow Flag Status Set Register

The SPMOVSSET_EL0 characteristics are:

Purpose

Sets the state of the overflow bit for the implemented event counters.

Configuration

This register is present only when FEAT_SPMU is implemented. Otherwise, direct accesses to SPMOVSSET_EL0 are UNDEFINED.

Attributes

SPMOVSSET_EL0 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
P63P62P61P60P59P58P57P56P55P54P53P52P51P50P49P48P47P46P45P44P43P42P41P40P39P38P37P36P35P34P33P32
P31P30P29P28P27P26P25P24P23P22P21P20P19P18P17P16P15P14P13P12P11P10P9P8P7P6P5P4P3P2P1P0

P<m>, bit [m], for m = 63 to 0

Event counter <m> unsigned overflow bit set.

P<m>Meaning
0b0

Event counter <m> has not overflowed.

0b1

Event counter <m> has overflowed.

The reset behavior of this field is:

Accessing this field has the following behavior:

Accessing SPMOVSSET_EL0

To access SPMOVSSET_EL0 for System PMU <s>, set SPMSELR_EL0.SYSPMUSEL to s.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, SPMOVSSET_EL0

op0op1CRnCRmop2
0b100b0110b10010b11100b011

if PSTATE.EL == EL0 then X[t, 64] = SPMOVSSET_EL0[UInt(SPMSELR_EL0.SYSPMUSEL)]; elsif PSTATE.EL == EL1 then X[t, 64] = SPMOVSSET_EL0[UInt(SPMSELR_EL0.SYSPMUSEL)]; elsif PSTATE.EL == EL2 then X[t, 64] = SPMOVSSET_EL0[UInt(SPMSELR_EL0.SYSPMUSEL)]; elsif PSTATE.EL == EL3 then X[t, 64] = SPMOVSSET_EL0[UInt(SPMSELR_EL0.SYSPMUSEL)];

MSR SPMOVSSET_EL0, <Xt>

op0op1CRnCRmop2
0b100b0110b10010b11100b011

if PSTATE.EL == EL0 then SPMOVSSET_EL0[UInt(SPMSELR_EL0.SYSPMUSEL)] = X[t, 64]; elsif PSTATE.EL == EL1 then SPMOVSSET_EL0[UInt(SPMSELR_EL0.SYSPMUSEL)] = X[t, 64]; elsif PSTATE.EL == EL2 then SPMOVSSET_EL0[UInt(SPMSELR_EL0.SYSPMUSEL)] = X[t, 64]; elsif PSTATE.EL == EL3 then SPMOVSSET_EL0[UInt(SPMSELR_EL0.SYSPMUSEL)] = X[t, 64];


30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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