TCR2_EL1, Extended Translation Control Register (EL1)

The TCR2_EL1 characteristics are:

Purpose

The control register for stage 1 of the EL1&0 translation regime.

Configuration

This register is present only when FEAT_TCR2 is implemented. Otherwise, direct accesses to TCR2_EL1 are UNDEFINED.

Attributes

TCR2_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0DisCH1DisCH0RES0HAFTPTTWIRES0D128AIEPOEE0POEPIEPnCH

Unless stated otherwise, all the bits in TCR2_EL1, when they have the value 1, are permitted to be cached in a TLB.

Bits [63:16]

Reserved, RES0.

DisCH1, bit [15]
When FEAT_D128 is implemented and TCR2_EL1.D128 == 1:

Disable Contiguous Hint for Start Table for VARange 1.

DisCH1Meaning
0b0

Contiguous Hint of Block or Page descriptors of the Start Table for VARange 1 are not affected by this field.

0b1

Contiguous Hint of Block or Page descriptors of the Start Table for VARange 1 are disabled.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

DisCH0, bit [14]
When FEAT_D128 is implemented and TCR2_EL1.D128 == 1:

Disable Contiguous Hint for Start Table for VARange 0.

DisCH0Meaning
0b0

Contiguous Hint of Block or Page descriptors of the Start Table for VARange 0 are not affected by this field.

0b1

Contiguous Hint of Block or Page descriptors of the Start Table for VARange 0 are disabled.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Bits [13:12]

Reserved, RES0.

HAFT, bit [11]
When FEAT_HAFT is implemented:

Hardware managed Access Flag for Tables.

Enables the Hardware managed Access Flag for Tables.

HAFTMeaning
0b0

Hardware managed Access Flag for Tables is disabled.

0b1

Hardware managed Access Flag for Tables is enabled.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

PTTWI, bit [10]
When FEAT_THE is implemented:

Permit Translation table walk Incoherence.

Permits RCWS instructions to have Reduced Coherence property.

PTTWIMeaning
0b0

Write accesses generated by RCWS at EL1&0 do not have the Reduced Coherence property.

0b1

Write accesses generated by RCWS at EL1&0 have the Reduced Coherence property if HCRX_EL2.PTTWI is 1.

This bit is permitted to be built as a read-only bit with a fixed value of 0.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Bits [9:6]

Reserved, RES0.

D128, bit [5]
When FEAT_D128 is implemented:

Enable 128-bit Page Table Descriptors.

Enables VMSAv9-128 translation system for the Stage 1 EL1&0 Translation Process.

D128Meaning
0b0

Translation system follows VMSA-64 translation process.

0b1

Translation system follows VMSAv9-128 translation process.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

AIE, bit [4]
When FEAT_AIE is implemented:

Enable Attribute Indexing Extension. Control for Attribute Indexing Extension for Stage 1 EL1&0 Translation Process.

AIEMeaning
0b0

Attribute Indexing Extension Disabled.

0b1

Attribute Indexing Extension Enabled.

This field is RES1 when TCR2_EL1.D128 is set.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

POE, bit [3]
When FEAT_S1POE is implemented:

POE. Controls setting of permission overlay for EL1 accesses in stage 1 of the EL1&0 translation regime.

POEMeaning
0b0

Permission overlay disabled for EL1 access in stage 1 of EL1&0 translation regime.

0b1

Permission overlay enabled for EL1 access in stage 1 of EL1&0 translation regime.

This bit is not permitted to be cached in a TLB.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

E0POE, bit [2]
When FEAT_S1POE is implemented:

EL0 POE. controls setting of permission overlay in stage 1 of the EL1 translation regime.

E0POEMeaning
0b0

Permission overlay disabled for EL0 access in stage 1 of EL1&0 translation regime.

0b1

Permission overlay enabled for EL0 access in stage 1 of EL1&0 translation regime.

This bit is not permitted to be cached in a TLB.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

PIE, bit [1]
When FEAT_S1PIE is implemented:

Select Permission Model. Controls setting of indirect permission model in Stage 1 EL1 Translation Process.

PIEMeaning
0b0

Direct permission model.

0b1

Indirect permission model.

This field is RES1 when TCR2_EL1.D128 is set.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

PnCH, bit [0]
When FEAT_THE is implemented:

Protected attribute enable.Indicates use of bit[52] of the stage 1 translation table entry.

PnCHMeaning
0b0

Bit[52] of each stage 1 translation table entry does not indicate protected attribute.

0b1

Bit[52] of each stage 1 translation table entry indicates protected attribute.

This field is RES0 when TCR2_EL1.D128 is set.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Accessing TCR2_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, TCR2_EL1

op0op1CRnCRmop2
0b110b0000b00100b00000b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.TCR2En == '0' then UNDEFINED; elsif EL2Enabled() && HCR_EL2.TRVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.TCR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.TCR2En == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.TCR2En == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then X[t, 64] = NVMem[0x270]; else X[t, 64] = TCR2_EL1; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.TCR2En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.TCR2En == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '1' then X[t, 64] = TCR2_EL2; else X[t, 64] = TCR2_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = TCR2_EL1;

MSR TCR2_EL1, <Xt>

op0op1CRnCRmop2
0b110b0000b00100b00000b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.TCR2En == '0' then UNDEFINED; elsif EL2Enabled() && HCR_EL2.TVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGWTR_EL2.TCR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.TCR2En == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.TCR2En == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then NVMem[0x270] = X[t, 64]; else TCR2_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.TCR2En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.TCR2En == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '1' then TCR2_EL2 = X[t, 64]; else TCR2_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then TCR2_EL1 = X[t, 64];

MRS <Xt>, TCR2_EL12

op0op1CRnCRmop2
0b110b1010b00100b00000b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then X[t, 64] = NVMem[0x270]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.TCR2En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.TCR2En == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = MAIR_EL1; else UNDEFINED; elsif PSTATE.EL == EL3 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' then X[t, 64] = MAIR_EL1; else UNDEFINED;

MSR TCR2_EL12, <Xt>

op0op1CRnCRmop2
0b110b1010b00100b00000b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then NVMem[0x270] = X[t, 64]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.TCR2En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.TCR2En == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else MAIR_EL1 = X[t, 64]; else UNDEFINED; elsif PSTATE.EL == EL3 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' then MAIR_EL1 = X[t, 64]; else UNDEFINED;


30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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