The TRCIDR3 characteristics are:
Returns the base architecture of the trace unit.
External register TRCIDR3 bits [31:0] are architecturally mapped to AArch64 System register TRCIDR3[31:0].
This register is present only when FEAT_ETE is implemented. Otherwise, direct accesses to TRCIDR3 are RES0.
TRCIDR3 is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NOOVERFLOW | NUMPROC[2:0] | SYSSTALL | STALLCTL | SYNCPR | TRCERR | RES0 | EXLEVEL_NS_EL2 | EXLEVEL_NS_EL1 | EXLEVEL_NS_EL0 | EXLEVEL_S_EL3 | EXLEVEL_S_EL2 | EXLEVEL_S_EL1 | EXLEVEL_S_EL0 | RES0 | NUMPROC[4:3] | CCITMIN |
Indicates if overflow prevention is implemented.
NOOVERFLOW | Meaning |
---|---|
0b0 |
Overflow prevention is not implemented. |
0b1 |
Overflow prevention is implemented. |
If TRCIDR3.STALLCTL == 0 then this field is 0.
Indicates the number of PEs available for tracing.
NUMPROC | Meaning |
---|---|
0b00000 |
The trace unit can trace one PE. |
This field reads as 0b00000.
The NUMPROC field is split as follows:
Indicates if stalling of the PE is permitted.
SYSSTALL | Meaning |
---|---|
0b0 |
Stalling of the PE is not permitted. |
0b1 |
Stalling of the PE is permitted. |
The value of this field might be dynamic and change based on system conditions.
If TRCIDR3.STALLCTL == 0 then this field is 0.
Indicates if trace unit implements stalling of the PE.
STALLCTL | Meaning |
---|---|
0b0 |
Stalling of the PE is not implemented. |
0b1 |
Stalling of the PE is implemented. |
Indicates if an implementation has a fixed synchronization period.
SYNCPR | Meaning |
---|---|
0b0 |
TRCSYNCPR is read/write so software can change the synchronization period. |
0b1 |
TRCSYNCPR is read-only so the synchronization period is fixed. |
This field reads as 0.
Indicates forced tracing of System Error exceptions is implemented.
TRCERR | Meaning |
---|---|
0b0 |
Forced tracing of System Error exceptions is not implemented. |
0b1 |
Forced tracing of System Error exceptions is implemented. |
This field reads as 1.
Reserved, RES0.
Indicates if Non-secure EL2 is implemented.
EXLEVEL_NS_EL2 | Meaning |
---|---|
0b0 |
Non-secure EL2 is not implemented. |
0b1 |
Non-secure EL2 is implemented. |
Indicates if Non-secure EL1 is implemented.
EXLEVEL_NS_EL1 | Meaning |
---|---|
0b0 |
Non-secure EL1 is not implemented. |
0b1 |
Non-secure EL1 is implemented. |
Indicates if Non-secure EL0 is implemented.
EXLEVEL_NS_EL0 | Meaning |
---|---|
0b0 |
Non-secure EL0 is not implemented. |
0b1 |
Non-secure EL0 is implemented. |
Indicates if EL3 is implemented.
EXLEVEL_S_EL3 | Meaning |
---|---|
0b0 |
EL3 is not implemented. |
0b1 |
EL3 is implemented. |
Indicates if Secure EL2 is implemented.
EXLEVEL_S_EL2 | Meaning |
---|---|
0b0 |
Secure EL2 is not implemented. |
0b1 |
Secure EL2 is implemented. |
Indicates if Secure EL1 is implemented.
EXLEVEL_S_EL1 | Meaning |
---|---|
0b0 |
Secure EL1 is not implemented. |
0b1 |
Secure EL1 is implemented. |
Indicates if Secure EL0 is implemented.
EXLEVEL_S_EL0 | Meaning |
---|---|
0b0 |
Secure EL0 is not implemented. |
0b1 |
Secure EL0 is implemented. |
Reserved, RES0.
Indicates the minimum value that can be programmed in TRCCCCTLR.THRESHOLD.
If TRCIDR0.TRCCCI == 1 then the minimum value of this field is 0x001.
If TRCIDR0.TRCCCI == 0 then this field is zero.
Component | Offset | Instance |
---|---|---|
ETE | 0x1EC | TRCIDR3 |
This interface is accessible as follows:
05/07/2022 17:08; b0421fa9a8865165f9b91af9b4a566111f866305
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