The AMCNTENCLR1 characteristics are:
Disable control bits for the auxiliary activity monitors event counters, AMEVCNTR1<n>.
External register AMCNTENCLR1 bits [31:0] are architecturally mapped to AArch64 System register AMCNTENCLR1_EL0[31:0].
External register AMCNTENCLR1 bits [31:0] are architecturally mapped to AArch32 System register AMCNTENCLR1[31:0].
The power domain of AMCNTENCLR1 is IMPLEMENTATION DEFINED.
This register is present only when FEAT_AMUv1 is implemented. Otherwise, direct accesses to AMCNTENCLR1 are RES0.
AMCNTENCLR1 is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | P15 | P14 | P13 | P12 | P11 | P10 | P9 | P8 | P7 | P6 | P5 | P4 | P3 | P2 | P1 | P0 |
Reserved, RES0.
Activity monitor event counter disable bit for AMEVCNTR1<n>.
When N is less than 16, bits [15:N] are RAZ, where N is the value in AMCGCR.CG1NC.
Possible values of each bit are:
P<n> | Meaning |
---|---|
0b0 |
When read, means that AMEVCNTR1<n> is disabled. |
0b1 |
When read, means that AMEVCNTR1<n> is enabled. |
The reset behavior of this field is:
If the number of auxiliary activity monitor event counters implemented is zero, reads of AMCNTENCLR1 are RAZ. Software must treat reserved accesses as RES0. See 'Access requirements for reserved and unallocated registers'.
The number of auxiliary activity monitor event counters implemented is zero exactly when AMCFGR.NCG == 0b0000.
Component | Offset | Instance |
---|---|---|
AMU | 0xC24 | AMCNTENCLR1 |
Accesses to this interface are RO.
30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.