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ID_AA64PFR2_EL1, AArch64 Processor Feature Register 2

The ID_AA64PFR2_EL1 characteristics are:

Purpose

Reserved for future expansion of information about implemented PE features in AArch64 state.

For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'.

Configuration

There are no configuration notes.

Attributes

ID_AA64PFR2_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0MTEFARMTESTOREONLYMTEPERM

Bits [63:12]

Reserved, RES0.

MTEFAR, bits [11:8]

Information reported in FAR_ELx on a synchronous exception due to a Tag Check Fault. Defined values are:

MTEFARMeaning
0b0000

On a synchronous exception due to a Tag Check Fault, FAR_ELx[63:60] is UNKNOWN.

Support for Memory Tagging when Address tagging is enabled.

0b0001

On a synchronous exception due to a Tag Check Fault, FAR_ELx[63:60] is not UNKNOWN.

This feature is identified as FEAT_MTE_TAGGED_FAR.

All other values are reserved.

This field is valid when ID_AA64PFR1_EL1.MTE >= 0b0010 and ID_AA64PFR1_EL1.MTEX >= 0b0001.

FEAT_MTE4 implements the functionality identified by the value 0b0001.

From Armv8.9, the only permitted value is 0b0001.

MTESTOREONLY, bits [7:4]

Store-only Tag checking, identified as FEAT_MTE_STORE_ONLY. Defined values are:

MTESTOREONLYMeaning
0b0000

FEAT_MTE_STORE_ONLY is not supported.

0b0001

FEAT_MTE_STORE_ONLY is supported.

All other values are reserved.

This field is valid when ID_AA64PFR1_EL1.MTE >= 0b0010 and ID_AA64PFR1_EL1.MTEX >= 0b0001.

FEAT_MTE4 implements the functionality identified by the value 0b0001.

From Armv8.9, the only permitted value is 0b0001.

MTEPERM, bits [3:0]

Tag access permissions. Defined values are:

MTEPERMMeaning
0b0000

FEAT_MTE_PERM is not supported.

0b0001

FEAT_MTE_PERM is supported.

All other values are reserved.

This field is valid when ID_AA64PFR1_EL1.MTE >= 0b0010.

Accessing ID_AA64PFR2_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, ID_AA64PFR2_EL1

op0op1CRnCRmop2
0b110b0000b00000b01000b010

if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && (IsFeatureImplemented(FEAT_FGT) || !IsZero(ID_AA64PFR2_EL1) || boolean IMPLEMENTATION_DEFINED "ID_AA64PFR2_EL1 trapped by HCR_EL2.TID3") && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = ID_AA64PFR2_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = ID_AA64PFR2_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = ID_AA64PFR2_EL1;


30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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