The PMCID1SR characteristics are:
Contains the sampled value of CONTEXTIDR_EL1, captured on reading PMPCSR[31:0].
PMCID1SR is in the Core power domain.
This register is present only when FEAT_PCSRv8p2 is implemented. Otherwise, direct accesses to PMCID1SR are RES0.
Before Armv8.2, the PC Sample-based Profiling Extension can be implemented in the external debug register space, as indicated by the value of EDDEVID.PCSample.
PMCID1SR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CONTEXTIDR_EL1 |
Context ID. The value of CONTEXTIDR that is associated with the most recent PMPCSR sample. When the most recent PMPCSR sample is generated:
Because the value written to PMCID1SR is an indirect read of CONTEXTIDR, it is CONSTRAINED UNPREDICTABLE whether PMCID1SR is set to the original or new value if PMPCSR samples:
The reset behavior of this field is:
IMPLEMENTATION DEFINED extensions to external debug might make the value of this register UNKNOWN, see 'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN'.
Component | Offset | Instance |
---|---|---|
PMU | 0x208 | PMCID1SR |
This interface is accessible as follows:
Component | Offset | Instance |
---|---|---|
PMU | 0x228 | PMCID1SR |
This interface is accessible as follows:
05/07/2022 17:08; b0421fa9a8865165f9b91af9b4a566111f866305
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