The SPMCR_EL0 characteristics are:
Main control register for the System Performance Monitors.
This register is present only when FEAT_SPMU is implemented. Otherwise, direct accesses to SPMCR_EL0 are UNDEFINED.
SPMCR_EL0 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | TRO | HDBG | FZO | NA | RES0 | EX | RES0 | P | E |
Reserved, RES0.
Trace enable. For more information on this field, see 'CoreSight PMU Architecture'.
The reset behavior of this field is:
Accessing this field has the following behavior:
Reserved, RES0.
Halt-on-debug. For more information on this field, see 'CoreSight PMU Architecture'.
The reset behavior of this field is:
Accessing this field has the following behavior:
Reserved, RES0.
Freeze-on-overflow. For more information on this field, see 'CoreSight PMU Architecture'.
Note that, if implemented by a System PMU, then freeze-on-overflow affects only the counters of that System PMU, not other System PMUs nor the PE PMU.
The reset behavior of this field is:
Reserved, RES0.
Not accessible. For more information on this field, see 'CoreSight PMU Architecture'.
The reset behavior of this field is:
Access to this field is RO.
Reserved, RES0.
Reserved, RES0.
Export enable. For more information on this field, see 'CoreSight PMU Architecture'.
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Event counter reset.
P | Meaning |
---|---|
0b0 |
Write is ignored. |
0b1 |
Reset all event counters to zero. If the cycle counter is implemented, the cycle counter is not reset. |
Resetting the event counters does not affect any overflow flags.
Access to this field is WO/RAZ.
Count enable. This bit controls the System Performance Monitor.
E | Meaning |
---|---|
0b0 |
Monitor is disabled. |
0b1 |
Monitor is enabled. |
Performance monitor overflow IRQs are only signaled when this bit is set to 1.
The reset behavior of this field is:
To access SPMCR_EL0 for System PMU <s>, set SPMSELR_EL0.SYSPMUSEL to s.
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b011 | 0b1001 | 0b1100 | 0b000 |
if PSTATE.EL == EL0 then X[t, 64] = SPMCR_EL0[UInt(SPMSELR_EL0.SYSPMUSEL)]; elsif PSTATE.EL == EL1 then X[t, 64] = SPMCR_EL0[UInt(SPMSELR_EL0.SYSPMUSEL)]; elsif PSTATE.EL == EL2 then X[t, 64] = SPMCR_EL0[UInt(SPMSELR_EL0.SYSPMUSEL)]; elsif PSTATE.EL == EL3 then X[t, 64] = SPMCR_EL0[UInt(SPMSELR_EL0.SYSPMUSEL)];
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b011 | 0b1001 | 0b1100 | 0b000 |
if PSTATE.EL == EL0 then SPMCR_EL0[UInt(SPMSELR_EL0.SYSPMUSEL)] = X[t, 64]; elsif PSTATE.EL == EL1 then SPMCR_EL0[UInt(SPMSELR_EL0.SYSPMUSEL)] = X[t, 64]; elsif PSTATE.EL == EL2 then SPMCR_EL0[UInt(SPMSELR_EL0.SYSPMUSEL)] = X[t, 64]; elsif PSTATE.EL == EL3 then SPMCR_EL0[UInt(SPMSELR_EL0.SYSPMUSEL)] = X[t, 64];
30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f
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