The PMUSERENR_EL0 characteristics are:
Enables or disables EL0 access to the Performance Monitors.
AArch64 System register PMUSERENR_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMUSERENR[31:0].
PMUSERENR_EL0 is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | |||||||||||||||||||||||||||||||
RES0 | TID | IR | UEN | ER | CR | SW | EN |
Reserved, RES0.
Trap ID registers. Traps EL0 read access to common event identification registers.
TID | Meaning |
---|---|
0b0 |
Accesses to PMCEID<n>_EL0 and PMCEID<n> are not trapped by this mechanism. |
0b1 |
EL0 read accesses to PMCEID<n>_EL0 and PMCEID<n> are trapped. |
In AArch64 state, the register accesses affected by this control are:
In AArch32 state, the register accesses affected by this control are:
When trapped, reads generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, and:
The reset behavior of this field is:
Reserved, RES0.
Instruction counter Read enable.
When PMUSERENR_EL0.UEN is 0, PMUSERENR_EL0.IR enables EL0 reads of the instruction counter.
When PMUSERENR_EL0.UEN is 1, EL0 reads of the instruction counter and EL0 writes to PMZR_EL0 are enabled by PMUSERENR_EL0.UEN, unless trapped by another control, and PMUSERENR_EL0.IR controls the behavior of EL0 writes to the instruction counter and PMZR_EL0.
IR | Meaning |
---|---|
0b0 | When PMUSERENR_EL0.UEN == 0: EL0 reads of the instruction counter are disabled. When PMUSERENR_EL0.UEN == 1: Permitted EL0 writes are not affected by this mechanism. |
0b1 | When PMUSERENR_EL0.UEN == 0: EL0 reads of the instruction counter are enabled, unless trapped by another control. When PMUSERENR_EL0.UEN == 1: Permitted EL0 writes to the instruction counter and PMZR_EL0.F0 are ignored. |
In AArch64 state, the register accesses affected by this control are:
When disabled, reads generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, reported using EC syndrome value 0x18.
Ignored writes are not trapped and do not generate an exception.
The reset behavior of this field is:
Reserved, RES0.
User Enable, with access controlled by PMUACR_EL1. Enables EL0 read/write access to PMU registers, other than PMCR_EL0. Software can restrict permitted accesses using PMUSERENR_EL0.{IR,ER,CR} and PMUACR_EL1.
UEN | Meaning |
---|---|
0b0 |
EL0 accesses to PMU registers are trapped, unless enabled by PMUSERENR_EL0.{IR,ER,CR,EN}. |
0b1 |
EL0 accesses to PMU registers are enabled, unless trapped by another control. A permitted access might be restricted by PMUSERENR_EL0.{IR,ER,CR} and PMUACR_EL1. |
In AArch64 state, the register accesses affected by this control are:
In AArch32 state, the register accesses affected by this control are:
When trapped, reads and writes generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, and:
The reset behavior of this field is:
Reserved, RES0.
Event counters Read enable.
When PMUSERENR_EL0.{UEN,EN} is {0,0}, PMUSERENR_EL0.ER enables EL0 reads of the event counters and EL0 reads and writes of the select register.
When PMUSERENR_EL0.{UEN,EN} is {1,0}, EL0 reads of the event counters and EL0 writes to PMZR_EL0 are enabled by PMUSERENR_EL0.UEN, unless trapped by another control, and PMUSERENR_EL0.ER controls the behavior of EL0 writes to the event counters and PMZR_EL0.
ER | Meaning |
---|---|
0b0 | When PMUSERENR_EL0.UEN == 0: EL0 reads of the event counters and EL0 reads and writes of the select register are disabled, unless enabled by PMUSERENR_EL0.EN. When PMUSERENR_EL0.UEN == 1: Permitted EL0 writes are not affected by this mechanism. |
0b1 | When PMUSERENR_EL0.UEN == 0: EL0 reads of the event counters and EL0 reads and writes of the select register are enabled, unless trapped by another control. When PMUSERENR_EL0.UEN == 1: Permitted EL0 writes to the event counters and PMZR_EL0.P[30:0] are ignored, unless enabled by PMUSERENR_EL0.EN. |
In AArch64 state, the register accesses affected by this control are:
In AArch32 state, the register accesses affected by this control are:
When disabled, reads and writes generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, and:
Ignored writes are not trapped and do not generate an exception.
This field is ignored by the PE when PMUSERENR_EL0.EN == 1.
The reset behavior of this field is:
Event counters Read enable.
When PMUSERENR_EL0.EN is 0, PMUSERENR_EL0.ER enables EL0 reads of the event counters and EL0 reads and writes of the select register.
ER | Meaning |
---|---|
0b0 |
EL0 reads of the event counters and EL0 reads and writes of the select register are disabled, unless enabled by PMUSERENR_EL0.EN. |
0b1 |
EL0 reads of the event counters and EL0 reads and writes of the select register are enabled, unless trapped by another control. |
In AArch64 state, the register accesses affected by this control are:
In AArch32 state, the register accesses affected by this control are:
When disabled, reads and writes generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, and:
This field is ignored by the PE when PMUSERENR_EL0.EN == 1.
The reset behavior of this field is:
Cycle counter Read enable.
When PMUSERENR_EL0.{UEN,EN} is {0,0}, PMUSERENR_EL0.CR enables EL0 reads of the cycle counter.
When PMUSERENR_EL0.{UEN,EN} is {1,0}, EL0 reads of the cycle counter and EL0 writes to PMZR_EL0 are enabled by PMUSERENR_EL0.UEN, unless trapped by another control, and PMUSERENR_EL0.CR controls the behavior of EL0 writes to the cycle counter and PMZR_EL0.
CR | Meaning |
---|---|
0b0 | When PMUSERENR_EL0.UEN == 0: EL0 reads of the cycle counter are disabled, unless enabled by PMUSERENR_EL0.EN. When PMUSERENR_EL0.UEN == 1: Permitted EL0 writes are not affected by this mechanism. |
0b1 | When PMUSERENR_EL0.UEN == 0: EL0 reads of the cycle counter are enabled, unless trapped by another control. When PMUSERENR_EL0.UEN == 1: Permitted EL0 writes to the cycle counter and PMZR_EL0.C are ignored, unless enabled by PMUSERENR_EL0.EN. |
In AArch64 state, the register accesses affected by this control are:
In AArch32 state, the register accesses affected by this control are:
When disabled, reads generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, and:
Ignored writes are not trapped and do not generate an exception.
This field is ignored by the PE when PMUSERENR_EL0.EN == 1.
The reset behavior of this field is:
Cycle counter Read enable.
When PMUSERENR_EL0.EN is 0, PMUSERENR_EL0.CR enables EL0 reads of the cycle counter.
CR | Meaning |
---|---|
0b0 |
EL0 reads of the cycle counter are disabled, unless enabled by PMUSERENR_EL0.EN. |
0b1 |
EL0 reads of the cycle counter are enabled, unless trapped by another control. |
In AArch64 state, the register accesses affected by this control are:
In AArch32 state, the register accesses affected by this control are:
When disabled, reads generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, and:
This field is ignored by the PE when PMUSERENR_EL0.EN == 1.
The reset behavior of this field is:
Software increment register Write enable.
When PMUSERENR_EL0.UEN is 0, PMUSERENR_EL0.SW enables EL0 writes to the Software increment register.
When PMUSERENR_EL0.UEN is 1, EL0 writes to the Software increment register are enabled by PMUSERENR_EL0.UEN, unless trapped by another control, and PMUSERENR_EL0.SW controls the behavior of EL0 writes to the Software increment register.
SW | Meaning |
---|---|
0b0 | When PMUSERENR_EL0.UEN == 0: EL0 writes to the Software increment register are disabled, unless enabled by PMUSERENR_EL0.EN. When PMUSERENR_EL0.UEN == 1: Permitted EL0 writes are not affected by this mechanism. |
0b1 | When PMUSERENR_EL0.UEN == 0: EL0 writes to the Software increment register are enabled, unless trapped by another control. When PMUSERENR_EL0.UEN == 1: Permitted EL0 writes to the Software increment register ignore the value of PMUACR_EL1. |
In AArch64 state, the register accesses affected by this control are:
In AArch32 state, the register accesses affected by this control are:
When disabled, writes generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, and:
This field is ignored by the PE when PMUSERENR_EL0.EN == 1.
The reset behavior of this field is:
Software increment register Write enable.
When PMUSERENR_EL0.EN is 0, PMUSERENR_EL0.SW enables EL0 writes to the Software increment register.
SW | Meaning |
---|---|
0b0 |
EL0 writes to the Software increment register are disabled, unless enabled by PMUSERENR_EL0.EN. |
0b1 |
EL0 writes to the Software increment register are enabled, unless trapped by another control. |
In AArch64 state, the register accesses affected by this control are:
In AArch32 state, the register accesses affected by this control are:
When disabled, writes generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, and:
This field is ignored by the PE when PMUSERENR_EL0.EN == 1.
The reset behavior of this field is:
Enable. Enables EL0 read/write access to PMU registers, other than the instruction counter.
EN | Meaning |
---|---|
0b0 |
EL0 accesses to PMU registers are trapped, unless enabled by PMUSERENR_EL0.{UEN,ER,CR}. |
0b1 |
EL0 accesses to PMU registers are enabled, unless trapped by another control. |
In AArch64 state, the register accesses affected by this control are:
When FEAT_PMUv3_ICNTR is implemented, this field does not affect MRS and MSR accesses to PMICNTR_EL0 and PMICFILTR_EL0.
In AArch32 state, the register accesses affected by this control are:
When trapped, reads and writes generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, and:
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b011 | 0b1001 | 0b1110 | 0b000 |
if PSTATE.EL == EL0 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMUSERENR_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMUSERENR_EL0; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMUSERENR_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMUSERENR_EL0; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMUSERENR_EL0; elsif PSTATE.EL == EL3 then X[t, 64] = PMUSERENR_EL0;
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b011 | 0b1001 | 0b1110 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.PMUSERENR_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMUSERENR_EL0 = X[t, 64]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMUSERENR_EL0 = X[t, 64]; elsif PSTATE.EL == EL3 then PMUSERENR_EL0 = X[t, 64];
30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f
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