no old file | htmldiff from- | (new) |
The TRBDEVID1 characteristics are:
Provides discovery information for the component.
For additional information, see the CoreSight Architecture Specification.
This register is present only when FEAT_TRBE_EXT is implemented. Otherwise, direct accesses to TRBDEVID1 are RES0.
TRBDEVID1 is in the Core power domain.
TRBDEVID1 is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | PMG_MAX | PARTID_MAX |
Reserved, RES0.
Largest permitted PMG value. The TRBMPAM.PMG field must implement at least enough bits to represent TRBDEVID1.PMG_MAX.
Reserved, RES0.
Largest permitted PARTID value. The TRBMPAM.PARTID field must implement at least enough bits to represent TRBDEVID1.PARTID_MAX.
Reserved, RES0.
Component | Offset | Instance |
---|---|---|
TRBE | 0xFC4 | TRBDEVID1 |
This interface is accessible as follows:
30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
no old file | htmldiff from- | (new) |