PMZR_EL0, Performance Monitors Zero with Mask

The PMZR_EL0 characteristics are:

Purpose

Zero the set of counters specified by the mask written to PMZR_EL0.

Configuration

This register is present only when FEAT_PMUv3p9 is implemented. Otherwise, direct accesses to PMZR_EL0 are UNDEFINED.

Attributes

PMZR_EL0 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0F0
CP30P29P28P27P26P25P24P23P22P21P20P19P18P17P16P15P14P13P12P11P10P9P8P7P6P5P4P3P2P1P0

Bits [63:33]

Reserved, RES0.

F<m>, bit [m+32], for m = 0
When FEAT_PMUv3_ICNTR is implemented:

Zero fixed-function instruction counter.

F<m>Meaning
0b0

Do not set fixed-function counter <m> to zero.

0b1

Set fixed-function counter <m> to zero.

Writing 1 to PMZR_EL0.F[0] zeros the instruction counter, PMICNTR_EL0.

The reset behavior of this field is:

Access to this field is W1C.


Otherwise:

Reserved, RES0.

C, bit [31]

Zero PMCCNTR_EL0.

CMeaning
0b0

Do not set Cycle counter to zero.

0b1

Set Cycle counter to zero.

Access to this field is W1C.

P<m>, bit [m], for m = 30 to 0

Zero PMEVCNTR<n>_EL0.

P<m>Meaning
0b0

Do not set Event counter <m> to zero.

0b1

Set Event counter <m> to zero.

Access to this field is W1C.

Accessing PMZR_EL0

Accesses to this register use the following encodings in the System register encoding space:

MSR PMZR_EL0, <Xt>

op0op1CRnCRmop2
0b110b0110b10010b11010b100

if PSTATE.EL == EL0 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then UNDEFINED; elsif PMUSERENR_EL0.EN == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMZR_EL0 = X[t, 64]; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMZR_EL0 = X[t, 64]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMZR_EL0 = X[t, 64]; elsif PSTATE.EL == EL3 then PMZR_EL0 = X[t, 64];


30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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