PMU

The PMU characteristics are:

Configuration

PMCCFILTR_EL0[31:0] and PMCCFILTR_EL0[31:0] are mapped to each other.

When FEAT_PMUv3_EXT64 is implemented, PMCCFILTR_EL0[63:32] and PMCCFILTR_EL0[63:32] are mapped to each other.

PMCCFILTR_EL0[31:0] and PMCCFILTR[31:0] are mapped to each other.

PMCCNTR_EL0[63:0] and PMCCNTR_EL0[63:0] are mapped to each other.

PMCCNTR_EL0[63:0] and PMCCNTR[63:0] are mapped to each other.

When FEAT_PMUv3_SS is implemented, PMCCNTSVR_EL1[63:0] and PMCCNTSVR_EL1[63:0] are mapped to each other.

When FEAT_PMUv3_EXT32 is implemented, PMCEID0[31:0] and PMCEID0_EL0[31:0] are mapped to each other.

When FEAT_PMUv3_EXT32 is implemented, PMCEID0[31:0] and PMCEID0[31:0] are mapped to each other.

When FEAT_PMUv3_EXT32 is implemented, PMCEID1[31:0] and PMCEID1_EL0[31:0] are mapped to each other.

When FEAT_PMUv3_EXT32 is implemented, PMCEID1[31:0] and PMCEID1[31:0] are mapped to each other.

When FEAT_PMUv3_EXT32 is implemented, PMCEID2[31:0] and PMCEID0_EL0[63:32] are mapped to each other.

When FEAT_PMUv3_EXT32 is implemented, PMCEID2[31:0] and PMCEID2[31:0] are mapped to each other.

When FEAT_PMUv3_EXT32 is implemented, PMCEID3[31:0] and PMCEID3[31:0] are mapped to each other.

PMCNTEN[31:0] and PMCNTENSET_EL0[31:0] are mapped to each other.

When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented, PMCNTEN[63:32] and PMCNTENSET_EL0[63:32] are mapped to each other.

PMCNTEN[31:0] and PMCNTENSET[31:0] are mapped to each other.

PMCNTEN[31:0] and PMCNTENCLR_EL0[31:0] are mapped to each other.

When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented, PMCNTEN[63:32] and PMCNTENCLR_EL0[63:32] are mapped to each other.

PMCNTEN[31:0] and PMCNTENCLR[31:0] are mapped to each other.

PMCNTENCLR_EL0[31:0] and PMCNTENCLR_EL0[31:0] are mapped to each other.

When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented, PMCNTENCLR_EL0[63:32] and PMCNTENCLR_EL0[63:32] are mapped to each other.

PMCNTENCLR_EL0[31:0] and PMCNTENCLR[31:0] are mapped to each other.

PMCNTENCLR_EL0[31:0] and PMCNTENSET_EL0[31:0] are mapped to each other.

When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented, PMCNTENCLR_EL0[63:32] and PMCNTENSET_EL0[63:32] are mapped to each other.

PMCNTENCLR_EL0[31:0] and PMCNTENSET[31:0] are mapped to each other.

PMCNTENSET_EL0[31:0] and PMCNTENSET_EL0[31:0] are mapped to each other.

When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented, PMCNTENSET_EL0[63:32] and PMCNTENSET_EL0[63:32] are mapped to each other.

PMCNTENSET_EL0[31:0] and PMCNTENCLR_EL0[31:0] are mapped to each other.

When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented, PMCNTENSET_EL0[63:32] and PMCNTENCLR_EL0[63:32] are mapped to each other.

PMCNTENSET_EL0[31:0] and PMCNTENCLR[31:0] are mapped to each other.

PMCNTENSET_EL0[31:0] and PMCNTENSET[31:0] are mapped to each other.

PMCR_EL0[7:0] and PMCR_EL0[7:0] are mapped to each other.

PMCR_EL0[7:0] and PMCR[7:0] are mapped to each other.

PMEVCNTR<n>_EL0[31:0] and PMEVCNTR<n>_EL0[31:0] are mapped to each other.

When FEAT_PMUv3p5 is implemented, PMEVCNTR<n>_EL0[63:32] and PMEVCNTR<n>_EL0[63:32] are mapped to each other.

PMEVCNTR<n>_EL0[31:0] and PMEVCNTR<n>[31:0] are mapped to each other.

When FEAT_PMUv3_SS is implemented, PMEVCNTSVR<n>_EL1[63:0] and PMEVCNTSVR<n>_EL1[63:0] are mapped to each other.

PMEVTYPER<n>_EL0[63:0] and PMEVTYPER<n>_EL0[63:0] are mapped to each other.

PMEVTYPER<n>_EL0[31:0] and PMEVTYPER<n>[31:0] are mapped to each other.

When FEAT_PMUv3_ICNTR is implemented, PMICFILTR_EL0[63:0] and PMICFILTR_EL0[63:0] are mapped to each other.

When FEAT_PMUv3_ICNTR is implemented and FEAT_PMUv3_SS is implemented, PMICNTSVR_EL1[63:0] and PMICNTSVR_EL1[63:0] are mapped to each other.

When FEAT_PMUv3_ICNTR is implemented, PMICNTR_EL0[63:0] and PMICNTR_EL0[63:0] are mapped to each other.

PMINTEN[31:0] and PMINTENSET_EL1[31:0] are mapped to each other.

When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented, PMINTEN[63:32] and PMINTENSET_EL1[63:32] are mapped to each other.

PMINTEN[31:0] and PMINTENSET[31:0] are mapped to each other.

PMINTEN[31:0] and PMINTENCLR_EL1[31:0] are mapped to each other.

When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented, PMINTEN[63:32] and PMINTENCLR_EL1[63:32] are mapped to each other.

PMINTEN[31:0] and PMINTENCLR[31:0] are mapped to each other.

PMINTENCLR_EL1[31:0] and PMINTENCLR_EL1[31:0] are mapped to each other.

When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented, PMINTENCLR_EL1[63:32] and PMINTENCLR_EL1[63:32] are mapped to each other.

PMINTENCLR_EL1[31:0] and PMINTENCLR[31:0] are mapped to each other.

PMINTENCLR_EL1[31:0] and PMINTENSET_EL1[31:0] are mapped to each other.

When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented, PMINTENCLR_EL1[63:32] and PMINTENSET_EL1[63:32] are mapped to each other.

PMINTENCLR_EL1[31:0] and PMINTENSET[31:0] are mapped to each other.

PMINTENSET_EL1[31:0] and PMINTENSET_EL1[31:0] are mapped to each other.

When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented, PMINTENSET_EL1[63:32] and PMINTENSET_EL1[63:32] are mapped to each other.

PMINTENSET_EL1[31:0] and PMINTENSET[31:0] are mapped to each other.

PMINTENSET_EL1[31:0] and PMINTENCLR_EL1[31:0] are mapped to each other.

When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented, PMINTENSET_EL1[63:32] and PMINTENCLR_EL1[63:32] are mapped to each other.

PMINTENSET_EL1[31:0] and PMINTENCLR[31:0] are mapped to each other.

PMOVS[31:0] and PMOVSSET_EL0[31:0] are mapped to each other.

When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented, PMOVS[63:32] and PMOVSSET_EL0[63:32] are mapped to each other.

PMOVS[31:0] and PMOVSSET[31:0] are mapped to each other.

PMOVS[31:0] and PMOVSCLR_EL0[31:0] are mapped to each other.

When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented, PMOVS[63:32] and PMOVSCLR_EL0[63:32] are mapped to each other.

PMOVS[31:0] and PMOVSR[31:0] are mapped to each other.

PMOVSCLR_EL0[31:0] and PMOVSCLR_EL0[31:0] are mapped to each other.

When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented, PMOVSCLR_EL0[63:32] and PMOVSCLR_EL0[63:32] are mapped to each other.

PMOVSCLR_EL0[31:0] and PMOVSR[31:0] are mapped to each other.

PMOVSCLR_EL0[31:0] and PMOVSSET_EL0[31:0] are mapped to each other.

When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented, PMOVSCLR_EL0[63:32] and PMOVSSET_EL0[63:32] are mapped to each other.

PMOVSCLR_EL0[31:0] and PMOVSSET[31:0] are mapped to each other.

PMOVSSET_EL0[31:0] and PMOVSSET_EL0[31:0] are mapped to each other.

When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented, PMOVSSET_EL0[63:32] and PMOVSSET_EL0[63:32] are mapped to each other.

PMOVSSET_EL0[31:0] and PMOVSSET[31:0] are mapped to each other.

PMOVSSET_EL0[31:0] and PMOVSCLR_EL0[31:0] are mapped to each other.

When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented, PMOVSSET_EL0[63:32] and PMOVSCLR_EL0[63:32] are mapped to each other.

PMOVSSET_EL0[31:0] and PMOVSR[31:0] are mapped to each other.

PMSWINC_EL0[31:0] and PMSWINC_EL0[31:0] are mapped to each other.

PMSWINC_EL0[31:0] and PMSWINC[31:0] are mapped to each other.

Attributes

PMU is a block of size: 4096 bytes

Contents

OffsetNameAccessor conditionRegister conditionMost permissive accessSize
0x000 + (8 * n) for n in 30:0PMEVCNTR<n>_EL0-When FEAT_PMUv3_EXT is implementedRW64 bit Register, when FEAT_PMUv3p5 is implemented 32 bit Register, otherwise
0x0F8PMCCNTR_EL0-When FEAT_PMUv3_EXT is implementedRW64 bit Register
0x100PMICNTR_EL0When FEAT_PMUv3_ICNTR is implementedWhen FEAT_PMUv3_ICNTR is implementedRW64 bit Register
0x200PMPCSR-When FEAT_PMUv3_EXT is implemented and FEAT_PCSRv8p2 is implementedRO64 bit Register
0x208PMCID1SRWhen FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT32 is implemented and FEAT_PCSRv8p2 is implementedRO32 bit Register
0x208PMVCIDSRWhen FEAT_PMUv3_EXT64 is implementedWhen FEAT_PMUv3_EXT64 is implemented and FEAT_PCSRv8p2 is implementedRO64 bit Register
0x20CPMVIDSRWhen FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT32 is implemented, FEAT_PCSRv8p2 is implemented and EL2 is implementedRO32 bit Register
0x220PMPCSR-When FEAT_PMUv3_EXT is implemented and FEAT_PCSRv8p2 is implementedRO64 bit Register
0x228PMCID1SRWhen FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT32 is implemented and FEAT_PCSRv8p2 is implementedRO32 bit Register
0x228PMCCIDSRWhen FEAT_PMUv3_EXT64 is implementedWhen FEAT_PMUv3_EXT is implementedRO64 bit Register
0x22CPMCID2SRWhen FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT32 is implementedRO32 bit Register
0x230PMPCSCTLWhen FEAT_PCSRv8p9 is implementedWhen FEAT_PCSRv8p9 is implementedRW64 bit Register
0x400 + (4 * n) for n in 30:0PMEVTYPER<n>_EL0[31:0]When FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT is implementedRW64 bit Register
0x400 + (8 * n) for n in 30:0PMEVTYPER<n>_EL0[63:0]When FEAT_PMUv3_EXT64 is implementedWhen FEAT_PMUv3_EXT is implementedRW64 bit Register
0x47CPMCCFILTR_EL0When FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT is implementedRW64 bit Register, when FEAT_PMUv3_EXT64 is implemented 32 bit Register, otherwise
0x480PMICFILTR_EL0When FEAT_PMUv3_ICNTR is implementedWhen FEAT_PMUv3_ICNTR is implementedRW64 bit Register
0x4F8PMCCFILTR_EL0When FEAT_PMUv3_EXT64 is implementedWhen FEAT_PMUv3_EXT is implementedRW64 bit Register, when FEAT_PMUv3_EXT64 is implemented
0x600 + (8 * n) for n in 30:0PMEVCNTSVR<n>_EL1When FEAT_PMUv3_SS is implementedWhen FEAT_PMUv3_SS is implementedRO64 bit Register
0x6F8PMCCNTSVR_EL1When FEAT_PMUv3_SS is implementedWhen FEAT_PMUv3_SS is implementedRO64 bit Register
0x700PMICNTSVR_EL1When FEAT_PMUv3_SS is implemented and FEAT_PMUv3_ICNTR is implementedWhen FEAT_PMUv3_ICNTR is implemented and FEAT_PMUv3_SS is implementedRO64 bit Register
0xA00 + (4 * n) for n in 30:0PMEVTYPER<n>_EL0[63:32]When FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT is implementedRW64 bit Register
0xC00PMCNTENSET_EL0When FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT is implementedRW64 bit Register
0xC04PMCNTENSET_EL0[63:32]When FEAT_PMUv3_EXT32 is implemented and (FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented)When FEAT_PMUv3_EXT is implementedRW64 bit Register, when FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented 32 bit Register, otherwise
0xC10PMCNTENWhen FEAT_PMUv3_EXT64 is implementedWhen FEAT_PMUv3_EXT64 is implementedRW64 bit Register
0xC20PMCNTENCLR_EL0When FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT is implementedRW64 bit Register
0xC24PMCNTENCLR_EL0[63:32]When FEAT_PMUv3_EXT32 is implemented and (FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented)When FEAT_PMUv3_EXT is implementedRW64 bit Register, when FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented 32 bit Register, otherwise
0xC40PMINTENSET_EL1When FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT is implementedRW64 bit Register
0xC44PMINTENSET_EL1[63:32]When FEAT_PMUv3_EXT32 is implemented and (FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented)When FEAT_PMUv3_EXT is implementedRW64 bit Register, when FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented 32 bit Register, otherwise
0xC50PMINTENWhen FEAT_PMUv3_EXT64 is implementedWhen FEAT_PMUv3_EXT64 is implementedRW64 bit Register
0xC60PMINTENCLR_EL1When FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT is implementedRW64 bit Register
0xC64PMINTENCLR_EL1[63:32]When FEAT_PMUv3_EXT32 is implemented and (FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented)When FEAT_PMUv3_EXT is implementedRW64 bit Register, when FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented 32 bit Register, otherwise
0xC80PMOVSCLR_EL0When FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT is implementedRW64 bit Register
0xC84PMOVSCLR_EL0[63:32]When FEAT_PMUv3_EXT32 is implemented and (FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented)When FEAT_PMUv3_EXT is implementedRW64 bit Register, when FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented 32 bit Register, otherwise
0xC90PMOVSWhen FEAT_PMUv3_EXT64 is implementedWhen FEAT_PMUv3_EXT64 is implementedRW64 bit Register
0xCA0PMSWINC_EL0When FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT32 is implemented and an implementation implements PMSWINC_EL0WO32 bit Register
0xCC0PMOVSSET_EL0When FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT is implementedRW64 bit Register
0xCC4PMOVSSET_EL0[63:32]When FEAT_PMUv3_EXT32 is implemented and (FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented)When FEAT_PMUv3_EXT is implementedRW64 bit Register, when FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented 32 bit Register, otherwise
0xCE0PMCGCR0When FEAT_PMUv3_ICNTR is implementedWhen FEAT_PMUv3_ICNTR is implementedRO32 bit Register
0xE00PMCFGR-When FEAT_PMUv3_EXT is implementedRO64 bit Register, when FEAT_PMUv3_EXT64 is implemented 32 bit Register, otherwise
0xE04PMCR_EL0When FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT is implementedRW64 bit Register, when FEAT_PMUv3_EXT64 is implemented 32 bit Register, otherwise
0xE08PMIIDRWhen FEAT_PMUv3_EXT64 is implementedWhen (FEAT_PMUv3_EXT32 is implemented and an implementation implements PMIIDR) or FEAT_PMUv3_EXT64 is implementedRO64 bit Register, when FEAT_PMUv3_EXT64 is implemented
0xE10PMCR_EL0When FEAT_PMUv3_EXT64 is implementedWhen FEAT_PMUv3_EXT is implementedRW64 bit Register, when FEAT_PMUv3_EXT64 is implemented
0xE20PMCEID0When FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT32 is implementedRO32 bit Register
0xE24PMCEID1When FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT32 is implementedRO32 bit Register
0xE28PMCEID2When FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT32 is implemented and FEAT_PMUv3p1 is implementedRO32 bit Register
0xE2CPMCEID3When FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT32 is implemented and FEAT_PMUv3p1 is implementedRO32 bit Register
0xE30PMSSCR_EL1When FEAT_PMUv3_SS is implementedWhen FEAT_PMUv3_SS is implementedRW64 bit Register
0xE40PMMIR-When FEAT_PMUv3_EXT is implemented and FEAT_PMUv3p4 is implementedRO64 bit Register, when FEAT_PMUv3_EXT64 is implemented 32 bit Register, otherwise
0xF00PMITCTRLWhen FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT32 is implemented and an implementation implements PMITCTRLRW32 bit Register
0xFA8PMDEVAFFWhen FEAT_PMUv3_EXT64 is implementedWhen FEAT_PMUv3_EXT64 is implementedRO64 bit Register
0xFA8PMDEVAFF0When FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT32 is implementedRO32 bit Register
0xFACPMDEVAFF1When FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT32 is implementedRO32 bit Register
0xFB0PMLARWhen FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT32 is implementedWO32 bit Register
0xFB4PMLSRWhen FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT32 is implementedRO32 bit Register
0xFB8PMAUTHSTATUS-When FEAT_PMUv3_EXT is implementedRO32 bit Register
0xFBCPMDEVARCH-When FEAT_PMUv3_EXT is implementedRO32 bit Register
0xFC8PMDEVIDWhen FEAT_PMUv3_EXT32 is implementedWhen FEAT_PMUv3_EXT32 is implementedRO32 bit Register
0xFCCPMDEVTYPE-When an implementation implements PMDEVTYPERO32 bit Register
0xFD0PMPIDR4-When FEAT_PMUv3_EXT is implemented and an implementation implements PMPIDR4RO32 bit Register
0xFE0PMPIDR0-When FEAT_PMUv3_EXT is implemented and an implementation implements PMPIDR0RO32 bit Register
0xFE4PMPIDR1-When FEAT_PMUv3_EXT is implemented and an implementation implements PMPIDR1RO32 bit Register
0xFE8PMPIDR2-When FEAT_PMUv3_EXT is implemented and an implementation implements PMPIDR2RO32 bit Register
0xFECPMPIDR3-When FEAT_PMUv3_EXT is implemented and an implementation implements PMPIDR3RO32 bit Register
0xFF0PMCIDR0-When FEAT_PMUv3_EXT is implemented and an implementation implements PMCIDR0RO32 bit Register
0xFF4PMCIDR1-When FEAT_PMUv3_EXT is implemented and an implementation implements PMCIDR1RO32 bit Register
0xFF8PMCIDR2-When FEAT_PMUv3_EXT is implemented and an implementation implements PMCIDR2RO32 bit Register
0xFFCPMCIDR3-When FEAT_PMUv3_EXT is implemented and an implementation implements PMCIDR3RO32 bit Register

Direct accesses to other offsets in this block are RES0.


30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.