EDDEVID1, External Debug Device ID register 1

The EDDEVID1 characteristics are:

Purpose

Provides extra information for external debuggers about features of the debug implementation.

Configuration

If FEAT_DoPD is implemented, this register is in the Core power domain.

If FEAT_DoPD is not implemented, this register is in the Debug power domain.

Attributes

EDDEVID1 is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
RES0HSRPCSROffset

Bits [31:8]

Reserved, RES0.

HSR, bits [7:4]

Indicates support for the External Debug Halt Status Register (EDHSR). Defined values are:

HSRMeaning
0b0000

EDHSR is not implemented. The PE follows behaviors consistent with the EDHSR fields having a zero value.

0b0001

EDHSR is implemented.

All other values are reserved.

If FEAT_SME is implemented, the permitted values are 0b0000 and 0b0001.

If FEAT_SME is not implemented, the only permitted value is 0b0000.

PCSROffset, bits [3:0]

Indicates the offset applied to PC samples returned by reads of EDPCSR. Permitted values of this field in Armv8 are:

PCSROffsetMeaning
0b0000

EDPCSR not implemented.

0b0010

EDPCSR implemented, and samples have no offset applied and do not sample the instruction set state in AArch32 state.

When FEAT_PCSRv8p2 is implemented, the only permitted value is 0b0000.

Note

FEAT_PCSRv8p2 implements the PC Sample-based Profiling Extension in the Performance Monitors register space, as indicated by the value of PMDEVID.PCSample.

Accessing EDDEVID1

EDDEVID1 can be accessed through the external debug interface:

ComponentOffsetInstance
Debug0xFC4EDDEVID1

This interface is accessible as follows:


05/07/2022 17:07; b0421fa9a8865165f9b91af9b4a566111f866305

Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.