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PMINTENSET_EL1, Performance Monitors Interrupt Enable Set register

The PMINTENSET_EL1 characteristics are:

Purpose

Enables the generation of interrupt requests on overflows from the Cycle Count Register, PMU.PMCCNTR_EL0, and the event counters PMU.PMEVCNTR<n>_EL0. Reading the register shows which overflow interrupt requests are enabled.PMCCNTR_EL0, and the event counters PMEVCNTR<n>_EL0. Reading the register shows which overflow interrupt requests are enabled.

Configuration

External register PMINTENSET_EL1 bits [31:0] are architecturally mapped to AArch64 System register PMINTENSET_EL1[31:0].

External register PMINTENSET_EL1 bits [63:32] are architecturally mapped to AArch64 System register PMINTENSET_EL1[63:32] when FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented.

External register PMINTENSET_EL1 bits [31:0] are architecturally mapped to AArch32 System register PMINTENSET[31:0].

External register PMINTENSET_EL1 bits [31:0] are architecturally mapped to AArch64 System register PMINTENCLR_EL1[31:0].

External register PMINTENSET_EL1 bits [63:32] are architecturally mapped to AArch64 System register PMINTENCLR_EL1[63:32] when FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented.

External register PMINTENSET_EL1 bits [31:0] are architecturally mapped to AArch32 System register PMINTENCLR[31:0].

This register is present only when FEAT_PMUv3_EXT is implemented. Otherwise, direct accesses to PMINTENSET_EL1 are RES0.

PMINTENSET_EL1 is in the Core power domain.

Attributes

PMINTENSET_EL1 is a: 32-bit register.

This register is part of the PMU block.

Field descriptions

When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented:

6331623061296028592758265725562455235422532152205119501849174816471546144513441243114210419408397386375364353342331320
313029282726252423222120191817161514131211109876543210
RES0F0
CP30P29P28P27P26P25P24P23P22P21P20P19P18P17P16P15P14P13P12P11P10P9P8P7P6P5P4P3P2P1P0

Bits [63:33]

Reserved, RES0.

F0, bit [32]
When FEAT_PMUv3_ICNTR is implemented:

Interrupt request on unsigned overflow of PMU.PMICNTR_EL0 enable. On writes, allows software to enable the interrupt request on unsigned overflow of PMU.PMICNTR_EL0. On reads, returns the interrupt request on unsigned overflow of PMU.PMICNTR_EL0 enable status.

F0Meaning
0b0

Interrupt request on unsigned overflow of PMU.PMICNTR_EL0 disabled.

0b1

Interrupt request on unsigned overflow of PMU.PMICNTR_EL0 enabled.

The reset behavior of this field is:

Accessing this field has the following behavior:


Otherwise:

Reserved, RES0.

C, bit [31]

PMCCNTR_EL0PMU.PMCCNTR_EL0 overflow interrupt request enable bit. Possible values are:

CMeaning
0b0

When read, means the cycle counter overflow interrupt request is disabled. When written, has no effect.

0b1

When read, means the cycle counter overflow interrupt request is enabled. When written, enables the cycle count overflow interrupt request.

The reset behavior of this field is:

P<n>, bit [n], for n = 30 to 0

Event counter overflow interrupt request enable bit for PMU.PMEVCNTR<n>_EL0.PMEVCNTR<n>_EL0.

If PMU.PMCFGR.N is less than 31, bits [30:PMU.PMCFGR.N] are RAZ/WI.PMCFGR.N is less than 31, bits [30:PMCFGR.N] are RAZ/WI.

P<n>Meaning
0b0

When read, means that the PMU.PMEVCNTR<n>_EL0 event counter interrupt request is disabled. When written, has no effect.PMEVCNTR<n>_EL0 event counter interrupt request is disabled. When written, has no effect.

0b1

When read, means that the PMU.PMEVCNTR<n>_EL0 event counter interrupt request is enabled. When written, enables the PMU.PMEVCNTR<n>_EL0 interrupt request.PMEVCNTR<n>_EL0 event counter interrupt request is enabled. When written, enables the PMEVCNTR<n>_EL0 interrupt request.

The reset behavior of this field is:

Accessing PMINTENSET_EL1

Note

SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.

PMINTENSET_EL1 can be accessed through the external debug interface:

Otherwise:

313029282726252423222120191817161514131211109876543210
CP30P29P28P27P26P25P24P23P22P21P20P19P18P17P16P15P14P13P12P11P10P9P8P7P6P5P4P3P2P1P0
ComponentOffsetInstance
PMU0xC40PMINTENSET_EL1

This interface is accessible as follows:

C, bit [31]

PMU.PMCCNTR_EL0 overflow interrupt request enable bit.

CMeaning
0b0

When read, means the cycle counter overflow interrupt request is disabled. When written, has no effect.

0b1

When read, means the cycle counter overflow interrupt request is enabled. When written, enables the cycle count overflow interrupt request.

The reset behavior of this field is:

P<n>, bit [n], for n = 30 to 0

Event counter overflow interrupt request enable bit for PMU.PMEVCNTR<n>_EL0.

If PMU.PMCFGR.N is less than 31, bits [30:PMU.PMCFGR.N] are RAZ/WI.

P<n>Meaning
0b0

When read, means that the PMU.PMEVCNTR<n>_EL0 event counter interrupt request is disabled. When written, has no effect.

0b1

When read, means that the PMU.PMEVCNTR<n>_EL0 event counter interrupt request is enabled. When written, enables the PMU.PMEVCNTR<n>_EL0 interrupt request.

The reset behavior of this field is:

Accessing PMINTENSET_EL1

Note

SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.

Accesses to this register use the following encodings in the external debug interface:

When FEAT_PMUv3_EXT64 is implemented
BlockAccess at address 0xC40

PMINTENSET_EL1 can be accessed through the PMU block as follows:

FrameOffset
PMU0xC40

When FEAT_PMUv3_EXT32 is implemented
BlockAccess at address 0xC40

PMINTENSET_EL1 can be accessed through the PMU block as follows:

FrameOffsetRange
PMU0xC4031:0

When (FEAT_PMUv3_EXT32 is implemented and FEAT_PMUv3p9 is implemented) or FEAT_PMUv3_ICNTR is implemented
BlockAccess at address 0xC44

PMINTENSET_EL1 can be accessed through the PMU block as follows:

FrameOffsetRange
PMU0xC4463:32

3005/0907/2022 1517:5708; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96fb0421fa9a8865165f9b91af9b4a566111f866305

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