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PMUSERENR_EL0, Performance Monitors User Enable Register

The PMUSERENR_EL0 characteristics are:

Purpose

Enables or disables EL0 access to the Performance Monitors.

Configuration

AArch64 System register PMUSERENR_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMUSERENR[31:0].

This register is present only when FEAT_PMUv3 is implemented. Otherwise, direct accesses to PMUSERENR_EL0 are UNDEFINED.

Attributes

PMUSERENR_EL0 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0TIDERIRCRUENSWERENCRSWEN

Bits [63:74]

Reserved, RES0.

TIDER, bit [63]
When FEAT_PMUv3p9 is implemented:

In AArch64 state, trapped accesses are reported using EC syndrome value 0x18.

In AArch32 state, trapped accesses are reported using EC syndrome value 0x03.

TrapEvent IDcounter registers.Read. Traps EL0 read access to common event identificationcounters registers.to EL1, or to EL2 when it is implemented and enabled for the current Security state andHCR_EL2.TGE is 1.

TIDERMeaning
0b0

EL0 using AArch32: EL0 reads of the PMXEVCNTR and PMEVCNTR<n>, and EL0 read/write accesses to the PMSELR, are trapped if PMUSERENR_EL0.EN is also 0.

AccessesEL0 tousing PMCEID<n>_EL0AArch64: andEL0 PMCEID<n>reads areof not trapped by this mechanism.thePMXEVCNTR_EL0 and PMEVCNTR<n>_EL0, and EL0 read/write accesses to the PMSELR_EL0, are trapped if PMUSERENR_EL0.EN is also 0.

0b1

EL0Overrides readPMUSERENR_EL0.EN accesses to PMCEID<n>_EL0 and PMCEID<n> are trapped.enables:

In AArch64 state, the register accesses affected by this control are:

In AArch32 state, the register accesses affected by this control are:

When trapped, reads generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, and:

The reset behavior of this field is:


Otherwise:

CR, bit [2]

In AArch64 state, trapped accesses are reported using EC syndrome value 0x18.

In AArch32 state, trapped MRC accesses are reported using EC syndrome value 0x03, trapped MRRC accesses are reported using EC syndrome value 0x04.

CRMeaning
0b0

EL0 using AArch64: EL0 read accesses to the PMCCNTR_EL0 are trapped if PMUSERENR_EL0.EN is also 0.

EL0 using AArch32: EL0 read accesses to the PMCCNTR are trapped if PMUSERENR_EL0.EN is also 0.

0b1

Overrides PMUSERENR_EL0.EN and enables access to:

The reset behavior of this field is:

Reserved, RES0.

Cycle counter Read. Traps EL0 access to cycle counter reads to EL1, or to EL2 when it is implemented and enabled for the current Security state and HCR_EL2.TGE is 1.

IRSW, bit [51]
When FEAT_PMUv3_ICNTR is implemented:

InstructionTraps counterSoftware ReadIncrement enable.writes to EL1, or to EL2 when it is implemented and enabled for the current Security state andHCR_EL2.TGE is 1.

When PMUSERENR_EL0.UEN is 0, PMUSERENR_EL0.IR enables EL0 reads of the instruction counter.

In AArch64 state, trapped accesses are reported using EC syndrome value 0x18.

When PMUSERENR_EL0.UEN is 1, EL0 reads of the instruction counter and EL0 writes to PMZR_EL0 are enabled by PMUSERENR_EL0.UEN, unless trapped by another control, and PMUSERENR_EL0.IR controls the behavior of EL0 writes to the instruction counter and PMZR_EL0.

In AArch32 state, trapped accesses are reported using EC syndrome value 0x03.

IRSWMeaning
0b0

WhenEL0 PMUSERENR_EL0.UENusing == 0AArch64: EL0 readswrites ofto the instruction counter are disabled.PMSWINC_EL0 are trapped if PMUSERENR_EL0.EN is also 0.

WhenEL0 PMUSERENR_EL0.UENusing == 1AArch32: Permitted EL0 writes areto not affected by this mechanism.thePMSWINC are trapped if PMUSERENR_EL0.EN is also 0.

0b1

WhenOverrides PMUSERENR_EL0.UENPMUSERENR_EL0.EN ==and 0:enables EL0access reads of the instruction counter are enabled, unless trapped by another control.to:

When PMUSERENR_EL0.UEN == 1: Permitted EL0 writes to the instruction counter and PMZR_EL0.F0 are ignored.

In AArch64 state, the register accesses affected by this control are:

When disabled, reads generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, reported using EC syndrome value 0x18.

Ignored writes are not trapped and do not generate an exception.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

UEN, bit [4]
When FEAT_PMUv3p9 is implemented:

User Enable, with access controlled by PMUACR_EL1. Enables EL0 read/write access to PMU registers, other than PMCR_EL0. Software can restrict permitted accesses using PMUSERENR_EL0.{IR,ER,CR} and PMUACR_EL1.

UENMeaning
0b0

EL0 accesses to PMU registers are trapped, unless enabled by PMUSERENR_EL0.{IR,ER,CR,EN}.

0b1

EL0 accesses to PMU registers are enabled, unless trapped by another control. A permitted access might be restricted by PMUSERENR_EL0.{IR,ER,CR} and PMUACR_EL1.

In AArch64 state, the register accesses affected by this control are:

In AArch32 state, the register accesses affected by this control are:

When trapped, reads and writes generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, and:

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

ER, bit [3]
When FEAT_PMUv3p9 is implemented:

Event counters Read enable.

When PMUSERENR_EL0.{UEN,EN} is {0,0}, PMUSERENR_EL0.ER enables EL0 reads of the event counters and EL0 reads and writes of the select register.

When PMUSERENR_EL0.{UEN,EN} is {1,0}, EL0 reads of the event counters and EL0 writes to PMZR_EL0 are enabled by PMUSERENR_EL0.UEN, unless trapped by another control, and PMUSERENR_EL0.ER controls the behavior of EL0 writes to the event counters and PMZR_EL0.

ERMeaning
0b0

When PMUSERENR_EL0.UEN == 0: EL0 reads of the event counters and EL0 reads and writes of the select register are disabled, unless enabled by PMUSERENR_EL0.EN.

When PMUSERENR_EL0.UEN == 1: Permitted EL0 writes are not affected by this mechanism.

0b1

When PMUSERENR_EL0.UEN == 0: EL0 reads of the event counters and EL0 reads and writes of the select register are enabled, unless trapped by another control.

When PMUSERENR_EL0.UEN == 1: Permitted EL0 writes to the event counters and PMZR_EL0.P[30:0] are ignored, unless enabled by PMUSERENR_EL0.EN.

In AArch64 state, the register accesses affected by this control are:

In AArch32 state, the register accesses affected by this control are:

When disabled, reads and writes generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, and:

Ignored writes are not trapped and do not generate an exception.

This field is ignored by the PE when PMUSERENR_EL0.EN == 1.

The reset behavior of this field is:


Otherwise:

Event counters Read enable.

When PMUSERENR_EL0.EN is 0, PMUSERENR_EL0.ER enables EL0 reads of the event counters and EL0 reads and writes of the select register.

ERMeaning
0b0

EL0 reads of the event counters and EL0 reads and writes of the select register are disabled, unless enabled by PMUSERENR_EL0.EN.

0b1

EL0 reads of the event counters and EL0 reads and writes of the select register are enabled, unless trapped by another control.

In AArch64 state, the register accesses affected by this control are:

In AArch32 state, the register accesses affected by this control are:

When disabled, reads and writes generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, and:

This field is ignored by the PE when PMUSERENR_EL0.EN == 1.

The reset behavior of this field is:

CR, bit [2]
When FEAT_PMUv3p9 is implemented:

Cycle counter Read enable.

When PMUSERENR_EL0.{UEN,EN} is {0,0}, PMUSERENR_EL0.CR enables EL0 reads of the cycle counter.

When PMUSERENR_EL0.{UEN,EN} is {1,0}, EL0 reads of the cycle counter and EL0 writes to PMZR_EL0 are enabled by PMUSERENR_EL0.UEN, unless trapped by another control, and PMUSERENR_EL0.CR controls the behavior of EL0 writes to the cycle counter and PMZR_EL0.

CRMeaning
0b0

When PMUSERENR_EL0.UEN == 0: EL0 reads of the cycle counter are disabled, unless enabled by PMUSERENR_EL0.EN.

When PMUSERENR_EL0.UEN == 1: Permitted EL0 writes are not affected by this mechanism.

0b1

When PMUSERENR_EL0.UEN == 0: EL0 reads of the cycle counter are enabled, unless trapped by another control.

When PMUSERENR_EL0.UEN == 1: Permitted EL0 writes to the cycle counter and PMZR_EL0.C are ignored, unless enabled by PMUSERENR_EL0.EN.

In AArch64 state, the register accesses affected by this control are:

In AArch32 state, the register accesses affected by this control are:

When disabled, reads generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, and:

Ignored writes are not trapped and do not generate an exception.

This field is ignored by the PE when PMUSERENR_EL0.EN == 1.

The reset behavior of this field is:


Otherwise:

Cycle counter Read enable.

When PMUSERENR_EL0.EN is 0, PMUSERENR_EL0.CR enables EL0 reads of the cycle counter.

CRMeaning
0b0

EL0 reads of the cycle counter are disabled, unless enabled by PMUSERENR_EL0.EN.

0b1

EL0 reads of the cycle counter are enabled, unless trapped by another control.

In AArch64 state, the register accesses affected by this control are:

In AArch32 state, the register accesses affected by this control are:

When disabled, reads generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, and:

This field is ignored by the PE when PMUSERENR_EL0.EN == 1.

The reset behavior of this field is:

SW, bit [1]
When FEAT_PMUv3p9 is implemented:

Software increment register Write enable.

When PMUSERENR_EL0.UEN is 0, PMUSERENR_EL0.SW enables EL0 writes to the Software increment register.

When PMUSERENR_EL0.UEN is 1, EL0 writes to the Software increment register are enabled by PMUSERENR_EL0.UEN, unless trapped by another control, and PMUSERENR_EL0.SW controls the behavior of EL0 writes to the Software increment register.

SWMeaning
0b0

When PMUSERENR_EL0.UEN == 0: EL0 writes to the Software increment register are disabled, unless enabled by PMUSERENR_EL0.EN.

When PMUSERENR_EL0.UEN == 1: Permitted EL0 writes are not affected by this mechanism.

0b1

When PMUSERENR_EL0.UEN == 0: EL0 writes to the Software increment register are enabled, unless trapped by another control.

When PMUSERENR_EL0.UEN == 1: Permitted EL0 writes to the Software increment register ignore the value of PMUACR_EL1.

In AArch64 state, the register accesses affected by this control are:

In AArch32 state, the register accesses affected by this control are:

When disabled, writes generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, and:

This field is ignored by the PE when PMUSERENR_EL0.EN == 1.

The reset behavior of this field is:


Otherwise:

Software increment register Write enable.

When PMUSERENR_EL0.EN is 0, PMUSERENR_EL0.SW enables EL0 writes to the Software increment register.

SWMeaning
0b0

EL0 writes to the Software increment register are disabled, unless enabled by PMUSERENR_EL0.EN.

0b1

EL0 writes to the Software increment register are enabled, unless trapped by another control.

In AArch64 state, the register accesses affected by this control are:

In AArch32 state, the register accesses affected by this control are:

When disabled, writes generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, and:

This field is ignored by the PE when PMUSERENR_EL0.EN == 1.

The reset behavior of this field is:

EN, bit [0]

Enable.Traps Enables EL0 read/writeaccesses access to PMUthe Performance Monitor registers to EL1, otheror thanto EL2 when it is implemented and enabled for the instructioncurrent counter.Security state andHCR_EL2.TGE is 1, from both Execution states as follows:

ENMeaning
0b0

While at EL0, accesses to PMUthe specified registers at EL0 are trapped, unless enabledoverridden by one of PMUSERENR_EL0.{UEN,ER, CR, SW}.

0b1

EL0While accessesat toEL0, PMUsoftware registerscan areaccess enabled,all unlessof trappedthe byspecified another control.registers.

In AArch64 state, the register accesses affected by this control are:

Note

When FEAT_PMUv3_ICNTR is implemented, this field does not affect MRS and MSR accesses to PMICNTR_EL0 and PMICFILTR_EL0.

In AArch32 state, the register accesses affected by this control are:

When trapped, reads and writes generate an exception to EL1, or to EL2 when EL2 is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, and:

The reset behavior of this field is:

Accessing PMUSERENR_EL0

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PMUSERENR_EL0

op0op1CRnCRmop2
0b110b0110b10010b11100b000

if PSTATE.EL == EL0 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMUSERENR_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMUSERENR_EL0; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMUSERENR_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMUSERENR_EL0; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMUSERENR_EL0; elsif PSTATE.EL == EL3 then X[t, 64] = PMUSERENR_EL0;

MSR PMUSERENR_EL0, <Xt>

op0op1CRnCRmop2
0b110b0110b10010b11100b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.PMUSERENR_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMUSERENR_EL0 = X[t, 64]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMUSERENR_EL0 = X[t, 64]; elsif PSTATE.EL == EL3 then PMUSERENR_EL0 = X[t, 64];


3005/0907/2022 1517:5808; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96fb0421fa9a8865165f9b91af9b4a566111f866305

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