The PMICFILTR_EL0 characteristics are:
Configures the Instruction Counter.
External register PMICFILTR_EL0 bits [63:0] are architecturally mapped to AArch64 System register PMICFILTR_EL0[63:0].
This register is present only when FEAT_PMUv3_ICNTR is implemented. Otherwise, direct accesses to PMICFILTR_EL0 are RES0.
PMICFILTR_EL0 is in the Core power domain.
If FEAT_Debugv8p4 is implemented, the OPTIONAL Software Lock is not implemented.
PMICFILTR_EL0 is a 64-bit register.
This register is part of the PMU block.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | SYNC | RES0 | |||||||||||||||||||||||||||||
P | U | NSK | NSU | NSH | M | RES0 | SH | T | RLK | RLU | RLH | RES0 | evtCount |
Reserved, RES0.
Synchronous mode. Controls whether a PMU exception generated by the counter is synchronous or asynchronous.
SYNC | Meaning |
---|---|
0b0 |
Asynchronous PMU exception is enabled. |
0b1 |
Synchronous PMU exception is enabled. |
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
EL1 filtering. Controls counting instructions in EL1.
P | Meaning |
---|---|
0b0 |
This bit has no effect on filtering of instructions. |
0b1 |
Instructions in EL1 are not counted. |
If EL3 is implemented, then counting instructions in Non-secure EL1 is further controlled by PMICFILTR_EL0.NSK, and counting instructions in EL3 is further controlled by PMICFILTR_EL0.M.
If FEAT_RME is implemented, then counting instructions in Realm EL1 is further controlled by PMICFILTR_EL0.RLK.
The reset behavior of this field is:
EL0 filtering. Controls counting instructions in EL0.
U | Meaning |
---|---|
0b0 |
This bit has no effect on filtering of instructions. |
0b1 |
Instructions in EL0 are not counted. |
If EL3 is implemented, then PMICFILTR_EL0.NSU further controls filtering instructions in Non-secure EL0.
If FEAT_RME is implemented, then counting instructions in Realm EL1 is further controlled by PMICFILTR_EL0.RLU.
The reset behavior of this field is:
Non-secure EL1 filtering. Controls counting instructions in Non-secure EL1. If PMICFILTR_EL0.NSK is equal to PMICFILTR_EL0.P, then instructions in Non-secure EL1 are counted. Otherwise, instructions in Non-secure EL1 are not counted.
NSK | Meaning |
---|---|
0b0 | If PMICFILTR_EL0.P == 0, then this bit has no effect on filtering of instructions. If PMICFILTR_EL0.P == 1, then instructions in Non-secure EL1 are not counted. |
0b1 | If PMICFILTR_EL0.P == 0, then instructions in Non-secure EL1 are not counted. If PMICFILTR_EL0.P == 1, then this bit has no effect on filtering of instructions. |
The reset behavior of this field is:
Reserved, RES0.
Non-secure EL0 filtering. Controls counting instructions in Non-secure EL0. If PMICFILTR_EL0.NSU is equal to PMICFILTR_EL0.U, then instructions in Non-secure EL0 are counted. Otherwise, instructions in Non-secure EL0 are not counted.
NSU | Meaning |
---|---|
0b0 | If PMICFILTR_EL0.U == 0, then this bit has no effect on filtering of instructions. If PMICFILTR_EL0.U == 1, then instructions in Non-secure EL0 are not counted. |
0b1 | If PMICFILTR_EL0.U == 0, then instructions in Non-secure EL0 are not counted. If PMICFILTR_EL0.U == 1, then this bit has no effect on filtering of instructions. |
The reset behavior of this field is:
Reserved, RES0.
EL2 filtering. Controls counting instructions in EL2.
NSH | Meaning |
---|---|
0b0 |
Instructions in EL2 are not counted. |
0b1 |
This bit has no effect on filtering of instructions. |
If EL3 is implemented and FEAT_SEL2 is implemented, then counting instructions in Secure EL2 is further controlled by PMICFILTR_EL0.SH.
If FEAT_RME is implemented, then counting instructions in Realm EL2 is further controlled by PMICFILTR_EL0.RLH.
The reset behavior of this field is:
Reserved, RES0.
EL3 filtering. Controls counting instructions in EL3. If PMICFILTR_EL0.M is equal to PMICFILTR_EL0.P, then instructions in EL3 are counted. Otherwise, instructions in EL3 are not counted.
M | Meaning |
---|---|
0b0 | If PMICFILTR_EL0.P == 0, then this bit has no effect on filtering of instructions. If PMICFILTR_EL0.P == 1, then instructions in EL3 are not counted. |
0b1 | If PMICFILTR_EL0.P == 0, then instructions in EL3 are not counted. If PMICFILTR_EL0.P == 1, then this bit has no effect on filtering of instructions. |
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Secure EL2 filtering. Controls counting instructions in Secure EL2. If PMICFILTR_EL0.SH is not equal to PMICFILTR_EL0.NSH, then instructions in Secure EL2 are counted. Otherwise, instructions in Secure EL2 are not counted.
SH | Meaning |
---|---|
0b0 | If PMICFILTR_EL0.NSH == 0, then instructions in Secure EL2 are not counted. If PMICFILTR_EL0.NSH == 1, then this bit has no effect on filtering of instructions. |
0b1 | If PMICFILTR_EL0.NSH == 0, then this bit has no effect on filtering of instructions. If PMICFILTR_EL0.NSH == 1, then instructions in Secure EL2 are not counted. |
The reset behavior of this field is:
Accessing this field has the following behavior:
Reserved, RES0.
Non-transactional state filtering. Controls counting instructions in Non-transactional state.
T | Meaning |
---|---|
0b0 |
This bit has no effect on filtering of instructions. |
0b1 |
Instructions in Non-transactional state are not counted. |
The reset behavior of this field is:
Reserved, RES0.
Realm EL1 filtering. Controls counting instructions in Realm EL1. If PMICFILTR_EL0.RLK is equal to PMICFILTR_EL0.P, then instructions in Realm EL1 are counted. Otherwise, instructions in Realm EL1 are not counted.
RLK | Meaning |
---|---|
0b0 | If PMICFILTR_EL0.P == 0, then this bit has no effect on filtering of instructions. If PMICFILTR_EL0.P == 1, then instructions in Realm EL1 are not counted. |
0b1 | If PMICFILTR_EL0.P == 0, then instructions in Realm EL1 are not counted. If PMICFILTR_EL0.P == 1, then this bit has no effect on filtering of instructions. |
The reset behavior of this field is:
Reserved, RES0.
Realm EL0 filtering. Controls counting instructions in Realm EL0. If PMICFILTR_EL0.RLU is equal to PMICFILTR_EL0.U, then instructions in Realm EL0 are counted. Otherwise, instructions in Realm EL0 are not counted.
RLU | Meaning |
---|---|
0b0 | If PMICFILTR_EL0.U == 0, then this bit has no effect on filtering of instructions. If PMICFILTR_EL0.U == 1, then instructions in Realm EL0 are not counted. |
0b1 | If PMICFILTR_EL0.U == 0, then instructions in Realm EL0 are not counted. If PMICFILTR_EL0.U == 1, then this bit has no effect on filtering of instructions. |
The reset behavior of this field is:
Reserved, RES0.
Realm EL2 filtering. Controls counting instructions in Realm EL2. If PMICFILTR_EL0.RLH is not equal to PMICFILTR_EL0.NSH, then instructions in Realm EL2 are counted. Otherwise, instructions in Realm EL2 are not counted.
RLH | Meaning |
---|---|
0b0 | If PMICFILTR_EL0.NSH == 0, then instructions in Realm EL2 are not counted. If PMICFILTR_EL0.NSH == 1, then this bit has no effect on filtering of instructions. |
0b1 | If PMICFILTR_EL0.NSH == 0, then this bit has no effect on filtering of instructions. If PMICFILTR_EL0.NSH == 1, then instructions in Realm EL2 are not counted. |
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Event to count.
Reads as 0x0008.
Access to this field is RO.
Accesses to this register use the following encodings in the external debug interface:
PMICFILTR_EL0 can be accessed through the PMU block as follows:
Frame | Offset |
---|---|
PMU | 0x480 |
30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f
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