HDFGRTR2_EL2, Hypervisor Debug Fine-Grained Read Trap Register 2

The HDFGRTR2_EL2 characteristics are:

Purpose

Provides controls for traps of MRS and MRC reads of debug, trace, PMU, and Statistical Profiling System registers.

Configuration

This register is present only when FEAT_FGT2 is implemented. Otherwise, direct accesses to HDFGRTR2_EL2 are UNDEFINED.

Attributes

HDFGRTR2_EL2 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0nTRCITECR_EL1nPMSDSFR_EL1nSPMDEVAFF_EL1nSPMIDnSPMSCR_EL1nSPMACCESSR_EL1nSPMCR_EL0nSPMOVSnSPMINTENnSPMCNTENnSPMSELR_EL0nSPMEVTYPERn_EL0nSPMEVCNTRn_EL0nPMSSCR_EL1nPMSSDATAnMDSELR_EL1nPMUACR_EL1nPMICFILTR_EL0nPMICNTR_EL0nPMIAR_EL1nPMECR_EL1

Bits [63:21]

Reserved, RES0.

nTRCITECR_EL1, bit [20]
When FEAT_ITE is implemented:

Trap MRS reads of TRCITECR_EL1 at EL1 using AArch64 to EL2.

nTRCITECR_EL1Meaning
0b0

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MRS reads of TRCITECR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.

0b1

MRS reads of TRCITECR_EL1 are not trapped by this mechanism.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nPMSDSFR_EL1, bit [19]
When FEAT_SPE_FDS is implemented:

Trap MRS reads of PMSDSFR_EL1 at EL1 using AArch64 to EL2.

nPMSDSFR_EL1Meaning
0b0

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MRS reads of PMSDSFR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.

0b1

MRS reads of PMSDSFR_EL1 are not trapped by this mechanism.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nSPMDEVAFF_EL1, bit [18]
When FEAT_SPMU is implemented:

Trap MRS reads of SPMDEVAFF_EL1 at EL1 using AArch64 to EL2.

nSPMDEVAFF_EL1Meaning
0b0

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MRS reads of SPMDEVAFF_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.

0b1

MRS reads of SPMDEVAFF_EL1 are not trapped by this mechanism.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nSPMID, bit [17]
When FEAT_SPMU is implemented:

Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2:

nSPMIDMeaning
0b0

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MRS reads at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.

0b1

MRS reads of the System registers listed above are not trapped by this mechanism.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nSPMSCR_EL1, bit [16]
When FEAT_SPMU is implemented:

Trap MRS reads of SPMSCR_EL1 at EL1 using AArch64 to EL2.

nSPMSCR_EL1Meaning
0b0

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MRS reads of SPMSCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.

0b1

MRS reads of SPMSCR_EL1 are not trapped by this mechanism.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nSPMACCESSR_EL1, bit [15]
When FEAT_SPMU is implemented:

Trap MRS reads of SPMACCESSR_EL1 at EL1 using AArch64 to EL2.

nSPMACCESSR_EL1Meaning
0b0

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MRS reads of SPMACCESSR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.

0b1

MRS reads of SPMACCESSR_EL1 are not trapped by this mechanism.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nSPMCR_EL0, bit [14]
When FEAT_SPMU is implemented:

Trap MRS reads of SPMCR_EL0 at EL1 and EL0 using AArch64 to EL2.

nSPMCR_EL0Meaning
0b0

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MRS reads of SPMCR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.

0b1

MRS reads of SPMCR_EL0 are not trapped by this mechanism.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nSPMOVS, bit [13]
When FEAT_SPMU is implemented:

Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 and EL0 using AArch64 of any of the following AArch64 System registers to EL2:

nSPMOVSMeaning
0b0

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MRS reads at EL1 and EL0 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.

0b1

MRS reads of the System registers listed above are not trapped by this mechanism.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nSPMINTEN, bit [12]
When FEAT_SPMU is implemented:

Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2:

nSPMINTENMeaning
0b0

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MRS reads at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.

0b1

MRS reads of the System registers listed above are not trapped by this mechanism.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nSPMCNTEN, bit [11]
When FEAT_SPMU is implemented:

Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 and EL0 using AArch64 of any of the following AArch64 System registers to EL2:

nSPMCNTENMeaning
0b0

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MRS reads at EL1 and EL0 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.

0b1

MRS reads of the System registers listed above are not trapped by this mechanism.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nSPMSELR_EL0, bit [10]
When FEAT_SPMU is implemented:

Trap MRS reads of SPMSELR_EL0 at EL1 and EL0 using AArch64 to EL2.

nSPMSELR_EL0Meaning
0b0

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MRS reads of SPMSELR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.

0b1

MRS reads of SPMSELR_EL0 are not trapped by this mechanism.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nSPMEVTYPERn_EL0, bit [9]
When FEAT_SPMU is implemented:

Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 and EL0 using AArch64 of any of the following AArch64 System registers to EL2:

nSPMEVTYPERn_EL0Meaning
0b0

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MRS reads at EL1 and EL0 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.

0b1

MRS reads of the System registers listed above are not trapped by this mechanism.

Regardless of the value of this bit, if event counter n is not implemented, a read of SPMEVTYPER<n>_EL0, SPMEVFILTR<n>_EL0, or SPMEVFILT2R<n>_EL0 is UNDEFINED.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nSPMEVCNTRn_EL0, bit [8]
When FEAT_SPMU is implemented:

Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 and EL0 using AArch64 of any of the following AArch64 System registers to EL2: SPMEVCNTR<n>_EL0.

nSPMEVCNTRn_EL0Meaning
0b0

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MRS reads at EL1 and EL0 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.

0b1

MRS reads of the System registers listed above are not trapped by this mechanism.

Regardless of the value of this bit, if event counter n is not implemented, a read of SPMEVCNTR<n>_EL0 is UNDEFINED.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nPMSSCR_EL1, bit [7]
When FEAT_PMUv3_SS is implemented:

Trap MRS reads of PMSSCR_EL1 at EL1 using AArch64 to EL2.

nPMSSCR_EL1Meaning
0b0

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MRS reads of PMSSCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.

0b1

MRS reads of PMSSCR_EL1 are not trapped by this mechanism.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nPMSSDATA, bit [6]
When FEAT_PMUv3_SS is implemented:

Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2:

nPMSSDATAMeaning
0b0

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MRS reads at EL1 using AArch64 of any of the System registers listed above are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.

0b1

MRS reads of the System registers listed above are not trapped by this mechanism.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nMDSELR_EL1, bit [5]
When FEAT_Debugv8p9 is implemented:

Trap MRS reads of MDSELR_EL1 at EL1 using AArch64 to EL2.

nMDSELR_EL1Meaning
0b0

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MRS reads of MDSELR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.

0b1

MRS reads of MDSELR_EL1 are not trapped by this mechanism.

It is IMPLEMENTATION DEFINED whether this field is implemented or is RES0 when 16 or fewer breakpoints are implemented, 16 or fewer watchpoints are implemented, and MDSELR_EL1 is implemented as RAZ/WI.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nPMUACR_EL1, bit [4]
When FEAT_PMUv3p9 is implemented:

Trap MRS reads of PMUACR_EL1 at EL1 using AArch64 to EL2.

nPMUACR_EL1Meaning
0b0

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MRS reads of PMUACR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.

0b1

MRS reads of PMUACR_EL1 are not trapped by this mechanism.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nPMICFILTR_EL0, bit [3]
When FEAT_PMUv3_ICNTR is implemented:

Trap MRS reads of PMICFILTR_EL0 at EL1 and EL0 using AArch64 to EL2.

nPMICFILTR_EL0Meaning
0b0

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MRS reads of PMICFILTR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.

0b1

MRS reads of PMICFILTR_EL0 are not trapped by this mechanism.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nPMICNTR_EL0, bit [2]
When FEAT_PMUv3_ICNTR is implemented:

Trap MRS reads of PMICNTR_EL0 at EL1 and EL0 using AArch64 to EL2.

nPMICNTR_EL0Meaning
0b0

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H, TGE} != {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MRS reads of PMICNTR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.

0b1

MRS reads of PMICNTR_EL0 are not trapped by this mechanism.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nPMIAR_EL1, bit [1]
When FEAT_SEBEP is implemented:

Trap MRS reads of PMIAR_EL1 at EL1 using AArch64 to EL2.

nPMIAR_EL1Meaning
0b0

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MRS reads of PMIAR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.

0b1

MRS reads of PMIAR_EL1 are not trapped by this mechanism.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nPMECR_EL1, bit [0]
When FEAT_EBEP is implemented:

Trap MRS reads of PMECR_EL1 at EL1 using AArch64 to EL2.

nPMECR_EL1Meaning
0b0

If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn2 == 1, then MRS reads of PMECR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.

0b1

MRS reads of PMECR_EL1 are not trapped by this mechanism.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Accessing HDFGRTR2_EL2

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, HDFGRTR2_EL2

op0op1CRnCRmop2
0b110b1000b00110b00010b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then X[t, 64] = NVMem[0x1A0]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then X[t, 64] = HDFGRTR2_EL2; elsif PSTATE.EL == EL3 then X[t, 64] = HDFGRTR2_EL2;

MSR HDFGRTR2_EL2, <Xt>

op0op1CRnCRmop2
0b110b1000b00110b00010b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then NVMem[0x1A0] = X[t, 64]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then HDFGRTR2_EL2 = X[t, 64]; elsif PSTATE.EL == EL3 then HDFGRTR2_EL2 = X[t, 64];


30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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