SPMEVFILTR<n>_EL0, Additional System Performance Monitors Event Filter Control Register, n = 0 - 63

The SPMEVFILTR<n>_EL0 characteristics are:

Purpose

For System Performance Monitors requiring additional event selection controls.

Configuration

This register is present only when FEAT_SPMU is implemented. Otherwise, direct accesses to SPMEVFILTR<n>_EL0 are UNDEFINED.

Attributes

SPMEVFILTR<n>_EL0 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
IMPLEMENTATION DEFINED
IMPLEMENTATION DEFINED

IMPLEMENTATION DEFINED, bits [63:0]

IMPLEMENTATION DEFINED.

Accessing SPMEVFILTR<n>_EL0

To access SPMEVFILTR<n>_EL0 for System PMU <s>, set SPMSELR_EL0.SYSPMUSEL to s and SPMSELR_EL0.BANK to n[5:4].

SPMEVFILTR<n>_EL0 reads-as-zero and ignores writes if event counter <n> is not implemented.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, SPMEVFILTR<m>_EL0 ; Where m = 0-15

op0op1CRnCRmop2
0b100b0110b11100b010:m[3]m[2:0]

integer m = UInt(CRm<0>:op2<2:0>); if PSTATE.EL == EL0 then X[t, 64] = SPMEVFILTR_EL0[UInt(SPMSELR_EL0.SYSPMUSEL), m]; elsif PSTATE.EL == EL1 then X[t, 64] = SPMEVFILTR_EL0[UInt(SPMSELR_EL0.SYSPMUSEL), m]; elsif PSTATE.EL == EL2 then X[t, 64] = SPMEVFILTR_EL0[UInt(SPMSELR_EL0.SYSPMUSEL), m]; elsif PSTATE.EL == EL3 then X[t, 64] = SPMEVFILTR_EL0[UInt(SPMSELR_EL0.SYSPMUSEL), m];

MSR SPMEVFILTR<m>_EL0, <Xt> ; Where m = 0-15

op0op1CRnCRmop2
0b100b0110b11100b010:m[3]m[2:0]

integer m = UInt(CRm<0>:op2<2:0>); if PSTATE.EL == EL0 then SPMEVFILTR_EL0[UInt(SPMSELR_EL0.SYSPMUSEL), m] = X[t, 64]; elsif PSTATE.EL == EL1 then SPMEVFILTR_EL0[UInt(SPMSELR_EL0.SYSPMUSEL), m] = X[t, 64]; elsif PSTATE.EL == EL2 then SPMEVFILTR_EL0[UInt(SPMSELR_EL0.SYSPMUSEL), m] = X[t, 64]; elsif PSTATE.EL == EL3 then SPMEVFILTR_EL0[UInt(SPMSELR_EL0.SYSPMUSEL), m] = X[t, 64];


30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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