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PMEVCNTSVR<n>_EL1, Performance Monitors Event Count Saved Value Register <n>, n = 0 - 30

The PMEVCNTSVR<n>_EL1 characteristics are:

Purpose

Captures the PMU Event counter <n>, PMU.PMEVCNTR<n>_EL0.

Configuration

External register PMEVCNTSVR<n>_EL1 bits [63:0] are architecturally mapped to AArch64 System register PMEVCNTSVR<n>_EL1[63:0].

This register is present only when FEAT_PMUv3_SS is implemented. Otherwise, direct accesses to PMEVCNTSVR<n>_EL1 are RES0.

PMEVCNTSVR<n>_EL1 is in the Core power domain.

If event counter n is not implemented:

Attributes

PMEVCNTSVR<n>_EL1 is a 64-bit register.

This register is part of the PMU block.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
EVCNT
EVCNT

EVCNT, bits [63:0]

Sampled Event Count. The value of PMU.PMEVCNTR<n>_EL0 at the last Capture event.

The reset behavior of this field is:

Accessing PMEVCNTSVR<n>_EL1

Accesses to this register use the following encodings in the external debug interface:

BlockAccess at address 0x600 + (8 * n)

PMEVCNTSVR<n>_EL1 can be accessed through the PMU block as follows:

FrameOffset
PMU0x600 + (8 * n)

30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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