(old) htmldiff from-(new)

PMMIR, Performance Monitors Machine Identification Register

The PMMIR characteristics are:

Purpose

Describes Performance Monitors parameters specific to the implementation.

Configuration

This register is present only when FEAT_PMUv3_EXT is implemented and FEAT_PMUv3p4 is implemented. Otherwise, direct accesses to PMMIR are RES0.

PMMIR is in the Core power domain.

This register is present only when FEAT_PMUv3p4 is implemented. Otherwise, direct accesses to PMMIR are RES0.

Attributes

PMMIR is a: 32-bit register.

This register is part of the PMU block.

Field descriptions

When FEAT_PMUv3_EXT64 is implemented:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0EDGETHWIDTHBUS_WIDTHBUS_SLOTSSLOTS
313029282726252423222120191817161514131211109876543210
RES0THWIDTHBUS_WIDTHBUS_SLOTSSLOTS

Bits [6331:2824]

Reserved, RES0.

EDGE, bits [27:24]

PMU event edge detection. Indicates implementation of the FEAT_PMUv3_EDGE feature.

EDGEMeaning
0b0000

FEAT_PMUv3_EDGE is not implemented.

0b0001

FEAT_PMUv3_EDGE is implemented.

All other values are reserved.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

THWIDTH, bits [23:20]

PMEVTYPER<n>_EL0PMU.PMEVTYPER<n>..TH width. Indicates implementation of the FEAT_PMUv3_TH feature, and, if implemented, the size of the PMEVTYPER<n>_EL0 feature, and, if implemented, the size of the PMU.PMEVTYPER<n>..TH field.

THWIDTHMeaning
0b0000

FEAT_PMUv3_TH is not implemented.

0b0001

1 bit. PMU.PMEVTYPER<n>.TH[11:1] are PMEVTYPER<n>_EL0.TH[11:1] are RES0.

0b0010

2 bits. PMU.PMEVTYPER<n>.TH[11:2] are PMEVTYPER<n>_EL0.TH[11:2] are RES0.

0b0011

3 bits. PMU.PMEVTYPER<n>.TH[11:3] are PMEVTYPER<n>_EL0.TH[11:3] are RES0.

0b0100

4 bits. PMU.PMEVTYPER<n>.TH[11:4] are PMEVTYPER<n>_EL0.TH[11:4] are RES0.

0b0101

5 bits. PMU.PMEVTYPER<n>.TH[11:5] are PMEVTYPER<n>_EL0.TH[11:5] are RES0.

0b0110

6 bits. PMU.PMEVTYPER<n>.TH[11:6] are PMEVTYPER<n>_EL0.TH[11:6] are RES0.

0b0111

7 bits. PMU.PMEVYPETR<n>.TH[11:7] are PMEVTYPER<n>_EL0.TH[11:7] are RES0.

0b1000

8 bits. PMU.PMEVTYPER<n>.TH[11:8] are PMEVTYPER<n>_EL0.TH[11:8] are RES0.

0b1001

9 bits. PMU.PMEVTYPER<n>.TH[11:9] are PMEVTYPER<n>_EL0.TH[11:9] are RES0.

0b1010

10 bits. PMU.PMEVTYPER<n>.TH[11:10] are PMEVTYPER<n>_EL0.TH[11:10] are RES0.

0b1011

11 bits. PMU.PMEVTYPER<n>.TH[11] is PMEVTYPER<n>_EL0.TH[11] is RES0.

0b1100

12 bits.

All other values are reserved.

If FEAT_PMUv3_TH is not implemented, this field is zero.

Otherwise, the largest value that can be written to PMU.PMEVTYPER<n>.TH is 2PMEVTYPER<n>_EL0.TH is 2(PMMIR.THWIDTH) minus one.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

BUS_WIDTH, bits [19:16]

Bus width. Indicates the number of bytes each BUS_ACCESS event relates to. Encoded as Log2(number of bytes), plus one.

BUS_WIDTHMeaning
0b0000

The information is not available.

0b0011

Four bytes.

0b0100

8 bytes.

0b0101

16 bytes.

0b0110

32 bytes.

0b0111

64 bytes.

0b1000

128 bytes.

0b1001

256 bytes.

0b1010

512 bytes.

0b1011

1024 bytes.

0b1100

2048 bytes.

All other values are reserved.

Each transfer is up to this number of bytes. An access might be smaller than the bus width.

When this field is nonzero, each access counted by BUS_ACCESS is at most BUS_WIDTH bytes. An implementation might treat a wide bus as multiple narrower buses, such that a wide access on the bus increments the BUS_ACCESS counter by more than one.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

BUS_SLOTS, bits [15:8]

Bus count. The largest value by which the BUS_ACCESS event might increment in a single BUS_CYCLES cycle.

When this field is nonzero, the largest value by which the BUS_ACCESS event might increment in a single BUS_CYCLES cycle is BUS_SLOTS.

If the bus count information is not available, this field will read as zero.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

SLOTS, bits [7:0]

Operation width. The largest value by which the STALL_SLOT event might increment by in a single cycle. If the STALL_SLOT event is not implemented, this field might read as zero.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Accessing PMMIR

If the Core power domain is off or in a low-power state, access on this interface returns an Error.

PMMIR can be accessed through the external debug interface:

Otherwise:

313029282726252423222120191817161514131211109876543210
RES0EDGETHWIDTHBUS_WIDTHBUS_SLOTSSLOTS
ComponentOffsetInstance
PMU0xE40PMMIR

This interface is accessible as follows:

Bits [31:28]

Reserved, RES0.

EDGE, bits [27:24]

PMU event edge detection. Indicates implementation of the FEAT_PMUv3_EDGE feature.

EDGEMeaning
0b0000

FEAT_PMUv3_EDGE is not implemented.

0b0001

FEAT_PMUv3_EDGE is implemented.

All other values are reserved.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

THWIDTH, bits [23:20]

PMU.PMEVTYPER<n>.TH width. Indicates implementation of the FEAT_PMUv3_TH feature, and, if implemented, the size of the PMU.PMEVTYPER<n>.TH field.

THWIDTHMeaning
0b0000

FEAT_PMUv3_TH is not implemented.

0b0001

1 bit. PMU.PMEVTYPER<n>.TH[11:1] are RES0.

0b0010

2 bits. PMU.PMEVTYPER<n>.TH[11:2] are RES0.

0b0011

3 bits. PMU.PMEVTYPER<n>.TH[11:3] are RES0.

0b0100

4 bits. PMU.PMEVTYPER<n>.TH[11:4] are RES0.

0b0101

5 bits. PMU.PMEVTYPER<n>.TH[11:5] are RES0.

0b0110

6 bits. PMU.PMEVTYPER<n>.TH[11:6] are RES0.

0b0111

7 bits. PMU.PMEVYPETR<n>.TH[11:7] are RES0.

0b1000

8 bits. PMU.PMEVTYPER<n>.TH[11:8] are RES0.

0b1001

9 bits. PMU.PMEVTYPER<n>.TH[11:9] are RES0.

0b1010

10 bits. PMU.PMEVTYPER<n>.TH[11:10] are RES0.

0b1011

11 bits. PMU.PMEVTYPER<n>.TH[11] is RES0.

0b1100

12 bits.

All other values are reserved.

If FEAT_PMUv3_TH is not implemented, this field is zero.

Otherwise, the largest value that can be written to PMU.PMEVTYPER<n>.TH is 2(PMMIR.THWIDTH) minus one.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

BUS_WIDTH, bits [19:16]

Bus width. Indicates the number of bytes each BUS_ACCESS event relates to. Encoded as Log2(number of bytes), plus one.

BUS_WIDTHMeaning
0b0000

The information is not available.

0b0011

Four bytes.

0b0100

8 bytes.

0b0101

16 bytes.

0b0110

32 bytes.

0b0111

64 bytes.

0b1000

128 bytes.

0b1001

256 bytes.

0b1010

512 bytes.

0b1011

1024 bytes.

0b1100

2048 bytes.

All other values are reserved.

Each transfer is up to this number of bytes. An access might be smaller than the bus width.

When this field is nonzero, each access counted by BUS_ACCESS is at most BUS_WIDTH bytes. An implementation might treat a wide bus as multiple narrower buses, such that a wide access on the bus increments the BUS_ACCESS counter by more than one.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

BUS_SLOTS, bits [15:8]

Bus count. The largest value by which the BUS_ACCESS event might increment in a single BUS_CYCLES cycle.

When this field is nonzero, the largest value by which the BUS_ACCESS event might increment in a single BUS_CYCLES cycle is BUS_SLOTS.

If the bus count information is not available, this field will read as zero.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

SLOTS, bits [7:0]

Operation width. The largest value by which the STALL_SLOT event might increment in a single cycle. If the STALL_SLOT event is not implemented, this field might read as zero.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Accessing PMMIR

If the Core power domain is off or in a low-power state, access on this interface returns an Error.

Accesses to this register use the following encodings in the external debug interface:

BlockAccess at address 0xE40

PMMIR can be accessed through the PMU block as follows:

FrameOffset
PMU0xE40

3005/0907/2022 1517:5708; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96fb0421fa9a8865165f9b91af9b4a566111f866305

Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

(old) htmldiff from-(new)