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SPMSELR_EL0, System Performance Monitors Select Register

The SPMSELR_EL0 characteristics are:

Purpose

Selects the System PMU and event counter registers to access.

Configuration

This register is present only when FEAT_SPMU is implemented. Otherwise, direct accesses to SPMSELR_EL0 are UNDEFINED.

Attributes

SPMSELR_EL0 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0SYSPMUSELRES0BANK

Bits [63:10]

Reserved, RES0.

SYSPMUSEL, bits [9:4]

System PMU Select. Selects a System PMU <s> to access.

Values 0x20 to 0x3F are reserved.

The reset behavior of this field is:

Bits [3:2]

Reserved, RES0.

BANK, bits [1:0]

System PMU bank access control. Selects a bank of 16 System PMU event counters and related controls to access.

BANKMeaning
0b00

Select event counters 0 to 15.

0b01

Select event counters 16 to 31.

0b10

Select event counters 32 to 47.

0b11

Select event counters 48 to 63.

The reset behavior of this field is:

Accessing SPMSELR_EL0

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, SPMSELR_EL0

op0op1CRnCRmop2
0b100b0110b10010b11000b101

if PSTATE.EL == EL0 then X[t, 64] = SPMSELR_EL0; elsif PSTATE.EL == EL1 then X[t, 64] = SPMSELR_EL0; elsif PSTATE.EL == EL2 then X[t, 64] = SPMSELR_EL0; elsif PSTATE.EL == EL3 then X[t, 64] = SPMSELR_EL0;

MSR SPMSELR_EL0, <Xt>

op0op1CRnCRmop2
0b100b0110b10010b11000b101

if PSTATE.EL == EL0 then SPMSELR_EL0 = X[t, 64]; elsif PSTATE.EL == EL1 then SPMSELR_EL0 = X[t, 64]; elsif PSTATE.EL == EL2 then SPMSELR_EL0 = X[t, 64]; elsif PSTATE.EL == EL3 then SPMSELR_EL0 = X[t, 64];


30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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