The PMEVTYPER<n>_EL0 characteristics are:
Configures event counter <n>, where <n> is 0 to 30.
External register PMEVTYPER<n>_EL0 bits [63:0] are architecturally mapped to AArch64 System register PMEVTYPER<n>_EL0[63:0].
External register PMEVTYPER<n>_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMEVTYPER<n>[31:0].
This register is present only when FEAT_PMUv3_EXT is implemented. Otherwise, direct accesses to PMEVTYPER<n>_EL0 are RES0.
PMEVTYPER<n>_EL0 is in the Core power domain.
If event counter n is not implemented:
PMEVTYPER<n>_EL0 is a 64-bit register.
This register is part of the PMU block.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TC | TE | RES0 | SYNC | RES0 | TH | ||||||||||||||||||||||||||
P | U | NSK | NSU | NSH | M | MT | SH | T | RLK | RLU | RLH | RES0 | evtCount[15:10] | evtCount[9:0] |
Threshold Control.
Defines the threshold function. In the description of this field:
Comparisons treat VB and TH as unsigned integer values.
TC | Meaning |
---|---|
0b001 |
Equal to not-equal. The counter increments by 1 on each processor cycle when VB is not equal to TH and VB was equal to TH on the previous processor cycle. |
0b010 | Equal to/from not-equal. The counter increments by 1 on each processor cycle when either:
|
0b011 |
Not-equal to equal. The counter increments by 1 on each processor cycle when VB is equal to TH and VB was not equal to TH on the previous processor cycle. |
0b101 |
Less-than to greater-than-or-equal. The counter increments by 1 on each processor cycle when VB is greater than or equal to TH and VB was less than TH on the previous processor cycle. |
0b110 | Less-than to/from greater-than-or-equal. The counter increments by 1 on each processor cycle when either:
|
0b111 |
Greater-than-or-equal to less-than. The counter increments by 1 on each processor cycle when VB is less than TH and VB was greater than or equal to TH on the previous processor cycle. |
All other values are reserved.
The reset behavior of this field is:
Threshold Control.
Defines the threshold function. In the description of this field:
Comparisons treat VB and TH as unsigned integer values.
TC | Meaning |
---|---|
0b000 |
Not-equal. The counter increments by VB on each processor cycle when VB is not equal to TH. If TH is zero, the threshold function is disabled. |
0b001 |
Not-equal, count. The counter increments by 1 on each processor cycle when VB is not equal to TH. |
0b010 |
Equals. The counter increments by VB on each processor cycle when VB is equal to TH. |
0b011 |
Equals, count. The counter increments by 1 on each processor cycle when VB is equal to TH. |
0b100 |
Greater-than-or-equal. The counter increments by VB on each processor cycle when VB is greater than or equal to TH. |
0b101 |
Greater-than-or-equal, count. The counter increments by 1 on each processor cycle when VB is greater than or equal to TH. |
0b110 |
Less-than. The counter increments by VB on each processor cycle when VB is less than TH. |
0b111 |
Less-than, count. The counter increments by 1 on each processor cycle when VB is less than TH. |
The reset behavior of this field is:
Reserved, RES0.
Threshold Control.
Defines the threshold function. In the description of this field:
Comparisons treat VB and TH as unsigned integer values.
Threshold Edge. Enables the edge condition. When PMEVTYPER<n>.TE is 1, the event counter increments on cycles when the result of the threshold condition changes. See PMEVTYPER<n>.TC for more information.
TE | Meaning |
---|---|
0b0 |
Threshold edge condition disabled. |
0b1 |
Threshold edge condition enabled. |
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Synchronous Mode. Controls whether a PMU exception generated by the counter is synchronous or asynchronous.
SYNC | Meaning |
---|---|
0b0 |
Asynchronous PMU exception is enabled. |
0b1 |
Synchronous PMU exception is enabled. |
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Threshold value. Provides the unsigned value for the threshold function defined by PMEVTYPER<n>_EL0.TC.
If PMEVTYPER<n>_EL0.TC is 0b000 and PMEVTYPER<n>_EL0.TH is zero, then the threshold function is disabled.
If PMMIR_EL1.THWIDTH is less than 12, then bits PMEVTYPER<n>_EL0.TH[11:PMMIR_EL1.THWIDTH] are RES0. This accounts for the behavior when writing a value greater-than-or-equal-to 2(PMMIR_EL1.THWIDTH).
The reset behavior of this field is:
Reserved, RES0.
Privileged filtering bit. Controls counting in EL1.
If EL3 is implemented, then counting in Non-secure EL1 is further controlled by the PMEVTYPER<n>_EL0.NSK bit.
If FEAT_RME is implemented, then counting in Realm EL1 is further controlled by the PMEVTYPER<n>_EL0.RLK bit.
P | Meaning |
---|---|
0b0 |
Count events in EL1. |
0b1 |
Do not count events in EL1. |
The reset behavior of this field is:
User filtering bit. Controls counting in EL0.
If EL3 is implemented, then counting in Non-secure EL0 is further controlled by the PMEVTYPER<n>_EL0.NSU bit.
If FEAT_RME is implemented, then counting in Realm EL0 is further controlled by the PMEVTYPER<n>_EL0.RLU bit.
U | Meaning |
---|---|
0b0 |
Count events in EL0. |
0b1 |
Do not count events in EL0. |
The reset behavior of this field is:
Non-secure EL1 (kernel) modes filtering bit. Controls counting in Non-secure EL1.
If the value of this bit is equal to the value of the PMEVTYPER<n>_EL0.P bit, events in Non-secure EL1 are counted.
Otherwise, events in Non-secure EL1 are not counted.
The reset behavior of this field is:
Reserved, RES0.
Non-secure EL0 (Unprivileged) filtering bit. Controls counting in Non-secure EL0.
If the value of this bit is equal to the value of the PMEVTYPER<n>_EL0.U bit, events in Non-secure EL0 are counted.
Otherwise, events in Non-secure EL0 are not counted.
The reset behavior of this field is:
Reserved, RES0.
EL2 (Hypervisor) filtering bit. Controls counting in EL2.
If FEAT_SEL2 and EL3 are implemented, counting in Secure EL2 is further controlled by the PMEVTYPER<n>_EL0.SH bit.
If FEAT_RME is implemented, then counting in Realm EL2 is further controlled by the PMEVTYPER<n>_EL0.RLH bit.
NSH | Meaning |
---|---|
0b0 |
Do not count events in EL2. |
0b1 |
Count events in EL2. |
The reset behavior of this field is:
Reserved, RES0.
EL3 filtering bit.
If the value of this bit is equal to the value of the PMEVTYPER<n>_EL0.P bit, events in EL3 are counted.
Otherwise, events in EL3 are not counted.
Most applications can ignore this field and set its value to 0b0.
This field is not visible in the AArch32 PMEVTYPER<n> System register.
The reset behavior of this field is:
Reserved, RES0.
Multithreading.
MT | Meaning |
---|---|
0b0 |
Count events only on controlling PE. |
0b1 |
Count events from any PE with the same affinity at level 1 and above as this PE. |
The reset behavior of this field is:
Reserved, RES0.
Secure EL2 filtering.
If the value of this bit is not equal to the value of the PMEVTYPER<n>_EL0.NSH bit, events in Secure EL2 are counted.
Otherwise, events in Secure EL2 are not counted.
This field is not visible in the AArch32 PMEVTYPER<n> System register.
The reset behavior of this field is:
Reserved, RES0.
Transactional state filtering bit. Controls counting of Attributable events in Non-transactional state.
T | Meaning |
---|---|
0b0 |
This bit has no effect on the filtering of events. |
0b1 |
Do not count Attributable events in Non-transactional state. |
For each Unattributable event, it is IMPLEMENTATION DEFINED whether the filtering applies.
The reset behavior of this field is:
Reserved, RES0.
Realm EL1 (kernel) filtering bit. Controls counting in Realm EL1.
If the value of this bit is equal to the value of the PMEVTYPER<n>_EL0.P bit, events in Realm EL1 are counted.
Otherwise, events in Realm EL1 are not counted.
The reset behavior of this field is:
Reserved, RES0.
Realm EL0 (unprivileged) filtering bit. Controls counting in Realm EL0.
If the value of this bit is equal to the value of the PMEVTYPER<n>_EL0.U bit, events in Realm EL0 are counted.
Otherwise, events in Realm EL0 are not counted.
The reset behavior of this field is:
Reserved, RES0.
Realm EL2 filtering bit. Controls counting in Realm EL2.
If the value of this bit is not equal to the value of the PMEVTYPER<n>_EL0.NSH bit, events in Realm EL2 are counted.
Otherwise, events in Realm EL2 are not counted.
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Extension to evtCount[9:0]. For more information, see evtCount[9:0].
The reset behavior of this field is:
Reserved, RES0.
Event to count. The event number of the event that is counted by event counter PMU.PMEVCNTR<n>_EL0.
Software must program this field with an event that is supported by the PE being programmed.
The ranges of event numbers allocated to each type of event are shown in 'Allocation of the PMU event number space'.
If FEAT_PMUv3p8 is implemented and PMEVTYPER<n>_EL0.evtCount is programmed to an event that is reserved or not supported by the PE, no events are counted and the value returned by a direct or external read of the PMEVTYPER<n>_EL0.evtCount field is the value written to the field.
Arm recommends this behavior for all implementations of FEAT_PMUv3.
Otherwise, if PMEVTYPER<n>_EL0.evtCount is programmed to an event that is reserved or not supported by the PE, the behavior depends on the value written:
UNPREDICTABLE means the event must not expose privileged information.
The reset behavior of this field is:
If FEAT_PMUv3_TH is implemented, and at least one of FEAT_PMUv3_TH or FEAT_PMUv3p8 is implemented, bits [63:32] of this interface are accessible at offset 0xA00 + (4*n). Otherwise accesses at this offset are IMPLEMENTATION DEFINED.
SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.
Accesses to this register use the following encodings in the external debug interface:
PMEVTYPER<n>_EL0 can be accessed through the PMU block as follows:
Frame | Offset | Range |
---|---|---|
PMU | 0x400 + (4 * n) | 31:0 |
PMEVTYPER<n>_EL0 can be accessed through the PMU block as follows:
Frame | Offset | Range |
---|---|---|
PMU | 0x400 + (8 * n) | 63:0 |
PMEVTYPER<n>_EL0 can be accessed through the PMU block as follows:
Frame | Offset | Range |
---|---|---|
PMU | 0xA00 + (4 * n) | 63:32 |
30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f
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