TRBIDR_EL1, Trace Buffer ID Register

The TRBIDR_EL1 characteristics are:

Purpose

Describes constraints on using the Trace Buffer Unit to an external debugger.

Configuration

This register is present only when FEAT_TRBE is implemented. Otherwise, direct accesses to TRBIDR_EL1 are RES0.

Attributes

TRBIDR_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0RAOPAlign

Bits [63:6]

Reserved, RES0.

Bit [5]

Reserved, RAO.

P, bit [4]

This field reads as an UNKNOWN value.

Align, bits [3:0]

Defines the minimum alignment constraint for writes to TRBPTR_EL1 and TRBTRG_EL1.

AlignMeaning
0b0000

Byte.

0b0001

Halfword.

0b0010

Word.

0b0011

Doubleword.

0b0100

16 bytes.

0b0101

32 bytes.

0b0110

64 bytes.

0b0111

128 bytes.

0b1000

256 bytes.

0b1001

512 bytes.

0b1010

1KB.

0b1011

2KB.

All other values are reserved.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Accessing TRBIDR_EL1

TRBIDR_EL1 can be accessed through the external debug interface:

ComponentOffsetInstance
TRBE0x030TRBIDR_EL1

Accesses to this interface are RO.


30/09/2022 15:58; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.