EDHSR, External Debug Halting Syndrome Register

The EDHSR characteristics are:

Purpose

Holds syndrome information for a debug event.

Configuration

This register is present only when (FEAT_SME is implemented and an implementation implements EDHSR) or FEAT_Debugv8p9 is implemented. Otherwise, direct accesses to EDHSR are RES0.

EDHSR is in the Core power domain.

Attributes

EDHSR is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0WPTWPTVWPFFnPRES0VNCRRES0FnVRES0CMRES0WnRRES0

Bits [63:24]

Reserved, RES0.

WPT, bits [23:18]

Watchpoint number. When EDHSR.WPTV is 1, holds the index of a watchpoint that triggered the Watchpoint debug event.

The reset behavior of this field is:

WPTV, bit [17]

Watchpoint number valid.

WPTVMeaningApplies when
0b0

EDHSR.WPT field is not valid, and holds an UNKNOWN value.

When FEAT_SME is implemented and FEAT_Debugv8p9 is not implemented
0b1

EDHSR.WPT field is valid, and holds the number of a watchpoint that triggered the Watchpoint debug event.

The reset behavior of this field is:

WPF, bit [16]

Watchpoint match might be False.

WPFMeaningApplies when
0b0

The watchpoint matched the original access or set of contiguous accesses.

0b1

The watchpoint matched an access or set of contiguous accesses where the lowest accessed address was rounded down to the nearest multiple of 16 bytes and the highest accessed address was rounded up to the nearest multiple of 16 bytes minus 1, but the watchpoint might not have matched the original address of the access or set of contiguous accesses.

When (FEAT_SVE is implemented and FEAT_Debugv8p9 is implemented) or FEAT_SME is implemented

The reset behavior of this field is:

FnP, bit [15]

EDWAR not Precise.

FnPMeaningApplies when
0b0

If the EDWAR is valid, it holds the virtual address of an access or sequence of contiguous accesses that triggered the Watchpoint debug event.

0b1

If the EDWAR is valid, it holds any virtual address within the smallest implemented translation granule that contains the virtual address of an access or set of contiguous accesses that triggered the Watchpoint debug event.

When (FEAT_SVE is implemented and FEAT_Debugv8p9 is implemented) or FEAT_SME is implemented

The reset behavior of this field is:

Bit [14]

Reserved, RES0.

VNCR, bit [13]
When FEAT_NV2 is implemented and FEAT_Debugv8p9 is implemented:

VNCR_EL2 access. Indicates that the Watchpoint debug event came from use of VNCR_EL2 register by EL1 code.

VNCRMeaning
0b0

The Watchpoint debug event was not generated by the use of VNCR_EL2 by EL1 code.

0b1

The Watchpoint debug event was generated by the use of VNCR_EL2 by EL1 code.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Bits [12:11]

Reserved, RES0.

FnV, bit [10]

EDWAR not Valid.

FnVMeaningApplies when
0b0

EDWAR is valid.

0b1

EDWAR is not valid, and holds an UNKNOWN value.

When (FEAT_SVE is implemented and FEAT_Debugv8p9 is implemented) or FEAT_SME is implemented

The reset behavior of this field is:

Bit [9]

Reserved, RES0.

CM, bit [8]
When FEAT_Debugv8p9 is implemented:

Cache maintenance. Indicates whether the Watchpoint debug event came from a cache maintenance instruction.

CMMeaning
0b0

The Watchpoint debug event was not generated by the execution of one of the System instructions identified in the description of value 1.

0b1

The Watchpoint debug event was generated by the execution of a cache maintenance instruction. The DC ZVA, DC GVA, and DC GZVA instructions are not cache maintenance instructions, and therefore do not cause this bit to be set to 1.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Bit [7]

Reserved, RES0.

WnR, bit [6]
When FEAT_Debugv8p9 is implemented:

Write not Read. Indicates whether the Watchpoint debug event was caused by an instruction writing to a memory location, or by an instruction reading from a memory location.

WnRMeaning
0b0

Watchpoint debug event caused by an instruction reading from a memory location.

0b1

Watchpoint debug event caused by an instruction writing to a memory location.

For Watchpoint debug events on cache maintenance instructions, this bit is set to 1.

For Watchpoint debug events from an atomic instruction, this bit is set to 0 if a read of the location would have generated the Watchpoint debug event, otherwise it is set to 1.

If multiple watchpoints match on the same access, it is UNPREDICTABLE which watchpoint generates the Watchpoint debug event.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Bits [5:0]

Reserved, RES0.

Accessing EDHSR

EDHSR can be accessed through the external debug interface:

ComponentOffsetInstance
Debug0x038EDHSR

This interface is accessible as follows:


30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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