The PMCGCR0 characteristics are:
Encodes the number of PMU.PMEVCNTR<n>_EL0 counters implemented.
This register is present only when FEAT_PMUv3_ICNTR is implemented. Otherwise, direct accesses to PMCGCR0 are RES0.
PMCGCR0 is in the Core power domain.
PMCGCR0 is a 32-bit register.
This register is part of the PMU block.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | CG1NC | CG0NC |
Reserved, RES0.
Number of counters in group 1, which comprises the instruction counter PMICNTR_EL0.
Reads as 0x01.
Access to this field is RO.
Number of counters in group 0, which comprises the event counters PMEVCNTR<n>_EL0 and the cycle counter PMCCNTR_EL0.
This field reads as PMCFGR.N.
Accesses to this register use the following encodings in the external debug interface:
PMCGCR0 can be accessed through the PMU block as follows:
Frame | Offset |
---|---|
PMU | 0xCE0 |
30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f
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