PMSSCR_EL1, Performance Monitors Snapshot Status and Capture Register

The PMSSCR_EL1 characteristics are:

Purpose

Holds status information about the captured counters and provides a mechanism for software to initiate a sample.

Configuration

This register is present only when FEAT_PMUv3_SS is implemented. Otherwise, direct accesses to PMSSCR_EL1 are RES0.

Attributes

PMSSCR_EL1 is a 64-bit register.

This register is part of the PMU block.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0NC
RES0SS

Bits [63:33]

Reserved, RES0.

NC, bit [32]

No Capture. Indicates whether the PMU counters have been captured.

NCMeaning
0b0

PMU counters captured.

0b1

PMU counters not captured.

The reset behavior of this field is:

Bits [31:1]

Reserved, RES0.

SS, bit [0]

Snapshot Capture and Status.

SSMeaning
0b0

On a read: The Capture event has completed.

On a write: Ignored.

0b1

On a read: The Capture event has not completed.

On a write: Initiate a capture immediately.

It is CONSTRAINED UNPREDICTABLE whether a Capture event has completed if this field is modified when the Capture event is ongoing.

Note

If FEAT_Debugv8p4 is implemented, the OPTIONAL Software Lock is not implemented.

The reset behavior of this field is:

Accessing this field has the following behavior:

Accessing PMSSCR_EL1

Accesses to this register use the following encodings in the external debug interface:

BlockAccess at address 0xE30

PMSSCR_EL1 can be accessed through the PMU block as follows:

FrameOffset
PMU0xE30

30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.