PMPCSCTL, PC Sample-based Profiling Control Register

The PMPCSCTL characteristics are:

Purpose

Controls the PC Sample-based Profiling feature.

Configuration

This register is present only when FEAT_PCSRv8p9 is implemented. Otherwise, direct accesses to PMPCSCTL are RES0.

PMPCSCTL is in the Core power domain.

Attributes

PMPCSCTL is a 64-bit register.

This register is part of the PMU block.

Field descriptions

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313029282726252423222120191817161514131211109876543210
RES0
RES0SSRES0IMPEN

Bits [63:5]

Reserved, RES0.

SS, bit [4]
When FEAT_PMUv3_SS is implemented:

Sample on Snapshot.

Controls whether the following registers are sampled on a PMU snapshot Capture event:

PMU.PMCID1SR, PMU.PMCID2SR, and PMU.PMPCSR.

SSMeaning
0b0

Sample on Read.

0b1

Sample on Snapshot.

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Bits [3:2]

Reserved, RES0.

IMP, bit [1]

Profiling enable implemented.

IMPMeaning
0b0

PMPCSCTL.EN reads-as-zero and ignores writes.

0b1

PMPCSCTL.EN is a read-write control bit.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

EN, bit [0]
When PMU.PMPCSCTL.IMP == 1:

PC Sample-based Profiling Enable.

ENMeaning
0b0

PC Sample-based Profiling is suspended.

0b1

PC Sample-based Profiling is active.

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

Accessing PMPCSCTL

Accesses to this register use the following encodings in the external debug interface:

BlockAccess at address 0x230

PMPCSCTL can be accessed through the PMU block as follows:

FrameOffset
PMU0x230

30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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