PMCNTENSET_EL0, Performance Monitors Count Enable Set register

The PMCNTENSET_EL0 characteristics are:

Purpose

Enables the Cycle Count Register, PMU.PMCCNTR_EL0, and any implemented event counters PMU.PMEVCNTR<n>_EL0. Reading this register shows which counters are enabled.

Configuration

External register PMCNTENSET_EL0 bits [31:0] are architecturally mapped to AArch64 System register PMCNTENSET_EL0[31:0].

External register PMCNTENSET_EL0 bits [63:32] are architecturally mapped to AArch64 System register PMCNTENSET_EL0[63:32] when FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented.

External register PMCNTENSET_EL0 bits [31:0] are architecturally mapped to AArch64 System register PMCNTENCLR_EL0[31:0].

External register PMCNTENSET_EL0 bits [63:32] are architecturally mapped to AArch64 System register PMCNTENCLR_EL0[63:32] when FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented.

External register PMCNTENSET_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMCNTENCLR[31:0].

External register PMCNTENSET_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMCNTENSET[31:0].

This register is present only when FEAT_PMUv3_EXT is implemented. Otherwise, direct accesses to PMCNTENSET_EL0 are RES0.

PMCNTENSET_EL0 is in the Core power domain.

Attributes

PMCNTENSET_EL0 is a:

This register is part of the PMU block.

Field descriptions

When FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3p9 is implemented or FEAT_PMUv3_ICNTR is implemented:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0F0
CP30P29P28P27P26P25P24P23P22P21P20P19P18P17P16P15P14P13P12P11P10P9P8P7P6P5P4P3P2P1P0

Bits [63:33]

Reserved, RES0.

F0, bit [32]
When FEAT_PMUv3_ICNTR is implemented:

PMU.PMICNTR_EL0 enable. On writes, allows software to enable PMU.PMICNTR_EL0. On reads, returns the PMU.PMICNTR_EL0 enable status.

F0Meaning
0b0

PMU.PMICNTR_EL0 disabled.

0b1

PMU.PMICNTR_EL0 enabled.

The reset behavior of this field is:

Accessing this field has the following behavior:


Otherwise:

Reserved, RES0.

C, bit [31]

PMU.PMCCNTR_EL0 enable bit. Enables the cycle counter register.

CMeaning
0b0

When read, means the cycle counter is disabled. When written, has no effect.

0b1

When read, means the cycle counter is enabled. When written, enables the cycle counter.

The reset behavior of this field is:

P<n>, bit [n], for n = 30 to 0

Event counter enable bit for PMU.PMEVCNTR<n>_EL0.

If PMU.PMCFGR.N is less than 31, bits [30:PMU.PMCFGR.N] are RAZ/WI.

P<n>Meaning
0b0

When read, means that PMU.PMEVCNTR<n>_EL0 is disabled. When written, has no effect.

0b1

When read, means that PMU.PMEVCNTR<n>_EL0 event counter is enabled. When written, enables PMU.PMEVCNTR<n>_EL0.

The reset behavior of this field is:

Otherwise:

313029282726252423222120191817161514131211109876543210
CP30P29P28P27P26P25P24P23P22P21P20P19P18P17P16P15P14P13P12P11P10P9P8P7P6P5P4P3P2P1P0

C, bit [31]

PMU.PMCCNTR_EL0 enable bit. Enables the cycle counter register.

CMeaning
0b0

When read, means the cycle counter is disabled. When written, has no effect.

0b1

When read, means the cycle counter is enabled. When written, enables the cycle counter.

The reset behavior of this field is:

P<n>, bit [n], for n = 30 to 0

Event counter enable bit for PMU.PMEVCNTR<n>_EL0.

If PMU.PMCFGR.N is less than 31, bits [30:PMU.PMCFGR.N] are RAZ/WI.

P<n>Meaning
0b0

When read, means that PMU.PMEVCNTR<n>_EL0 is disabled. When written, has no effect.

0b1

When read, means that PMU.PMEVCNTR<n>_EL0 event counter is enabled. When written, enables PMU.PMEVCNTR<n>_EL0.

The reset behavior of this field is:

Accessing PMCNTENSET_EL0

Note

SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.

Accesses to this register use the following encodings in the external debug interface:

When FEAT_PMUv3_EXT64 is implemented
BlockAccess at address 0xC00

PMCNTENSET_EL0 can be accessed through the PMU block as follows:

FrameOffset
PMU0xC00

When FEAT_PMUv3_EXT32 is implemented
BlockAccess at address 0xC00

PMCNTENSET_EL0 can be accessed through the PMU block as follows:

FrameOffsetRange
PMU0xC0031:0

When (FEAT_PMUv3_EXT32 is implemented and FEAT_PMUv3p9 is implemented) or FEAT_PMUv3_ICNTR is implemented
BlockAccess at address 0xC04

PMCNTENSET_EL0 can be accessed through the PMU block as follows:

FrameOffsetRange
PMU0xC0463:32

30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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