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PMICNTR_EL0, Performance Monitors Instruction Counter Register

The PMICNTR_EL0 characteristics are:

Purpose

If event counting is not prohibited and the instruction counter is enabled, the counter increments for each architecturally-executed instruction, according to the configuration specified by PMU.PMICFILTR_EL0.

Configuration

External register PMICNTR_EL0 bits [63:0] are architecturally mapped to AArch64 System register PMICNTR_EL0[63:0].

This register is present only when FEAT_PMUv3_ICNTR is implemented. Otherwise, direct accesses to PMICNTR_EL0 are RES0.

PMICNTR_EL0 is in the Core power domain.

Attributes

PMICNTR_EL0 is a 64-bit register.

This register is part of the PMU block.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
ICNT
ICNT

ICNT, bits [63:0]

Instruction Counter.

The reset behavior of this field is:

Accessing PMICNTR_EL0

Accesses to this register use the following encodings in the external debug interface:

BlockAccess at address 0x100

PMICNTR_EL0 can be accessed through the PMU block as follows:

FrameOffset
PMU0x100

30/09/2022 15:57; 21c5a6dd0fdaf10a712e2f2d6fffbdbd66d4d96f

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