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Logical shift left by immediate (predicated).
Shift left by immediate each active element of the source vector, and destructively place the results in the corresponding elements of the source vector. The immediate shift amount is an unsigned value in the range 0 to number of bits per element minus 1. Inactive elements in the destination vector register remain unmodified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | tszh | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | Pg | tszl | imm3 | Zdn |
if !HaveSVE() then UNDEFINED; bits(4) tsize = tszh:tszl; case tsize of when '0000' UNDEFINED; when '0001' esize = 8; when '001x' esize = 16; when '01xx' esize = 32; when '1xxx' esize = 64; integer g = UInt(Pg); integer dn = UInt(Zdn); integer shift = UInt(tsize:imm3) - esize;
<Zdn> | Is the name of the source and destination scalable vector register, encoded in the "Zdn" field. |
<T> |
Is the size specifier,
encoded in
tszh:tszl:
|
<Pg> | Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
<const> | Is the immediate shift amount, in the range 0 to number of bits per element minus 1, encoded in "tsz:imm3". |
CheckSVEEnabled(); integer elements = VL DIV esize; bits(VL) operand1 = Z[dn]; bits(PL) mask = P[g]; bits(VL) result; for e = 0 to elements-1 bits(esize) element1 = Elem[operand1, e, esize]; if ElemP[mask, e, esize] == '1' then Elem[result, e, esize] = LSL(element1, shift); else Elem[result, e, esize] = Elem[operand1, e, esize]; Z[dn] = result;
If PSTATE.DIT is 1:
This instruction might be immediately preceded in program order by a MOVPRFX instruction.instruction Thethat conforms to all of the following requirements, otherwise the behavior of either or both instructions is MOVPRFXunpredictable instruction must conform to all of the following requirements, otherwise the behavior of the:
Internal version only: isa v31.05bv31.04, AdvSIMD v29.02, pseudocode v2019-12_rc3_1v2019-09_rc2_1, sve v2019-12_rc3v2019-09_rc3
; Build timestamp: 2019-12-13T112019-09-27T17:0228
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