1. Introduction

This is the 2019-12 release of the A64 ISA XML for Future Architecture Technologies.

The Proprietary Notice gives details of the terms and conditions under which this package is provided.

2. Contents

3. Release Notes

Change history

This is the A64 ISA XML for Future Architecture Technologies (2019-12).

The following general changes are made:

• The "Operational Information" for the following SVE2 instructions stated that they could be used predictably with both an unpredicated and predicated MOVPRFX instruction. That has been relaxed to require that they are predictable only when preceded by an unpredicated MOVPRFX instruction.
  
  • ADDP, Add pairwise
  • FMINP, Floating-point minimum pairwise
  • FADDP, Floating-point add pairwise
  • FMINNMP, Floating-point minimum number pairwise
  • FMAXP, Floating-point maximum pairwise
  • FMAXNMP, Floating-point maximum number pairwise
  • SMINP, Signed minimum pairwise
  • SMAXP, Signed maximum pairwise
  • UMINP, Unsigned minimum pairwise
  • UMAXP, Unsigned maximum pairwise
• The "Operational Information" for a large number of SVE instructions incorrectly stated that they were affected by PSTATE.DIT. That has been corrected. The changes and changed instructions can be located in the diff PDF.
• The "Operational Information" for the following SVE instructions incorrectly stated that they could be used with a predicated MOVPRFX instruction. That has been corrected to state that they can only be used with an unpredicated MOVPRFX instruction.
  
  • CLASTA (vectors)
  • CLASTB (vectors)
  • COMPACT
  • LASTA (vectors)
  • LASTB (vectors)
  • SPLICE
• The description for Advanced SIMD ZIP1 instruction is corrected to state that it reads from the lower half of two source SIMD & FP registers.
  The description for Advanced SIMD ZIP2 instruction is corrected to state that it reads from the upper half of two source SIMD & FP registers.
• The decode pseudocode for A64 instructions BRK, HLT, BTI, PACIASP, PACIBSP was appearing incorrectly and has been updated to reflect the correct code.
• The pseudocode for the Advanced SIMD UADDLP and SADDLP instructions, whilst previously correct, has been updated to more intuitively describe the UADDLP and SADDLP instructions.
• The text in the "Operational information" section that describes the conditions under which an SVE instruction may be predictably prefixed by a MOVPRFX instruction has been clarified.

The following changes are made to the Shared Pseudocode:

• In functions CheckSVEEnabled(), IsSVEEnabled(), AArch64.IsFPEnabled(), CheckFPAdvSIMDEnabled(), and CheckFPAdvSIMDTrap() checks of the FPEN and ZEN fields in CPACR_EL1, CPTR_EL2, and CPTR_EL3 have been made consistent. In the functions CheckAdvSIMDOrFPEnabled() and AArch32.IsFPEnabled(), the check for CPACR.cp10 Constrained Unpredictable behaviour is moved to the existing case statement.
• Added a definition of the NVMem[] accessors in both the assignment and Non-assignment forms.
• The function AArch64.CheckForERetTrap() had an error in the part of code that describes trap of ERET to EL2 due to fine grained trap controls. This has been corrected.
• The function AArch64.ReportException() now checks the current security state is secure before updating the value of HPFAR_EL2.NS.
• The function SecondStageTranslate() now sets memory attributes to Normal Non-cacheable when HCR_EL2.PTW is 0 and the translation table is in Device memory.
• Fixed check in DebugTargetFrom() function that determines whether debug exceptions should be routed to EL2.
• The functions CombineS1S2Desc() and CombineS1S2AttrHints() are refactored to remove redundancy in the code.
• Corrected the AArch64.TakeException() and AArch64.TakeExceptionInDebugState() functions to read the SCTLR register of the target exception level.
• The values for shareable and outershareable memory attributes have been initialised when apply_forced_writeback is enabled in S2AttrDecode(). Earlier they were not initialised.
• In functions AArch32.BreakpointValueMatch(), AArch64.BreakpointValueMatch(), and CreatePCSample() the checks for HaveVirtHostExt() before using CONTEXTIDR_EL2 are changed to a check for whether CONTEXTIDR_EL2 is implemented.
• The Strip() function is corrected to remove the incorrect trapping of instructions XPACD, XPACI, XPACLRI with the HCR_EL2.API and the SCR_EL3.API control bits.
• The function InterruptPending() now additionally checks for physical and virtual IRQ and FIQ interrupts.
• The function AArch64.TakeException() did not set the correct value of 0b10 (and not 0b01) to SPSR_EL1.M[3:2] when HCR_EL2.{NV2, NV} == {1,1} and an exception is taken from EL1 and taken to EL1.
• With the addition of TTST(Small Page Table) feature, TxSZ can now hold a maximum value of 48, giving a minimum input size of 16. This could lead to more cases which results in the misprogramming of the contiguous bit. One such case is that the given input size is not within the addressable range. This change is checking for the same case dynamically using the new values of TnSZ and input size.
• Bits 60 to 63 of a faulting Virtual Address reported for a Synchronous Tag Check Fail abort written to FAR_EL1, FAR_EL2 or FAR_EL3 are now reported as UNKNOWN.
• Usage of the function SetNotTagCheckedInstruction() is inverted and the function is renamed as SetTagCheckedInstruction().

Known issues

• AArch64 Pseudocode does not describe the configurable delay in the trapping of WFE instructions as defined by the v8.6 TWED feature.
• For the following functions:
  • S2CacheDisabled()
  • S2ConvertAttrsHints()
  Current pseudocode does not consider the effect of HCR_EL2.CD when HCR_EL2.FWB == 1

Potential upcoming changes