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USDOT (vector)

Dot Product vector form with unsigned and signed integers. This instruction performs the dot product of the four unsigned 8-bit integer values in each 32-bit element of the first source register with the four signed 8-bit integer values in the corresponding 32-bit element of the second source register, accumulating the result into the corresponding 32-bit element of the destination register.

From Armv8.2, this is an optional instruction. ID_AA64ISAR0_EL1.I8MM indicates whether this instruction is supported.

Vector
(Armv8.6)

313029282726252423222120191817161514131211109876543210
0Q001110100Rm100111RnRd

Vector

USDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>

if !HaveInt8MatMulExt() then UNDEFINED; integer n = UInt(Rn); integer m = UInt(Rm); integer d = UInt(Rd); integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV 32;

Assembler Symbols

<Vd>

Is the name of the SIMD&FP third source and destination register, encoded in the "Rd" field.

<Ta> Is an arrangement specifier, encoded in Q:
Q<Ta>
02S
14S
<Vn>

Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Tb> Is an arrangement specifier, encoded in Q:
Q<Tb>
08B
116B
<Vm>

Is the name of the second SIMD&FP source register, encoded in the "Rm" field.

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n]; bits(datasize) operand2 = V[m]; bits(datasize) operand3 = V[d]; bits(datasize) result; for e = 0 to elements-1 bits(32) res = Elem[operand3, e, 32]; for b = 0 to 3 integer element1 = UInt(Elem[operand1, 4*e+b, 8]); [operand1, 4 * e + b, 8]); integer element2 = SInt(Elem[operand2, 4*e+b, 8]); [operand2, 4 * e + b, 8]); res = res + element1 * element2; Elem[result, e, 32] = res; V[d] = result;


Internal version only: isa v31.05b, AdvSIMD v29.02, pseudocode v2019-12_rc3_1, sve v2019-12_rc3 ; Build timestamp: 2019-12-13T11:3502

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Confidential.Non-Confidential.

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