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Bitwise exclusive OR of three vectors.
Bitwise exclusive OR the corresponding elements of all three source vectors, and destructively place the results in the corresponding elements of the destination and first source vector. This instruction is unpredicated.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | Zm | 0 | 0 | 1 | 1 | 1 | 0 | Zk | Zdn |
if !HaveSVE2() then UNDEFINED; integer m = UInt(Zm); integer k = UInt(Zk); integer dn = UInt(Zdn);
<Zdn> | Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field. |
<Zm> | Is the name of the second source scalable vector register, encoded in the "Zm" field. |
<Zk> | Is the name of the third source scalable vector register, encoded in the "Zk" field. |
CheckSVEEnabled(); bits(VL) operand1 = Z[dn]; bits(VL) operand2 = Z[m]; bits(VL) operand3 = Z[k]; Z[dn] = operand1 EOR operand2 EOR operand3;
If PSTATE.DIT is 1:
This instruction might be immediately preceded in program order by a MOVPRFX instruction.instruction Thethat conforms to all of the following requirements, otherwise the behavior of either or both instructions is MOVPRFXunpredictable instruction must conform to all of the following requirements, otherwise the behavior of the:
Internal version only: isa v31.05bv31.04, AdvSIMD v29.02, pseudocode v2019-12_rc3_1v2019-09_rc2_1, sve v2019-12_rc3v2019-09_rc3
; Build timestamp: 2019-12-13T112019-09-27T17:0228
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