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Contiguous load and replicate eight halfwords (immediate index).
Load eight contiguous halfwords to elements of a short, 128-bit (quadword) vector from the memory address generated by a 64-bit scalar base address and immediate index that is a multiple of 16 in the range -128 to +112 added to the base address.
Inactive elements will not read Device memory or signal a fault, and are set to zero. The resulting short vector is then replicated to fill the long destination vector. Only the first eight predicate elements are used and higher numbered predicate elements are ignored.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | imm4 | 0 | 0 | 1 | Pg | Rn | Zt |
if !HaveSVE() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer g = UInt(Pg); integer esize = 16; integer offset = SInt(imm4);
<Zt> | Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. |
<Pg> | Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
<Xn|SP> | Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
<imm> | Is the optional signed immediate byte offset, a multiple of 16 in the range -128 to 112, defaulting to 0, encoded in the "imm4" field. |
CheckSVEEnabledCheckSVEEnabled();
();
integer elements = 128 DIV esize;
bits(64) base;
bits(64) addr;
bits(PL) mask = P[g]; // low 16 bits only
bits(128) result;
constant integer mbytes = esize DIV 8;
if n == 31 thenbits(
PL) mask = P[g]; // low 16 bits only
bits(128) result;
constant integer mbytes = esize DIV 8;
if n == 31 then
CheckSPAlignment();
if HaveMTEExt() then() then SetNotTagCheckedInstruction(TRUE);
base = SetTagCheckedInstruction(FALSE);
base = SP[];
else
if HaveMTEExt() then() then SetNotTagCheckedInstruction(FALSE);
base = SetTagCheckedInstruction(TRUE);
base = X[n];
addr = base + offset * 16;
for e = 0 to elements-1
if ElemP[mask, e, esize] == '1' then if
ElemP[mask, e, esize] == '1' then
Elem[result, e, esize] = Mem[addr, mbytes, AccType_NORMAL];
else
Elem[result, e, esize] = Zeros();
addr = addr + mbytes;
Z[t] = addr = addr + mbytes; Z[t] = Replicate(result, VL(result, VL DIV 128);DIV 128);
Internal version only: isa v31.05bv31.04, AdvSIMD v29.02, pseudocode v2019-12_rc3_1v2019-09_rc2_1, sve v2019-12_rc3v2019-09_rc3
; Build timestamp: 2019-12-13T112019-09-27T17:0228
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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