(old) htmldiff from-(new)

SMLSLB (indexed)

Signed multiply-subtract long from accumulator (bottom, indexed).

Multiply the even-numbered signed elements within each 128-bit segment of the first source vector by the specified signed element in the corresponding second source vector segment and destructively subtract from the overlapping double-width elements of the addend vector.

The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment. The index range is from 0 to one less than the number of elements per 128-bit segment, encoded in 2 or 3 bits depending on the size of the element.

It has encodings from 2 classes: 32-bit and 64-bit

32-bit

313029282726252423222120191817161514131211109876543210
01000100101i3hZm1010i3l0ZnZda

32-bit

SMLSLB <Zda>.S, <Zn>.H, <Zm>.H[<imm>]

if !HaveSVE2() then UNDEFINED; integer esize = 16; integer index = UInt(i3h:i3l); integer n = UInt(Zn); integer m = UInt(Zm); integer da = UInt(Zda); integer sel = 0;

64-bit

313029282726252423222120191817161514131211109876543210
01000100111i2hZm1010i2l0ZnZda

64-bit

SMLSLB <Zda>.D, <Zn>.S, <Zm>.S[<imm>]

if !HaveSVE2() then UNDEFINED; integer esize = 32; integer index = UInt(i2h:i2l); integer n = UInt(Zn); integer m = UInt(Zm); integer da = UInt(Zda); integer sel = 0;

Assembler Symbols

<Zda>

Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.

<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zm>

For the 32-bit variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.

For the 64-bit variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.

<imm>

For the 32-bit variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.

For the 64-bit variant: is the element index, in the range 0 to 3, encoded in the "i2h:i2l" fields.

Operation

CheckSVEEnabledCheckSVEEnabled(); integer elements = VL DIV (2 * esize); integer eltspersegment = 128 DIV (2 * esize); bits(VL) operand1 = Z[n]; bits(VL) operand2 = Z[m]; bits(VL) result = Z[da]; for e = 0 to elements-1 integer s = e - e MOD eltspersegment; integer element1 =(); integer elements = VL DIV (2 * esize); integer eltspersegment = 128 DIV (2 * esize); bits(VL) operand1 = Z[n]; bits(VL) operand2 = Z[m]; bits(VL) result = Z[da]; for e = 0 to elements-1 integer s = e - e MOD eltspersegment; integer element1 = SInt(Elem[operand1, 2 * e + sel, esize]); integer element2 = SInt(Elem[operand2, 2 * s + index, esize]); bits(2*esize) product = (element1 * element2)<2*esize-1:0>; integer element3 = SInt(Elem[result, e, 2*esize] =[result, e, 2*esize]); integer res = element3 - element1 * element2; Elem[result, e, 2*esize] = res<2*esize-1:0>; Z[result, e, 2*esize] - product; Z[da] = result;[da] = result;

Operational information

If PSTATE.DIT is 1:

This instruction might be immediately preceded in program order by a MOVPRFX instruction.instruction Thethat conforms to all of the following requirements, otherwise the behavior of either or both instructions is MOVPRFXunpredictable instruction must conform to all of the following requirements, otherwise the behavior of the:

The MOVPRFX and this instruction is unpredictableinstructions that can be used with this instruction are as follows:


Internal version only: isa v31.05bv31.04, AdvSIMD v29.02, pseudocode v2019-12_rc3_1v2019-09_rc2_1, sve v2019-12_rc3v2019-09_rc3 ; Build timestamp: 2019-12-13T112019-09-27T17:0228

Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

(old) htmldiff from-(new)