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Contiguous load three-byte structures to three vectors (immediate index).
Contiguous load three-byte structures, each to the same element number in three vector registers from the memory address generated by a 64-bit scalar base and an immediate index which is a multiple of 3 in the range -24 to 21 that is multiplied by the vector's in-memory size, irrespective of predication,
Each predicate element applies to the same element number in each of the three vector registers, or equivalently to the three consecutive bytes in memory which make up each structure. Inactive elements will not read Device memory or signal a fault, and the corresponding element is set to zero in each of the three destination vector registers.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | imm4 | 1 | 1 | 1 | Pg | Rn | Zt |
if !HaveSVE() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer g = UInt(Pg); integer esize = 8; integer offset = SInt(imm4); integer nreg = 3;
<Zt1> | Is the name of the first scalable vector register to be transferred, encoded in the "Zt" field. |
<Zt2> | Is the name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32. |
<Zt3> | Is the name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32. |
<Pg> | Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
<Xn|SP> | Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
<imm> | Is the optional signed immediate vector offset, a multiple of 3 in the range -24 to 21, defaulting to 0, encoded in the "imm4" field. |
CheckSVEEnabledCheckSVEEnabled();
integer elements = VL DIV esize;
bits(64) base;
bits(64) addr;
bits(PL) mask = P[g];
constant integer mbytes = esize DIV 8;
array [0..2] of bits(VL) values;
if n == 31 then();
integer elements =
VL DIV esize;
bits(64) base;
bits(64) addr;
bits(PL) mask = P[g];
constant integer mbytes = esize DIV 8;
array [0..2] of bits(VL) values;
if n == 31 then
CheckSPAlignment();
if HaveMTEExt() then() then SetNotTagCheckedInstruction(TRUE);
base = SetTagCheckedInstruction(FALSE);
base = SP[];
else
if HaveMTEExt() then() then SetNotTagCheckedInstruction(FALSE);
base = SetTagCheckedInstruction(TRUE);
base = X[n];
addr = base + offset * elements * nreg * mbytes;
for e = 0 to elements-1
for r = 0 to nreg-1
if ElemP[mask, e, esize] == '1' then if
ElemP[mask, e, esize] == '1' then
Elem[values[r], e, esize] = Mem[addr, mbytes, AccType_NORMAL];
else
Elem[values[r], e, esize] = Zeros();
addr = addr + mbytes;
for r = 0 to nreg-1
Z();
addr = addr + mbytes;
for r = 0 to nreg-1
Z[(t+r) MOD 32] = values[r];[(t+r) MOD 32] = values[r];
Internal version only: isa v31.05bv31.04, AdvSIMD v29.02, pseudocode v2019-12_rc3_1v2019-09_rc2_1, sve v2019-12_rc3v2019-09_rc3
; Build timestamp: 2019-12-13T112019-09-27T17:0228
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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