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LD1ROH (scalar plus scalar)

Contiguous load and replicate sixteen halfwords (scalar index).

Load sixteen contiguous halfwords to elements of a 256-bit (octaword) vector from the memory address generated by a 64-bit scalar base address and scalar index which is multiplied by 2 and added to the base address.

Inactive elements will not read Device memory or signal a fault, and are set to zero.

The resulting 256-bit vector is then replicated to fill the destination vector. The instruction requires that the current vector length is at least 256 bits, and if the current vector length is not an integer multiple of 256 bits then the trailing bits in the destination vector are set to zero.

Only the first sixteen predicate elements are used and higher numbered predicate elements are ignored.

ID_AA64ZFR0_EL1.F64MM indicates whether this instruction is implemented.

313029282726252423222120191817161514131211109876543210
10100100101Rm000PgRnZt

SVE

LD1ROH { <Zt>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]

if !HaveSVEFP64MatMulExt() then UNDEFINED; if Rm == '11111' then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer m = UInt(Rm); integer g = UInt(Pg); integer esize = 16;

Assembler Symbols

<Zt>

Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.

<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Xm>

Is the 64-bit name of the general-purpose offset register, encoded in the "Rm" field.

Operation

CheckSVEEnabledCheckSVEEnabled(); if VL < 256 then UNDEFINED; integer elements = 256 DIV esize; bits(64) base; bits(64) addr; bits(PL) mask = P[g]; // low bits only bits(64) offset; bits(256) result; constant integer mbytes = esize DIV 8; (); if VL < 256 then UNDEFINED; integer elements = 256 DIV esize; bits(64) base; bits(64) addr; bits(PL) mask = P[g]; // low bits only bits(64) offset; bits(256) result; constant integer mbytes = esize DIV 8; if HaveMTEExt() then() then SetNotTagCheckedInstruction(FALSE); if n == 31 then SetTagCheckedInstruction(TRUE); if n == 31 then CheckSPAlignment(); base = SP[]; else base = X[n]; offset = X[m]; addr = base + UInt(offset) * mbytes; for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then if ElemP[mask, e, esize] == '1' then Elem[result, e, esize] = Mem[addr, mbytes, AccType_NORMAL]; else Elem[result, e, esize] = Zeros(); addr = addr + mbytes; Z[t] = addr = addr + mbytes; Z[t] = ZeroExtend(Replicate(result, VL DIV 256), VL(result, VL DIV 256), VL););


Internal version only: isa v31.05bv31.04, AdvSIMD v29.02, pseudocode v2019-12_rc3_1v2019-09_rc2_1, sve v2019-12_rc3v2019-09_rc3 ; Build timestamp: 2019-12-13T112019-09-27T17:0228

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