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Signed add and accumulate long pairwise.
Add pairs of adjacent signed integer values and accumulate the results into the overlapping double-width elements of the destination vector.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | size | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | Pg | Zn | Zda |
if !HaveSVE2() then UNDEFINED; if size == '00' then UNDEFINED; integer esize = 8 << UInt(size); integer g = UInt(Pg); integer n = UInt(Zn); integer da = UInt(Zda);
<Zda> | Is the name of the second source and destination scalable vector register, encoded in the "Zda" field. |
<T> |
Is the size specifier,
encoded in
size:
|
<Pg> | Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
<Zn> | Is the name of the first source scalable vector register, encoded in the "Zn" field. |
<Tb> |
Is the size specifier,
encoded in
size:
|
CheckSVEEnabledCheckSVEEnabled();
integer elements = VL DIV esize;
bits(PL) mask = P[g];
bits(VL) operand_acc = Z[da];
bits(VL) operand_src = Z[n];
bits(VL) result;
for e = 0 to elements-1
if ElemP[mask, e, esize] == '0' then();
integer elements =
VL DIV esize;
bits(PL) mask = P[g];
bits(VL) operand_acc = Z[da];
bits(VL) operand_src = Z[n];
bits(VL) result;
for e = 0 to elements-1
if ElemP[mask, e, esize] == '0' then
Elem[result, e, esize] = Elem[operand_acc, e, esize];
else
integer element1 = SInt(Elem[operand_src, 2*e + 0, esize DIV 2]);
integer element2 = SInt(Elem[operand_src, 2*e + 1, esize DIV 2]);
bits(esize) sum = (element1 + element2)<esize-1:0>; integer element3 =
SInt(Elem[result, e, esize] =[operand_acc, e, esize]); Elem[result, e, esize] = (element1 + element2 + element3)<esize-1:0>;
Z[operand_acc, e, esize] + sum;
Z[da] = result;[da] = result;
If PSTATE.DIT is 1:
This instruction might be immediately preceded in program order by a MOVPRFX instruction.instruction Thethat conforms to all of the following requirements, otherwise the behavior of either or both instructions is MOVPRFXunpredictable instruction must conform to all of the following requirements, otherwise the behavior of the:
Internal version only: isa v31.05bv31.04, AdvSIMD v29.02, pseudocode v2019-12_rc3_1v2019-09_rc2_1, sve v2019-12_rc3v2019-09_rc3
; Build timestamp: 2019-12-13T112019-09-27T17:0228
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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