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Load Register (literal) calculates an address from the PC value and an immediate offset, loads a word from memory, and writes it to a register. For information about memory accesses, see Load/Store addressing modes.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | x | 0 | 1 | 1 | 0 | 0 | 0 | imm19 | Rt | ||||||||||||||||||||||
opc |
integer t = UInt(Rt); MemOp memop = MemOp_LOAD; boolean signed = FALSE; integer size; bits(64) offset; case opc of when '00' size = 4; when '01' size = 8; when '10' size = 4; signed = TRUE; when '11' memop = MemOp_PREFETCH; offset = SignExtend(imm19:'00', 64); boolean tag_checked = FALSE;
<Wt> | Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field. |
<Xt> | Is the 64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field. |
<label> | Is the program label from which the data is to be loaded. Its offset from the address of this instruction, in the range +/-1MB, is encoded as "imm19" times 4. |
bits(64) address = PC[] + offset;
bits(size*8) data;
if HaveMTEExt() then() then
SetNotTagCheckedInstruction(!tag_checked);
case memop of
when
SetTagCheckedInstruction(tag_checked);
case memop of
when MemOp_LOAD
data = Mem[address, size, AccType_NORMAL];
if signed then
X[t] = SignExtend(data, 64);
else
X[t] = data;
when MemOp_PREFETCHPrefetch(address, t<4:0>);
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: isa v31.05bv31.04, AdvSIMD v29.02, pseudocode v2019-12_rc3_1v2019-09_rc2_1, sve v2019-12_rc3v2019-09_rc3
; Build timestamp: 2019-12-13T112019-09-27T17:0228
Copyright © 2010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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