XAR

Bitwise exclusive OR and rotate right by immediate.

Bitwise exclusive OR the corresponding elements of the first and second source vectors, then rotate each result element right by an immediate amount. The final results are destructively placed in the corresponding elements of the destination and first source vector. This instruction is unpredicated.

313029282726252423222120191817161514131211109876543210
00000100tszh1tszlimm3001101ZmZdn

SVE2

XAR <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, #<const>

if !HaveSVE2() then UNDEFINED; bits(4) tsize = tszh:tszl; case tsize of when '0000' UNDEFINED; when '0001' esize = 8; when '001x' esize = 16; when '01xx' esize = 32; when '1xxx' esize = 64; integer m = UInt(Zm); integer dn = UInt(Zdn); integer rot = (2 * esize) - UInt(tsize:imm3);

Assembler Symbols

<Zdn>

Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.

<T> Is the size specifier, encoded in tszh:tszl:
tszh tszl <T>
00 00 RESERVED
00 01 B
00 1x H
01 xx S
1x xx D
<Zm>

Is the name of the second source scalable vector register, encoded in the "Zm" field.

<const>

Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tsz:imm3".

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(VL) operand1 = Z[dn]; bits(VL) operand2 = Z[m]; bits(VL) result; for e = 0 to elements-1 bits(esize) element1 = Elem[operand1, e, esize]; bits(esize) element2 = Elem[operand2, e, esize]; Elem[result, e, esize] = ROR(element1 EOR element2, rot); Z[dn] = result;

Operational information

If PSTATE.DIT is 1:

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:


Internal version only: isa v31.05b, AdvSIMD v29.02, pseudocode v2019-12_rc3_1, sve v2019-12_rc3 ; Build timestamp: 2019-12-13T11:02

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