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INSR (scalar)

Insert general-purpose register in shifted vector.

Shift the destination vector left by one element, and then place a copy of the least-significant bits of the general-purpose register in element 0 of the destination vector. This instruction is unpredicated.

313029282726252423222120191817161514131211109876543210
00000101size100100001110RmZdn

SVE

INSR <Zdn>.<T>, <R><m>

if !HaveSVE() then UNDEFINED; integer esize = 8 << UInt(size); integer dn = UInt(Zdn); integer m = UInt(Rm);

Assembler Symbols

<Zdn>

Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.

<T> Is the size specifier, encoded in size:
size<T>
00B
01H
10S
11D
<R> Is a width specifier, encoded in size:
size<R>
01W
x0W
11X
<m>

Is the number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rm" field.

Operation

CheckSVEEnabled(); bits(VL) dest = Z[dn]; bits(esize) src = X[m]; Z[dn] = dest<VL-esize-1:0> : src;

Operational information

If PSTATE.DIT is 1:

This instruction might be immediately preceded in program order by a MOVPRFX instruction.instruction Thethat conforms to all of the following requirements, otherwise the behavior of either or both instructions is MOVPRFXunpredictable instruction must conform to all of the following requirements, otherwise the behavior of the:

The MOVPRFX and this instruction is unpredictableinstructions that can be used with this instruction are as follows:


Internal version only: isa v31.05bv31.04, AdvSIMD v29.02, pseudocode v2019-12_rc3_1v2019-09_rc2_1, sve v2019-12_rc3v2019-09_rc3 ; Build timestamp: 2019-12-13T112019-09-27T17:0228

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