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UADALP

Unsigned add and accumulate long pairwise.

Add pairs of adjacent unsigned integer values and accumulate the results into the overlapping double-width elements of the destination vector.

313029282726252423222120191817161514131211109876543210
01000100size000101101PgZnZda

SVE2

UADALP <Zda>.<T>, <Pg>/M, <Zn>.<Tb>

if !HaveSVE2() then UNDEFINED; if size == '00' then UNDEFINED; integer esize = 8 << UInt(size); integer g = UInt(Pg); integer n = UInt(Zn); integer da = UInt(Zda);

Assembler Symbols

<Zda>

Is the name of the second source and destination scalable vector register, encoded in the "Zda" field.

<T> Is the size specifier, encoded in size:
size<T>
00RESERVED
01H
10S
11D
<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Tb> Is the size specifier, encoded in size:
size<Tb>
00RESERVED
01B
10H
11S

Operation

CheckSVEEnabledCheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(VL) operand_acc = Z[da]; bits(VL) operand_src = Z[n]; bits(VL) result; for e = 0 to elements-1 if ElemP[mask, e, esize] == '0' then(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(VL) operand_acc = Z[da]; bits(VL) operand_src = Z[n]; bits(VL) result; for e = 0 to elements-1 if ElemP[mask, e, esize] == '0' then Elem[result, e, esize] = Elem[operand_acc, e, esize]; else integer element1 = UInt(Elem[operand_src, 2*e + 0, esize DIV 2]); integer element2 = UInt(Elem[operand_src, 2*e + 1, esize DIV 2]); bits(esize) sum = (element1 + element2)<esize-1:0>; integer element3 = UInt(Elem[result, e, esize] =[operand_acc, e, esize]); Elem[result, e, esize] = (element1 + element2 + element3)<esize-1:0>; Z[operand_acc, e, esize] + sum; Z[da] = result;[da] = result;

Operational information

If PSTATE.DIT is 1:

This instruction might be immediately preceded in program order by a MOVPRFX instruction.instruction Thethat conforms to all of the following requirements, otherwise the behavior of either or both instructions is MOVPRFXunpredictable instruction must conform to all of the following requirements, otherwise the behavior of the:

The MOVPRFX and this instruction is unpredictableinstructions that can be used with this instruction are as follows:


Internal version only: isa v31.05bv31.04, AdvSIMD v29.02, pseudocode v2019-12_rc3_1v2019-09_rc2_1, sve v2019-12_rc3v2019-09_rc3 ; Build timestamp: 2019-12-13T112019-09-27T17:0228

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