1. Introduction

This is the 2020-03 release of the A64 ISA XML for Future Architecture Technologies.

The Proprietary Notice gives details of the terms and conditions under which this package is provided.

2. Contents

3. Release Notes

Change history

This is the A64 ISA XML for Future Architecture Technologies (2020-03).

The following general changes are made:

• A64 instruction set Load/store register (register offset) encoding index table improvement.
  The row for x0x has been removed from the Load/store register (register offset) table.
• The descriptions for Atomic instructions added as part of Armv8.1 have been corrected to correctly reflect the instructions that have neither acquire nor release semantics.
• The encodings of the CFP, CPP, and CVP have been corrected to refer to the right SYS alias.

The following changes are made to the Shared Pseudocode:

• The Pseudocode for functions AArch64.ExceptionReturn(), AArch64.TakeException(), AArch64.CheckSystemAccess(), Halt(), MemSingleNF(), AArch64.MemSingle[] and execute Pseudocode for AArch64 barrier instructions are corrected to add the missing HaveTME() guard.
• The Pseudocode function MPAMisVirtual() has been corrected for case when HCR_EL2.E2H is 1.
• Reintroduced minimum Exception level and Security State checks to Pseudocode function CheckSystemAccess.
• Decode Pseudocode for VMSR is updated to explicitly define the Constraint Unpredictable behaviour.
• Pseudocode function S1AttrDecode() simplified the setting of memory attributes for tagged memory.
• In Pseudocode function TakeException, the setting of sync_errors uses target_el.
• Added check for HaveMTEExt to MTE instruction Pseudocode.
• The Pseudocode function AArch64.InstructionAbort() added a check for SCR_EL3.EASE when calculating vect_offset.
• Renamed the Pseudocode functions TagCheckFail to TagCheckFault, ReportTagCheckFail to ReportTagCheckFault, and TagCheckFault to RaiseTagCheckFault.
• In Pseudocode function AArch64.CountEvents when checking EL2 filtering in the non secure case the check is now for NHS == '0'.
• AArch64 Pseudocode function AArch64.HaveFlagManipulateExt() is updated to reflect architectural relaxation where feature ARMv8.4-CONDM is permitted to be built from 8.2.
• Pseudocode function AArch64.FirstStageTranslate() updates InGuardedPage variable to FALSE when Stage 1 translation is disabled.
• Pseudocode function TranslationTableWalk() now considers the case when ARMv8.2-LVA is supported but not implemented.
• In Pseudocode function TranslationTableWalk() checks are added for TCR_EL2.NFD0 and TCR_EL2.NFD1 when the current exception level IsInHost().
• The Pseudocode function CollectContextIDR2 is corrected to return FALSE when either EL2 is not implemented or EL2 is not enabled in the current Security state.
• Pseudocode function CollectPhysicalAddress now also checks for IsSecureEL2Enabled()
• In Pseudocode functions AArch64.ESBOperation and AArch32.ESBOperation the check for masked Physical SError pending is changed to a check for a masked Physical SError pending that can be synchronized by an Error synchronization event.
• In pseudocode function mapvpmw, the call to REM is changed to MOD.
• In Psuedocode function AArch64.TranslationTableWalk(), E0PD checks for use of el rather than PSTATE.EL.
• Execute Pseudocode for AArch64 WFE instruction implements configurable delay on trapping of WFE.
• The Psuedocode functions AllocationTagAccessIsEnabled() and TagCheckFail() check for privileged access and calls to these functions pass an AccType.
• The pseudocode function AArch64.SetExclusiveMonitors now calls AArch64.CheckAlignment to check alignment.
• Pseudocode functions CombineS1S2AttrHints(), S2AttrDecode() and S2ConvertAttrsHints() are updated to correctly describe the effect of HCR_EL2.CD bit. Code in these functions is also refactored around Force-write-back feature description.
• In the Pseudocode function TranslationTableWalk, added check for IMPLEMENTATION DEFINED bits[15:12] of the translation table descriptor to be zero for 64KByte translation granules in implementations that don't have 52 bits of PA.
• Pseudocode function CountEvents() is updated to add check for HaveEL(EL3) before usage of PMEVTYPER.SH.
• Pseudocode function Halt() is corrected to set PSTATE.>SSBS, IT, T< to UNKNOWN, PSTATE.TC0 to 1, and PSTATE.BTYPE to 0.
• In pseudocode functions AArch32.BreakpointValueMatch(), AArch64.BreakpointValueMatch(), and CreatePCSample() the checks for HaveVirtHostExt() before using CONTEXTIDR_EL2 are changed to a check for whether CONTEXTIDR_EL2 is implemented.
• The Pseudocode function CalculateTBI() has been removed and calls to this function are replaced with EffectiveTBI(). AddrTop() has been refactored to use EffectiveTBI().
• Pseudocode function SoftwareStep_SteppedEX() describes that ESR_ELx.EX is UNKNOWN if AArch32 LDREX and LDAEX instruction failed its condition code test.

Known issues

• The Halt() function does not set the EDWAR register on receiving a Watchpoint debug event.
  This will be corrected in a future release.
• The current pseudocode does not clearly identify the address in FAR_ELx on an exception due to a tag check fault caused by a DC ZVA instruction. The pseudocode will be amended to ensure that, on an exception due to a tag check fault caused by a DC ZVA instruction, FAR_ELx for the target exception level contains the lowest address that gave rise to the fault.
• Pseudocode functions CombineS1S2AttrHints(), S2AttrDecode() and S2ConvertAttrsHints() currently do not consider the effect of HCR_EL2.CD when FWB == 1.
  This Pseudocode will be updated to correctly describe the effect of HCR_EL2.CD bit. Code in these functions will also be refactored around Force-write-back feature description.
• The Pseudocode function Halt() does not set PSTATE.{IT, SS, SSBS, T} to UNKNOWN, PSTATE.TCO to '1' and PSTATE.BTYPE to '00'.
  This will be corrected to set PSTATE. to UNKNOWN, PSTATE.TC0 to 1, and PSTATE.BTYPE to 0
• The address in FAR_ELx on an exception due to a tag check fault caused by a DC ZVA instruction is not clearly called out by the architecture.
  The architecture will be clarified to say:
  "On an exception due to a tag check fault caused by a DC ZVA instruction, FAR_ELx for the target exception level contains the lowest address that gave rise to the fault."
• From ARM8.4, the LDP, LDNP and STP instructions applying to 2 64-bit registers to Normal Inner-WB, Outer-WB Cacheable memory are single-copy atomic for all 16 bytes if the overall memory access is aligned to 16 bytes. From ARMv8.4, LDP, LDNP and STP instructions to Normal Inner-WB, Outer-WB Cacheable memory that access fewer than 16 bytes, where all accessed bytes are within a single 16-byte quantity aligned to 16 bytes, are single-copy atomic for all of the bytes accessed.
  This architectural behaviour is not currently described by the pseudocode for the LDP, LDNP and STP instructions.
• ARMv8.4-NV makes nested virtualization optional. The current pseudocode does not reflect this relaxation of the architecture.
• The description for the _ChooseRandomNonExcludedTag() function states that implementation is expected to generate a non-deterministic tag selection.
  The architecture will be relaxed to permit implementations to treat GCR_EL1.RRND as RES0 other than for the purpose of reading and writing the register field. The _ChooseRandomNonExcludedTag() function will be permitted to generate a non-deterministic selection from the set of non-excluded // Allocation Tags.
• The SetPSTATEFromPSR() function currently does not describe the behaviour of the PSTATE.TCO, PSTATE.DIT, PSTATE.UAO and PSTATE.BTYPE fields when there is an illegal exception return.
  This will be amended to show that these fields are bit UNKNOWN when an illegal exception is returned.
• The pseudocode for the STGZ and ST2GZ instructions does not clearly express the intent of the architecture to prevent writes of any data or tag to memory if the access is not aligned to the tag granule.
  The pseudocode for these instructions will be corrected to show that unaligned STG instructions will fault before any memory writes occur.
• The EffectiveTCF() function does not include the case where SCTLR_ELx.TCF or SCTLR_ELx.TCF0 is set to the reserved '11' value.
  This will be amended to show the effect of tcf == 11. The Unpredictable enumeration will be extended with a condition on memory tagging.
• The pseudocode function AArch64.TakePhysicalSErrorException() calls a function ClearPendingPhysicalSError() that is not defined.
  A definition for ClearPendingPhysicalSError() will be added.

Potential upcoming changes