(old) htmldiff from-(new)

SADDLBT

Signed add long (bottom + top).

Add the even-numbered signed elements of the first source vector to the odd-numbered signed elements of the second source vector, and place the results in the overlapping double-width elements of the destination vector. This instruction is unpredicated.

313029282726252423222120191817161514131211109876543210
01000101size0Zm100000ZnZd
Stb

SVE2

SADDLBT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>

if !HaveSVE2() then UNDEFINED; if size == '00' then UNDEFINED; integer esize = 8 << UInt(size); integer n = UInt(Zn); integer m = UInt(Zm); integer d = UInt(Zd); integer sel1 = 0; integer sel2 = 1; boolean unsigned = FALSE;

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T> Is the size specifier, encoded in size:
size<T>
00RESERVED
01H
10S
11D
<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Tb> Is the size specifier, encoded in size:
size<Tb>
00RESERVED
01B
10H
11S
<Zm>

Is the name of the second source scalable vector register, encoded in the "Zm" field.

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(VL) operand1 = Z[n]; bits(VL) operand2 = Z[m]; bits(VL) result; for e = 0 to elements-1 integer element1 = Int(Elem[operand1, 2*e + sel1, esize DIV 2], unsigned); integer element2 = Int(Elem[operand2, 2*e + sel2, esize DIV 2], unsigned); integer res = element1 + element2; Elem[result, e, esize] = res<esize-1:0>; Z[d] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v32.03v31.05b, AdvSIMD v29.02, pseudocode v2020-03v2019-12_rc3_1, sve v2020-03_rc1v2019-12_rc3 ; Build timestamp: 2020-04-15T132019-12-13T11:3302

Copyright © 2010-20202010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

(old) htmldiff from-(new)