TSB CSYNC

Trace Synchronization Barrier. This instruction is a barrier that synchronizes the trace operations of instructions.

If ARMv8.4-Trace is not implemented, this instruction executes as a NOP.

System
(Armv8.4)

313029282726252423222120191817161514131211109876543210
11010101000000110010001001011111
CRmop2

System

TSB CSYNC

if !HaveSelfHostedTrace() then EndOfInstruction();

Operation

TraceSynchronizationBarrier();


Internal version only: isa v32.03, AdvSIMD v29.02, pseudocode v2020-03, sve v2020-03_rc1 ; Build timestamp: 2020-04-15T14:44

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