STNT1H (scalar plus immediate)

Contiguous store non-temporal halfwords from vector (immediate index).

Contiguous store non-temporal of halfwords from elements of a vector register to the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements are not written to memory.

A non-temporal store is a hint to the system that this data is unlikely to be referenced again soon.

313029282726252423222120191817161514131211109876543210
111001001001imm4111PgRnZt
msz<1>msz<0>

SVE

STNT1H { <Zt>.H }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]

if !HaveSVE() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer g = UInt(Pg); integer esize = 16; integer offset = SInt(imm4);

Assembler Symbols

<Zt>

Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.

<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<imm>

Is the optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(64) base; bits(64) addr; constant integer mbytes = esize DIV 8; bits(VL) src; bits(PL) mask = P[g]; if n == 31 then if LastActiveElement(mask, esize) >= 0 || ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); if HaveMTEExt() then SetTagCheckedInstruction(FALSE); base = SP[]; else if HaveMTEExt() then SetTagCheckedInstruction(TRUE); base = X[n]; src = Z[t]; addr = base + offset * elements * mbytes; for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then Mem[addr, mbytes, AccType_STREAM] = Elem[src, e, esize]; addr = addr + mbytes;


Internal version only: isa v32.03, AdvSIMD v29.02, pseudocode v2020-03, sve v2020-03_rc1 ; Build timestamp: 2020-04-15T13:33

Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.