(old) htmldiff from-(new)

PMULLT

Polynomial multiply long (top).

Polynomial multiply over [0, 1] the corresponding odd-numbered elements of the first and second source vectors, and place the results in the overlapping double-width elements of the destination vector. This instruction is unpredicated.

ID_AA64ZFR0_EL1.AES indicates whether the instruction variant with 64-bit source and 128-bit destination elements is implemented.

313029282726252423222120191817161514131211109876543210
01000101size0Zm011011ZnZd
UT

SVE2

PMULLT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>

if !HaveSVE2() then UNDEFINED; if size == '00' && !HaveSVE2PMULL128() then UNDEFINED; case size of when '00' esize = 128; when '01' esize = 16; when '10' UNDEFINED; when '11' esize = 64; integer n = UInt(Zn); integer m = UInt(Zm); integer d = UInt(Zd);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T> Is the size specifier, encoded in size:
size<T>
00Q
01H
10RESERVED
11D
<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Tb> Is the size specifier, encoded in size:
size<Tb>
00D
01B
10RESERVED
11S
<Zm>

Is the name of the second source scalable vector register, encoded in the "Zm" field.

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(VL) operand1 = Z[n]; bits(VL) operand2 = Z[m]; bits(VL) result; for e = 0 to elements-1 bits(esize DIV 2) element1 = Elem[operand1, 2*e + 1, esize DIV 2]; bits(esize DIV 2) element2 = Elem[operand2, 2*e + 1, esize DIV 2]; Elem[result, e, esize] = PolynomialMult(element1, element2); Z[d] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v32.03v31.05b, AdvSIMD v29.02, pseudocode v2020-03v2019-12_rc3_1, sve v2020-03_rc1v2019-12_rc3 ; Build timestamp: 2020-04-15T132019-12-13T11:3302

Copyright © 2010-20202010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

(old) htmldiff from-(new)