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SHRNT

Shift right narrow by immediate (top).

Shift each unsigned integer value in the source vector elements right by an immediate value, and place the truncated results in the odd-numbered half-width destination elements, leaving the even-numbered elements unchanged. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. This instruction is unpredicated.

313029282726252423222120191817161514131211109876543210
010001010tszh1tszlimm3000101ZnZd
URT

SVE2

SHRNT <Zd>.<T>, <Zn>.<Tb>, #<const>

if !HaveSVE2() then UNDEFINED; bits(3) tsize = tszh:tszl; case tsize of when '000' UNDEFINED; when '001' esize = 8; when '01x' esize = 16; when '1xx' esize = 32; integer n = UInt(Zn); integer d = UInt(Zd); integer shift = (2 * esize) - UInt(tsize:imm3);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T> Is the size specifier, encoded in tszh:tszl:
tszhtszl<T>
000RESERVED
001B
01xH
1xxS
<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Tb> Is the size specifier, encoded in tszh:tszl:
tszhtszl<Tb>
000RESERVED
001H
01xS
1xxD
<const>

Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tsz:imm3".

Operation

CheckSVEEnabled(); integer elements = VL DIV (2 * esize); bits(VL) operand = Z[n]; bits(VL) result = Z[d]; for e = 0 to elements-1 bits(2*esize) element = Elem[operand, e, 2*esize]; integer res = UInt(element) >> shift; Elem[result, 2*e + 1, esize] = res<esize-1:0>; Z[d] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: isa v32.03v31.05b, AdvSIMD v29.02, pseudocode v2020-03v2019-12_rc3_1, sve v2020-03_rc1v2019-12_rc3 ; Build timestamp: 2020-04-15T132019-12-13T11:3302

Copyright © 2010-20202010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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