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Floating-point base 2 logarithm as integer.
This instruction returns the signed integer base 2 logarithm of each floating-point input element |x| after normalization.
This is the unbiased exponent of x used in the representation of the floating-point value, such that, for positive x, x = significand × 2exponent.
The integer results are placed in elements of the destination vector which have the same width (esize) as the floating-point input elements:
* If x is normal, the result is the base 2 logarithm of x.
* If x is subnormal, the result corresponds to the normalized representation.
* If x is infinite, the result is 2(esize-1)-1.
* If x is ±0.0 or NaN, the result is -2(esize-1).
Inactive elements in the destination vector register remain unmodified.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | size | 0 | 1 | 0 | 1 | Pg | Zn | Zd | |||||||||||
U |
if !HaveSVE2() then UNDEFINED; if size == '00' then UNDEFINED; integer esize = 8 << UInt(size); integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Zd);
<Zd> | Is the name of the destination scalable vector register, encoded in the "Zd" field. |
<T> |
Is the size specifier,
encoded in
size:
|
<Pg> | Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
<Zn> | Is the name of the source scalable vector register, encoded in the "Zn" field. |
CheckSVEEnabled();
integer elements =CheckSVEEnabled();
integer elements = VL DIV esize;
bits(PL) mask = P[g];
bits(VL) operand = Z[n];
bits(VL) result = Z[d];
for e = 0 to elements-1
bits(esize) element = VL DIV esize;
bits(PL) mask = P[g];
bits(VL) operand = Z[n];
bits(VL) result = Z[d];
for e = 0 to elements-1
bits(esize) element = Elem[operand, e, esize];
if if ElemP[mask, e, esize] == '1' then ElemP[mask, e, esize] == '1' then
Elem[result, e, esize] = FPLogB(element, FPCR<31:0>);
Z[d] = result;[result, e, esize] = FPLogB(element, FPCR);
Z[d] = result;
This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:
Internal version only: isa v32.03v31.05b, AdvSIMD v29.02, pseudocode v2020-03v2019-12_rc3_1, sve v2020-03_rc1v2019-12_rc3
; Build timestamp: 2020-04-15T132019-12-13T11:3302
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This document is Non-Confidential.
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