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Floating-point minimum pairwise.
Compute the minimum value of each pair of adjacent floating-point elements within each source vector, and interleave the results from corresponding lanes. The interleaved result values are destructively placed in the first source vector.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | size | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | Pg | Zm | Zdn |
if !HaveSVE2() then UNDEFINED; if size == '00' then UNDEFINED; integer esize = 8 << UInt(size); integer g = UInt(Pg); integer m = UInt(Zm); integer dn = UInt(Zdn);
<Zdn> | Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field. |
<T> |
Is the size specifier,
encoded in
size:
|
<Pg> | Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
<Zm> | Is the name of the second source scalable vector register, encoded in the "Zm" field. |
CheckSVEEnabled();
integer elements =CheckSVEEnabled();
integer elements = VL DIV esize;
bits(PL) mask = P[g];
bits(VL) operand1 = Z[dn];
bits(VL) operand2 = Z[m];
bits(VL) result = Z[dn];
bits(esize) element1;
bits(esize) element2;
for e = 0 to elements-1
if ElemP[mask, e, esize] == '1' then
if IsEven(e) then
element1 = VL DIV esize;
bits(PL) mask = P[g];
bits(VL) operand1 = Z[dn];
bits(VL) operand2 = Z[m];
bits(VL) result = Z[dn];
bits(esize) element1;
bits(esize) element2;
for e = 0 to elements-1
if ElemP[mask, e, esize] == '1' then
if IsEven(e) then
element1 = Elem[operand1, e + 0, esize];
element2 = Elem[operand1, e + 1, esize];
else
element1 = Elem[operand2, e - 1, esize];
element2 = Elem[operand2, e + 0, esize];
Elem[result, e, esize] = FPMin(element1, element2, FPCR<31:0>);
Z[dn] = result;(element1, element2, FPCR);
Z[dn] = result;
This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:
Internal version only: isa v32.03v31.05b, AdvSIMD v29.02, pseudocode v2020-03v2019-12_rc3_1, sve v2020-03_rc1v2019-12_rc3
; Build timestamp: 2020-04-15T132019-12-13T11:3302
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