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SQXTNB

Signed saturating extract narrow (bottom).

Saturate the signed integer value in each source element to half the original source element width, and place the results in the even-numbered half-width destination elements, while setting the odd-numbered elements to zero.

313029282726252423222120191817161514131211109876543210
010001010tszh1tszl000010000ZnZd
UT

SVE2

SQXTNB <Zd>.<T>, <Zn>.<Tb>

if !HaveSVE2() then UNDEFINED; bits(3) tsize = tszh:tszl; case tsize of when '001' esize = 16; when '010' esize = 32; when '100' esize = 64; otherwise UNDEFINED; integer n = UInt(Zn); integer d = UInt(Zd);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T> Is the size specifier, encoded in tszh:tszl:
tszhtszl<T>
000RESERVED
001B
010H
x11RESERVED
100S
101RESERVED
110RESERVED
<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

<Tb> Is the size specifier, encoded in tszh:tszl:
tszhtszl<Tb>
000RESERVED
001H
010S
x11RESERVED
100D
101RESERVED
110RESERVED

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(VL) operand1 = Z[n]; bits(VL) result; integer halfesize = esize DIV 2; for e = 0 to elements-1 integer element1 = SInt(Elem[operand1, e, esize]); bits(halfesize) res = SignedSat(element1, halfesize); Elem[result, 2*e + 0, halfesize] = res; Elem[result, 2*e + 1, halfesize] = Zeros(); Z[d] = result;


Internal version only: isa v32.03v31.05b, AdvSIMD v29.02, pseudocode v2020-03v2019-12_rc3_1, sve v2020-03_rc1v2019-12_rc3 ; Build timestamp: 2020-04-15T132019-12-13T11:3302

Copyright © 2010-20202010-2019 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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