SQXTNT
Signed saturating extract narrow (top).
Saturate the signed integer value in each source element to half the original source element width, and place the results in the odd-numbered half-width destination elements, leaving the even-numbered elements unchanged.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | tszh | 1 | tszl | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | Zn | Zd |
| | | | | | U | T | | |
if !HaveSVE2() then UNDEFINED;
bits(3) tsize = tszh:tszl;
case tsize of
when '001' esize = 16;
when '010' esize = 32;
when '100' esize = 64;
otherwise UNDEFINED;
integer n = UInt(Zn);
integer d = UInt(Zd);
Assembler Symbols
<Zd> | Is the name of the destination scalable vector register, encoded in the "Zd" field. |
<T> |
Is the size specifier,
encoded in
tszh:tszl :
tszh | tszl | <T> |
---|
0 | 00 | RESERVED | 0 | 01 | B | 0 | 10 | H | x | 11 | RESERVED | 1 | 00 | S | 1 | 01 | RESERVED | 1 | 10 | RESERVED |
|
<Zn> | Is the name of the first source scalable vector register, encoded in the "Zn" field. |
<Tb> |
Is the size specifier,
encoded in
tszh:tszl :
tszh | tszl | <Tb> |
---|
0 | 00 | RESERVED | 0 | 01 | H | 0 | 10 | S | x | 11 | RESERVED | 1 | 00 | D | 1 | 01 | RESERVED | 1 | 10 | RESERVED |
|
Operation
CheckSVEEnabled();
integer elements = VL DIV esize;
bits(VL) operand1 = Z[n];
bits(VL) result = Z[d];
integer halfesize = esize DIV 2;
for e = 0 to elements-1
integer element1 = SInt(Elem[operand1, e, esize]);
bits(halfesize) res = SignedSat(element1, halfesize);
Elem[result, 2*e + 1, halfesize] = res;
Z[d] = result;
Internal version only: isa v32.03v31.05b, AdvSIMD v29.02, pseudocode v2020-03v2019-12_rc3_1, sve v2020-03_rc1v2019-12_rc3
; Build timestamp: 2020-04-15T132019-12-13T11:3302
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