SUDOT (by element)
Dot product index form with signed and unsigned integers. This instruction performs the dot product of the four signed 8-bit integer values in each 32-bit element of the first source register with the four unsigned 8-bit integer values in an indexed 32-bit element of the second source register, accumulating the result into the corresponding 32-bit element of the destination vector.
From Armv8.2, this is an optional instruction. ID_AA64ISAR0_EL1.I8MM indicates whether this instruction is supported.
Vector
(Armv8.6)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | Q | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | L | M | Rm | 1 | 1 | 1 | 1 | H | 0 | Rn | Rd |
| | | | US | | | | | | | | | |
if !HaveInt8MatMulExt() then UNDEFINED;
boolean op1_unsigned = (US == '1');
boolean op2_unsigned = (US == '0');
integer n = UInt(Rn);
integer m = UInt(M:Rm);
integer d = UInt(Rd);
integer i = UInt(H:L);
integer datasize = if Q == '1' then 128 else 64;
integer elements = datasize DIV 32;
Assembler Symbols
<Vd> | Is the name of the SIMD&FP third source and destination register, encoded in the "Rd" field. |
<Ta> |
Is an arrangement specifier,
encoded in
Q :
|
<Vn> | Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
<Tb> |
Is an arrangement specifier,
encoded in
Q :
|
<Vm> | Is the name of the second SIMD&FP source register, encoded in the "M:Rm" fields. |
<index> | Is the immediate index of a quadtuplet of four 8-bit elements in the range 0 to 3, encoded in the "H:L" fields. |
Operation
CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(128) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
for e = 0 to elements-1
bits(32) res = Elem[operand3, e, 32];
for b = 0 to 3
integer element1 = Int(Elem[operand1, 4*e+b, 8], op1_unsigned);
[operand1, 4 * e + b, 8], op1_unsigned);
integer element2 = Int(Elem[operand2, 4*i+b, 8], op2_unsigned);
[operand2, 4 * i + b, 8], op2_unsigned);
res = res + element1 * element2;
Elem[result, e, 32] = res;
V[d] = result;
Internal version only: isa v32.03, AdvSIMD v29.02, pseudocode v2020-03, sve v2020-03_rc1
; Build timestamp: 2020-04-15T142020-04-15T13:4433
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