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Half-precision floating-point multiply-add long to single-precision (top).
This half-precision floating-point multiply-add long instruction widens the odd-numbered 16-bit half-precision elements in the first source vector and the corresponding elements in the second source vector to single-precision format and then destructively multiplies and adds these values without intermediate rounding to the overlapping 32-bit single-precision elements of the addend and destination vector. This instruction is unpredicated.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | Zm | 1 | 0 | 0 | 0 | 0 | 1 | Zn | Zda | ||||||||||||
o2 | op | T |
if !HaveSVE2() then UNDEFINED; integer esize = 32; integer n = UInt(Zn); integer m = UInt(Zm); integer da = UInt(Zda); boolean op1_neg = FALSE;
<Zda> | Is the name of the third source and destination scalable vector register, encoded in the "Zda" field. |
<Zn> | Is the name of the first source scalable vector register, encoded in the "Zn" field. |
<Zm> | Is the name of the second source scalable vector register, encoded in the "Zm" field. |
CheckSVEEnabled();
integer elements =CheckSVEEnabled();
integer elements = VL DIV esize;
bits(VL) operand1 = Z[n];
bits(VL) operand2 = Z[m];
bits(VL) operand3 = Z[da];
bits(VL) result;
for e = 0 to elements-1
bits(esize DIV 2) element1 = VL DIV esize;
bits(VL) operand1 = Z[n];
bits(VL) operand2 = Z[m];
bits(VL) operand3 = Z[da];
bits(VL) result;
for e = 0 to elements-1
bits(esize DIV 2) element1 = Elem[operand1, 2 * e + 1, esize DIV 2];
bits(esize DIV 2) element2 = Elem[operand2, 2 * e + 1, esize DIV 2];
bits(esize) element3 = Elem[operand3, e, esize];
if op1_neg then element1 = FPNeg(element1);
Elem[result, e, esize] = FPMulAddH(element3, element1, element2, FPCR<31:0>);
Z[da] = result;[result, e, esize] = FPMulAddH(element3, element1, element2, FPCR);
Z[da] = result;
This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:
Internal version only: isa v32.03v31.05b, AdvSIMD v29.02, pseudocode v2020-03v2019-12_rc3_1, sve v2020-03_rc1v2019-12_rc3
; Build timestamp: 2020-04-15T132019-12-13T11:3302
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This document is Non-Confidential.
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