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Unsigned by signed integer indexed dot product.
The unsigned by signed integer indexed dot product instruction computes the dot product of a group of four unsigned 8-bit integer values held in each 32-bit element of the first source vector multiplied by a group of four signed 8-bit integer values in an indexed 32-bit element of the second source vector, and then destructively adds the widened dot product to the corresponding 32-bit element of the destination vector.
The groups within the second source vector are specified using an immediate index which selects the same group position within each 128-bit vector segment. The index range is from 0 to 3. This instruction is unpredicated.
ID_AA64ZFR0_EL1.I8MM indicates whether this instruction is implemented.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | i2 | Zm | 0 | 0 | 0 | 1 | 1 | 0 | Zn | Zda | |||||||||||
size<1> | size<0> | U |
if !HaveSVE() || !HaveInt8MatMulExt() then UNDEFINED; integer esize = 32; integer index = UInt(i2); integer n = UInt(Zn); integer m = UInt(Zm); integer da = UInt(Zda);
<Zda> | Is the name of the third source and destination scalable vector register, encoded in the "Zda" field. |
<Zn> | Is the name of the first source scalable vector register, encoded in the "Zn" field. |
<Zm> | Is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field. |
<imm> | Is the immediate index of a quadtuplet of four 8-bit elements within each 128-bit vector segment, in the range 0 to 3, encoded in the "i2" field. |
CheckSVEEnabled();
integer elements =CheckSVEEnabled();
integer elements = VL DIV esize;
integer eltspersegment = 128 DIV esize;
bits(VL) operand1 = Z[n];
bits(VL) operand2 = Z[m];
bits(VL) operand3 = Z[da];
bits(VL) result;
for e = 0 to elements-1
integer segmentbase = e - e MOD eltspersegment;
integer s = segmentbase + index;
bits(esize) res = VL DIV esize;
integer eltspersegment = 128 DIV esize;
bits(VL) operand1 = Z[n];
bits(VL) operand2 = Z[m];
bits(VL) operand3 = Z[da];
bits(VL) result;
for e = 0 to elements-1
integer segmentbase = e - (e MOD eltspersegment);
integer s = segmentbase + index;
bits(esize) res = Elem[operand3, e, esize];
for i = 0 to 3
integer element1 = UInt(Elem[operand1, 4 * e + i, esize DIV 4]);
integer element2 = SInt(Elem[operand2, 4 * s + i, esize DIV 4]);
res = res + element1 * element2;
Elem[result, e, esize] = res;
Z[da] = result;[result, e, esize] = res;
Z[da] = result;
This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:
Internal version only: isa v32.03v31.05b, AdvSIMD v29.02, pseudocode v2020-03v2019-12_rc3_1, sve v2020-03_rc1v2019-12_rc3
; Build timestamp: 2020-04-15T132019-12-13T11:3302
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