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LD1D (scalar plus scalar)

Contiguous load doublewords to vector (scalar index).

Contiguous load of doublewords to elements of a vector register from the memory address generated by a 64-bit scalar base and scalar index which is multiplied by 8 and added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements will not not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.

313029282726252423222120191817161514131211109876543210
10100101111Rm010PgRnZt
dtype<3:1>dtype<0>

LD1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]

if !HaveSVE() then UNDEFINED; if Rm == '11111' then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer m = UInt(Rm); integer g = UInt(Pg); integer esize = 64; integer msize = 64; boolean unsigned = TRUE;

Assembler Symbols

<Zt>

Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.

<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Xm>

Is the 64-bit name of the general-purpose offset register, encoded in the "Rm" field.

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(64) base; bits(64) addr; bits(PL) mask = P[g]; bits(VL) result; bits(msize) data; bits(64) offset; constant integer mbytes = msize DIV 8; ifbits(64) offset = X[m]; constant integer mbytes = msize DIV 8; if HaveMTEExt() then SetTagCheckedInstruction(TRUE); if !if n == 31 then ifAnyActiveElementLastActiveElement(mask, esize) then if n == 31 &&(mask, esize) >= 0 || ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); else if n == 31 then base = CheckSPAlignment(); base = if n == 31 then SP[] else[]; else base = X[n]; offset = for e = 0 to elements-1 addr = base + XUInt[m]; for e = 0 to elements-1 (offset) * mbytes; if ElemP[mask, e, esize] == '1' then bits(64) addr = base + (UInt(offset) + e) * mbytes; [mask, e, esize] == '1' then data = Mem[addr, mbytes, AccType_NORMAL]; Elem[result, e, esize] = Extend(data, esize, unsigned); else Elem[result, e, esize] = Zeros();(); offset = offset + 1; Z[t] = result;


Internal version only: isa v32.13v32.12, AdvSIMD v29.05v29.04, pseudocode v2020-12v2020-09_xml, sve v2020-12v2020-09_rc2b ; Build timestamp: 2020-12-16T142020-09-30T19:4116

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