(old) | htmldiff from- | (new) |
This instruction starts a new transaction. If the transaction started successfully, the destination register is set to zero. If the transaction failed or was canceled, then all state modifications that were performed transactionally are discarded and the destination register is written with a non-zero value that encodes the cause of the failure.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | Rt |
TSTART <Xt>
if !HaveTME() then UNDEFINED; integer t = UInt(Rt);
CheckTMEEnabled();
boolean IsEL1Regime;
case PSTATE.EL of
when EL0
IsEL1Regime = S1TranslationRegime() == EL1;
if IsEL1Regime then
tme = SCTLR_EL1.TME0;
tmt = SCTLR_EL1.TMT0;
else
tme = SCTLR_EL2.TME0;
tmt = SCTLR_EL2.TMT0;
when EL1
tme = SCTLR_EL1.TME;
tmt = SCTLR_EL1.TMT;
when EL2
tme = SCTLR_EL2.TME;
tmt = SCTLR_EL2.TMT;
when EL3
tme = SCTLR_EL3.TME;
tmt = SCTLR_EL3.TMT;
otherwise
Unreachable();
enable = tme == '1';
trivial = tmt == '1';
if !enable then
TransactionStartTrap(t);
elsif trivial then
TSTATE.nPC =elsif trivial then NextInstrAddr();
TSTATE.Rt = t;
FailTransaction(TMFailure_TRIVIAL, FALSE);
elsif TSTATE.depth == 255 then
FailTransaction(TMFailure_NEST, FALSE);
elsif TSTATE.depth == 0 then
TSTATE.nPC = NextInstrAddr();
TSTATE.Rt = t;
ClearExclusiveLocal(ProcessorID());
TakeTransactionCheckpoint();
StartTrackingTransactionalReadsWrites();
TSTATE.depth = TSTATE.depth + 1;
X[t] = Zeros(64);
Internal version only: isa v32.12v32.06, AdvSIMD v29.04, pseudocode v2020-09_xmlv2020-06_rel, sve v2020-09_rc2bv2020-06_rel0
; Build timestamp: 2020-09-30T192020-07-03T13:1613
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
(old) | htmldiff from- | (new) |