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PRFD (scalar plus immediate)

Contiguous prefetch doublewords (immediate index).

Contiguous prefetch of doubleword elements from the memory address generated by a 64-bit scalar base and immediate index in the range -32 to 31 which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address.

The predicate may be used to suppress prefetches from unwanted addresses.

313029282726252423222120191817161514131211109876543210
1000010111imm6011PgRn0prfop
msz<1>msz<0>

PRFD <prfop>, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]

if !HaveSVE() then UNDEFINED; integer esize = 64; integer g = UInt(Pg); integer n = UInt(Rn); integer level = UInt(prfop<2:1>); boolean stream = (prfop<0> == '1'); pref_hint = if prfop<3> == '0' then Prefetch_READ else Prefetch_WRITE; integer scale = 3; integer offset = SInt(imm6);

Assembler Symbols

<prfop> Is the prefetch operation specifier, encoded in prfop:
prfop<prfop>
0000PLDL1KEEP
0001PLDL1STRM
0010PLDL2KEEP
0011PLDL2STRM
0100PLDL3KEEP
0101PLDL3STRM
x11x#uimm4
1000PSTL1KEEP
1001PSTL1STRM
1010PSTL2KEEP
1011PSTL2STRM
1100PSTL3KEEP
1101PSTL3STRM
<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<imm>

Is the optional signed immediate vector offset, in the range -32 to 31, defaulting to 0, encoded in the "imm6" field.

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(64) base; bits(64) addr; ifif n == 31 then base = AnyActiveElement(mask, esize) then base = if n == 31 then SP[] else[]; else base = X[n]; addr = base + ((offset * elements) << scale); for e = 0 to elements-1 if ElemP[mask, e, esize] == '1' then integer eoff = (offset * elements) + e; bits(64) addr = base + (eoff << scale);[mask, e, esize] == '1' then Hint_Prefetch(addr, pref_hint, level, stream);(addr, pref_hint, level, stream); addr = addr + (1 << scale);


Internal version only: isa v32.13v32.12, AdvSIMD v29.05v29.04, pseudocode v2020-12v2020-09_xml, sve v2020-12v2020-09_rc2b ; Build timestamp: 2020-12-16T142020-09-30T19:4116

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