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FCVTX

Floating-point down convert, rounding to odd (predicated).

Convert active double-precision floating-point elements from the source vector to single-precision, rounding to Odd, and place the results in the even-numbered 32-bit elements of the destination vector, while setting the odd-numbered elements to zero. Inactive elements in the destination vector register remain unmodified.

Rounding to Odd (aka Von Neumann rounding) permits a two-step conversion from double-precision to half-precision without incurring intermediate rounding errors.

313029282726252423222120191817161514131211109876543210
0110010100001010101PgZnZd

FCVTX <Zd>.S, <Pg>/M, <Zn>.D

if !HaveSVE2() then UNDEFINED; integer esize = 64; integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Zd); integer s_esize = 64; integer d_esize = 32;

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(PL) mask = P[g]; bits(VL) operand = Z[n]; bits(VL) result = Z[d]; for e = 0 to elements-1 bits(esize) element = Elem[operand, e, esize]; if ElemP[mask, e, esize] == '1' then bits(d_esize) res = FPConvertSVE(element<s_esize-1:0>, FPCR[],(element<s_esize-1:0>, FPCR, FPRounding_ODD); Elem[result, e, esize] = ZeroExtend(res); Z[d] = result;

Operational information

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:


Internal version only: isa v32.12v32.06, AdvSIMD v29.04, pseudocode v2020-09_xmlv2020-06_rel, sve v2020-09_rc2bv2020-06_rel0 ; Build timestamp: 2020-09-30T192020-07-03T13:1613

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