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Branch with Link to Register calls a subroutine at an address in a register, setting register X30 to PC+4.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | Rn | 0 | 0 | 0 | 0 | 0 | ||||
Z | op | A | M | Rm |
BLR <Xn>
integer n = UInt(Rn); BranchType branch_type; integer m = UInt(Rm); boolean pac = (A == '1'); boolean use_key_a = (M == '0'); boolean source_is_sp = ((Z == '1') && (m == 31)); if !pac && m != 0 then UNDEFINED; elsif pac && !HavePACExt() then UNDEFINED; case op of when '00' branch_type = BranchType_INDIR; when '01' branch_type = BranchType_INDCALL; when '10' branch_type = BranchType_RET; otherwise UNDEFINED; if pac then if Z == '0' && m != 31 then UNDEFINED; if branch_type == BranchType_RET then if n != 31 then UNDEFINED; n = 30; source_is_sp = TRUE;
<Xn> | Is the 64-bit name of the general-purpose register holding the address to be branched to, encoded in the "Rn" field. |
bits(64) target = X[n];
boolean auth_then_branch = TRUE;
if pac then
bits(64) modifier = if source_is_sp then SP[] else X[m];
if use_key_a then
target = AuthIA(target, modifier, auth_then_branch);
else
target = AuthIB(target, modifier, auth_then_branch);
if branch_type == BranchType_RET then
if HaveCSRExt() && CallStackRecordingActive() then
RemoveCallStackRecord();
if branch_type == BranchType_INDCALL then
if HaveCSRExt() && CallStackRecordingActive() then
AddCallStackRecord then();
X[30] = PC[] + 4;
// Value in BTypeNext will be used to set PSTATE.BTYPE
case branch_type of
when BranchType_INDIR // BR, BRAA, BRAB, BRAAZ, BRABZ
if InGuardedPage then
if n == 16 || n == 17 then
BTypeNext = '01';
else
BTypeNext = '11';
else
BTypeNext = '01';
when BranchType_INDCALL // BLR, BLRAA, BLRAB, BLRAAZ, BLRABZ
BTypeNext = '10';
when BranchType_RET // RET, RETAA, RETAB
BTypeNext = '00';
BranchTo(target, branch_type);
Internal version only: isa v32.13v32.12, AdvSIMD v29.05v29.04, pseudocode v2020-12v2020-09_xml, sve v2020-12v2020-09_rc2b
; Build timestamp: 2020-12-16T142020-09-30T19:4116
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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