1. Introduction

This is the 2020-12 release of the A64 ISA XML for Future Architecture Technologies.

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2. Contents

3. Release Notes

Change history

This is the A64 ISA XML for Future Architecture Technologies (2020-12).

The following general changes are made:

• The release removes the content for FEAT_CSRE.
• Significant updates to FEAT_BRBE pseudocode to aid readability, add missing functionality, and correct incorrect functionality.
• The following features are added to the MPAM system architecture: Error MSI, Monitor Overflow MSI, and Monitor Overflow Status.
• The optimized pseudocode for the double-precision variants of the FADDP, FMAXNMP, FMAXP, FMINNMP, and FMINP instructions is corrected to add missing checks.
• The FEAT_MTE feature is split into FEAT_MTE, Instruction only, and FEAT_MTE2, Full MTE, features.
• The STGP operational pseudocode is updated to check access is aligned to a tag granule.
• The execute code for CSEL, CSINC, CSINV, CSNEG, CCMP, and CCMN is updated to create a dependency only via the register which is selected, not both of its input registers.
• The STGP pre-index and post-index decode pseudocode is updated to check for the presence of FEAT_MTE.
• The decode pseudocode for SUBP(S) and STG pre-index/post-index MTE instructions is updated to check for the presence of FEAT_MTE.
• The ST64BV0 operational pseudocode is updated to correctly store the content of ACCDATA_EL1 in case of a Big Endian access.

The following changes are made to the instruction definitions:

• None.

The following changes are made to the Shared Pseudocode:

• Removed unused function ReservedValue().
• The decoding of Load/Store Multiple instructions inside FirstStageTranslation is replaced by a new memory accessor type AccType_ATOMICSTREAM.
• Removed unused function UnallocatedEncoding().
• Permission checks for Data/Instruction cache maintenance instructions corrected.
• The pseudocode function AArch64.ExceptionReturn() moves the call to SynchroniseContext() following the checks for error synchronization.
• The pseudocode functions AArch64.SecondStageTranslate() and AArch32.SecondStageTranslate() are updated to not generate an alignment fault to a memory location marked as Device for stage 2 for stage 1 walks.
• The pseudocode function ProfilingBufferOwner() is updated to account for Secure EL2.
• The pseudocode function AArch64.WatchpointMatch() is updated to check for check for the atomic Read-Write memory access with the DBGWCR.LSC configuration.
• The pseudocode function CollectTimeStamp() is adjusted to include the missing reserved value checks.
• The pseudocode function CombineS1S2AttrHints() is corrected to take into account Device memory when S2FWB is enabled.
• The pseudocode function AArch64.SoftwareStepException() is updated to include the IFSC of Debug Exception.
• The pseudocode functions AArch64.CheckPermission() and AArch32.CheckPermission() are updated to initialise priv_xn and user_xn prior to PAN checks that re determines the value of priv_w.
• The pseudocode function TraceTimeStamp() is updated to not treat the value '10' for TRFCR_EL1.TS and TRFCR_EL2.TS as UNPREDICTABLE in all cases.
• In pseudocode function AArch64.CheckWatchpoint() WnR bit to be set as 'read' in Atomic read-write operations if DBGWCR.LSC has a match on read.
• The pseudocode function IsSErrorEdgeTriggered() takes a new parameter indicating the target Exception level. This function now checks the Execution state of the target Exception level to determine the correct syndrome checks. In AArch64 state syndrome<24> is now checked to establish if the SError is IMPLEMENTATION DEFINED.
• The pseudocode functions AArch64.FirstStageTranslate() and AArch64.SecondStageTranslate() are updated with a check for data abort when the memory attribute of the data location accessed is not one of Normal Inner Non-cacheable Outer Non-cacheable, Device-GRE, Device-nGRE, Device-nGnRE, Device-nGnRnE.
• The access type AccType_DC_UNPRIV is now qualified with PSTATE.EL and AccType_DC. DC_UNPRIV usage is removed from the pseudocode.
• The pseudocode function AArch64.WFxTrap() now correctly updates the Instruction Specific Syndrome if execution of WFET or WFIT is trapped.
• The pseudocode function AArch64.FaultSyndrome() now correctly sets the Load/Store Type field within the ISS when an LD64B, ST64B, ST64BV, or ST64BV0 instruction generates a Data Abort for a Translation fault, Access flag fault, or Permission fault. AArch64.ExclusiveFault() takes two additional boolean parameters: secondstage and s1fs1walk.
• Enumeration literal Unpredictable_PMUEventCount is added for Constrained Unpredictable access to Performance Monitor Event Count register access.
• Enumeration literal Unpredictable_IGNORETRAPINDEBUG is added for register access trap ignore in Debug state.
• The pseudocode functions CheckLDST64BEnabled(), CheckST64BVEnabled(), and CheckST64BV0Enabled() now check if the bits in HCRX_EL2 behave as 0 for indirect reads.
• The pseudocode for FEAT_XS is partially included in this release, including the addition of the pseudocode for the Arch64 DSBnXS instruction and the updates related to FEAT_XS in the DSB instructions.

Known issues

• Clarification required to MRS/MSR instruction behavior with the SYS instruction following relaxation.
• The description of DSB encoding when FEAT-SSBS implemented will be clarified by making SSBB and PSSBB architectural aliases of DSB, and point to SSBB when CRm is 0b0000, and PSSBB when CRm is 0b0100.
• In the browsable XML, hyperlinking with some pseudocode functions do not link correctly.
• Some architectural features have limited or no descriptions in pseudocode and are not fully covered by the functional testing. Affected features are listed below:
  • Address translation system instructions.
  • Ordering of memory accesses.
  • Self-hosted debug and behavior of PE when in Debug state.
  • Trace architecture, including self-hosted trace and external trace.
  • RAS architecture.
  • Statistical Profiling Extension.
  • Performance Monitors Extension.
  • Activity Monitors Extension.
  • Generic Timers.
  • Generic Interrupt Controller.
  • Multi-processing.
• The LDP, LDNP and STP instruction pseudocode does not show single-copy atomicity for 16 byte accesses, if the overall memory access is aligned to 16 bytes, or for access fewer than 16 bytes, where all accessed bytes are within a single 16-byte quantity aligned to 16 bytes, to Normal Inner-WB, Outer-WB Cacheable memory.

Potential upcoming changes

• The Shared pseudocode for VMSA will be refactored.
• The pseudocode for FEAT_XS and FEAT_LPA2 will be added.
• The pseudocode for system instructions will be added.