UQXTNT

Unsigned saturating extract narrow (top).

Saturate the unsigned integer value in each source element to half the original source element width, and place the results in the odd-numbered half-width destination elements, leaving the even-numbered elements unchanged.

313029282726252423222120191817161514131211109876543210
010001010tszh1tszl000010011ZnZd
UT

UQXTNT <Zd>.<T>, <Zn>.<Tb>

if !HaveSVE2() then UNDEFINED; bits(3) tsize = tszh:tszl; case tsize of when '001' esize = 16; when '010' esize = 32; when '100' esize = 64; otherwise UNDEFINED; integer n = UInt(Zn); integer d = UInt(Zd);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T> Is the size specifier, encoded in tszh:tszl:
tszh tszl <T>
0 00 RESERVED
0 01 B
0 10 H
x 11 RESERVED
1 00 S
1 01 RESERVED
1 10 RESERVED
<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Tb> Is the size specifier, encoded in tszh:tszl:
tszh tszl <Tb>
0 00 RESERVED
0 01 H
0 10 S
x 11 RESERVED
1 00 D
1 01 RESERVED
1 10 RESERVED

Operation

CheckSVEEnabled(); integer elements = VL DIV esize; bits(VL) operand1 = Z[n]; bits(VL) result = Z[d]; integer halfesize = esize DIV 2; for e = 0 to elements-1 integer element1 = UInt(Elem[operand1, e, esize]); bits(halfesize) res = UnsignedSat(element1, halfesize); Elem[result, 2*e + 1, halfesize] = res; Z[d] = result;


Internal version only: isa v32.12, AdvSIMD v29.04, pseudocode v2020-09_xml, sve v2020-09_rc2b ; Build timestamp: 2020-09-30T19:16

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