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FMINV

Floating-point minimum recursive reduction to scalar.

Floating-point minimum horizontally over all lanes of a vector using a recursive pairwise reduction, and place the result in the SIMD&FP scalar destination register. Inactive elements in the source vector are treated as +Infinity.

313029282726252423222120191817161514131211109876543210
01100101size000111001PgZnVd

FMINV <V><d>, <Pg>, <Zn>.<T>

if !HaveSVE() then UNDEFINED; if size == '00' then UNDEFINED; integer esize = 8 << UInt(size); integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Vd);

Assembler Symbols

<V> Is a width specifier, encoded in size:
size<V>
00RESERVED
01H
10S
11D
<d>

Is the number [0-31] of the destination SIMD&FP register, encoded in the "Vd" field.

<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

<T> Is the size specifier, encoded in size:
size<T>
00RESERVED
01H
10S
11D

Operation

CheckSVEEnabled(); bits(PL) mask = P[g]; bits(VL) operand = if) operand = AnyActiveElement(mask, esize) then Z[n] else Zeros(); [n]; bits(esize) identity = FPInfinity('0'); V[d] = ReducePredicated(ReduceOp_FMIN, operand, mask, identity);


Internal version only: isa v32.13v32.12, AdvSIMD v29.05v29.04, pseudocode v2020-12v2020-09_xml, sve v2020-12v2020-09_rc2b ; Build timestamp: 2020-12-16T142020-09-30T19:4116

Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

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