AES mix columns.
The AESMC instruction reads a 16-byte state array from each 128-bit segment of the source register, and performs a single round of the MixColumns() transformation on each state array in accordance with the AES standard. Each updated state array is destructively placed in the corresponding segment of the first source vector. This instruction is unpredicated.
ID_AA64ZFR0_EL1.AES indicates whether this instruction is implemented.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Zdn | ||||
size<1> | size<0> |
if !HaveSVE2AES() then UNDEFINED; integer dn = UInt(Zdn);
<Zdn> |
Is the name of the source and destination scalable vector register, encoded in the "Zdn" field. |
CheckSVEEnabled(); integer segments = VL DIV 128; bits(VL) operand = Z[dn]; bits(VL) result; for s = 0 to segments-1 Elem[result, s, 128] = AESMixColumns(Elem[operand, s, 128]); Z[dn] = result;
If PSTATE.DIT is 1:
Internal version only: isa v32.13, AdvSIMD v29.05, pseudocode v2020-12, sve v2020-12 ; Build timestamp: 2020-12-16T16:53
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