(old) | htmldiff from- | (new) |
Floating-point down convert, rounding to odd (top, predicated).
Convert active double-precision floating-point elements from the source vector to single-precision, rounding to Odd, and place the results in the odd-numbered 32-bit elements of the destination vector, leaving the even-numbered elements unchanged. Inactive elements in the destination vector register remain unmodified.
Rounding to Odd (aka Von Neumann rounding) permits a two-step conversion from double-precision to half-precision without incurring intermediate rounding errors.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | Pg | Zn | Zd |
if !HaveSVE2() then UNDEFINED; integer esize = 64; integer g = UInt(Pg); integer n = UInt(Zn); integer d = UInt(Zd);
<Zd> | Is the name of the destination scalable vector register, encoded in the "Zd" field. |
<Pg> | Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
<Zn> | Is the name of the first source scalable vector register, encoded in the "Zn" field. |
CheckSVEEnabled();
integer elements = VL DIV esize;
bits(PL) mask = P[g];
bits(VL) operand = Z[n];
bits(VL) result = Z[d];
for e = 0 to elements-1
if ElemP[mask, e, esize] == '1' then
bits(esize) element = Elem[operand, e, esize];
Elem[result, 2*e + 1, esize DIV 2] = FPConvertSVE(element, FPCR[],(element, FPCR, FPRounding_ODD);
Z[d] = result;
Internal version only: isa v32.12v32.06, AdvSIMD v29.04, pseudocode v2020-09_xmlv2020-06_rel, sve v2020-09_rc2bv2020-06_rel0
; Build timestamp: 2020-09-30T192020-07-03T13:1613
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
(old) | htmldiff from- | (new) |