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Scatter store non-temporal words.
Scatter store non-temporal of words from the active elements of a vector register to the memory addresses generated by a vector base plus a 64-bit unscaled scalar register offset. Inactive elements are not written to memory.
A non-temporal store is a hint to the system that this data is unlikely to be referenced again soon.
It has encodings from 2 classes: 32-bit unscaled offset and 64-bit unscaled offset
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | Rm | 0 | 0 | 1 | Pg | Zn | Zt | ||||||||||||||
msz<1> | msz<0> |
if !HaveSVE2() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Zn); integer m = UInt(Rm); integer g = UInt(Pg); integer esize = 32; integer msize = 32;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | Rm | 0 | 0 | 1 | Pg | Zn | Zt | ||||||||||||||
msz<1> | msz<0> |
if !HaveSVE2() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Zn); integer m = UInt(Rm); integer g = UInt(Pg); integer esize = 64; integer msize = 32;
<Zt> | Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. |
<Pg> | Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
<Zn> | Is the name of the base scalable vector register, encoded in the "Zn" field. |
<Xm> | Is the optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field. |
CheckSVEEnabled();
integer elements = VL DIV esize;
bits(PLVL) mask =) base = PZ[g];
bits([n];
bits(64) offset =VLX) base;
bits(64) offset;
[m];
bits(VL) src;
constant integer mbytes = msize DIV 8;
if) src = HaveMTEExtZ() then[t];
bits( SetTagCheckedInstructionPL(TRUE);
if) mask = AnyActiveElementP(mask, esize) then
base =[g];
bits(64) addr;
constant integer mbytes = msize DIV 8;
if ZHaveMTEExt[n];
offset =() then XSetTagCheckedInstruction[m];
src = Z[t];
(TRUE);
for e = 0 to elements-1
if ElemP[mask, e, esize] == '1' then
bits(64) addr = addr = ZeroExtend(Elem[base, e, esize], 64) + offset;
Mem[addr, mbytes, AccType_STREAM] = Elem[src, e, esize]<msize-1:0>;
Internal version only: isa v32.13v32.12, AdvSIMD v29.05v29.04, pseudocode v2020-12v2020-09_xml, sve v2020-12v2020-09_rc2b
; Build timestamp: 2020-12-16T142020-09-30T19:4116
Copyright © 2010-2020 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.
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