Cortex-A65AE

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Architecture Document

Version: 2025-03

Recommended

March 25, 2025

Arm A-profile Architecture Registers

This document provides descriptions in HTML format for the A-profile system registers and memory-mapped registers.

BPIALL: Branch Predictor Invalidate All

Purpose ... opc1 CRn CRm opc2 0b1111 0b000 0b0111 0b0101 0b110 if !IsFeatureImplemented(FEAT_AA32EL1) then UNDEFINED; elsif PSTATE.EL == EL0 then

ATS1CPRP: Address Translate Stage 1 Current state PL1 Read PAN

CRn CRm opc2 0b1111 0b000 0b0111 0b1001 ... if !(IsFeatureImplemented(FEAT_AA32EL1) && IsFeatureImplemented(FEAT_PAN2)) then UNDEFINED; elsif PSTATE.EL == EL0 then

Architecture Document

Version: 2025-03

March 25, 2025

Arm A-profile A64 Instruction Set Architecture

This document provides descriptions in HTML format for the A-profile A64 Instruction Set Architecture.

BTI: Branch target identification.

For more information, see PSTATE.BTYPE. ... System (FEAT_BTI) 31 30 29 28 27 26 25 24 23 22 21 ... 3 2 ... 1 ... 0 ... x ... CRm op2

CBLT (register): Compare signed less than register and branch: an alias of CB<cc> (register).

8 7 6 5 4 3 2 ... sf ... 1 ... 0 ... cc ... CBLT <Wm>, <Wt>, <label> ... Applies when (sf == 1) ... is equivalent to CBGT <Xt>, <Xm>, <label> Assembler Symbols

Architecture Document

Version: 2025-03

March 25, 2025

Arm A-profile A32/T32 Instruction Set Architecture

This document provides descriptions in HTML format for the A-profile A32 and T32 Instruction Set Architecture.

A32 Instructions by Encoding

1 0 cond op0 op1 Decode fields Instruction details ... 00x Data-processing and miscellaneous instructions ... 010 ... != 1111 011 ... Media instructions 10x

Branch, branch with link, and block data transfer

Load/Store Multiple ... Branch (immediate) Exception Save/Restore The encodings in this section are decoded from Branch, branch with link, and block ... 31 30 29 28 27

Architecture Document

Version: L.a

Recommended

December 10, 2024

Arm Architecture Reference Manual for A-profile architecture

This Manual describes the Arm® architecture v8, Armv8, and the Arm® architecture v9, Armv9. The architecture describes the operation of an Armv8-A and an Armv9-A Processing element (PE).

PDF - 100.3 MB

Architecture Document

Version: 2024-12

December 17, 2024

TLBIASIDIS: TLB Invalidate by ASID match, Inner Shareable

This document provides descriptions in HTML format for the A-profile system registers and memory-mapped registers.

Architecture Document

Version: 2024-12

December 17, 2024

BFXIL: Bitfield extract and insert at low end: an alias of BFM.

This document provides descriptions in HTML format for the A-profile A64 Instruction Set Architecture.

Architecture Document

Version: 2024-12

December 17, 2024

CMP (immediate): Compare (immediate).

This document provides descriptions in HTML format for the A-profile A32 and T32 Instruction Set Architecture.

Architecture Document

Version: 2024-09

September 30, 2024

Load/Store Word, Unsigned Byte (immediate, literal)

This document provides descriptions in HTML format for the A-profile A32 and T32 Instruction Set Architecture.

Architecture Document

Version: 2024-09

September 30, 2024

BFXIL: Bitfield extract and insert at low end: an alias of BFM.

This document provides descriptions in HTML format for the A-profile A64 Instruction Set Architecture.

Architecture Document

Version: 2024-09

September 30, 2024

TLBIMVAALIS: TLB Invalidate by VA, All ASID, Last level, Inner Shareable

This document provides descriptions in HTML format for the A-profile system registers and memory-mapped registers.

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