Infrastructure FVPs

The Neoverse Infrastructure compute subsystems are targeted at cloud-to-edge infrastructure markets.

Note:

• The software stack targeting these FVPs only supports a Linux host development environment.
• These models implement full mesh topologies but do not represent full CPU core counts for large scale infrastructure systems and are typically implemented with a maximum of 16 cores. Details are currently available to lead partners.
• For more information about reference designs, click the following cards. 

Click the following links to jump to the relevant FVP download section: Neoverse V3 r1, V3, V2, V1, N1 Edge, E1 Edge, and SGI-575 Reference Designs. 

Neoverse V3 r1 Reference Design FVP (RD-V3 r1) is based on the same major revision of system architecture and IP set as RD V3, but includes revision updates to key IPs, changes to memory/interrupt maps and a new topology configuration.

• RD-V3-r1: The primary reference platform is the RD-V3-r1 FVP download package. This includes a dual chip system model variant based on a 9x8 CMN mesh.
• RD-V3-r1-Cfg1: The RD-V3-r1-Cfg1 variant includes a quad chip system model, based on a smaller 3x4 CMN mesh. This derivative is designed to enable Partners prototyping the smaller topology in FPGA environments.

• RD-V3: The primary reference platform is the RD-V3 FVP download package. This includes both single chip (RD-V3) and quad (RD-V3-Cfg2) system model variants based on a 7x6 CMN mesh.
• RD-V3-Cfg1: The RD-V3-Cfg1 FVP download package includes a single chip system model with a smaller 3x3 CMN mesh. This derivative is designed to enable Partners prototyping the smaller topology in FPGA environments.

RD V2 is an Arm compute subsystem targeted at cloud-to-edge infrastructure markets.

The RD-N2 Technical Overview provides detailed information on the subsystem the FVP models.

• RD-N2: The primary reference platform is the RD-N2 download package. This includes both single and quad (RD-N2-Cfg2) chip system model variants based on a 6x6 CMN-700 mesh.
• RD-N2-Cfg1: The RD-N2-Cfg1 FVP download package includes a single chip system model with a smaller 3x3 CMN-700 mesh. This derivative is designed to enable Partners prototyping the smaller topology in FPGA environments.
• RD-N2-Cfg3: The RD-N2-Cfg3 FVP download package includes a single chip system model with a 10x6 CMN-700 mesh. This derivative is designed to provide Partners with an example of configuring the Genesis N2 Chiplet CSS RTL mesh topology in firmware.

The Neoverse V1 Reference Design FVP download provides an FVP model of both a single chiplet subsystem and a reduced core count quad chiplet subsystem. The Neoverse V1 Reference Design Software Developer Guide provides detailed information on the subsystem the FVP models.

The Neoverse N1 Edge Reference Design FVP download provides a single and dual chip FVP implementation. Basic system information is available in the Arm Fast Models documentation.

This compute subsystem is based around the E1 multithreading (SMT) microarchitecture CPU and targets data transport workloads in infrastructure markets. Basic system information is available in the Arm Fast Models documentation.

This legacy compute subsystem is based on a previous System Guidance series of Reference Designs for Infrastructure applications. Learn more about SGI-575 on Arm Community.

View the FVP EULA

View all Ecosystem FVPs