Neoverse N1 SDP

Key Resources

Specifications

The Neoverse N1 System Development Platform (SDP) is an N1 CPU-based development platform for hardware prototyping, software development, system validation, and performance profiling or tuning. N1 SDP platform consists of a hardware board with Neoverse N1 SoC running a complete Armv8.2-A open-source software stack that is available through GitHub and other hosting sites such as Linaro.

Development Platform	Armv8.2-A
Clusters	Two dual-core Neoverse N1 CPU
System-on-Chip Compliant Architecture	Server Based System Architecture v3. Server Based Boot Requirements.
Supports	Dual-channel DDR4-2667 memory. x16 PCIe or CCIX Gen4 links for coherent chip-to-chip attach through CCIX. Real-time debug and trace capability using CoreSight SoC-400. Full speed operation for N1 CPUs.
Linux Software Package for N1 SDP	Trusted Firmware-A. AArch64 Linux kernel with supporting file systems and drivers including those for PCIe and CCIX, chip-to-chip boot, and symmetric multi-processing. Universal Extensible Firmware Interface (UEFI) and Advanced Configuration and Power Interface (ACPI) support.
N1 backplane fabric	Coherent mesh interconnect (CMN-600). I/O Memory Management Unit (MMU-600). Generic Interrupt Controller (GIC-600).
Enables	AArch64 kernel and tools development for Neoverse N1 platform. PCIe Gen4 and CCIX ecosystem development. Secure boot, OS, and hypervisor development through Trusted Firmware-A. Development of coherent acceleration use cases using a CCIX compatible FPGA board that connects over CCIX link to the Neoverse N1 board. Real-time debug using P-JTAG and 32-bit trace debug.
Manufacturing Process	7nm targeting CPU
Frequency	2.6GHz
Hardware Features	Dual-core, dual-cluster SMP configuration with a total of 4 N1 CPUs. N1CPU 2.6GHz operating speed Caches (per core): L1 64kB instruction cache and data cache, 1MB private L2 cache Caches (shared): shared 2MB L3 between all cores, 8MB shared system level cache (SLC), both can be configured down to size zero Internal CMN-600 interconnect operating up to 2GHz. GIC-600 and MMU-600 for interrupt management and I/O virtualization support. 2 x 72-bit DMC-620 memory controller for dual channel DDR4 2667MHz memory. Two Cortex-M7 CPUs functioning as System Control Processor (SCP) and Management Control Processor (MCP) for supporting event logging, power and device management. CoreSight SoC-400 functional debug and trace capability.
Board expansion support with corresponding external ports	1x CCIX Gen4 x16 port: Support for one x16 CCIX capable adapter card. 1x PCIe x16 Gen3 link to 48-lane switch with downstream slots and peripherals: x16 PCIe Gen3 x8 PCIe Gen3 x1 PCIe Gen3 x1 Gigabit Ethernet x1 SATA III x1 USB 3.0 32-bit MIPI-60 trace port, JTAG debug port and Arm CoreSight 20 JTAG connector for debug only. Optional PCIe Gen3 riser card kit to connect two N1 SDP boards back-to-back over CCIX for Symmetric Multi-Threading (SMT) operation.
Software Features Available from Arm	SCP Firmware: System initialization, cold boot flow, control clocks and, device management. Trusted Firmware-A: Provides a reference implementation of Secure world software for Armv8-A, including a Secure monitor executing at Exception level 3 (EL3). 64-bit Linux drivers including those for PCIe, CCIX, SMP, and more. UEFI and ACPI support. Scripts for downloading open-source components including Linux kernel.

Components

OPEN SOURCE SOFTWARE

SCP Firmware

System initialization, cold boot flow, control clocks and, device management

SOFTWARE STANDARDS

Trusted Firmware-A

Provides a reference implementation of Secure world software for Armv8-A, including a Secure monitor executing at Exception level 3 (EL3).

SOFTWARE STANDARDS

Advanced Configuration and Power Interface (ACPI)

An industry standard, provided by the UEFI forum, where Arm is a board member.

SYSTEM IP

CoreLink CMN-600

The Arm CoreLink CMN-600 Coherent Mesh Network is designed for intelligent connected systems.

SYSTEM IP

CoreLink MMU-600

The MMU-600 is a System-level Memory Management Unit (SMMU) that translates an input address to an output address.

SYSTEM IP

CoreLink GIC-600

The CoreLink Generic Interrupt Controller-600 (GIC-600) detects, manages, virtualizes and distributes interrupts for Armv8.0-A processors.

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