Approach

The course uses on demand training videos blended with live instructor led sessions delivered virtually via Zoom. Learning activities such as interactive workbooks, walkthrough examples and quizzes are also incorporated into the training to help bring the learning to life. A pre course call with the engineer delivering the training is also recommended to ensure we meet your specific teams training needs.

Course Details

Total Duration	3 days
Scheduling	Multiple 1/2 day sessions
Delivery Method	Instructor led live classroom with supporting online video where relevant
Location	Virtual via Zoom - other options available on request
Audience	SoC / Interconnect architects designing the interconnect back plane / memory subsystem. Integration and verification engineers who will need to configure and verify the functionality of the coherent interconnect
Prerequisites	Experience with coherent bus protocols and/or interconnects is helpful although not required Basic understanding of Arm architecture memory types is helpful although not required
Related Products	CoreLink CMN-700, CMN-600, CMN-600AE, CI-700, CCI-550, CCI-500, CCI-400

Topics

Agendas will be created from the following list of fundamental and optional topics. Optional topics can be used to tailor the training to meet your specific, mobile, infrastructure or architectural design.

Key:* Online and on-demand
Fundamental Topics - for CHI based interconnects	Fundamental Topics - for ACE based interconnects
AMBA5 CHI protocol detailed overview CHI protocol fundamentals Transaction flows DVM operations Atomics overview Cache stashing Direct Memory Transfer (DMT) and Direct Cache Transfer (DCT) IO Deallocation RAS features MPAM MTE CoreLink Coherent Interconnect Hardware Overview Cache coherency System Address Map Initialization Error Handling Debug, Trace and PMU Cross-chip support QoS features ACE-Lite Integration Functional Safety (CMN-600AE only)	AMBA4 ACE protocol detailed overview: Channels and Signals Transaction Ordering RACK/WACK Exclusives Barriers DVM Transactions ACE-Lite CoreLink Coherent Interconnect Hardware Overview Functional behaviour QoS Error handling Programming Configuration Integration

Example Training Courses

Examples of how the above topics can be combined into differing course options are given below.

Arm CMN-700 Hardware Design

CHI.D
CHI.E
CMN-700 Overview
CMN-700 SAM
CMN-700 Initialization
CMN-700 HN-F and Coherency
CMN-700 Error Handling
CMN-700 Debug, Trace and PMU
CMN-700 ACE-Lite Integration
CMN-700 CML Overview