Release Notes for Arm® A32/T32 ISA XML for Arm®v8-A Architecture, up to and including Arm®v8.5 (00bet10).

Change history

The following changes are made:

  • DCPS instructions have been split into separate pages describing DCPS1, DCPS2, and DCPS3.
  • Pseudocode for A32 and T32 variants of VPMIN and VPMAX instructions is adjusted to remove a redundant check of when Q == '1'.
  • Uses of the name 'type' in the pseudocode have been renamed.

Known issues

  • The descriptions of CONSTRAINED UNPREDICTABLE behaviors for the A1 and A2 encodings of the STRBT, STRHT, and STRT are incorrect. These will be fixed in a future release.
  • The table for the "Advanced SIMD two registers and shift amount" class within the A32 and T32 encoding index page includes a column "imm3H:L" with the value "!= 0000" for all rows. This condition applies to all instructions in this table, and so is removed.
  • The encoding diagram for the "Advanced SIMD and floating-point 32-bit move" class within the A32 and T32 encoding index page shows bits[3:0] as "1111". This is incorrect, as the next level of decode shows these bits as "(0)(0)(0)(0)".