Release Notes for A64 ISA XML for Arm®v8-A Architecture, up to and including Arm®v8.5 (00bet10).
The following changes are made:
- The operation code for MSR (immediate) instruction is corrected to account for the TCO register. Also, the data structure in pseudocode that implements the PSTATE is updated to include a bit field for the TCO register.
- Pseudocode for LDRAA and LDRAB instructions is corrected to define the right order of trapping on these instructions.
- The STG(Z)(2)G and LDG(Z)(2)G instruction is updated to reflect the architectural change in the encoding and the syntax of these instructions.
- ISA XML descriptions and pseudocode added for newly introduced ARMv8.5-MemTag instructions, STGM, LDGM, STZGM (replaced with original STGV, LDGV, STZGV instructions).
- The function EL2Enabled() is corrected to reflect the effect of SecureEL2 in the case of when EL3 is not implemented or when the function is executed from EL3.
- The function CheckTag() related to MTE is corrected to use the right memory access function for accessing the in memory tag, used for comparison between a physical tag and an allocation tag.
- The function Vpart-non assignment form is corrected to return value from SVE register file as opposed to from SIMD&FP register file. The function is also corrected to permit register widths of 32-bit and 64-bit when part == 1.
- The function AArch64.TranslationTableWalk() is corrected to use VTCR_EL2.NSW and VSTCR_EL2.SW bits to derive the value of variable 'ns_table' which is used to set the security of the memory access reading the table.
- The function CombineS1S2Desc() is corrected to honour the rules for feature "Stage2 force write-back" to describe the resultant memory type after combining memory attributes from stage1 and stage2 translation descriptors.
- The function AArch64.TranslationTableWalk() is corrected to support the fact that blocks that are larger than the supported output address size is supported when using large output address functionality.
- The function SetPSTATEFromPSR is adjusted to implement the architectural relaxation where PSTATE.SSBS returns an UNKNOWN for an illegal exception return.
- The function AArch64.GenerateDebugExceptionsFrom() is corrected to describe the effect of Secure EL2.
- The function AArch64.CheckSystemAccess() is corrected to specify the read and write to PSTATE.DIT and PSTATE.SSBS bits using MRS / MSR (immediate) instructions.
- The function AArch64.TakeException() is corrected to use the right Exception class value in the reported fault when a memory access, due to Nested Virtualization, faults to generate a synchronous external abort under conditions where External Aborts are configured to be taken to EL3.
- The function AArch64.TranslationTableWalk() is corrected to specify that the maximum input address size for second stage of translation, is constrained by the implemented PA size.
- The function ELUsingAArch32() is corrected to specify that the SCR_EL3.RW is read as '1' when SCR_EL3.EEL2 is set to '1'. Also, the function is corrected to remove an incorrect check that EL2 is not using AArch32 in the current Security state.
- The functions HaveNVExt() and HaveNV2Ext() are modified to specify that the nested virtualization feature is optional.
- The functions AddPAC() and Auth() are enhanced to specify further architectural enhancements to the PAC feature.
- The function AllocationTagAccessIsEnabled() is corrected to take into account the effect of SCR_EL3.NS bit.
- The function AArch64.S1AttrDecode() is modified to specify the effects of MTE on stage1 memory attribute decode during address translation.
- The function AddressWithAllocationTag() is corrected to specify the effects of SCR_EL3.ATA, HCR_EL2.ATA, SCTLR_ELx.ATA or SCTLR_ELx.ATA0 control bits.
- Various corrections to the ISA encoding tables.
- Address translation does not take into account the fact that HCR_EL3.DCT bit only effects stage 1 translation and not stage 2. Also, when combining the stage 1 and stage 2 memory attributes, the accesses to memory are Tagged, when the combined effects of stage 1 and stage2 translations define memory as Normal memory, Inner and Outer Write-Back Non-Transient Read-Allocate Write-Allocate.
- The function AArch64.AllocationTagFromAddress() incorrectly describes the function as returning '0000' if access to allocation tags is disabled.
- In instructions IRG, ADDG, SUBG, LDG, the conversion from LogicalTag to AllocationTag based on bit in the Xn value, is incorrect. This conversion based on bit will be removed. Also, the functions AArch64.TransformTag(), AArch64.AddressWithAllocationTag(), AArch64.AllocationTagFromAddress() does not reflect this simplification of converting between a Logical and a Physical Tag.
- The function AArch64.EffectiveTCF() is missing code to cover the case where SCTLR_ELx.TCF or SCTLR_ELx.TCF0 is set to the reserved '11' value.
- The PC Sample-based Profiling Extension is not fully described, so the changes to this area in Armv8.2 are not implemented.
- The encoding diagram for "LSL (immediate)" shows the field "imms" in bits[15:10] as "!= x11111". This is incorrect because the 64 bit variant permits the value "011111", therefore this condition will be removed.
- The description for HINT overlaps with other defined instructions.