Release Notes for A64 Instruction Set Architecture for Armv8.5-A 2019-06 (bet)

Change history

The following general changes are made:

  • SVE instructions that may be prefixed by a MOVPRFX instruction now contain Operational information that describes which variants of MOVPRFX can be used, and the register constraints to be honored to guarantee predictable behavior.

The following changes are made to the instruction definitions:

  • The instruction description of HVC has been corrected to describe when the instruction is UNDEFINED.
  • The SVE Permute Vector - Predicated table has two new UNALLOCATED entries:

    op1 op2 op3
    0 111 0
    0 111 1
  • The description of the Secure Monitor Call (SMC) instruction has been altered to include behavior when EL2 is enabled in the current security state.
  • The Prefetch Memory (immediate), PRFM, instruction was missing from the 00bet10 XML release. That defect has been rectified.
  • The CPY(immediate) instruction has been split into CPY (immediate, merging) and CPY (immediate, zeroing).
  • All assembler mnemonics accepted by assemblers are not case-sensitive, and the AXFlag and XAFlag instructions have been made uppercase.

The following changes are made to the Shared Pseudocode:

  • The FPToFixedJS() pseudocode function is corrected to describe the effect when FPCR.FZ == '1' with a positive denormal number as the input. This affects the behavior of the FJCVTS instruction.
  • The Watchpoint and Breakpoint Debug pseudocode is updated to reflect the behavior expected for Secure EL2.
  • Added CheckValidStateMatch() as a refactor to StateMatch() as part of Secure EL2 corrections to Debug behavior.
  • The function CountEvents() is corrected for the behavior expected for Secure EL2.
  • The Watchpoint Debug pseudocode corrected for ARMv8.4-NV.
  • The function CollectRecord() is corrected for behavior expected for ARMv8.3-SPE.
  • The function AArch64.EffectiveTCF() is expanded to handle Reserved SCTLR_ELx.TCF.
  • The function AArch64.AddressWithAllocationTag() is modified to check for access to allocation tags.
  • The function AArch64.TransformTag() is replaced by AArch64.PhysicalTag().
  • Added IsCorePowered() to describe when the Core power domain is powered on.
  • Implemented the ARMv8.3-DoDP feature.
  • The MPAMisVirtual() function is updated to test for TGE and E2H.
  • Added HaveELUsingSecurityState() to identify if a given Exception level and Security state is supported.
  • Corrections to the implementation of ARMv8.4-FWB.

Known issues

  • The PC Sample-based Profiling Extension is not fully described in the pseudocode, so the changes to this area in Armv8.2 are not implemented.
  • The encoding diagram for "LSL (immediate)" shows the field "imms" in bits[15:10] as "!= x11111". This is incorrect because the 64 bit variant permits the value "011111", therefore this condition will be removed.
  • The description for HINT overlaps with other defined instructions. The definitive reference for the instruction encodings in this area of the ISA is the Arm Architecture Reference Manual.
  • The function CombineS1S2Desc() contains an incorrect expression for NSPACE(NoFault)(), this should instead be a function call to NoFault().
  • In the pseudocode functions LSL_C(), LSR_C() and ASR_C() the recently added clamping of the shift amount to the element size may generate an incorrect carry flag value for the AArch32 LSLS, LSRS, and ASRS instructions. The line "shift = if shift > N then N else shift;" is removed.
  • The SVE MOV(S) aliases of AND(S) (predicates), ORR(S) (predicates) and SEL (predicates) are missing a qualifier to differentiate the different types of instructions.
  • The SVE CLASTA (vectors), CLASTB (vectors), COMPACT, LASTA (vectors), LASTB (vectors), and SPLICE instructions incorrectly state that they can be used with a predicated MOVPRFX instruction.
  • In the optimized ISA, the BTI instruction is described as a NOP instead of setting BTypeNext to '00'.