Release notes for the AArch32 Instruction Set Architecture for Armv8.6-A (2020-06)

Change history

The following general changes are made:

The following changes are made to the instruction definitions:

  • In the VFMAB and VFMAT descriptions, the Assembler Symbols section incorrectly referred to 'T' in the encoding field. This has been corrected to refer to 'Q'.
  • In the ISA XML format, multiple <iclass> elements containing a single encoding each, the hrefs in <classesintro> and ID of <iclass> would equal the encoding name. This would happen only in this case.
    These IDs are now unique.
    There is no change in the representation of data in HTML or PDF.
  • An encoding clash in the "System register access, Advanced SIMD, and floating-point" section has been fixed.
  • In the top-level 32-bit decode table of the T32 encoding index, the "Data-processing (plain binary immediate)" class is now qualified by op1 = 'xxxx0' and a new UNALLOCATED row has been added for op0 = '10x1', op1 = 'xxxx1', op3 = '0'.
  • T32 Data-processing (register) encodings now explicitly state that encodings for op1 != 1111 are UNALLOCATED.
  • "The A32 and T32 ISA Advanced SIMD and floating-point load/store tables contained entries for VSTR and UNALLOCATED with duplicate encodings. The entries for UNALLOCATED have been removed."
  • The VCMLA encoding was overlapping with UNALLOCATED. It has been corrected in this release.
  • The encoding of VFMAL in T32 state has been corrected so that op2 is '10'.
  • All VST4 (single 4-element structure from one lane) instructions now appear on the same page.

The following changes are made to the Shared Pseudocode:

  • The Pseudocode functions AArch64.CountEvents() and AArch32.CountEvents() are updated to add checks to prohibit cycle counting if FEAT_PMUv3p5 Extension is implemented. AArch64.CountEvents() is also updated to add checks on AArch64 registers when setting filter bits. AArch32.CountEvents() is also updated to add declaration for hpmd variable.
  • The Pseudocode function ALUExceptionReturn() is updated to be explicit with CONSTRAINED UNPREDICTABLE choices for AArch32 instructions when the destination register is the PC.
  • The shared Pseudocode function AArch32.FirstStageTranslate() is corrected to not do the domain fault checks during address translation for AArch32 cache maintenance operations.
  • In the T32 encoding index, clarified that the "Data-processing (register)" instruction class is only valid when op1 = '1111'.
  • The Pseudocode function Halt() is corrected to set PSTATE.<SSBS, IT, T> to UNKNOWN, PSTATE.TC0 to 1, and PSTATE.BTYPE to 0.
  • The Pseudocode function SetPSTATEFromPSR() is updated to correctly reflect the values to various PSTATE bits on an illegal exception return.
  • The Pseudocode functions AArch64.CheckWatchpoint() and AArch32.CheckWatchpoint() are updated to set the external debug watchpoint address register EDWAR when PE enters the debug state for a watchpoint.
  • For compatibility between AArch32 and ARMv7, the pseudocode is corrected so that T32 instructions at the hardware-aligned address after the exception vector do not generate VCR exceptions.

Known issues

  • For instructions CSDB and ESB the T1 encoding shows CSDB{<c>}.W This is incorrect, it should be CSDB{<c>}.{<q>}
  • In the PDF diff files the operations pseudocode for some instructions has a defect in presentation for the 'when' condition. Where this defect is present, the action is appended to the condition on the same line, rather than being on the following line.
  • Some architectural features have limited or no descriptions in the Pseudocode and are not fully covered by the functional testing. Affected features are listed below:
    • Address translation system instructions
    • Ordering of memory accesses
    • Self-hosted debug and behaviour of PE when in debug state (external debug)
    • Trace architecture (Includes self-hosted trace and external trace)
    • RAS architecture
    • Statistical profiling
    • Performance monitor counter
    • Activity monitor
    • Generic timer
    • Generic Interrupt Controller
    • Multi-processing