Release notes for the A64 Instruction Set Architecture for Armv8.7-A
(2021-03)

31 March 2021

Product Status

The information in this release is at Beta quality. Beta quality means that all major features of the specification are included, some details might be missing.

Change history

The following general changes are made:

  • The pseudocode for VMSAv8-64 is rewritten with the intent of:
    • Improved structure and readability.
    • More consistent use of terminology, aligned with the normative text in chapter D5, "The AArch64 Virtual Memory System Architecture".
    • Decoupling of translation configuration from the walk process and fault reporting mechanisms.
  • The pseudocode for FEAT_LPA2 is added.
  • The pseudocode for FEAT_XS is added.
  • The pseudocode functions A64 TLBI System instructions are renamed.
  • The pseudocode function BranchTo() is updated to add a boolean parameter branch_conditional, indicating whether the branch taken was conditional. All calls to the function are updated accordingly.
  • Where encodings of the same instruction are differentiated by the value of a single field, their encodings in the encoding index are not merged unless all possible values of that field are explicitly specified.

 

The following changes are made to the instruction definitions:

  • In CFP, CPP, and DVP, mentions of speculation being observable in side channels have been removed, and clarification that predictions cannot be used to exploitatively control speculative execution is added.

 

The following changes are made to the Shared Pseudocode:

  • The HaveUA16Ext() function is renamed to HaveLSE2Ext() throughout the codebase.
  • The pseudocode function CheckAllInAlignedQuantity() is added.
  • The MemSingle[] functions are updated to use CheckAllInAlignedQuantity() if LSE2 is implemented.
  • The Mem[] functions are updated to relax atomicity checks for Normal memory if LSE2 is implemented.
  • The pseudocode for LDP, LDNP and STP is updated to issue atomic reads and writes if LSE2 is implemented and the accesses are to Normal memory.
  • SSBB and PSSBB are changed from machine instructions to architectural aliases of DSB, equivalent to DSB #0 and DSB #4 respectively. The pseudocode for DSB is expended to reflect this functionality.
  • The psuedocode for OSLockStatus() and SoftwareLockStatus() functions is included.
  • The pseudocode function AArch64.TakeExceptionInDebugState() is corrected to clarify that SCTLR[].IESB and/or SCR_EL3.NMEA might be ignored in Debug state.
  • The pseudocode functions AArch64.ExceptionReturn() and AArch64.TakeException() are corrected regarding sync errors when FEAT_DoubleFault is implemented and FEAT_IESB is not implemented.
  • E0PD checks from the pseudocode function AArch64.TranslationTableWalk() are moved into the function AArch64.FirstStageTranslate().
  • The pseudocode function AArch64.FaultSyndrome() is corrected to check for a Synchronous External abort when setting iss<12:11>.
  • The pseudocode function AArch64.AccessIsTagChecked() is corrected: cache maintenance instructions excluded from a tag check.
  • The pseudocode function AArch64.TagCheckFault() is corrected to handle the CONSTRAINED UNPREDICTABLE case when FEAT_MTE3 is not implemented and TCF == '11'.
  • The pseudocode function AArch64.S1Translate() is updated to show relaxation on the effect of SCTLR_ELx.C == '0' on whether the resultant memory attributes are Tagged as CONSTRAINED UNPREDICTABLE.
  • The pseudocode function AArch64.EffectiveTCF() now uses translation regime instead of Execution context.
  • The Pseudocode function FPDefaultNaN() is updated to take an FPCRType parameter and calls to this function are updated accordingly.
  • The pseudocode function GenMPAMcurEL() is corrected to generate the PARTID under right conditions.
  • The pseudocode function TLBI_RIPAS2() is corrected to account for the distinction between the Non-secure and Secure IPA spaces.
  • The operational pseudocode for UZP1 and UZP2 instructions is updated to support vector lengths that are odd multiple of 128bits.

 

Known issues

  • In the browsable XML, hyperlinking with some pseudocode functions do not link correctly.
  • Clarification required to MRS/MSR instruction behavior with the SYS instruction following relaxation.
  • The Pseudocode function AArch32.CheckWatchpoint() is updated to check for excluded data types and scenarios.
  • The pseudocode for the AArch32 LDC and STC instructions do not show possible traps to Hyp mode.
  • In the pseudocode function AArch64.BreakpointValueMatch(), the BXVR_match check is missing.
  • Some architectural features have limited or no descriptions in pseudocode and are not fully covered by the functional testing. Affected features are listed below:
    • Address translation, Instruction Cache, Data Cache System instructions.
    • Ordering of memory accesses.
    • Self-hosted and halting debug.
    • Self-hosted trace and external trace.
    • RAS architecture.
    • Statistical Profiling Extension.
    • Performance Monitors Extension.
    • Activity Monitors Extension.
    • Generic Timers.
    • Generic Interrupt Controller.
    • Multi-processing.

 

Potential upcoming changes

  • The pseudocode for IC and DC System instructions will be added.
  • The pseudocode for AT System instructions will be added and will correctly account for the determination of EL.