Release notes for the AArch32 Instruction Set Architecture for Armv8.7-A
(2021-03)

31 March 2021

Product Status

The information in this release is at Beta quality. Beta quality means that all major features of the specification are included, some details might be missing.

Change history

The following general changes are made:

  • The pseudocode for VMSAv8-32 is rewritten with the intent of:
    • Improved structure and readability.
    • Decoupling of translation configuration from the walk process and fault reporting mechanisms.
  • Pseudocode functions for A32 TLBI System instructions are added.
  • The pseudocode function BranchTo() is updated to add a boolean parameter branch_conditional, indicating whether the branch taken was conditional. All calls to the function are updated accordingly.
  • Where encodings of the same instruction are differentiated by the value of a single field, their encodings in the encoding index are not merged unless all possible values of that field are explicitly specified.

 

The following changes are made to the instruction definitions:

  • Half-precision to single- or double-precision variants of VCVTB and VCVTT are corrected to give the proper values of their 'size' decode fields: size==10 when converting to a single-precision register, and size==11 when converting to a double-precision register.
  • CONSTRAINED UNPREDICTABLE text for 'wback && n==15' is removed from the T4 encoding of STR (immediate) and T3 encoding of STRB (immediate).
  • The A1 and T1 encodings for the following instructions are corrected to show the relevant associated feature FEAT_AA3218MM: VUMMLA, VSUDOT, VSMMLA, VUSDOT (by element), VUSDOT (vector), and VUSMMLA.
  • The T1 encoding of the VDOT (by element) instruction is corrected to show the relevant associated feature FEAT_AA32BF16.

 

The following changes are made to the Shared Pseudocode:

  • A redundant UNPREDICTABLE check is removed from the VLD1 and VST1 (multiple single elements) T1 and A1 instructions. The variable 'regs' is renamed to 'pairs' for the VLD2 and VST2 (multiple 2-element structures) instructions.
  • The psuedocode for OSLockStatus() and SoftwareLockStatus() functions is included.
  • The pseudocode function AArch32.FullTranslate() is updated to select the correct translation regime of stage 1, accounting for monitor mode and host mode.
  • The pseudocode function AArch32.FaultSyndrome() is corrected to check for a Synchronous External abort when setting iss<12:11>.

 

Known issues

  • The Pseudocode function AArch32.CheckWatchpoint() is updated to check for excluded data types and scenarios.
  • The pseudocode for the AArch32 LDC and STC instructions do not show possible traps to Hyp mode.
  • In the browsable XML, hyperlinking with some pseudocode functions do not link correctly.
  • Some architectural features have limited or no descriptions in pseudocode and are not fully covered by the functional testing. Affected features are listed below:
    • Address translation, Instruction Cache, Data Cache System instructions.
    • Ordering of memory accesses.
    • Self-hosted and halting debug.
    • Self-hosted trace and external trace.
    • RAS architecture.
    • Statistical Profiling Extension.
    • Performance Monitors Extension.
    • Activity Monitors Extension.
    • Generic Timers.
    • Generic Interrupt Controller.
    • Multi-processing.

 

Potential upcoming changes

  • The pseudocode for IC and DC System instructions will be added.
  • The pseudocode for AT System instructions will be added and will correctly account for the determination of EL.