Release notes for the AArch32 Instruction Set Architecture for Armv8.7-A 2020-12

Product status

The information in this release covers multiple versions of the architecture. The content relating to different versions is given different quality ratings.

The information in this release relating to v8.7 of the architecture and the features introduced in this release is at Alpha quality. Alpha quality means that most major features of the specification are included, features and details might be missing.

The information in this release relating to versions of the architecture before v8.7 and features introduced in previous releases is at Beta quality. Beta quality means that all major features of the specification are included, some details might be missing.

Change history

The following general changes are made:

  • The UNDEFINED checks in the decode pseudocode for the VRECPE and VRSQRTE instructions is updated.
  • The encoding for T5 SUB, SUBS (immediate) is corrected.
  • The mask from pseudocode for MRS operation is updated to allow bits 23,22,21 of APSR to be read.

The following changes are made to the instruction definitions:

  • None.

The following changes are made to the Shared Pseudocode:

  • Removed unused function ReservedValue().
  • The decoding of Load/Store Multiple instructions inside FirstStageTranslation is replaced by a new memory accessor type AccType_ATOMICSTREAM.
  • Removed unused function UnallocatedEncoding().
  • Permission checks for Data/Instruction cache maintenance instructions corrected.
  • The pseudocode function AArch64.SecondStageTranslate() and AArch64.SecondStageTranslate() is updated to not generate an alignment fault to a memory location marked as Device for stage 2 for stage 1 walks.
  • The pseudocode function AArch32.GenerateDebugExceptionsFrom() is updated to check MDCR_EL3.SDD bit for debug exceptions enable when SecureEL2 is implemented.
  • The pseudocode function CollectTimeStamp() is adjusted to include the missing reserved value checks.
  • The pseudocode functions AArch32.GenerateDebugExceptionsFrom() is updated to call AArch64.GenerateDebugExceptionsFrom() function if the debug target exception level is in AArch64 execution state.
  • The pseudocode function AArch64.BranchTargetException() is removed from A32 ISA XML.
  • The pseudocode functions AArch64.CheckPermission() and AArch32.CheckPermission() are updated to initialize priv_xn and user_xn prior to PAN checks that re determines the value of priv_w.
  • The pseudocode function TraceTimeStamp() is updated to not treat the value '10' for TRFCR_EL1.TS and TRFCR_EL2.TS as UNPREDICTABLE in all cases.
  • The pseudocode function IsSErrorEdgeTriggered() takes a new parameter indicating the target Exception level. This function now checks the Execution state of the target Exception level to determine the correct syndrome checks.
  • The access type AccType_DC_UNPRIV is now qualified with PSTATE.EL and AccType_DC. DC_UNPRIV usage is removed from the pseudocode.
  • Enumeration literal Unpredictable_PMUEventCount is added for Constrained Unpredictable access to Performance Monitor Event Count register access.
  • Enumeration literal Unpredictable_IGNORETRAPINDEBUG is added for register access trap ignore in Debug state.
  • The pseudocode for FEAT_XS is partially included in this release.

Known issues

  • The execution pseudocode for the AArch32 LDC and STC instructions do not show possible traps to Hyp mode.
  • The entries for 'VCVTB - Half-precision to double-precision variant' and 'VCVTT - Half-precision to double-precision variant' in the 'Floating-point data-processing (two registers)' encoding tables are missing the value for the 'size' field. This will be fixed in a future release.
  • The pseudocode for FEAT_XS is not available in full. Effect of FEAT_XS on memory attributes and on A32 TLBI instructions is not present.
  • In the browsable XML, hyperlinking with some pseudocode functions do not link correctly.
  • Some architectural features have limited or no descriptions in pseudocode and are not fully covered by the functional testing. Affected features are listed below:
    • Address translation system instructions.
    • Ordering of memory accesses.
    • Self-hosted debug and behavior of PE when in Debug state.
    • Trace architecture, including self-hosted trace and external trace.
    • RAS architecture.
    • Statistical Profiling Extension.
    • Performance Monitors Extension.
    • Activity Monitors Extension.
    • Generic Timers.
    • Generic Interrupt Controller.
    • Multi-processing.

Potential upcoming changes

  • The Shared pseudocode for VMSA will be refactored.
  • The pseudocode for FEAT_XS and FEAT_LPA2 will be added.
  • The pseudocode for system instructions will be added.