Release notes for the AArch32 Instruction Set Architecture for Armv8.7-A
30 June 2021
The information in this release is at Beta quality. Beta quality means that all major features of the specification are included, some details might be missing.
The following general changes are made:
- Changed GetNumXXX() to NumXXXImplemented().
The following changes are made to the instruction descriptions:
- Refactored redundant check in VCVT (floating-point to integer, floating-point) and VCVT (integer to floating-point, floating-point) decode.
- Removed superfluous UNKNOWN assignment in VZIP and VUZP when d == m.
- Added xxxx0001011x case to A32 Move Special Register and Hints (immediate) decode table.
- Corrected HVC instruction descriptions to account for Secure EL2 and the HCR_EL2.HCD and HCR.HCD bits.
The following changes are made to the Shared Pseudocode:
- Removed unused function ReservedValue().
- The Pseudocode function AArch32.CheckWatchpoint() is updated to check for excluded data types and scenarios.
- AArch32.CheckAdvSIMDOrFPEnabled() checks of HCR_EL2 now checks EL2 is enabled in the current Security state. The check for !ELUsingAArch32(EL1) in the HCR_EL2.TGE == '1' case is removed.
- Pseudocode functions PhysMemRead() and PhysMemWrite() replace the _Mem accessor read and write forms and return a status structure instead of triggering external aborts, leaving the responsibility of handling aborts on the call sites.
- Pseudocode functions for AArch32 DC and IC System instructions are added and called from the System instruction accessibility pseudocode.
- Renamed the Pseudocode condition functions HaveAnyAArch32() to HaveAArch32() and HaveAnyAArch64() to HaveAArch64(), and updated the function comments to clarify their meaning. Removed the function HighestELUsingAArch32() and changed usage to !HaveAArch64().
- Pseudocode functions GenericCounterTick() and PhysicalCountInt() are defined.
- Overlapping definitions will be removed between UNALLOCATED when D==0 in System Register 64-bit move and UNDEFINED LDC (literal) in System register Load/Store.
- There is a mismatch between the encoding for VMOVL and some other instructions and the conditions defined for the groups they appear in. The encoding is correct. The group conditions for affected instructions will be clarified.
- The execution Pseudocode for the AArch32 LDC and STC instructions do not show possible traps to Hyp mode.
- In the browsable XML, hyperlinking with some Pseudocode functions do not link correctly.
- Some architectural features have limited or no descriptions in Pseudocode and are not fully covered by the functional testing. Affected features are listed below:
- Address translation, Instruction Cache, Data Cache System instructions.
- Ordering of memory accesses.
- Self-hosted and halting debug.
- Self-hosted trace and external trace.
- RAS architecture.
- Statistical Profiling Extension.
- Performance Monitors Extension.
- Activity Monitors Extension.
- Generic Timers.
- Generic Interrupt Controller.
Potential upcoming changes
- Pseudocode functions for AArch32 AT System instructions will be added and called from the System instruction accessibility pseudocode.