Release notes for the AArch32 Instruction Set Architecture for Armv8.7-A (2020-09)

Product status

The information in this release covers multiple versions of the architecture. The content relating to different versions is given different quality ratings.

The information in this release relating to v8.7 of the architecture and the features introduced in this release is at Alpha quality. Alpha quality means that most major features of the specification are included, features and details might be missing.

The information in this release relating to versions of the architecture before v8.7 and features introduced in previous releases is at Beta quality. Beta quality means that all major features of the specification are included, some details might be missing.

Change history

The following general changes are made:

  • The encoding table for "'Floating-point directed convert to integer" in A32/T32 ISAs is missing the 'op' column. This is now added.
  • In A32/T32 ISA, the 'Change Process State' table is updated to indicate that the values 'I' and 'F' must be 0 for SETEND.
  • The following tables are updated to extend the 'op2' field to include 10 and 11:
    • A32: System register access, Advanced SIMD, floating-point, and Supervisor call
    • T32: System register access, Advanced SIMD, and floating-point"
  • In the 'Unconditional instructions' on the 'Top-level encodings for A32', the op0 field is extended from covering bits[26:25] to bits[26:24].

The following changes are made to the instruction definitions:



The following changes are made to the Shared pseudocode:

  • The pseudocode function GetPSRFromPState() is updated to return a variable length value and SetPSTATEFromPSR() is updated to accept a variable length parameter. The functions Halt() and DebugExceptionReturnSS() are also updated to reflect these changes.
  • The pseudocode functions GetPSRFromPSTATE() and SetPSTATEFromPSR() now correctly copy to and from PSTATE.DIT on taking and returning from exceptions between AArch64 and AArch32 states. The pseudocode function Halt() is updated to remove code that now duplicates these efforts. The pseudocode function AArch64.FPTrappedException() is updated to remove the redundant argument "element". Also, the pseudocode function AArch32.FPTrappedException() is updated to remove the passing of the "element" argument to function AArch64.FPTrappedException().
  • The pseudocode function InterruptPending() is corrected to account for all sources of virtual interrupts.
  • The pseudocode function Halt() now assigns to the spsr variable instead of DSPSR when checking CONSTRAINED UNPREDICTABLE behaviour.
  • The pseudocode functions AArch32.TranslationTableWalkLD() and AArch32.FullTranslate() are updated to remove NV2 checks as those checks are only applicable in AArch64 state.
  • The pseudocode function AArch32.Abort() is corrected to use register HCR_EL2 when checking for routing to AArch64.
  • The pseudocode function AArch32.TranslationTableWalkSD() is updated to correct the checks for Stage 2 present in the current translation regime.
  • The pseudocode function ELIsInHost() is refactored to improve readability.
  • The Psuedocode function ExternalDebugInterruptsDisabled() is updated to show the change in EDSCR.INTdis width when ARMv8.4 Debug is implemented.
  • The pseudocode function DebugExceptionReturnSS() is updated to correct the check for ELUsingAArch32(dest) for the case where dest is EL0.
  • The pseudocode functions AArch64.WatchpointMatch() and AArch32.WatchpointMatch() are updated to correct the comment for "ispriv" argument to the functions.
  • The pseudocode function AArch32.ExceptionClass() is updated to remove Exception_ERetTrap and Exception_PACFail as they are AArch64 only exceptions.
  • The pseudocode functions AArch64.ExceptionClass() and AArch32.ExceptionClass() are corrected set the correct value for iL (instruction length) with a default value of '1' for cases where instruction length does not matter and to perform the assert check on the correctly set value of iL. Both checks of setting the value of iL and assert check on iL are moved from start of the functions to the end of the functions' body.
  • The pseudocode functions AArch64.AccessIsPrivileged() and AArch32.AccessIsPrivileged() are updated to remove duplicate checks for privileged access.
  • The pseudocode function SetPSTATEFromPSR() is updated to correctly reflect the values to various PSTATE bits on an illegal exception return.
  • The _Mem[] (non-assignment form) pseudocode accessor is updated to take an additional boolean parameter that signifies if a read is taking place as part of a write operation
  • Added checks before clearing pending physical SError in pseudocode functions AArch64.TakePhysicalSErrorException() and AArch32.TakePhysicalSErrorException().

Known issues

  • The new Armv8.7 pseudocode has been partially tested but may contain defects.
  • In the PDF diff files the operations pseudocode for some instructions has a defect in presentation for the 'when' condition. Where this defect is present, the action is appended to the condition on the same line, rather than being on the following line.
  • Some architectural features have limited or no descriptions in the Pseudocode and are not fully covered by the functional testing. Affected features are listed below:
    • Address translation system instructions
    • Ordering of memory accesses
    • Self-hosted debug and behaviour of PE when in debug state (external debug)
    • Trace architecture (Includes self-hosted trace and external trace)
    • RAS architecture
    • Statistical profiling
    • Performance monitor counter
    • Activity monitor
    • Generic timer
    • Generic Interrupt Controller
    • Multi-processing
  • The FPTrigSSel() function used by the SVE FTSSEL instruction has known issues with the modified NaN propagation rules.
  • The FTSMul() function used by SVE instruction FTSMUL has known issue that it will incorrectly generate an Input Denormal exception if the result is a denormal value.

Potential upcoming changes

  • The Shared pseudocode for VMSA will be refactored.