Release notes for the A64 Instruction Set Architecture for Armv9-A
(2021-06)

30 June 2021

Product Status

This release covers multiple versions of the architecture. The content relating to different versions is given different quality ratings.

The information related to features FEAT_RME and FEAT_SME is at Alpha quality. Alpha quality means that most major features of the specification are described in the manual, some features and details might be missing.

The information related to the remaining features is at Beta quality. Beta quality means that all major features of the specification are described, some details might be missing.

Change history

This is the A64 ISA XML for Armv9 (2021-06).

The following general changes are made:

  • This release of the Armv9 architecture XML introduces FEAT_SME, Scalable Matrix Extension.
  • Changed GetNumXXX() to NumXXXImplemented().
  • Translation regime to be considered in place of PSTATE.EL to populate TFSRE0_EL1 and TFSR_ELx in a Tag Check Fault.

The following changes are made to the instruction descriptions:

  • Feature names are added to SVE instructions.
  • Corrected HVC instruction descriptions to account for Secure EL2 and the HCR_EL2.HCD and HCR.HCD bits.
  • The SVE LD1R* load and broadcast instructions now generate Tag Unchecked access for a load or store that uses either of the following addressing modes:
    • A base register only, with the SP as the base register.
    • A base register plus immediate offset addressing form, with the SP as the base register.
  • Removed unused variable 'sboxout' from SM4E and SM4EKEY.
  • Corrected SABDL, SABDL2 instruction description to describe 'long' behavior instead of 'narrow' behavior.
  • USUBW, USUBW2 instruction description corrected to refer to 'unsigned integer values'.
  • Removed the loop from the operational Pseudocode for FRECPX half-precision, single-precision, and double-precision.
  • Operational information text has been added to SME instructions to indicate where subsequent instructions may be delayed due to dependencies on the general-purpose register, predicate register, or NZCV condition flags.

The following changes are made to the Shared Pseudocode:

  • Pseudocode functions PhysMemRead() and PhysMemWrite() replace the _Mem[] accessor read and write forms and return a status structure instead of triggering external aborts, leaving the responsibility of handling aborts on the call sites.
  • Removed unused function ReservedValue().
  • The Pseudocode function AArch32.CheckWatchpoint() is updated to check for excluded data types and scenarios.
  • EL2Enabled() qualifier now added with access to HCR_EL2, Exception logic improved for AArch64 routines.
  • In the Pseudocode function AArch64.BreakpointValueMatch(), the BXVR_match check is updated.
  • Pseudocode functions for AArch64 DC and IC System instructions are added and called from the System instruction accessibility pseudocode.
  • In the Pseudocode function AArch64.TakeException() and the AArch32.EnterXXXMode(), a call to CheckExceptionCatch(FALSE) is added after the calls to 'BranchTo()'.
  • The Pseudocode function AArch64.GenerateDebugExceptionsFrom() is updated to check SDER32_EL3.SUIDEN when Secure EL1 is using AArch32 and debug exceptions taken to SecureEL2.
  • Renamed the Pseudocode functions HaveAnyAArch32() to HaveAArch32() and HaveAnyAArch64() to HaveAArch64(), and updated the function comments to clarify their meaning. Removed the function HighestELUsingAArch32() and changed usage to !HaveAArch64().
  • IsVirtualSErrorPending() considered along with HCR_EL2.VSE for a pending virtual interrupt.
  • The Pseucocode function AArch32.ReportDataAbort() now adequately reflects when long/short descriptor format is used when reporting external aborts to monitor mode.
  • New Pseudocode functions GenericCounterTick() and PhysicalCountInt() have been defined.
  • The Pseudocode function AArch64.S2ApplyFWBMemAttrs() is updated to ensure the correct final shareability in the case when FWB is active and s2MemAttr<2:0> is '101' and stage 1 assigns device memory.
  • The Pseudocode function AArch64.S2ApplyFWBMemAttrs() is updated to ensure the correct final shareability in the case when FWB is active and stage 2 MemAttr<2:0> is '101' and stage 1 assigns Device memory or '111' and stage 1 assigns Device or Normal iNCoNC memory.
  • In Pseudocode function AArch64.CountEvents(), the sense of the SPME bit when used in conjunction with MPMX, is flipped.
  • The code extracting fields for TLBI operations for AArch64.TLBI_RVA(), is updated to avoid extracting non-existent 'NS' field in the argument register Xt.
  • The Pseudocode function AArch64.S2Translate() is simplified to remove redundant Alignment Fault check due to memory type when stage 2 is disabled.
  • In the code extracting fields for TLBI operations, specifically, TLBI VA and TLBI VAA, is updated to acquire the full set of bits representing the VA from the argument register Xt.
  • In the code extracting fields for TLBI operations, specifically those that operate on a range of input addresses, is updated to extract the correct range of bits in Xt representing TTL.
  • The Pseudocode function AArch64.WFxTrap() is updated to provide enhanced syndrome information for a trap on WFIT or WFET.
  • The Pseudocode function FPRoundBase() now checks if floating-point exceptions should be generated before setting FPSR.UFC to '1'.
  • The Pseudocode function GenMPAMcurEL() now returns the default PARTID and PMG when MPAM is not enabled.
  • The BRBINFINJ_EL1.TYPE and BRBINF<n>_EL1.TYPE field descriptions are updated to have two separate values for conditional and unconditional direct branches, and the function BRBEBranch() has been updated accordingly.
  • Added the EL2-related ALTSP behaviour for host applications at EL0.
  • In the Pseudocode functions AArch64.MemSingle[] (assignment and non-assignment form), MemLoad64B(), and MemStore64BWithRet(), the priority for RME granule protection checks is corrected to be higher than MTE Tag checking.

 

Known issues

  • Operational information in SME instructions updated for FEAT_SVE2 and FEAT_SME.
  • The Pseudocode description for RME does not include updates to debug functionality introduced by RME, nor its interactions with AMU or PMU. This includes the definition of the IsSecure() function not accounting for the new Security states introduced by RME.
  • Clarification for MSR and MRS action with unnamed registers.
  • The Pseudocode functions for TLBRecordType() and TLBContextType() are updated.
  • The description for FRECPX instruction will be clarified by removing incorrect references to vectors.
  • The SVE DUP (predicate) instruction introduced by FEAT_SME is expected to be renamed in the next XML release.
  • In the browsable XML, hyperlinking with some Pseudocode functions do not link correctly.
  • Some architectural features have limited or no descriptions in Pseudocode and are not fully covered by the functional testing. Affected features are listed below:
    • Address translation, Instruction Cache, Data Cache System instructions.
    • Ordering of memory accesses.
    • Self-hosted and halting debug.
    • Self-hosted trace, Trace Buffer Extension, and external trace.
    • RAS architecture.
    • Statistical Profiling Extension.
    • Performance Monitors Extension.
    • Activity Monitors Extension.
    • Generic Timers.
    • Generic Interrupt Controller.
    • Multi-processing.

 

Potential upcoming changes

  • Pseudocode functions for AArch64 AT System instructions will be added and called from the System instruction accessibility pseudocode.