Release notes for the A64 Instruction Set Architecture for Armv9-A

31 March 2021

Product Status

This release covers multiple versions of the architecture. The content relating to different versions is given different quality ratings.

The information related to feature FEAT_RME is at Alpha quality. Alpha quality means that most major features of the specification are described in the manual, some features and details might be missing.

The information related to the remaining features is at Beta quality. Beta quality means that all major features of the specification are described, some details might be missing.

Change history

This is the A64 ISA XML for Armv9 (2021-03).

The following general changes are made:

  • This is the first release of the V9 architecture, including the following optional features:
    • TRBE (Transaction Record Buffer Extension)
    • ETE (Embedded Trace Extension)
    • SVE2 (Scalable Vector Extension 2)
    • TME (Transaction Memory Extension)
    • BRBE (Brach Record Buffer Extension)
    • RME (Realm Management Extension)
  • The pseudocode for VMSAv8-64 and VMSAv8-32 is rewritten with the intent of:
    • Improved structure and readability.
    • More consistent use of terminology, aligned with the normative text in chapter D5, "The AArch64 Virtual Memory System Architecture".
    • Decoupling of translation configuration from the walk process and fault reporting mechanisms.
  • The pseudocode for FEAT_LPA2 is added.
  • The pseudocode for FEAT_XS is added.
  • The pseudocode functions A64 TLBI System instructions are renamed. Pseudocode functions for A32 TLBI System instructions are added.
  • The pseudocode function BranchTo() is updated to add a boolean parameter branch_conditional, indicating whether the branch taken was conditional. All calls to the function are updated accordingly.
  • Where encodings of the same instruction are differentiated by the value of a single field, their encodings in the encoding index are not merged unless all possible values of that field are explicitly specified.


The following changes are made to the instruction definitions:

  • In CFP, CPP, and DVP, mentions of speculation being observable in side channels have been removed, and clarification that predictions cannot be used to exploitatively control speculative execution is added.


The following changes are made to the Shared Pseudocode:

  • A redundant UNPREDICTABLE check is removed from the VLD1 and VST1 (multiple single elements) T1 and A1 instructions. The variable 'regs' is renamed to 'pairs' for the VLD2 and VST2 (multiple 2-element structures) instructions.
  • The HaveUA16Ext() function is renamed to HaveLSE2Ext() throughout the codebase.
  • The pseudocode function CheckAllInAlignedQuantity() is added.
  • The MemSingle[] functions are corrected to use CheckAllInAlignedQuantity() if LSE2 is implemented.
  • The Mem[] functions are updated to relax atomicity checks for Normal memory if LSE2 is implemented.
  • The pseudocode for LDP, LDNP and STP is updated to issue atomic reads and writes if LSE2 is implemented and the accesses are to Normal memory.
  • SSBB and PSSBB are changed from machine instructions to architectural aliases of DSB, equivalent to DSB #0 and DSB #4 respectively. The pseudocode for DSB is expended to reflect this functionality.
  • The psuedocode for OSLockStatus() and SoftwareLockStatus() functions is included.
  • The pseudocode function AArch64.TakeExceptionInDebugState() is corrected to clarify that SCTLR[].IESB and/or SCR_EL3.NMEA might be ignored in Debug state.
  • The pseudocode functions AArch64.ExceptionReturn() and AArch64.TakeException() are corrected regarding sync errors when FEAT_DoubleFault is implemented and FEAT_IESB is not implemented.
  • E0PD checks from the pseudocode function AArch64.TranslationTableWalk() are moved into the function AArch64.FirstStageTranslate().
  • The pseudocode function AArch32.FullTranslate() is updated to select the correct translation regime of stage 1, accounting for monitor mode and host mode.
  • AArch32.FaultSyndrome() and AArch64.FaultSyndrome() are corrected to check for a Synchronous External abort when setting iss<12:11>.
  • The pseudocode function AArch64.AccessIsTagChecked() is corrected: cache maintenance instructions excluded from a tag check.
  • The pseudocode function AArch64.TagCheckFault() is corrected to handle the CONSTRAINED UNPREDICTABLE case when FEAT_MTE3 is not implemented and TCF == '11'.
  • The pseudocode function AArch64.S1Translate() is updated to show relaxation on the effect of SCTLR_ELx.C == '0' on whether the resultant memory attributes are Tagged as CONSTRAINED UNPREDICTABLE.
  • The pseudocode function AArch64.EffectiveTCF() now uses translation regime instead of Execution context.
  • The Pseudocode function FPDefaultNaN() is updated to take an FPCRType parameter and calls to this function are updated accordingly.
  • The pseudocode function GenMPAMcurEL() is corrected to generate the PARTID under right conditions.
  • The pseudocode function TLBI_RIPAS2() is corrected to account for the distinction between the Non-secure and Secure IPA spaces.
  • The operational pseudocode for UZP1 and UZP2 instructions is updated to support vector lengths that are odd multiple of 128bits.
  • The pseudocode functions for AArch64.MemSingle[], in both its read and write form, are updated to add the missing transactional state access checks whereby the transactional memory access are guaranteed to be supported on the specified combination of memory type and memory attributes.
  • The pseudocode accessor function AArch32.MemSingle[] is updated to remove the TME related code since TME is only applicable in AArch64 context.
  • The shared pseudocode functions FilterBranchRecord(), BRBEBranch(), BranchTo(), and BranchToAddr() have been updated to correctly match on conditional or unconditional branches depending on the field values for BRBFCR_EL1.CONDIDInd and BRBFCR_EL1.DIRECT.
  • The pseudocode function BranchToAddr() has been simplified to remove a redundant call to BRBFCR_EL1.CONDDIR.


Known issues

  • Clarification required to MRS/MSR instruction behavior with the SYS instruction following relaxation.
  • The Pseudocode function AArch32.CheckWatchpoint() is updated to check for excluded data types and scenarios.
  • The pseudocode for the AArch32 LDC and STC instructions do not show possible traps to Hyp mode.
  • In the pseudocode function AArch64.BreakpointValueMatch(), the BXVR_match check is missing.
  • The pseudocode for MPAM for RME does not describe the EL2-related ALTSP behavior for host applications at EL0.
  • The pseudocode description for RME does not include updates to debug functionality introduced by RME, nor its interactions with AMU or PMU. This includes the definition of the IsSecure() function not accounting for the new Security states introduced by RME.
  • In the browsable XML, hyperlinking with some pseudocode functions do not link correctly.
  • Some architectural features have limited or no descriptions in pseudocode and are not fully covered by the functional testing. Affected features are listed below:
    • Address translation, Instruction Cache, Data Cache System instructions.
    • Ordering of memory accesses.
    • Self-hosted and halting debug.
    • Self-hosted trace, Trace Buffer Extension, and external trace.
    • RAS architecture.
    • Statistical Profiling Extension.
    • Performance Monitors Extension.
    • Activity Monitors Extension.
    • Generic Timers.
    • Generic Interrupt Controller.
    • Multi-processing.


Potential upcoming changes

  • The pseudocode for IC and DC System instructions will be added.
  • The pseudocode for AT System instructions will be added and will correctly account for the determination of EL.