Release notes for System Registers for Armv9-A
(2021-03)

31 March 2021

Product Status

This release covers multiple versions of the architecture. The content relating to different versions is given different quality ratings.

The information related to feature FEAT_RME is at Alpha quality. Alpha quality means that most major features of the specification are described in the manual, some features and details might be missing.

The information related to the remaining features is at Beta quality. Beta quality means that all major features of the specification are described, some details might be missing.

Armv9 change history

  • This is the first release of the V9 architecture, including the following optional features:
    • TRBE (Transaction Record Buffer Extension)
    • ETE (Embedded Trace Extension)
    • SVE2 (Scalable Vector Extension 2)
    • TME (Transaction Memory Extension)
    • BRBE (Brach Record Buffer Extension)
    • RME (Realm Management Extension)

 

Armv9 known issues

There are no known issues for this architecture version.

Armv8.7 change history

  • References to the System register VSTTBR_EL2 are removed from the VCTR_EL2.VS values table.
  • The accessibility pseudocode for the following registers is enhanced to describe when either the virtual or physical offset applies:
    • AArch64: CNTPCTSS_EL0, CNTPCT_EL0, CNTVCT_EL0, CNTVCTSS_EL0.
    • AArch32: CNTPCT, CNTPCTSS, CNTVCT, CNTVCTSS.
  • The lists of permitted values of MVFR1_EL1.SIMDHP and MVFR1.SIMDHP are corrected.
  • The HCR_EL2.TID2 field description is updated to indicate that the trap on EL0 accesses to CTR_EL0 when SCTLR_EL1.UCT is 0 is a higher priority than the trap due to HCR_EL2.TID2.
  • The accessibility pseudocode for the SDER32_EL2 register is corrected to include UNDEFINED exceptions in Non-secure state.
  • GIC, MPAM, AMU, and Generic Timer external register resets now described according to the power domain, GIC, MPAM, AMU, and Timer.
  • The accessibility pseudocode for the SDER register is corrected to include a debug access trap.
  • The EDSCR.INTdis field description is clarified to describe the behavior when FEAT_Debugv8p4 is not implemented.
  • The reset behavior of MPAM3_EL3.TRAP_LOWER is clarified to read that the field resets on a Warm reset rather than a Cold reset.
  • The descriptions in the WUE, UE, and ER fields in the following registers are updated to clarify when a deferred error can send an in-band error response:
    • AArch64: ERR<n>CTLR, ERR<n>FR and ERR<n>STATUS.
  • Text is added to ID_AA64PFR0_EL1 to clarify when FEAT_DoubleFault is present.
  • Clarification of SCTLR_EL3.IESB field behavior in Debug state.
  • Clarification of the reserved values of the NSE<n> and SE <n> fields in EDECCR: updates for when an Exception level is not implemented and for an additional qualifier on FEAT_SEL2, respectively.
  • ICC_BPR1_EL1.BinaryPoint field description is updated to include the effect of Secure EL2.
  • GITS_STATUSR.UMSI is clarified to remove the incorrect reference to GITS_SGIR.
  • In the following System instructions, mentions of speculation being observable in side channels are removed, and clarification that predictions cannot be used to exploitatively control speculative execution is added:
    • AArch64: CFP RCTX, CPP RCTX, DVP RCTX.
    • AArch32: CFPRCTX, CPPRCTX, DVPRCTX.
  • The description of ICV_CTLR_EL1.CBPR for value 0b1 is updated to the correct Secure and Non-secure reads and writes of ICV_BPR1_EL1.
  • External AMU registers AMCNTENCLR0, AMCNTENCLR1, AMCNTENSET0, and AMCNTENSET1, are updated to have a maximum of 15 event counters, to match the corresponding AArch64 and AArch32 registers.
  • The offset for Secure instance of MPAMF_ERR_MSI_MPAM is corrected to read 0x00DC.
  • The GICR_CLRLPIR and GICR_SETLPIR register descriptions are updated to indicate that they are implemented only if GICR_TYPER.Direct is 1 and IMPLEMENTATION DEFINED otherwise.
  • The accessibility pseudocode for the ICIALLUIS register is updated to remove checks for HCR2.TOCU/HCR_EL2.TOCU bits.
  • The architecture is relaxed to permit Armv8.2 implementations to implement the BUS_SLOTS and BUS_WIDTH fields in the PMMIR_EL1 and PMMIR registers.
  • In HAFGRTR_EL2, each of the fields AMEVCNTR1x_EL0 and AMEVTYPER1x_EL0 are made conditional on AMEVCNTR1<x> and AMEVTYPER1<x> registers being implemented. Otherwise, these fields are RES0.
  • An incorrect equation, 1 - 1/w, is removed from the MPAMCFG_CMAX.CMAX, MPAMCFG_MBW_MAX.MAX, and MPAMCFG_MBW_MIN.MIN field descriptions. It is replaced with a description of the correct equation, 1 - 1/(2^w).
  • ERR<n>PFGF.NA, bit[28], is added to define whether the component fakes detection of the error on an access to the component, or spontaneously in the fault injection state.
  • The CNTPOFF_EL2 description of when the counter offset is applied to the physical counter is clarified.
  • A fine-grained trap control for reads of the PMBIDR_EL1 register is added to HDFGRTR_EL2 at bit [63].
  • The following System register fields, which are currently conditional on FEAT_CSV2, are updated to be conditional on FEAT_CSV2_2 or FEAT_CSV2_1p2:
    • AArch64: HCR_EL2.EnSCXT, HFGRTR_EL2.SCXTNUM_EL0, HFGRTR_EL2.SCXTNUM_EL1, HFGWTR_EL2.SCXTNUM_EL0, HFGWTR_EL2.SCXTNUM_EL1, SCR_EL3.EnSCXT, SCTLR_EL1.EnSCXT, SCTLR_EL2.EnSCXT.
  • ID_AA64PFR1_EL1.CSV2_frac is corrected to indicate that FEAT_CSV2_2 can be implemented in Armv8.5.
  • The feature name FEAT_SVE_PMULL is renamed to FEAT_SVE_PMULL128.
  • ID_AA64MMFR1_EL1.PAN is updated to indicate that FEAT_PAN2 can be implemented from Armv8.1.
  • The GICR_VPROPBASER.Entry_Size field is clarified to specify that it is the size in 64-bit double words of a vPE Table entry, minus one.
  • The description of the EDPRSR.EPMAD is corrected to make the field conditional on FEAT_Debugv8p4 and FEAT_PMUv3 being implemented.
  • The description of the ESR_EL2.SRT field is corrected in 'ISS encoding for an exception from a Data Abort' to clarify that SRT is valid for specified stage 2 aborts.
  • Accessibility pseudocode that refers to the MDCR_EL3.NSPB field is reformatted to represent each bit value of the field separately. The architecture is unchanged.
  • The accessibility pseudocode for all TLBI System instructions is now updated to call ASL functions.
  • Many simple clarifications and corrections are also present, but are too small to be listed here.

 

Known issues

All issues identified in the below list would be fixed in a future release.

  • The architecture deprecates any use of MDRAR_EL1 and DBGDRAR. To this end, the Valid field description in the said registers are updated to indicate that Arm recommends that this field is set to zero.
  • The TTBRx_ELy.BADDR fields description of generating an Address size fault is updated to refer to the Effective value of TCR_ELy.IPS.
  • The condition for the SCTLR.EnRCTX field is corrected from FEAT_CSV2 to FEAT_SPECRES.
  • The HCR_EL2.{AMO, IMO, FMO} field descriptions are ambiguous and hence clarified as to when interrupts are taken.
  • The P<n> field description in the AArch64, AArch32, and External AMCNTENCLRx and AMCTENSETx registers is updated to cover the case where N is 16.
  • CNTHCTL_EL2.EVNTEN and CNTKCTL_EL1.EVNTEN are corrected to reset to an UNKNOWN value in all cases.
  • The EL2 conditions for the behavior of values 0b110x and 0b10xx in the EDSCR.RW field are corrected.
  • The ID_AA64MMFR0_EL1 TGranx_2 field descriptions are updated to clarify that they do not use the usual ID scheme.
  • The PMSIDR_EL1.MaxSize field description is updated to clarify that the values 0b0100 and 0b0101 are not permitted.
  • The list of permitted values for Armv8.5 implementations in the ID_MMFR4_EL1.EVT and ID_MMRF4.EVT descriptions will be clarified to indicate the dependency on support for AArch32.
  • The 'Configuration' in the ID_AA64ISAR2_EL1 description incorrectly specifies that this register is present from Armv8.7. In a future release, this will be corrected to indicate that this register was previously unnamed and reserved, RES0.

 

Potential upcoming changes

We are looking in improvements to the information that is provided in the XML. In some cases these changes may impact users. Here is a list of areas where we may make change in a future release:

  • We are looking at separating accessors (instructions/external accesses) from registers. This is likely to impact "Index by Encoding", "External registers by offset" and may introduce separate pages for instructions/accessors vs. the registers. This may impact the schema and the presentation of the content.
  • Some changes to register names may be introduced and there may be changes to the number of registers or names. The instructions accessing registers would be unchanged preserving the architecture intent.
  • We are considering obsoleting some DTD elements based on usage and analysis.
  • The instruction encoding tables currently present values as binary values, with the prefix "0b". We are considering whether these values are better represented in a syntax compatible with pseudocode.
  • The reset information in the 'Configuration' section of some register descriptions have incorrect information, and must not be relied upon. Please refer to the field descriptions for the correct reset information. The information in the 'Configuration' section will be removed in a future release.
  • Some fields have different names or sizes depending on a condition. These are currently represented as a flat list. We are looking at representing them as nested fields.