Release notes for A64 Instruction Set Architecture for Future Architecture Technologies (2020-09)

Product Status

This release covers multiple versions of the architecture. The content relating to different versions is given different quality ratings.

The information related to v8.7 of the architecture and features FEAT_ CSRE and FEAT_BRBE are at Alpha quality. Alpha quality means that most major features of the specification are described in the manual, some features and details might be missing.

The information related to versions of the architecture introduced before v8.7 of the architecture and for the remaining features (FEAT_SVE2, FEAT_TME, FEAT_TRBE and FEAT_ETE), which was also published in previous releases, is at BET quality. BET quality means that all major features of the specification are described, some details might be missing.

Change history

This is the A64 ISA XML for Future Architecture Technologies (2020-09).

The following general changes are made:

  • The encoding table for "'Floating-point directed convert to integer" in both A64 and A32 ISAs is missing the 'op' column. This column is now added.

The following changes are made to the instruction definitions:

  • The SUBS (shifted register) instruction is updated remove ambiguity in the Alias Conditions.
  • The decode pseudocode for instructions LDGM, STGM, and STZGM is updated to check the effect of value of ID_AA64PFR1_EL1.MTE field.
  • The LD*P[SW] and ST*XP instructions include some decode logic (for example, UNDEFINED checks) within the execute block. The decode logic has been moved from the execute to the decode block.
  • The following changes are made to the Shared pseudocode:

    • The Pseudocode function FailTransaction() is updated to include failure cause in case of a Trivial implementation. Execute Pseudocode for TSTART instruction is also updated to set values to Rt and the nPC fields in TSTATE before the FailTransaction() is called.
    • The pseudocode function AArch64.TranslationTableWalk() is updated to check for non-permitted table walks in case of unprivileged memory accesses.
    • The pseudocode CheckTransactionalSystemAccess() is adjusted to include the opcode encodings of CPP RCTX, CFP RCTX and DVP RCTX instructions that are permitted inside transactional state.
    • Pseudocode for TME is updated to fail the transaction with ERR cause in case of a WFI instruction.
    • The pseudocode function GetPSRFromPState() is updated to return a variable length value and SetPSTATEFromPSR() is updated to accept a variable length parameter. The functions Halt() and DebugExceptionReturnSS() are also updated to reflect these changes.
    • The pseudocode functions GetPSRFromPSTATE() and SetPSTATEFromPSR() now correctly copy to and from PSTATE.DIT on taking and returning from exceptions between AArch64 and AArch32 states. The pseudocode function Halt() is updated to remove code that now duplicates these efforts.
    • The pseudocode functions AArch64.SecondStageTranslate() and AArch32.SecondStageTranslate() are updated to not generate an alignment fault to a memory location marked as Device when using access type DC ZVA for stage 1 walks.
    • The pseudocode function AArch64.FPTrappedException() is updated to remove the redundant argument "element". Also, the pseudocode function AArch32.FPTrappedException() is updated to remove the passing of the "element" argument to function AArch64.FPTrappedException().
    • The pseudocode function InterruptPending() is corrected to account for all sources of virtual interrupts.
    • The pseudocode function Halt() now assigns to the SPSR variable instead of DSPSR when checking CONSTRAINED UNPREDICTABLE behavior.
    • The pseudocode function AArch64.FaultSyndrome() does not correctly describe the Data Abort ISS of ESR_ELx.ISV when RAS is not implemented. AArch64.FaultSyndrome() has been updated to account for RAS not being implemented.
    • The pseudocode function AArch64.TranslateAddressS1Off() has been corrected to ensure it always initializes variables.
    • The pseudocode function AArch64.BreakpointMatch has been corrected to ensure that any match is as per unpredictable behavior of DBGBVR_EL1.RESS fields.
    • The pseudocode for Mem[] incorrectly treats all NV2REGISTER accesses as big-endian when EL1 is configured for big-endian operation, regardless of the value of EL2. This is fixed by passing the AccType parameter to big-endian and removing the NV2REGISTER tests in Mem[]. All other calls to big-endian in the manual are updated to pass an appropriate parameter.
    • The pseudocode accessor AArch64.MemTag[] assignment-form is updated to reflect the CONSTRAINED UNPREDICTABLE behavior when storing tags to memory locations marked as Device.
    • The pseudocode function ELIsInHost() is refactored to improve readability.
    • The pseudocode function ExternalDebugInterruptsDisabled() is updated to show the change in EDSCR.INTdis width when ARMv8.4 Debug is implemented.
    • The pseudocode function CheckWatchpoint() check is updated so that data cache operations with DC_ZVA and DC_IVAC are distinguishable from other data cache maintenance instructions.
    • The pseudocode function DebugExceptionReturnSS() is updated to correct the check for ELUsingAArch32(dest) for the case where dest is EL0.
    • The pseudocode functions AArch64.WatchpointMatch() and AArch32.WatchpointMatch() are updated to correct the comment for "ispriv" argument to the functions.
    • The pseudocode functions AArch64.ExceptionClass() and AArch32.ExceptionClass() are corrected set the correct value for iL (instruction length) with a default value of '1' for cases where instruction length does not matter and to perform the assert check on the correctly set value of iL. Both checks of setting the value of iL and assert check on iL are moved from start of the functions to the end of the functions' body.
    • The function description for pseudocode function ChooseRandomNonExcludedTag() is updated to clarify the architectural description. When all bits of GCR_EL1.Exclude are 1, then the Allocation Tag value is 0, is exported in the definition of the IRG instruction when GCR_EL1.RRND is 1.
    • The pseudocode functions AArch64.AccessIsPrivileged() and AArch32.AccessIsPrivileged() are updated to remove duplicate checks for privileged access.
    • The pseudocode function SetPSTATEFromPSR() is updated to correctly reflect the values to various PSTATE bits on an illegal exception return.
    • The _Mem[] (non-assignment form) pseudocode function is updated to take an additional boolean parameter that signifies if a read is taking place as part of a write operation
    • Added checks before clearing pending physical SError in pseudocode functions AArch64.TakePhysicalSErrorException() and AArch32.TakePhysicalSErrorException().

    Known issues

    • In the PDF diff files the operations pseudocode for some instructions has a defect in presentation for the 'when' condition. Where this defect is present, the action is appended to the condition on the same line, rather than being on the following line.
    • Some architectural features have limited or no descriptions in the Pseudocode and are not fully covered by the functional testing. Affected features are listed below:
      • Address translation system instructions
      • Ordering of memory accesses
      • Self-hosted debug and behaviour of PE when in debug state (external debug)
      • Trace architecture (Includes self-hosted trace and external trace)
      • RAS architecture
      • Statistical profiling
      • Performance monitor counter
      • Activity monitor
      • Generic timer
      • Generic Interrupt Controller
      • Multi-processing
    • Pseudocode known issues

    • The new Armv8.7 pseudocode has been partially tested but may contain defects.
    • The new Future Architectures Technologies pseudocode has been partially tested but may contain defects.
    • There is no pseudocode present in this release for the following features:
      • FEAT_LPA2
      • FEAT_XS
    • The FPTrigSSel() function used by the SVE FTSSEL instruction has known issues with the modified NaN propagation rules.
    • The FTSMul() function used by SVE FTSMUL instruction has known issue that it will incorrectly generate an Input Denormal exception if the result is a denormal value.
    • BRBINF_EL1.CC cycle count encoding is not implemented.
    • BRBCR_ELx.MPRED recording of branch misprediction is not implemented.
    • RES0 fields in BRBINF_EL1 when adding half records are not implemented.
    • BRBCR_ELx.CC is not implemented.
    • BRBINF_EL1.LASTFAILED is not implemented.
    • Some BRBE pseudocode loops assume the number of records is fixed at 64.

    Potential upcoming changes

    • The Shared pseudocode for VMSA will be refactored.