Release notes for A64 Instruction Set Architecture for Future Architecture Technologies (2020-06)

Change history

This is the A64 ISA XML for Future Architecture Technologies (2020-06).

The following general changes are made:

  • Architectural feature names used in the XML have been altered to a new format. See List of new vs old names for a list of the old and new names.

The following changes are made to the instruction definitions:

  • In the ISA XML format, multiple <iclass> elements containing a single encoding each, the hrefs in <classesintro> and ID of <iclass> would equal the encoding name. This would happen only in this case.
    These IDs are now unique.
    There is no change in the representation of data in HTML or PDF.
  • Alignment check added before write to tag memory by the STGZ and ST2GZ instructions.

The following changes are made to the Shared Pseudocode:

  • The Pseudocode function AArch64.TakeException() is updated such that the effect of BTI is only reflected in the SPSR for A64 execution state.
  • The Pseudocode functions AArch64.CountEvents() and AArch32.CountEvents() are updated to add checks to prohibit cycle counting if v8.5 PMU Extension is implemented. AArch64.CountEvents() is also updated to add checks on AArch64 registers when setting filter bits. AArch32.CountEvents() is also updated to add declaration for hpmd variable.
  • The Pseudocode function AArch64.S1AttrDecode() is updated in order to ensure the correct combination of shareability information in the case when HCR_EL2.FWB==1
  • The Pseudocode function AArch64.TranslationTableWalk() is corrected to check for Unprivileged access when checking the value of TCR_EL1.E0PD0 or TCR_EL2.E0PD0.
  • The Pseudocode function AArch64.BreakPointValueMatch() is corrected to describe the effect of Secure EL2. The function is also updated to correct the condition on use of register CONTEXTIDR_EL2 such that this is allowed when either FEAT_VHE or FEAT_Debugv8p2 is supported.
  • The HaveUA16Ext() function is renamed to HaveLSE2Ext() throughout the codebase.
    A new function, CheckAllInAlignedQuantity(), is added.
    The MemSingle[] functions are updated to use the new function if LSE2 is implemented, and the Mem[] functions are updated to relax atomicity checks for Normal memory if FEAT_LSE2 is implemented.
    The pseudocode for LDP, LDNP and STP is updated to issue atomic reads and writes if LSE2 is implemented and the accesses are to Normal memory.
  • The Pseudocode function AArch64.TranslationTableWalk() is updated to correctly describe the CONSTRAINED UNPREDICTABLE behaviour for all cases of PE execution state when FEAT_LVA is not supported and configured memory region size is greater than the effective maximum. A similar change is also made when FEAT_LPA is not supported.
  • The Pseudocode functions CombineS1S2AttrHints(), S2ConvertAttrsHints() and AArch64.SecondStageTranslate() are updated to correctly describe the effect of HCR_EL2.CD and HCR_EL2.ID bits. Code in these functions is also refactored around Force-write-back feature description.
  • The Pseudocode function Halt() is corrected to set PSTATE.<SSBS, IT, T> to UNKNOWN, PSTATE.TC0 to 1, and PSTATE.BTYPE to 0.
  • The Pseudocode function SetPSTATEFromPSR() is updated to correctly reflect the values to various PSTATE bits on an illegal exception return.
  • The Pseudocode functions AArch64.CheckWatchpoint() and AArch32.CheckWatchpoint() are updated to set the external debug watchpoint address register EDWAR when PE enters the debug state for a watchpoint.

Known issues

  • The alias conditions for NEGS should be corrected to Rd != '11111' && Rn == '11111'
  • In the PDF diff files the operations pseudocode for some instructions has a defect in presentation for the 'when' condition. Where this defect is present, the action is appended to the condition on the same line, rather than being on the following line.
  • Some architectural features have limited or no descriptions in the Pseudocode and are not fully covered by the functional testing. Affected features are listed below:
    • Address translation system instructions
    • Ordering of memory accesses
    • Self-hosted debug and behaviour of PE when in debug state (external debug)
    • Trace architecture (Includes self-hosted trace and external trace)
    • RAS architecture
    • Statistical profiling
    • Performance monitor counter
    • Activity monitor
    • Generic timer
    • Generic Interrupt Controller
    • Multi-processing