Release notes for System Registers for Future Architecture Technologies 2020-12

Product Status

This release covers multiple versions of the architecture. The content relating to different versions is given different quality ratings.

The information related to v8.7 of the architecture and feature FEAT_BRBE is at Alpha quality. Alpha quality means that most major features of the specification are described in the manual, some features and details might be missing.

The information related to versions of the architecture introduced before v8.7 of the architecture and for the remaining features (FEAT_SVE2, FEAT_TME, FEAT_TRBE and FEAT_ETE), which was also published in previous releases, is at BET quality. BET quality means that all major features of the specification are described, some details might be missing.

Future Architecture Technologies change history

  • This release removes the content for FEAT_CSRE.

Future Architecture Technologies known issues

    There are no known issues for this architecture version.

Armv8.7 change history

  • The following features are added to the MPAM system architecture: Error MSI, Monitor Overflow MSI, and Monitor Overflow Status.
  • The condition NV == 1 is added to the accessibility pseudocode for all registers that trap on NV1,NV2 == 1,0. This new trap is added to accessibility pseudocode in SCXTNUM_EL1 and SCXTNUM_EL2.
  • The accessibility pseudocode for the following System registers is updated:
    • AArch32: DBGDSCRint, ICC_SRE.
  • The detail for level 0 translation faults is added to E0PDn fields in TCR_ELx.
  • The Purpose of several TLBI System instruction descriptions is updated to clarify that the Security state is indicated by the current value of SCR_EL3.NS.
  • The FEAT_MTE feature is split into FEAT_MTE, Instruction only, and FEAT_MTE2, Full MTE, features. This is reflected in the following:
    • AArch64 System instructions: DC CIGVAC, DC GVA, DC CISW, DC CIVAC, DC CSW, DC CVADP, DC CVAP, DC ISW, DC IVAC.
  • The definition of the following registers is updated to remove 'at the lowest affinity level, or PEs with MPIDR_EL1.MT set to 1':
    • AArch64: MPIDR_EL1.MT.
    • AArch32: MPIDR.MT.
  • The SDCR.TTRF field description is updated to match the description in the value table.
  • The FPCR.NEP field description is updated to include the FMULX(by element) instruction that is affected by this field.
  • A note is added to PAR_EL1.ATTR to clarify that the attributes presented are consistent with the stages of translation applied in the address translation instruction.
  • The following registers, where 'x greater than or equal to the IMPLEMENTATION DEFINED number of CLAIM tags', are updated from 'RAZ/SBZ' to 'RAZ/WI' to be consistent with the CoreSight Architecture Specification:
  • The reset information of the HSCTLR.TE field is corrected to be an IMPLEMENTATION DEFINED value in a system where the PE resets into EL2.
  • The ERR<n>PFGCTL.{MV, AV} fields are updated to indicate that writes to these fields are ignored if the node always records some syndrome in ERR<n>MISC<m>.
  • The following registers are updated to confirm the behavior of TCO fields when only FEAT_MTE is supported:
    • AArch64: SPSR_EL1, SPSR_EL2, SPSR_EL3, DSPSR_EL0, TCO.
  • The CSV2 field description in the following registers is clarified to refer to controlling speculative execution instead of affecting speculative execution:
    • AArch64: ID_AA64PFR0_EL1 and ID_PFR0_EL1.
    • AArch32: ID_PFR0.
    The ID_AA64PFR1_EL1.CSV2_frac field is introduced to improve resilience to Spectre variant 2. These features are identified as FEAT_CSV2_1p1 and FEAT_CSV2_1p2.
    FEAT_CSV2 is split into the following:
    • FEAT_CSV2 when ID_AA64PFR0_EL1.CSV2 is 0b0001 and ID_AA64PFR1_EL1.CSV2_frac is 0b0000.
    • FEAT_CSV2_2 when ID_AA64PFR0_EL1.CSV2 is 0b0010.
  • The caching statements in VSTTBR_EL2 are corrected.
  • The note in the PMCR_EL0.C field is updated to indicate that bits [63:0] of only the cycle counter are reset.
  • The fields in the FGT registers are clarified to indicate that they are not trapped rather than having no effect.
  • 0x1A is added to ERR<n>STATUS.SERR to cover any other error detected in the internal state of the component.
  • In HFGRTR_EL2 and HFGWTR_EL2, the behavior of fine-grained traps when fine-grained trapping or Secure EL2 is disabled is clarified.
  • The ID_AA64ISAR1_EL1.LS64 field is clarified to indicate that FEAT_LS64 is OPTIONAL in Armv8.7 implementations.
  • The SCR_EL3.FGTEn field description is updated to clarify when EL2 accesses are trapped.
  • The PMSNEVFR_EL1.E[1] field description is updated to indicate that the field is RAZ/WI if the PE does not support sampling of speculative instructions.
  • Updates to the schema and the XML DTD to allow for succinctly describing a non-contiguous mapping. For example, see FPCR and FPSR.
  • Register accesses are now updated to include ASL functions where applicable.
  • Many simple clarifications and corrections are also present, but are too small to be listed here.

Armv8.7 known issues

All issues identified in the below list would be fixed in a future release.

  • The HCR_EL2.TID2 field incorrectly refers to reads being UNDEFINED. This will be corrected to be 'trapped to EL1' in a future release.
  • The EDSCR.INTDis description fails to correctly indicate the behavior when Armv8.4-Debug is not implemented. This will be corrected in a future release.
  • The ID_AA64PFR0_EL1.RAS field will be clarified to indicate that the optional FEAT_DFE will be implemented if EL3 is implemented and the value of this field is 0b0010.
  • The SCTLR_EL3.IESB field is updated to reflect the relaxation of the behavior of IESB in Debug state.

Potential upcoming changes

We are looking in improvements to the information that is provided in the XML. In some cases these changes may impact users. Here is a list of areas where we may make change in a future release:

  • We are looking at separating accessors (instructions/external accesses) from registers. This is likely to impact "Index by Encoding", "External registers by offset" and may introduce separate pages for instructions/accessors vs. the registers. This may impact the schema and the presentation of the content.
  • Some changes to register names may be introduced and there may be changes to the number of registers or names. The instructions accessing registers would be unchanged preserving the architecture intent.
  • We are considering obsoleting some DTD elements based on usage and analysis.
  • The instruction encoding tables currently present values as binary values, with the prefix "0b". We are considering whether these values are better represented in a syntax compatible with pseudocode.
  • The reset information in the 'Configuration' section of some register descriptions have incorrect information, and must not be relied upon. Please refer to the field descriptions for the correct reset information. The information in the 'Configuration' section will be removed in a future release.
  • Some fields have different names or sizes depending on a condition. These are currently represented as a flat list. We are looking at representing them as nested fields.
  • In a future release, Arm will introduce specific reset domains for the following register specifications:
    • Timer reset domain for external Timer registers. These are currently IMPLEMENTATION DEFINED, and referenced generically as reset in the registers.
    • AMU reset domain, for AMU registers that are currently indicated as reset on Cold reset in the registers.
    • GIC reset domain for GICD, GICR, and GITS registers. These are currently generically referenced as reset in the registers.
    • MSC reset domain for MPAM registers prefixed with: MPAMCFG, MPAMF, and MSMON.
  • For the purposes of making the HTML output compatible with XHTML1.1, we are looking at making some changes to the IDs on elements in both HTML and XML. Fieldsets will have IDs included, which are namespaced to take into account any parent IDs, and generally done by index and the field range set.