Release notes for System Registers for Future Architecture Technologies (2020-09)

Product Status

This release covers multiple versions of the architecture. The content relating to different versions is given different quality ratings.

The information related to v8.7 of the architecture and features FEAT_ CSRE and FEAT_BRBE are at Alpha quality. Alpha quality means that most major features of the specification are described in the manual, some features and details might be missing.

The information related to versions of the architecture introduced before v8.7 of the architecture and for the remaining features (FEAT_SVE2, FEAT_TME, FEAT_TRBE and FEAT_ETE), which was also published in previous releases, is at BET quality. BET quality means that all major features of the specification are described, some details might be missing.

Future Architecture Technologies change history

  • This release of Arm Future Architecture Technologies introduces two new optional features:
    • Call Stack Recorder Extension (FEAT_CSRE)
    • Branch Record Buffer Extension (FEAT_BRBE)

Future Architecture Technologies known issues

    There are no known issues for this architecture version.

Armv8.7 change history

  • This is the first release of the System register XML that includes all the features introduced by the Armv8.7 Extensions.
  • The accessibility pseudocode for the following registers has been updated:
    • AArch32: DBGDRAR, DBGDSAR.
  • The ID_AA64PFR1_EL1.MTE field description has been updated to clarify the different features within the Memory Tagging Extension.
  • The SCTLR_ELx.ITFSB descriptions have been updated to call out the requirements on updating tag fault status registers.
  • The PCT and TS fields, where relevant, in the following registers are updated to correctly indicate the behavior when FEAT_ECV is implemented:
    • AArch64: PMSCR_EL1, PMSCR_EL2, TRFCR_EL1, TRFCR_EL2, and TRFCR.
    • AArch32: TRFCR.
  • The purpose of the ERR<n>MISCn registers has been updated to indicate what happens if the error is detected within an FRU.
  • The HCR_EL2.NV1 description has been updated to remove the incorrect reference to HCR_EL2.NV2.
  • The ID_AA64MMFR0_EL1.FGT description has been corrected to include the traps to EL3 and EL3 of the Debug Communications Channel registers.
  • The ID_AA64PFR0_EL1.RAS, ID_PFR0_EL1.RAS, and ID_PFR0.RAS field descriptions have been updated to indicate that FEAT_RASv1p1 is permitted to be implemented from Armv8.2.
  • The UFE field description in the following registers is updated to describe the effect of Flush-to-zero behavior:
    • AArch64: FPCR, FPSR.
    • AArch32: FPSCR.
  • The 'ISS encoding for exceptions with an unknown reason' description in ESR_ELx has been updated to include the priority of exceptions caused by HCR_EL2.E2H == 0.
  • The BF16 field in the following registers has been updated:
    • AArch64: ID_AA64ISAR1_EL1 and ID_ISAR6_EL1.
    • AArch32: ID_ISAR6.
  • The Purpose of the following System instructions is clarified to correctly indicate that the entry is from the final level of the translation table walk:
    • AArch64: TLBI RIPAS2LE1OS, TLBI RVALE3, TLBI RVALE3IS, TLBI RVALE3OS.
  • The reset information of the HDCR.{TDCC, HLP} fields have been updated to be 0 and architecturally UNKNOWN respectively.
  • Many simple clarifications and corrections are also present, but are too small to be listed here.

Armv8.6 known issues

All issues identified in the below list would be fixed in a future release.

  • The NV1==1 condition is added to the accessibility pseudocode for all registers that trap on HCR_EL2.{NV2, NV1} = {0, 1}.
  • The Purpose of the following AArch64 TLBI System instructions is updated to indicate the Security state of the translation regime to invalidate:
    • TLBI ASIDE1( ,IS,OS), TLBI RVAAE1( ,IS,OS), TLBI RVAALE1( ,IS, OS), TLBI RVAE1( ,IS, OS), TLBI RVALE1( ,IS,OS), TLBI VAAE1( ,IS, OS), TLBI VAALE1( ,IS,OS), TLBI VAE1( ,IS, OS), TLBI VALE1( ,IS,OS), TLBI VMALLE1( ,IS,OS), TLBI RVAE2( ,IS, OS), TLBI RVALE2( ,IS, OS), TLBI VAE2( ,IS, OS), TLBI VALE2( ,IS,OS).
  • The architecture is relaxed to made CONSTRAINED UNPREDICTABLE whether traps on the following registers are ignored in Debug state:
    • AArch64: MDCCINT_EL1, MDCCSR_EL0, OSDTREX_EL1, OSDTRTX_EL1.
    • AArch32: DBGDSCRint, DBGDIDR, DBGDSAR, DBGDRAR, DBGDTRRXext, DBGDTRTXext, DBGDCCINT.
  • The SDCR.TTRF field is updated to align with the information in the value table and indicate when an access generates a Monitor Trap exception.
  • Some GIC IRI registers, including GITS, GICR, and GICD registers, refer to a "Warm reset". This is incorrect and should simply refer to "reset".
  • The references to RAZ/SBZ are replaced with RAZ/WI in the reserved fields in the following registers:
    • AArch64: DBGCLAIMCLR_EL1, DBGCLAIMSET_EL1.
    • AArch32: DBGCLAIMCLR, DBGCLAIMSET.
    • External: CTICLAIMCLR, CTICLAIMSET, DBGCLAIMSET_EL1, DBGCLAIMCLR_EL1.

Potential upcoming changes

We are looking in improvements to the information that is provided in the XML. In some cases these changes may impact users. Here is a list of areas where we may make change in a future release:

  • When bits of two registers are architecturally mapped, it is captured in XML using (mapped_from_startbit, mapped_from_endbit) and (mapped_to_startbit, mapped_to_endbit) tags. This does not allow for succinctly describing a non-contiguous mapping. We are looking into refining the presentation in a future release.
  • We are looking at separating accessors (instructions/external accesses) from registers. This is likely to impact "Index by Encoding", "External registers by offset" and may introduce separate pages for instructions/accessors vs. the registers. This may impact the schema and the presentation of the content.
  • Some changes to register names may be introduced and there may be changes to the number of registers or names. The instructions accessing registers would be unchanged preserving the architecture intent.
  • Register accesses that always look like simple reads or writes might be extended to have some ASL expressions. Where register accesses cause additional side effects, ASL functions that describe these effects would be added. Currently these details are only expressed in text.
  • We are considering obsoleting some DTD elements based on usage and analysis.
  • The instruction encoding tables currently present values as binary values, with the prefix "0b". We are considering whether these values are better represented in a syntax compatible with pseudocode.
  • The reset information in the 'Configuration' section of some register descriptions have incorrect information, and must not be relied upon. Please refer to the field descriptions for the correct reset information. The information in the 'Configuration' section will be removed in a future release.