Release notes for System Registers for Future Architecture Technologies (2019-12)

Future Architecture Technologies change history

  • Reset information for registers is now given for each field in each register, rather than in the register Configuration section.
  • Two new encodings have been added to TRBMAR_EL1 in the Trace Buffer Extension for software compatibility with ARMv8.5-MemTag.
    • 0b0000 for innner cacheability attributes.
    • 0b1111 for outer cacheability attributes.
  • The following fields are no longer RES0 when a parent feature is not implemented. Instead they have a value of zero.
    • TRCIDR0.QFILT
    • TRCIDR2.VMIDOPT
    • TRCIDR2.VMIDSIZE
    • TRCIDR3.SYSSTALL
    • TRCIDR3.CCITMIN
    • TRCIDR5.NUMCNTR
    • TRCIDR5.NUMSEQSTATE
    • TRCIDR5.ATBTRIG
  • The following changes have been made to register TRBMAR_EL1:
    • For TRBMAR_EL1.Attr values describing Normal memory, where "Transient" is not explicitly called out, "Non-transient" is added.
    • TRBMAR_EL1.SH value "0b00" is changed from "Not shared" to "Non-shareable".
    • TRBMAR_EL1.SH is ignored when TRBMAR_EL1.Attr specifies either a Device or Normal Inner Non-cacheable Outer Non-cacheable memory type.
    • All Device and Normal Non-cacheable memory regions are always treated as Outer Shareable (Inner and Outer values have changed for TRBMAR_EL1.ATTR).
  • The encodings in TRBSR_EL1.FSC for level 0 Access Flag and Permission faults have been removed. These encodings are now reserved.
  • Many simple clarifications and corrections are also present, but are too small to be listed here. These can be seen in the Change Markup PDF provided.

Future Architecture Technologies known issues

  • The XML incorrectly states that this register is present only when ETE is implemented and TRCIDR5.TRACEIDSIZE != 0x00. This is changed. TRCTRACEIDR will be present when ETE is implemented.
  • The reset information in the 'Configuration' section of the register descriptions have incorrect information, and must not be relied upon. Please refer to the field descriptions for the correct reset information. The information in the 'Configuration' section will be removed in a future release.

Armv8.6 change history

  • The behavior of GCR_EL1.RRND has been relaxed.
  • The accessibility pseudocode of the following registers have been updated:
    • AArch64 registers: AMUSERENR_EL0, CNTV_CTL_EL0, CNTV_CVAL_EL0, CNTV_TVAL_EL0, PMUSERENR_EL0, RMR_EL2, RVBAR_EL2, VMPIDR_EL2, VPIDR_EL2
    • AArch32 registers: AMEVCNTR1<n>, DBGDRAR, DBGDSAR, DBGDAUTHSTATUS, ICC_AP0RN, ICC_AP1RN, ICC_ASGI1R, ICC_BPR0, MVBAR, PMUSERENR, RVBAR
    • AArch32 System instructions: DTLBIALL, DTLBIASID, DTLBIMVA, DCCIMVAC, DCCMVAC, DCIMVAC, DCCISW, DCCSW, DCISW, DCCMVAU, ICIALLU, ICIALLUIS, ICIMVAU
  • The RAS System Architecture v1.0 has been updated to permit the implementation of ERR<n>MISC2 and ERR<n>MISC3.
  • Some registers incorrectly had a statement about the register not having any effect if EL2 is not enabled. The text is hence deleted in the following registers:
    • DBGBVCR32_EL2, FPEXC32_EL2, IFSR32_EL2.
  • The description of the DC CGVAP has been updated to have the correct reference to DC CGDVAP.
  • The description of the VMID fields in the following registers have been corrected to clarify the VMID size:
    • AArch64 registers: DBGBVR_EL0
    • AArch32 registers: DBGBXVR
  • The RNDR and RNDRRS register descriptions incorrectly state that if a random number is not returned in a reasonable time, the value returned is UNKNOWN. This has been corrected to return 0.
  • The following registers were missing the check for the CNTHCTL_EL2.EL1TCT trap in their accessibility pseudocode:
    AArch64: CNTHV_CTL_EL2,CNTHV_CVAL_EL2, CNTHV_TVAL_EL2, CNTHVS_CTL_EL2, CNTHVS_CVAL_EL2, CNTHVS_TVAL_EL2.
    AArch32: CNTHV_CTL, CNTHV_CVAL, CNTHV_TVAL, CNTHVS_CTL, CNTHVS_CVAL, CNTHVS_TVAL.
  • The behavior of the MPAM1_EL1.FORCED_NS field has been tightened to be read-only.
  • Many simple clarifications and corrections are also present, but are too small to be listed here. These can be seen in the Change Markup PDF provided.

Armv8.6 known issues

  • MPAMVPM7_EL2, MPAM Virtual PARTID Mapping Register 7
    The Configuration states that:
    "This register is present only when MPAM is implemented, MPAMIDR_EL1.HAS_HCR == 1 and MPAMIDR_EL1.VPMR_MAX == 111."
    All values given here are in binary. The previous release used decimal representation, MPAMIDR_EL1.VPMR_MAX == 7.
  • The memory-mapped Generic Timer register descriptions have incorrect information, and so must not be relied upon. This will be corrected in a future release. The definitive source for these registers is the Arm Architecture Reference Manual Armv8, for Armv8-A architecture profile.
  • There are differences in the GIC registers in this XML package when compared to the GIC register descriptions in the Generic Interrupt Controller Architecture Specification document. The definitive source for these registers is the document, and there will be corrections to these registers in the next release.
  • The reset information in the 'Configuration' section of some register descriptions have incorrect information, and must not be relied upon. Please refer to the field descriptions for the correct reset information.
  • Tightening of the UNPREDICTABLE behavior of the uninmplemented AMU counter, event type, and set/clear registers.
  • HCDR.TDA traps missing in the AArch32 debug registers

Potential upcoming changes

We are looking in improvements to the information that is provided in the XML. In some cases these changes may impact users. Here is a list of areas where we may make changes in a future release:

  • The instruction encoding tables currently present values as binary values, with the prefix "0b". We are considering whether these values are better represented in a syntax compatible with pseudocode.
  • How the read/write behaviors in register fields are identified is being investigated.