Release Notes for A64 Instruction Set Architecture for Armv8.6 (2019-09)
The following general changes are made:
- Added support for Armv8.6.
The following changes are made to the instruction definitions:
- The execute Pseudocode for the BTI instruction in the optimised version of ISA XML is updated to handle the case when op == SystemHintOp_BTI.
- Clarification added to the <option> field for DSB to indicate that the 0 and 4 encodings are used for the SSBB and PSSBB instructions.
- The "Add/subtract (immediate, with tags)" instruction class was missing a decode on the value of "o2". This is corrected.
- The overlapping encodings in the "Move wide (immediate)" instruction class have been corrected.
- In "MSR (immediate)", the feature is corrected from "ARMv8.5-TCO" to "ARMv8.5-MemTag".
The following changes are made to the Shared Pseudocode:
- The pseudocode functions _MemTag read and write forms and _ChooseRandomNonExcludedTag declarations are added.
- The Pseudocode function CollectRecord() definition, where filtering by operation type, is updated to behave as CONSTRAINED UNPREDICTABLE whether no samples are recorded, or as if the PMSFCR.FT bit is set to 1.
- The Pseudocode function AArch64.SystemAccessTrapSyndrome() returns the syndrome information for trapping of SVE control registers.
- In the Pseudocode function AArch64.CheckSystemAccess(), the text in a comment line is updated to describe the effect when Secure EL2 is supported.
- The Pseudocode function CombineS1S2AttrHints() is updated to set the cache allocation hints to MemHint_No when the final memory type is Non-cacheable.
- The Pseudocode function AddPAC(), in the case of EL2 translation regime, is updated to use control bits from TCR_EL2.
- In the pseudocode function definitions LSL_C(), LSR_C() and ASR_C(), the clamping of the shift amount is deleted from all three functions. The clamping of the shift amount to the element size may generate an incorrect carry flag value for AArch32 LSL, LSR and ASR operators that update the condition flags.
- The Pseudocode function AArch64.CheckDebug() is updated to account for ARMv8.4-NV which requires that in the event of a watchpoint match on an MSR or MRS instruction converted to a memory access, a Watchpoint exception is generated only if all of debug exceptions are enabled, are routed to EL2 (MDCR_EL2.TDE=1), and enabled at EL2 (MDSCR_EL1.KDE=1). Also, the Watchpoint is taken to EL2 and reported with the ESR_EL2.EC code of 0x35.
- The Pseudocode functions AArch32.FirstStageTranslate() and AArch64.FirstStageTranslate() are updated to not check for nTLSMD if there is an AddressSizeFault from AArch64.TranslateAddressS1Off().
- The accessibility Pseudocode for all ID registers is corrected to trap with an error code of 0x18 only when the Armv8.4 feature "Read access to the ID registers" is implemented and enabled, else trapped with an error code 0x0.
- The Pseudocode function CheckSVEEnabled() is updated to align it with the CPACR_EL1 system register description which states that the fields in the register have no effect on execution at EL0 and EL1. It is also updated to account for the trap conditions when the value of CPTR_EL2.ZEN and CPTR_EL2.FPEN is 0b01.
- The Pseudocode function AArch64.CheckSystemAccess is updated to trap to EL2 on a MSR access to DAIF flags at EL0, if HCR_EL2.TGE==1.
- The definition of the Pseudocode function CombineS1S2Desc() is split into two variants AArch64.CombineS1S2Desc() and AArch32.CombineS1S2Desc().
- The Pseudocode functions Have52BitVAExt() and Have52BitPAExt() is updated to describe "52-bit large VA/IPA/PA support" as an optional feature in all architecture versions starting from Armv8.2 and onwards.
- The Pseudocode function descriptions for SoftwareStep_DidNotStep() and SoftwareStep_SteppedEX() are updated in order to clarify the cases where on taking a software step exception, the value to ESR_ELx.ISV and ESR_ELx.EX in the exception syndrome, is not known to be TRUE or FALSE.
- The Pseudocode function AArch64.TranslationTableWalk() is updated to correctly account for the Armv8.4-TTST feature, such that if size of the first pagetable is too small to hold the required number of contiguous entries, then contiguousbitcheck will fail.
- Pseudocode definition of helper functions used in AESx set of instructions is now provided.
- The PC Sample-based Profiling Extension is not fully described in the pseudocode, so the changes to this area in Armv8.2 are not implemented.
- The encoding diagram for "LSL (immediate)" shows the field "imms" in bits[15:10] as "!= x11111". This is incorrect because the 64 bit variant permits the value "011111", therefore this condition will be removed.
- The description for HINT overlaps with other defined instructions. The definitive reference for the instruction encodings in this area of the ISA is the Arm Architecture Reference Manual.
- The SVE MOV(S) aliases of AND(S) (predicates), ORR(S) (predicates) and SEL (predicates) are missing a qualifier to differentiate the different types of instructions.
- The SVE CLASTA (vectors), CLASTB (vectors), COMPACT, LASTA (vectors), LASTB (vectors), and SPLICE instructions incorrectly state that they can be used with a predicated MOVPRFX instruction.
- The "BCVTN, BCVTN2" instruction title for the encoding reads "Vector single-precision and BFloat16", which should read "Vector single-precision to BFloat16".
- The ZIP1 instruction needs correcting to specify it works on the lower half of the source registers. The ZIP2 instruction is corrected to specify it works on the upper half of the source registers.