Release Notes for AArch32 ISA for Armv8.6
The following general changes are made:
- Added support for Armv8.6.
The following changes are made to the instruction definitions:
- There is a clarification on all load and store multiple instructions where the memory locations specified by the instruction and the number of registers specified by the instruction become UNKNOWN.
- Clarification added to the <option> field for DSB to indicate that the 0 and 4 encodings are used for the SSBB and PSSBB instructions.
- The instruction description for the SB instruction was incomplete. This is corrected.
- The XML <docvar> element including the value "off8s_u" are corrected to "off9s_u" for consistency.
- The "op" bit in the T1 encodings for VQDMLAL and VQDMLSL is corrected to bit 9.
The following changes are made to the Shared Pseudocode:
- The Pseudocode function CollectRecord() definition, where filtering by operation type, is updated to behave as CONSTRAINED UNPREDICTABLE whether no samples are recorded, or as if the PMSFCR.FT bit is set to 1.
- The Pseudocode function AArch64.SystemAccessTrapSyndrome() returns the syndrome information for trapping of SVE control registers.
- The Pseudocode function CombineS1S2AttrHints() is updated to set the cache allocation hints to MemHint_No when the final memory type is Non-cacheable.
- In the pseudocode function definitions LSL_C(), LSR_C() and ASR_C(), the clamping of the shift amount is deleted from all three functions. The clamping of the shift amount to the element size may generate an incorrect carry flag value for AArch32 LSL, LSR and ASR operators that update the condition flags.
- The Pseudocode functions AArch32.FirstStageTranslate() and AArch64.FirstStageTranslate() are updated to not check for nTLSMD if there is an AddressSizeFault from AArch64.TranslateAddressS1Off().
- The definition of the Pseudocode function CombineS1S2Desc() is split into two variants AArch64.CombineS1S2Desc() and AArch32.CombineS1S2Desc().
- Pseudocode definition of helper functions used in AESx set of instructions is now provided.
- The table for the "Advanced SIMD two registers and shift amount" class within the A32 and T32 encoding index page includes a column "imm3H:L" with the value "!= 0000" for all rows. This condition applies to all instructions in this table, and so is removed.
- The encoding diagram for the "Advanced SIMD and floating-point 32-bit move" class within the A32 and T32 encoding index page shows bits[3:0] as "1111". This is incorrect, as the next level of decode shows these bits as "(0)(0)(0)(0)".
- There is an apparent clash in the following instruction encoding tables for A32 and T32:
- System register access, Advanced SIMD, and floating-point
- System register access, Advanced SIMD, floating-point, and Supervisor call
There are no overlapping encodings in this part of the instruction set. The "Advanced SIMD two registers and a scalar extension" are split as follows:
- All encodings with op3 = '0' will be moved to their own table, "Multiply with Accumulate" under the "Floating-point data-processing" group.
- All encodings with op3 = '1' will be moved to their own table, "Advanced SIMD dot product".
- The VCVTA, VCVTM, VCVTN and VCVTP (Advanced SIMD) instructions currently describe the target size as 32 bits. This can also be 16 bits, and so this needs correcting.