Release Notes for System Registers for Armv8.6

Change history

  • This is the first release of the System registers XML that includes all the features introduced by the Armv8.6 Extension.
  • The trap definitions of the ID registers have been corrected.
  • The trap definitions of the following registers have been corrected:
    • VMPIDR_EL2.
  • The behavior when the Memory Tagging Extension, ARMv8.5-MemTag, is not implemented has been clarified.
  • The behavior of the CSSELR.TnD bit has been clarified to describe Separate Allocation tags.
  • Clarified the relationship between the WXN and M fields in the HSCTLR, SCTLR, and SCTLR_ELx registers.
  • SCTLR_ELx.{TCF, TCF0} fields have been corrected to reflect that they are not permitted to be cached in the TLB.
  • The relationship between the ARMv8.0-SoftwareLock, ARMv8.3-DoPD, and ARMv8.4-Debug implementations is clarified in the following registers:
    • External debug registers: EDLAR and EDLSR.
    • Memory-mapped PMU registers: PMLAR and PMLSR.
  • The behavior of the HCR_EL2.TSC field has been relaxed.
  • The content within the <usage_constraint_text> and <access_mechanism_text> has been transferred into the <usage_constraint_text> and <access_text> elements. The <access_mechanism_text> fields have been removed.
  • Many simple clarifications and corrections are also present, but are too small to be listed here. These can be seen in the Change Markup PDF provided.

Known issues

  • MPAMVPM7_EL2, MPAM Virtual PARTID Mapping Register 7
    The Configuration states that:
    "This register is present only when MPAM is implemented, MPAMIDR_EL1.HAS_HCR == 1 and MPAMIDR_EL1.VPMR_MAX == 111."
    All values given here are in binary. The previous release used decimal representation, MPAMIDR_EL1.VPMR_MAX == 7.
  • The memory-mapped Generic Timer register descriptions have incorrect information, and so must not be relied upon. This will be corrected in a future release. The definitive source for these registers is the Arm Architecture Reference Manual Armv8, for Armv8-A architecture profile.
  • There are differences in the GIC registers in this XML package when compared to the GIC register descriptions in the Generic Interrupt Controller Architecture Specification document. The definitive source for these registers is the document, and there will be corrections to these registers in the next release.
  • The reset information in the 'Configuration' section of the register descriptions have incorrect information, and must not be relied upon. Please refer to the field descriptions for the correct reset information.
  • Updates to the RAS System Architecture v1.0 to permit the implementation of ERR<n>MISC2 and ERR<n>MISC3 registers.
  • The accessibility pseudocode for VMPIDR_EL2 and VPIDR_EL2 incorrectly refers to the AArch32 MRC instruction.
  • The CTR_EL0.DIC field incorrectly describes 'instruction to data coherence' rather than 'data to instruction coherence'.
  • The VMID field descriptions in the debug registers are incorrect as they are not correctly describing the conditions for the size of the VMID.
  • The accessibility for AMUSERENR_EL0 incorrectly considers the AMUSERENR_EL0.EN trap.
  • The RNDR and RNDRRS register descriptions incorrectly state that if a random number is not returned in a reasonable time, the value returned is UNKNOWN. This should be corrected to return 0.
  • The following registers are missing the check for the CNTHCTL_EL2.EL1TCT trap in their accessibility pseudocode:
  • In the descriptions of PMUSERENR_EL0.EN and PMUSERENR.EN, the PMUSERENR{_EL0} registers are included in the lists of registers that have a trap enabled on them by this bit. This is incorrect as these registers are always read-only at EL0. The accessibility pseudocode in the register descriptions for these registers correctly shows this. The self-reference is removed from the lists.
  • The MCR accessibility pseudocode for the AArch32 System register MAIR0 and MAIR1 are missing the test for CP15DISABLE2. While the PRRR and NMRR registers have this test, as MAIR0 and MAIR1 are accessed by the same MRC instruction, the accessibility pseudocode should be corrected to reflect this test.

Potential upcoming changes

We are looking in improvements to the information that is provided in the XML. In some cases these changes may impact users. Here is a list of areas where we may make changes in a future release:

  • The instruction encoding tables currently present values as binary values, with the prefix "0b". We are considering whether these values are better represented in a syntax compatible with pseudocode.
  • Some registers in the Arm architecture are recursive, for example ESR_ELn. We are looking into how these can be better represented in the XML.
  • How the read/write behaviors in register fields are identified is being investigated.
  • The reset information in the 'Configuration' section of the register descriptions have incorrect information, and must not be relied upon. Please refer to the field descriptions for the correct reset information. The information in the 'Configuration' section will be removed in a future release.