Release Notes for System Register for Future Architecture Technologies (2019-09)


Change history

  • The content within the <usage_constraint_text> and <access_mechanism_text> has been transferred into the <usage_constraint_text> and <access_text> elements. The <access_mechanism_text> fields have been removed.
  • Many simple clarifications and corrections are also present, but are too small to be listed here. These can be seen in the Change Markup PDF provided.

Known issues

  • None

Potential upcoming changes

We are looking in improvements to the information that is provided in the XML. In some cases these changes may impact users. Here is a list of areas where we may make changes in a future release:

  • The instruction encoding tables currently present values as binary values, with the prefix "0b". We are considering whether these values are better represented in a syntax compatible with pseudocode.
  • Some registers in the Arm architecture are recursive, for example ESR_ELn. We are looking into how these can be better represented in the XML.
  • How the read/write behaviors in register fields are identified is being investigated.
  • The reset information in the 'Configuration' section of the register descriptions have incorrect information, and must not be relied upon. Please refer to the field descriptions for the correct reset information. The information in the 'Configuration' section will be removed in a future release.