Release Notes for System Register XML for Arm®v8-A Architecture, up to and including Arm®v8.5 (00bet10).
- Introduced the ARMv8.5-CP15DISABLE2 feature.
- The description of PMU event counter ranges in MDCR_EL2.HPMN and associated registers has been corrected.
- Clarified the reset value of the HCPTR.TAM field.
- Corrected the description of the ID_AA64DFR0_EL1.DoubleLock, which identifies the presence of the OS Double Lock feature.
- The behavior of reading APSR has been relaxed such that some bits are UNKNOWN.
- Refinements to the descriptions of the Secure EL2 Generic timers.
- Corrections to the mappings between DFAR, HDFAR, HIFAR, and IFAR.
- Many simple clarifications and corrections are also present, but are too small to be listed here. These can be seen in the Change Markup PDF provided.
- The accessibility pseudocode for ID registers does not explicitly describe the effect of the ARMv8.4-IDST feature on the ESR_ELx.EC codes used for reads when an exception is generated.
- The memory-mapped Generic Timer register descriptions have incorrect information, and so must not be relied upon. This will be corrected in a future release. The definitive source for these registers is the Arm Architecture Reference Manual Armv8, for Armv8-A architecture profile.
- There are differences in the GIC registers in this XML package when compared to the GIC register descriptions in the Generic Interrupt Controller Architecture Specification document. The definitive source for these registers is the document, and there will be corrections to these registers in the next release.
- There are stylistic differences in the descriptions of some areas (e.g. ID register fields) for Armv8.3 when compared to equivalent descriptions for earlier architectures. These will be made consistent in a future release.