Release Notes for System Register XML for Future Architecture Technologies 2019-04. 

Change history

This is the first public release of Future Architecture Technologies and hence there are no listed changes.

Known issues

  • The following information is not present for PMSEVFR_EL1.E[16].
    Transactional. If TME is not implemented, this bit is RAZ/WI.
    The possible values of this bit are:

E[16]

Meaning

0

Transactional event is ignored.

1

Do not record samples that have the Transactional event == 0.

  • This bit is ignored by the PE when PMSFCR_EL1.FE == 0.
    This bit resets to an architecturally UNKNOWN value on a reset
  • The following information is not present for PMCCFILTR_EL0.T[23].
    Non-transactional state filtering bit. Controls counting in Non-transactional state. If TME is not implemented, this bit is RES0. 
    The possible values of this bit are:

T[23]

Meaning

0

This bit has no effect on filtering of cycles.

1

Do not count cycles in Non-transactional state.

  • This bit resets to an architecturally UNKNOWN value on a reset. 
  • For register TRBSR_EL1, the following bits must be preserved on a warm reset: 
    EC, bit [31:25] 
    IRQ, bit [22] 
    TRG, bit [21] 
    WRAP, bit [20] 
    S, bit [17] 
    MSS, bit [15:0] 

    This is not explicitly stated in the current XML. 
  • Links in the XML documentation to ESR_ELx will not work. These should be to ESR_EL1, ESR_EL2 or ESR_EL3 registers depending on the location.