Release Notes for System Register XML for Future Architecture Technologies 2019-06.
- Array representation in encoding has changed to align with pseudocode representation. Previously the array index was displayed in array brackets. The new representation moves the array index to outside the brackets. For example:
Previous representation New representation [n:2:0] n[2:0] 0b01[n:2:0] 0b01:n[2:0
- Many simple clarifications and corrections are also present, but are too small to be listed here. These can be seen in the Change Markup PDF provided.
- Links in the XML documentation to ESR_ELx will not work. These should be to ESR_EL1, ESR_EL2 or ESR_EL3 registers depending on the location.
Potential upcoming changes
We are looking in improvements to the information that is provided in the XML. In some cases these changes may impact users. Here is a list of areas where we may make changes in a future release:
- The instruction encoding tables currently present values as binary values, with the prefix "0b". We are considering whether these values are better represented in a syntax compatible with pseudocode.
- Some registers in the Arm architecture are recursive, for example ESR_ELn. We are looking into how these can be better represented in the XML.
- How the read/write behaviors in register fields are identified is being investigated.
- The content within the <usage_constraint_text> and <access_mechanism_text> is being transferred into the <access_text> element. In a future release the <usage_constraint_text> and <access_mechanism_text> will be removed.