CoreSight Architecture Overview

Arm CoreSight architecture documents consist of a set of architectural specifications to support the integration of various IP components in a standardised way, thus ensuring support from the tooling ecosystem. 

  • A guide on software optimization.

  • CoreSight Architecture

    • Common programmers model for Debug components
    • Common interfaces for reusability and interoperability
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  • Debugging an eclipse build.

  • Arm Debug Interface (ADI) architecture v6

    Access to embedded debug functionality.

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  • Debugging an eclipse build.

  • Arm Debug Interface (ADI) architecture v5

    Access to embedded debug functionality.

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  • A program that is running on a desktop.

  • High Speed Serial Trace Port (HSSTP)

    • Lower ASIC pin count
    • Increase possible bandwidth
    • Reduce silicon area

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  • Board that is the international standard.

  • Serial Wire Debug

    • 2-pin debug port
    • Low pin count
    • High-performance alternative to JTAG

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  • Hardware that validates a system.

  • CoreSight-BSA

    Ensures that debug and performance optimization software works seamlessly on all devices.

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  • Debugging an eclipse build.

  • Arm Embedded Trace Router

    Capturing trace in main memory.

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  • Hardware that validates a system.

  • CoreSight-PMU

    Event counters, and other performance monitors.

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  • Debugging an eclipse build.

  • Embedded Trace Macrocell Architecture

    • Processor instruction tracing
    • Processor data tracing
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  • Debugging an eclipse build.

  • CoreSight Program Flow Trace Architecture

    • Processor instruction tracing
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Arm Debug Interface

Arm Debug Interface ADIv5 and ADIv6 define a standard debug interface for debug components in an embedded SoC. This specification is written for system designers and engineers who are specifying, designing or implementing a debug interface to the ADIv5 or ADIv6 architecture specification.

Embedded Trace Macrocell Architecture Specification

An Embedded Trace Macrocell (ETM) is a real-time trace module providing instruction and data tracing of a processor. An ETM is an integral part of an Arm CoreSight debug and real-time trace solution.

This specification describes the Arm Embedded Trace Macrocell (ETM) architecture. All ETMs conform to a version of this architecture that covers the following areas of functionality:

  • The Programmer’s Model

  • The Trace Port Protocol

  • The Physical Interface

CoreSight Program Flow Trace Architecture Specification

A Program Trace Macrocell (PTM) is a real-time trace module providing instruction tracing of a processor. A PTM is an integral part of an Arm CoreSight debug and real-time trace solution.

This specification describes the Program Flow Trace Macrocell (PTM) architecture. All PTMs conform to a version of this architecture that covers the following areas of functionality:

  • The Programmer’s Model

  • The Trace Port Protocol

  • The Physical Interface

CoreSight Architecture Specification

The CoreSight architecture provides a set of standard interfaces and programmer model views enabling partners to define CoreSight components and integrate them within the CoreSight infrastructure.

High Speed Serial trace Port  (HSSTP)

The HSSTP architecture specification specifies a Serial Transmit Port (STP) as a replacement for an existing parallel data output port, suitable for transmitting high bandwidth data off-chip such as from the CoreSight solution.

CoreSight-BSA

Arm architecture covers a wide range of products, across many market segments, from embedded control, to mobile, to servers.

Base System Architectures (BSA) provide hardware requirements for a given type of product or market segment. The requirements are intended to ensure standard software, or operating systems, will operate correctly on machines compliant with the BSA.

The CoreSight Base System Architecture (CoreSight-BSA) is the BSA for ensuring that debug and performance optimization software works seamlessly on all devices. 

Resources