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HDLCD interface

Two HDMI PHYs on the V2M‑Juno motherboard provide video graphics.

Two HDLCD controllers in the Juno Arm® Development Platform SoC support all common 24‑bit RGB formats. These are simple frame buffers whose RGB video connects to I/O drivers that drive the PHYs. The PHYs can operate at a maximum pixel clock frequency of 165MHz. This interface supports HDMI 1.4a up to 1080p.

A typical use of HDLCD0 is for lower resolution video than HDLCD1.

The HDLCD 24‑bit data connects directly between the Juno Arm Development Platform SoC and the HDMI controllers on the V2M‑Juno motherboard. The HDMI controllers drive the HDMI connectors. The Juno Arm Development Platform SoC configures the HDMI controllers at powerup or reset over the AP I2C bus.

The HDMI controllers support I2S audio from the Juno Arm Development Platform SoC. They drive the audio to the HDMI connectors. The same audio stream connects to both HDMI connectors.

Note

Software that Arm supplies with the V2M‑Juno motherboard configures the Juno SoC and board to enable correct operation of the HDLCD interface and correct HDMI output.

The following figure shows the HDLCD video system on the V2M‑Juno motherboard.

Figure 2-11 V2M‑Juno motherboard HDLCD interface


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