The IOFPGA provides access to low bandwidth peripherals that the Juno Arm® Development Platform SoC does not provide. The Juno Arm Development Platform SoC provides access to the IOFPGA through an SMC interface.
The following figure shows the internal architecture of the IOFPGA and its connectivity to external peripherals, including the external interrupts to the GIC-400 interrupt controller in the Juno Arm Development Platform SoC.
Figure 2-10 IOFPGA internal architecture
The following table shows the peripherals and buses inside the IOFPGA.
Table 2-4 Peripherals and buses inside the IOFPGA
|Peripheral||Interface or application||Release version|
|PL050||Keyboard and mouse interfaces.||r1p0.|
|PL061||GPIO for additional user key entry and trusted keyboard entry.||r1p0.|
|PL180||User microSD card.||r1p0.|
|PL350 Series||SMC Controller.||r1p0.|
|AHB bus||-||AMBA 3 AHB-Lite Protocol Specification v1.0.|
|APB bus||-||AMBA 3 APB Protocol Specification v1.0.|