You copied the Doc URL to your clipboard.

Overview of V2M-Juno motherboard hardware

The V2M‑Juno motherboard hardware supports software evaluation and tooling development using the Arm®v8 architecture in the Juno Arm Development Platform SoC.

The following figure shows the hardware infrastructure of the V2M‑Juno motherboard.

Figure 2-1 V2M-Juno motherboard system architecture with LogicTile FPGA daughterboard


The V2M‑Juno motherboard contains the following components and interfaces:

  • One Juno Arm Development Platform SoC:

    • Dual‑core Cortex®‑A57, quad‑core Cortex‑A53, and quad‑core Mali™‑T624 GPU.
    • Memory interfaces, HDLCD display controllers, and other on‑chip peripherals.
  • Site for LogicTile Express daughterboard:
    • Two headers, HDRX and HDRY, enable you to fit any Versatile™ Express LogicTile daughterboard in this site.
    • Thin Links AXI master and slave interfaces to the LogicTile site.
  • One Cortex-M3 Motherboard Configuration Controller (MCC):
    • Supports configuration of the Juno SoC and V2M‑Juno motherboard at powerup or reset:
      • Clock generator configuration.
      • Loading of Real‑Time Clock (RTC) registers.
      • Board configuration.
      • Pre‑loading of external memory.
  • One microSD card that stores the following:
    • Board configuration files.
    • Software images.
  • One EEPROM that stores board identification information and file names for the configuration system.
  • Configuration ports.

    The following ports support Drag-and-Drop editing of configuration files in the configuration microSD card:

    • Configuration USB 2.0 port.
    • Configuration 10Mbps Ethernet port.

  • Two 32‑bit 4GB DDR3L on‑board memories:
    • Low‑power.
    • 800MHz, 1600 million transfers per second (MTs).
  • Static Memory Controller (SMC) 10/100 Ethernet port that uses a LAN9118 Ethernet controller.
  • Four USB 2.0 ports, USB 4-port hub and, USB PHY.
  • Two UARTs:

    • UART 0 can connect to the Juno SoC or to the MCC.
    • UART 1 can connect to the Juno SoC or to the Daughterboard Configuration Controller on the LogicTile daughterboard that is fitted in the daughterboard site.

      The board configuration files, that you can edit using the configuration ports, determine the connectivity of the UART ports during runtime.

      Note

      The Daughterboard Configuration Controller is a microcontroller on the LogicTile that controls the configuration of the daughterboard during powerup or reset.
  • Two HDLCD ports that each support:

    • HDMI 1.4a up to 1080p.
    • One I2S four-channel stereo audio output.
  • Additional user key entry:
    • Trusted User Keyboard entry using the secure keyboard connector.
    • Additional user key entry using the push buttons on the V2M‑Juno motherboard to simulate hand-held devices.
  • IOFPGA that contains registers that form part of the Power Control and DVFS system.

    The IOFPGA also provides access to the following low-bandwidth peripherals, user switches, and user LEDs that the Juno SoC does not provide:

    • 64MB NOR flash.
    • 256KB IOFPGA internal block RAM.
    • User microSD card slot.
    • Keyboard and mouse ports.
    • Six user push buttons for additional user key entry.
    • System registers.
    • Current, voltage, power, and energy meters.
    • Timers.
    • Eight user LEDs. Application software defines their meaning.

    Note

    The prototype V2M‑Juno motherboard also provides two SMC USB 2.0 ports that connect through the IOFPGA. See Overview of the prototype V2M‑Juno motherboard.
  • On‑board clocks that generate source clocks for Juno SoC and V2M‑Juno motherboard systems.
  • A real‑time clock in the MCC. A 3V coin battery powers the real‑time clock when the board is powered down.
  • Three system LEDs that connect to the MCC as follows:

    ON1 LED:
    Reserved for Arm use only.
    ON2 LED:
    Denotes ATX power supply powered up.
    Debug USB LED:
    Denotes read or write access to the configuration microSD card through the configuration USB 2.0 port.
  • Debug ports:
    • 32‑bit Arm CoreSight™ Trace port.
    • Processor CoreSight debug (P-JTAG) port.
Was this page helpful? Yes No