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Chapter 5 SAU register summary

Each of the SAU registers is 32 bits wide.

The following table shows the SAU register summary.

Address Name Type Reset value Processor security state Description
0xE000EDD0 SAU_CTRL RW 0x00000000 Secure SAU Control register
Non-secure RAZ/WI
0xE000EDD4 SAU_TYPE RO 0x0000000x Secure SAU Type register. Indicates the number of available regions
Non-secure RAZ/WI
0xE000EDD8 SAU_RNR RW UNKNOWN Secure SAU Region Number Register. Selects a region.
Non-secure RAZ/WI
0xE000EDDC SAU_RBAR RW UNKNOWN Secure SAU Region Base Address Register
Non-secure RAZ/WI
0xE000EDE0 SAU_RLAR RW UNKNOWN Secure SAU Region Limit Address Register
Non-secure RAZ/WI

SAU_CTRL register

The following figure and table show the SAU_CTRL register characteristics:

Figure 5-1 SAU_CTRL register

SAU_CTRL register

Bits [31:2] Field Reserved Description Reserved - read as 0 (RES0).
1 ALLNS All Non-secure. When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure.
0 ENABLE Enable. Enables the SAU.
Bits [31:2] Field Reserved Description Reserved - read as 0 (RES0).
1 ALLNS All Non-secure. When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure.
0 ENABLE Enable. Enables the SAU.

SAU_TYPE register

Figure 5-2 SAU_TYPE register

SAU_TYPE register

Bits Field Description
[31:8] Reserved Reserved - read as 0 (RES0).
[7:0] SREGION SAU regions. The number of implemented SAU regions.

SAU_RNR register

Figure 5-3 SAU_RNR register

SAU_RNR register

Bits Field Description
[31:8] Reserved Reserved - read as 0 (RES0).
[7:0] REGION Region number. Indicates the SAU region that SAU_RBAR and SAU_RLAR accesses.

SAU_RBAR register

Figure 5-4 SAU_RBAR register

SAU_RBAR register

Bits Field Description
[31:5] BADDR Base address. Holds bits [31:5] of the base address for the selected SAU region.
[4:0] Reserved Reserved - read as 0 (RES0).

SAU_RLAR register

Figure 5-5 SAU_RLAR register

SAU_RLAR register

Bits Field Notes
31:5 LADDR Limit address [31:5]. Bits [4:0] of the limit address are defined as 0x1F
4:2 Reserved Reserved - read as 0 (RES0).
1 NSC 0 Region is not Non-secure callable 1 Region is Non-secure callable
0 ENABLE 0 SAU region is enabled 1 SAU region is enabled

SAU region configuration

When the SAU is enabled, memory that is not covered by an enabled SAU region is Secure.

Figure 5-6 SAU region configuration

SAU region configuration

  • Regions are enabled individually using SAU_RLAR.
  • The region is Non-secure when SAU_RLAR.ENABLE = 1 and SAU_RLAR.NSC=0.
  • The region is Secure and Non-secure callable when SAU_RLAR.ENABLE = 1 and SAU_RLAR.NSC=1.

Configuration example

The following example CMSIS code shows how you can configure the SAU for two regions.

// Configure SAU using CMSIS
    
// Configure SAU Region 0 
// Start Address 0x00200000 
// Limit Address 0x003FFFE0 
// Secure non-secure callable

// Use CMSIS to access SAU Region Number Register (SAU_RNR) 
// Select region 0 
SAU->RNR = (0); 
// Set SAU Region Base Address Register (SAU_RBAR) 
SAU->RBAR = (0x00200000U & SAU_RBAR_BADDR_Msk); 
// Set SAU Region Limit Address Register (SAU_RLAR) 
SAU->RLAR = (0x003FFFE0U & SAU_RLAR_LADDR_Msk) |
   ((1U << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U;
   
   
// Configure SAU Region 1 
// Start Address 0x20200000 
// Limit Address 0x203FFFE0 
// Non-secure

// Select region 1 
SAU->RNR = (1); 
// Set SAU Region Base Address Register (SAU_RBAR) 
SAU->RBAR = (0x20200000U & SAU_RBAR_BADDR_Msk); 
// Set SAU Region Limit Address Register (SAU_RLAR) 
SAU->RLAR = (0x203FFFE0U & SAU_RLAR_LADDR_Msk) |
   ((0U << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U;

// Enable SAU 
// Use CMSIS to access SAU Control Register (SAU_CTRL) 
// Set ENABLE bit[0] to 1 
// Set ALLNS bit[1] to 1 
// All memory is secure when SAU is disabled

SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
   ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk);
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