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CMSIS

Cortex-M series processors provide software support with an initiative called the Cortex Microcontroller Software Interface Standard (CMSIS). One of the projects within CMSIS is CMSIS-CORE, a standardized Hardware Abstraction Layer (HAL) for accessing processor features. CMSIS-CORE is integrated in device driver code that is provided by microcontroller vendors, and being integrated into various software development suites.

Inside the processor-specific header files in CMSIS-CORE, the MPU registers are defined with a data structure (typedef) which provides standardized names for MPU registers.

Register

CMSIS symbols

CMSIS symbols for Non-secure alias

Descriptions

MPU_TYPE

MPU->TYPE

MPU_NS->TYPE

MPU Type Register

MPU_CTRL

MPU->CTRL

MPU_NS ->CTRL

MPU Control Register

MPU_RNR

MPU->RNR

MPU_NS ->RNR

MPU Region Number Register

MPU_RBAR

MPU->RBAR

MPU_NS ->RBAR

MPU Region Base Address Register

MPU_RLAR

MPU->RLAR

MPU_NS ->RLAR

MPU Region Base Limit Register

MPU_MAIR0

MPU->MAIR0

MPU_NS ->MAIR0

MPU Memory Attribute Indirection Register 0

MPU_MAIR1

MPU->MAIR1

MPU_NS ->MAIR1

MPU Memory Attribute Indirection Register 1

The ARMv8-M support in CMSIS starts from CMSIS version 5.0. For more information, see www.arm.com/cmsis and http://www.keil.com/pack/doc/CMSIS/Core/html/index.html.

While is possible to use the ARM assembly language to perform the initialization procedure, it is not particularly efficient. To disable the MPU using assembly language you might use:

MPU_CTRL EQU 0xE000ED94		// Address of the Non-secure register
LDR R0, =MPU_CTRL			// Copy MPU_CTRL into R0
LDR R1, [R0] 			    // Read MPU_CTRL
ORR R1, R1, #(0x0 << 20) 	     // Set bit 0 to disable the MPU
STR R1, [R0] 			    // Write back the modified value to
// MPU_CTRL
DSB
ISB

While the CMSIS equivalent is much more concise.

MPU->CTRL = 0;

ARM therefore recommends that you use CMSIS to control Cortex-M series processors.

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