You copied the Doc URL to your clipboard.

Memory type definitions in ARMv8-M architecture

Note

If you are not intending to implement or use a cache or write buffer, then some of the information within this module, for example cache attributes, is irrelevant.

In ARMv8-M architecture, memory types are divided into:

  • Normal memory.
  • Device memory.

Note

The Strongly Ordered (SO) device memory type in ARMv6-M and ARMv7-M is now a subset of the device memory type.

Normal Memory

The Normal Memory type is intended to be used for MPU regions that are used to access general instruction or data memory. Normal memory allows the processor to perform some memory access optimizations, such as access re-ordering or merging. Normal memory also allows memory to be cached and is suitable for holding executable code.

Normal memory must not be used to access peripheral MMIO registers. The Device memory type is intended for that use.

Note

The Normal Memory definition remains mostly unchanged from the ARMv7-M architecture.

Normal memory can have several attributes applied to it. The following memory attributes are available:

Cacheability

Memories can be cacheable or non-cacheable.

Shareability

Normal memory can be shareable or Non-shareable.

eXecute Never

Memories can be marked as executable or eXecute Never (XN).

Cacheability

The cacheability attribute can be further divided:

Cache policy

Write-Through / Write-Back.

Allocation

Cache line allocation hints, for read and write accesses.

Transient hint

A hint to the cache that the data might only be needed in the cache temporarily.

The architecture supports two levels of cache attributes. These are the inner cache and outer cache attributes.

Typically, the inner cache attribute is used by any integrated caches, while the outer cache attributes are exported on using the bus system sideband signals. Depending on the processor implementation, the inner cache attributes can also be exported to the memory system using extra sideband signals.

Configuring an MPU region with a cacheable memory type does not mean that the data must be cached, but only indicates to the hardware that it might be cached. If a region is defined as cacheable, software takes responsibility for performing any necessary cache maintenance operations.

Shareability

Many systems have multiple bus masters, either multiple processors or a mixture of processors and other masters such as DMA engines. The shareability attribute allows software to advertise to the hardware which of these devices must be able to see any updates to a particular area of memory.

The architecture manages this by grouping all masters into shareability groups. An example of this is shown in the following figure.

The following shareability domain options are available:

Non-shareable

This represents memory accessible only by a single processor or other agent, so memory accesses never have to be synchronized with other processors. Only the processor itself must see the information, though it can be made visible to other agents.

Inner Shareable

This represents a shareability domain that can be shared by multiple masters, but not necessarily all the agents in the system. A system might have multiple Inner Shareable domains. An operation that affects one Inner Shareable domain does not affect other Inner Shareable domains in the system. All agents inside this domain might be able to see the memory.

Outer Shareable

An Outer Shareable (OSH) domain reorder is shared by multiple agents and can consist of one or more Inner Shareable domains. An operation that affects an Outer Shareable domain also implicitly affects all Inner Shareable domains inside it. However, it does not otherwise behave as an Inner Shareable operation.

Defining the shareability of a memory region imposes some functional requirements on the hardware but it does not restrict how the hardware implements that functionality.

The OSH requirement is that all masters in the outer sharable domain can see the effects of any memory updates:

  • In a system without caches and just one level of RAM any master can see any memory update.
  • In a system with caches, not all masters can access all caches.
    • The system might employ hardware cache coherency to make updates visible.
    • The system might treat any shareable memory as non-cacheable, making updates visible.

The Memory Model Feature Register 0 (ID_MMFR0) provides some information about the available shareability domains and their behaviors.

Device Memory

Device memory must be used for memory regions that cover peripheral control registers. Some of the optimizations that are allowed to Normal memory, such as access merging or repeating, would be unsafe to a peripheral register.

The Device memory type has several attributes:

  • G or nG - Gathering or non-Gathering. Multiple accesses to a device can be merged into a single transaction except for operations with memory ordering semantics, for example, memory barrier instructions, load acquire/store release.
  • R or nR - Reordering.
  • E or nE - Early Write Acknowledge (similar to bufferable).

Only four combinations of these attributes are valid:

  • Device-nGnRnE
  • Device-nGnRE
  • Device-nGRE
  • Device-GRE

Note

Device-nGnRnE is equivalent to ARMv7-M Strongly Ordered memory type and Device-nGnRE is equivalent to ARMv7-M Device memory.

Device-nGRE and Device-GRE are new to ARMv8-M.

Typically peripheral control registers must be either Device-nGnRE, or Device-nGnRnE. This prevents reordering of the transactions in the programming sequences.

Device-nGRE and Device-GRE memory types can be useful for peripherals where memory access sequence and ordering does not affect results, for example, in bitmap or display buffers in a display interface. If the bus interface of such peripheral can only accept certain transfer sizes, the peripheral must be set to Device-nGRE.

Note

For most simple processor designs, reordering, and gathering (merging of transactions) do not occur even if the memory attribute configuration allows it to do so.

Device memory is shareable, and must be cached.

Attribute indirection

The attribute indirection mechanism allows multiple MPU regions to share a set of memory attributes. For example, in the following figure MPU regions 1, 2 and 3 are all assigned to SRAM, so they can share cache-related memory attributes.

The following figure shows an example of attribute indirection:

At the same time, regions 1, 2, and 3 can still have their own access permission, XN, and shareability attributes. This is required as each region can have different uses in the application.

Was this page helpful? Yes No