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MPU registers

The MPU is configured by a series of memory mapped registers in the System Control Space (SCS).

It is important to realize that all MPU registers are banked. If TrustZone is enabled, there is a set of MPU registers for the Secure state, and a mirror set for the Non-secure state. When accessing the MPU address between 0xE000ED90 and 0xE000EDC4, the type of MPU registers accessed is determined by the current state of the processor.

Non-secure code can access Non-secure MPU registers and Secure code can access Secure MPU registers. In addition, Secure code can access Non-secure MPU registers at their aliased address.

Secure access sees Secure MPU registers, Non-secure access sees Non-secure MPU registers. Secure software can also access Non-secure MPU registers using the alias address.

Secure Address

NS Address Alias

Register

Description

0xE000ED90

0xE002ED90

MPU_TYPE

MPU Type Register

0xE000ED94

0xE002ED94

MPU_CTRL

MPU Control Register

0xE000ED98

0xE002ED98

MPU_RNR

MPU Region Number Register

0xE000ED9C

0xE002ED9C

MPU_RBAR

MPU Region Base Address Register

0xE000EDA0

0xE002EDA0

MPU_RLAR

MPU Region Base Limit Register

0xE000EDA4

0xE002EDA4

MPU_RBAR_A1

MPU Region Base Address Register Alias 1

0xE000EDAC

0xE002EDAC

MPU_RBAR_A2

MPU Region Base Address Register Alias 2

0xE000EDB4

0xE002EDB4

MPU_RBAR_A3

MPU Region Base Address Register Alias 3

0xE000EDA8

0xE002EDA8

MPU_RLAR_A1

MPU Region Limit Address Register Alias 1

0xE000EDB0

0xE002EDB0

MPU_RLAR_A2

MPU Region Limit Address Register Alias 2

0xE000EDA8

0xE002EDB8

MPU_RLAR_A3

MPU Region Limit Address Register Alias 3

0xE000EDC0

0xE002EDC0

MPU_MAIR0

MPU Memory Attribute Indirection Register 0

0xE000EDC4

0xE002EDC4

MPU_MAIR0

MPU Memory Attribute Indirection Register 1

The programmers’ model for Secure MPU and Non-secure MPU are the same, but the number of MPU regions for the two MPUs can be different.

Note

In the ARMv8-M architecture, MPU_TYPE, MPU_CTRL and MPU_RNR are identical to those registers in the ARMv6-M and ARMv7-M architectures.

All MPU registers:

  • Are privileged access only. Unprivileged accesses generate a fault exception.
  • Must be accessed using 32-bit aligned transfers.

By default the MPU is disabled after reset.

The memory type is encoded as an 8-bit field that is stored in one of the Memory Attribute Indirection Registers (MAIR). Each MAIR register has four 8-bit fields, allowing eight memory types to be defined at any one time.

MPU_TYPE

The MPU Type register indicates how many regions the MPU supports for the selected security state. This register is read only.

mpu_type.png

Bits

Field

Reset

Description

31:16

Reserved - read as 0

0

Reserved

15:8

DREGION

IMPLEMENTATION DEFINED

Number of MPU regions that are supported by the MPU in selected security state.

7:1

Reserved - read as 0

0

Reserved

0

SEPARATE

0

Indicates support for separate instruction data address regions. ARMv8-M only supports unified MPU regions and therefore this bit is set to 0.

MPU_CTRL

The MPU CONTROL register provides various programmable bit fields for MPU enable and features.

mpu_ctrl.png

Bits

Field

Reset

Description

31:3

Reserved - read as 0

0

Reserved

2

PRIVDEFENA

0

Privileged background region enable.

When set to 1, this enables the default memory map for privilege code when the address accessed does not map into any MPU region. Unprivileged accesses to unmapped addresses result in faults.

When cleared to 0, all accesses to unmapped addresses result in faults.

1

HFNMIENA

0

MPU Enable for HardFault and NMI (Non-Maskable Interrupt).

When set to 1, MPU access rules apply to HardFault and NMI handlers.

When cleared to 0, HardFault and NMI handlers bypass MPU configuration as if MPU is disabled.

0

ENABLE

0

Enable control.

When set to 1, the MPU is enabled.

When cleared to 0, the MPU is disabled.

MPU_RNR

The MPU Region Number Register selects the region that is accessed by the MPU_RBAR and MPU_RLAR.

mpu_rnr.png

Bits

Field

Reset

Description

31:8

Reserved - read as 0

0

Reserved

7:0

REGION

Unknown

Region number. Selects and indicates the region that is accessed by the MPU_RBAR and MPU_RLAR.

Bits [7:2] of the region number is also used to select region number when accessing region setup via alias registers (MPU_RBAR_A{n} and MPU_RLAR_A{n}).

MPU_RBAR

The MPU Region Base Address Register defines the starting address of an MPU region and access permission.

mpu_rbar.png

Bits

Field

Reset

Description

31:5

BASE

Unknown

Starting address of MPU region address (bits [31:5] - the address must be aligned to multiple of 32 bytes)

4:3

SH

Unknown

Shareability for Normal memory

00 - Non-shareable

01 - Outer shareable

10 - Inner Shareable

This field is ignored if the memory attribute is set to Device memory type.

2:1

AP[2:1]

Unknown

Access permissions.

00 read/write by privileged code only

01 - read/write by any privilege level

10 - Read only by privileged code only

11 - Read only by any privilege level

0

XN

Unknown

eXecute Never attribute

0 - allow program execution in this region

1 - disallow program execution in this region

MPU_RLAR

The MPU Region Limit Address Register defines the ending address of an MPU region, region enable, and an indirection index to memory attribute array.

mpu_rlar.png

Bits

Field

Reset

Description

31:5

LIMIT

Unknown

Ending address (upper inclusive limit) of MPU region address (bits [31:5] - the address must be aligned to multiple of 32 bytes).

Bits [4:0] of the address value is assigned with 0x1F to provide the limit address to be checked against.

4

Reserved

0

Reserved

3:1

AttrIndx

Unknown

Attribute Index. Select memory attributes from attribute sets in MPU_MAIR0 and MPU_MAIR1

0

EN

0

Region enable

MPU_RBAR_A1/2/3 and MPU_RLAR_A1/2/3

This is an alias of the MPU_RBAR register to allow faster programming of different MPU regions. The region number that is selected when using MPU_RBARn and MPU_RLARn is equal to (MPU_RNR[7:2]<<2) + n. For example:

Condition

When Accessing

MPU Region accessed

MPU_RNR=0

MPU_RBAR / MPU_RLAR

0

MPU_RBAR_A1 / MPU_RLAR_A1

1

MPU_RBAR_A2 / MPU_RLAR_A2

2

MPU_RBAR_A3 / MPU_RLAR_A3

3

MPU_RNR=4

MPU_RBAR / MPU_RLAR

4

MPU_RBAR_A1 / MPU_RLAR_A1

5

MPU_RBAR_A2 / MPU_RLAR_A2

6

MPU_RBAR_A3 / MPU_RLAR_A3

7

This enables software to program multiple MPU regions quickly without the need to reprogram MPU_RNR every time.

MPU_MAIR0, MPU_MAIR1

The MPU Attribute Indirection Register 0 and 1 provide eight sets of memory attributes, which can be referenced using the AttrIndx field in MPU_RLAR to determine the memory attribute for an MPU region.

mpu_mair.png

The format of each memory attribute (ATTR1 through ATTR7) is described by MAIR_ATTR in the Armv8-M Architecture Reference Manual.

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