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Protected Memory System Architecture

The Protected Memory System Architecture (PMSAv8) is the architecture that defines the operation of the MPU inside the ARM processors.

Although the concepts for the MPU operations are similar, the MPU in the ARMv8-M architecture has a different programmers’ model to the MPU in previous versions of the M-profile ARM architecture.

The MPU programmers’ model allows the privileged software to define memory regions and assign memory access permission and memory attributes to each of them. Depending on the implementation of the processor, the MPU on ARMv8-M processors supports up to 16 regions. The memory attributes define the ordering and merging behaviors of that region, as well as caching and buffering attributes. Cache attributes can be used by internal caches, if available, and can be exported for use by system caches.

The MPU in the ARMv6-M and ARMv7-M architectures requires that an MPU memory region must be aligned to an address which is a multiple of the region size, and that the region size must be a power of two.

For example, when creating a memory region from an address 0x3BC00-0x80400, using the PMSAv7 architecture, multiple MPU region registers are required, as the following figure shows:

regions.jpg

In the ARMv8-M architecture, the size of an MPU region can be any size (including 274KB) but must have a a granularity of 32 bytes.

  • PMSAv8 does not include subregions as the region size is now more flexible.
  • Regions are now not allowed to overlap. As the MPU region definition is much more flexible, overlapping MPU regions are not necessary.
  • Memory regions define memory attributes using an index value which is then looked up in a set of memory attribute registers.
  • An individual MPU region is defined by:

Address >= MPU_RBAR.BASE:‘00000’; && Address <= MPU_RLAR.LIMIT:‘11111

Note

Many features of the ARMv8-M architecture are not implemented in ARMv8-M implementations, for example, Caches, Write Buffers and Tightly Coupled Memories (TCMs) are architectural features that are not currently in any ARMv8-M implementations.

The ARMv8-M architecture with Main Extension has a dedicated Memory Management Fault (MemManage) that is triggered by accesses that violate the access permissions that are configured for an MPU region. The Main Extension also provides the MemManage Fault Status Register (MMFSR) and the MemManage Fault Address Register (MMFAR) which provide information about the cause of the fault and the address being accessed in the case of data faults. These provide useful information to RTOS implementations that isolate memory on a per-thread basis, or provide demand stack allocation.

If the MemManage fault is disabled or cannot be triggered because the current execution priority is too high, the fault is escalated to a HardFault. ARMv8-M implementations without the Main Extension can only use the HardFault exception.

Certain memory accesses including exception vector fetches, accesses to System Control Space (SCS), which include MPU, NVIC, and SysTick, and the Private Peripheral Bus (PPB), which includes internal debug components, are not affected by the MPU settings. Also, the MPU configurations do not define the access permissions and attributes for debug accesses. System Space is always Execute never (XN).

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