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Exception Properties

Each exception has an associated identification number, a vector address that is the exception entry point in memory, and a priority level which determines the order in which multiple pending exceptions are handled (the lower the priority number, the higher the priority level).

Exception property

Description

Vector address

Exception entry point in memory.

Priority level

Determines the order in which multiple pending exceptions are handled.

Exception number

Identification for the exception.

Each exception has an associated exception number.

Exception number

Name

Security

1

Reset

Secure

2

Non-Maskable Interrupt

Configurable

3

Secure HardFault

Secure

3

Non-secure Hard Fault

Non-secure

4

MemManage

Banked

5

BusFault

Configurable

6

UsageFault

Banked

11

SVCall

Banked

12

DebugMonitor

Configurable

14

PendSV

Banked

15

SysTick

Banked

16+N

Interrupts #0 -N

Configurable

Vector address

The vector table contains the reset value of the stack pointer and the start addresses, also called exception vectors, for all exception handlers.

The following figure shows the order of the exception vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the exception handler is code.

vector_table.png

The first entry contains the initial stack pointer. All other entries are the addresses for the exception handlers.

On system reset, the vector table is at an IMPLEMENTATION DEFINED address. Privileged software can write to the Vector Table Offset Register (VTOR) to relocate the vector table start address to a different memory location. It is IMPLEMENTATION DEFINED which bits are writable.

The silicon vendor must configure the top range value, which depends on the number of interrupts implemented. The minimum alignment is 32 words, enough for up to 16 interrupts. For more interrupts, adjust the alignment by rounding up to the next power of two. For example, if you require 21 interrupts, the alignment must be on a 64-word boundary because the required table size is 37 words, and the next power of two is 64.

ARM recommends that you locate the vector table in the CODE, SRAM, External RAM, or External Device areas of the system memory map.

Using the Peripheral, Private Peripheral Bus, or Vendor-specific memory areas can lead to unpredictable behavior in some systems. This is because the processor might use different interfaces for load/store instructions and vector fetch in these memory areas. If the vector table is located in a region of memory that is cacheable, you must treat any store to the vector as self-modifying code and use cache maintenance instructions to synchronize the update.

The Vector Table Offset Register

The VTOR specifies the base address of the vector table as an offset from address 0x0.

At reset the TBLOFF field is fixed at 0x00000000 unless an implementation includes configuration input signals that determine the reset value.

Setting up the vector table

The following example code sets up a vector table for an ARMv8-M architecture with Main Extension implementation, mapped to address 0x0 at reset:

…
AREA    RESET, DATA, READONLY, ALIGN=8
EXPORT	_Vectors
EXPORT	_Vectors_End
EXPORT	_Vector_Size
_Vectors	DCD		_initial_sp
		DCD		Reset_Handler
		DCD		NMI_Handler		; The vector table at boot is 
							       ; minimally required to have 4
; values: stack_top, reset 
							        ; routine location, NMI ISR
							        ; location, Hardfault ISR
							        ; location
		DCD		HardFault_handler
		DCD		MemManage_Handler
		DCD		BusFault_Handler
		DCD		UsageFault_Handler
		DCD		0, 0, 0, 0		; The SVCall ISR location must be
							       ; populated if the SVC instruction
							       ; is used
		DCD		SVC_Handler
		DCD		DebugMon_Handler
		DCD		0
		DCD		PendSV_Handler
		DCD		SysTick_Handler	; Once interrupts are enabled, the 
							     ; vector table must then contain 
							     ; pointers to all enabled (by mask) 
							     ; exceptions
		; External Interrupts
; Add the vectors for the device specific external interrupts handler here
		DCD	<DeviceInterrupt>_IRQ_Handler ; 0: Default
_Vectors_End
_Vectors_Size  EQU  _Vectors_End - _Vectors
…

TheARMv8-M architecture table is very similar but MemManage, BusFault, Usage Fault and DebugMonitor do not exist and SysTick is optional.

Exception priorities

All exceptions have an associated priority, with a lower priority value indicating a higher priority to the exception, and configurable priorities for all exceptions except Reset, HardFault, and NMI. If software does not configure any priorities, all exceptions with a configurable priority have a priority of 0. Lower priority numbers take precedence.

Name

Exception Priority #

Interrupts #0 -N

0-255 (programmable)

SysTick

0-255 (programmable)

PendSV

0-255 (programmable)

DebugMonitor

0-255 (programmable)

SVCall

0-255 (programmable)

UsageFault

0-255 (programmable)

BusFault

0-255 (programmable)

MemManage

0-255 (programmable)

Non-secure Hard Fault

-1

Secure HardFault

-3 or -1 (programmable)

Non-Maskable Interrupt

-2

Reset

-4

Note

  • Configurable priority values are in the range 0-255. This means that the Reset, HardFault, and NMI exceptions, with fixed negative priority values, always have higher priority than any other exception.
  • Reset, NMI and Hard Fault are the highest priority exceptions and the only exceptions with fixed priority. All others have settable priority.

For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0].

Note

For the ARMv8-M architecture, the available programmable priorities are limited to preempting priorities of 0, 64, 128 and 192. For the ARMv8-M architecture with Main Extension, the number of priority bits is between 3 and 8 inclusive, left-justified in an 8-bit field. However, the available range of preempting priorities is programmable and at most the top 7 bits, giving 0-254 in multiples of 2.

If multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed before IRQ[1].

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